Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
90.74	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	5	35	87.50

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	5	35	87.50	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	56	1			T4	1		T22	1		T46	1
class_index[0x1]	40	1			T2	1		T4	3		T17	1
class_index[0x2]	50	1			T6	1		T31	1		T85	1
class_index[0x3]	54	1			T4	1		T68	1		T69	1

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	74	1			T4	3		T17	1		T69	1
intr_timeout_cnt[1]	48	1			T2	1		T4	2		T22	1
intr_timeout_cnt[2]	21	1			T69	1		T71	2		T123	1
intr_timeout_cnt[3]	11	1			T46	1		T31	1		T86	1
intr_timeout_cnt[4]	11	1			T82	1		T275	1		T111	1
intr_timeout_cnt[5]	7	1			T68	1		T71	1		T42	1
intr_timeout_cnt[6]	7	1			T285	1		T286	1		T111	3
intr_timeout_cnt[7]	15	1			T31	1		T87	1		T100	1
intr_timeout_cnt[8]	4	1			T287	1		T285	1		T25	1
intr_timeout_cnt[9]	2	1			T102	2		-	-		-	-

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	5	35	87.50	5

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x0]]	[intr_timeout_cnt[6]]	0	1	1
[class_index[0x0]]	[intr_timeout_cnt[9]]	0	1	1
[class_index[0x1]]	[intr_timeout_cnt[5]]	0	1	1
[class_index[0x1]]	[intr_timeout_cnt[9]]	0	1	1
[class_index[0x3]]	[intr_timeout_cnt[4]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	21	1			T4	1		T83	1		T84	1
class_index[0x0]	intr_timeout_cnt[1]	12	1			T22	1		T68	1		T69	1
class_index[0x0]	intr_timeout_cnt[2]	8	1			T69	1		T71	2		T81	1
class_index[0x0]	intr_timeout_cnt[3]	5	1			T46	1		T118	1		T288	1
class_index[0x0]	intr_timeout_cnt[4]	2	1			T111	1		T279	1		-	-
class_index[0x0]	intr_timeout_cnt[5]	2	1			T60	1		T289	1		-	-
class_index[0x0]	intr_timeout_cnt[7]	5	1			T31	1		T118	2		T94	1
class_index[0x0]	intr_timeout_cnt[8]	1	1			T290	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[0]	13	1			T4	2		T17	1		T75	1
class_index[0x1]	intr_timeout_cnt[1]	9	1			T2	1		T4	1		T46	1
class_index[0x1]	intr_timeout_cnt[2]	5	1			T27	1		T255	1		T291	1
class_index[0x1]	intr_timeout_cnt[3]	2	1			T86	1		T94	1		-	-
class_index[0x1]	intr_timeout_cnt[4]	4	1			T82	1		T275	1		T292	2
class_index[0x1]	intr_timeout_cnt[6]	4	1			T111	3		T293	1		-	-
class_index[0x1]	intr_timeout_cnt[7]	2	1			T118	2		-	-		-	-
class_index[0x1]	intr_timeout_cnt[8]	1	1			T285	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[0]	15	1			T255	3		T294	1		T114	1
class_index[0x2]	intr_timeout_cnt[1]	13	1			T6	1		T31	1		T85	1
class_index[0x2]	intr_timeout_cnt[2]	4	1			T30	1		T292	2		T295	1
class_index[0x2]	intr_timeout_cnt[3]	2	1			T296	1		T115	1		-	-
class_index[0x2]	intr_timeout_cnt[4]	5	1			T59	1		T189	1		T297	1
class_index[0x2]	intr_timeout_cnt[5]	1	1			T42	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[6]	2	1			T285	1		T286	1		-	-
class_index[0x2]	intr_timeout_cnt[7]	6	1			T87	1		T100	1		T118	1
class_index[0x2]	intr_timeout_cnt[8]	1	1			T25	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[9]	1	1			T102	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[0]	25	1			T69	1		T31	1		T33	1
class_index[0x3]	intr_timeout_cnt[1]	14	1			T4	1		T118	1		T107	1
class_index[0x3]	intr_timeout_cnt[2]	4	1			T123	1		T86	1		T81	1
class_index[0x3]	intr_timeout_cnt[3]	2	1			T31	1		T298	1		-	-
class_index[0x3]	intr_timeout_cnt[5]	4	1			T68	1		T71	1		T105	1
class_index[0x3]	intr_timeout_cnt[6]	1	1			T292	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[7]	2	1			T42	1		T299	1		-	-
class_index[0x3]	intr_timeout_cnt[8]	1	1			T287	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[9]	1	1			T102	1		-	-		-	-