Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	357829	1			T1	15		T2	35		T3	1201
all_values[1]	357829	1			T1	15		T2	35		T3	1201
all_values[2]	357829	1			T1	15		T2	35		T3	1201
all_values[3]	357829	1			T1	15		T2	35		T3	1201

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

712082

1

T1

19

T2

60

T3

2342

auto[1]

719234

1

T1

41

T2

80

T3

2462

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

870285

1

T1

55

T2

72

T3

2461

auto[1]

561031

1

T1

5

T2

68

T3

2343

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	103305	1			T1	3		T2	9		T3	291
all_values[0]	auto[0]	auto[1]	75251	1			T1	1		T2	9		T3	277
all_values[0]	auto[1]	auto[0]	104311	1			T1	7		T2	9		T3	322
all_values[0]	auto[1]	auto[1]	74962	1			T1	4		T2	8		T3	311
all_values[1]	auto[0]	auto[0]	108289	1			T1	4		T2	7		T3	313
all_values[1]	auto[0]	auto[1]	69084	1			T2	7		T3	267		T4	405
all_values[1]	auto[1]	auto[0]	110666	1			T1	11		T2	11		T3	333
all_values[1]	auto[1]	auto[1]	69790	1			T2	10		T3	288		T4	470
all_values[2]	auto[0]	auto[0]	109056	1			T1	6		T2	7		T3	288
all_values[2]	auto[0]	auto[1]	69133	1			T2	7		T3	287		T4	436
all_values[2]	auto[1]	auto[0]	110454	1			T1	9		T2	11		T3	313
all_values[2]	auto[1]	auto[1]	69186	1			T2	10		T3	313		T4	461
all_values[3]	auto[0]	auto[0]	111481	1			T1	5		T2	7		T3	310
all_values[3]	auto[0]	auto[1]	66483	1			T2	7		T3	309		T4	446
all_values[3]	auto[1]	auto[0]	112723	1			T1	10		T2	11		T3	291
all_values[3]	auto[1]	auto[1]	67142	1			T2	10		T3	291		T4	445