Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	357829	1			T1	15		T2	35		T3	1201
all_pins[1]	357829	1			T1	15		T2	35		T3	1201
all_pins[2]	357829	1			T1	15		T2	35		T3	1201
all_pins[3]	357829	1			T1	15		T2	35		T3	1201

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1150236	1			T1	56		T2	102		T3	3601
values[0x1]	281080	1			T1	4		T2	38		T3	1203
transitions[0x0=>0x1]	187290	1			T1	3		T2	20		T3	757
transitions[0x1=>0x0]	187522	1			T1	4		T2	21		T3	758

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	282867	1			T1	11		T2	27		T3	890
all_pins[0]	values[0x1]	74962	1			T1	4		T2	8		T3	311
all_pins[0]	transitions[0x0=>0x1]	74414	1			T1	3		T2	7		T3	310
all_pins[0]	transitions[0x1=>0x0]	66826	1			T2	10		T3	291		T4	443
all_pins[1]	values[0x0]	288039	1			T1	15		T2	25		T3	913
all_pins[1]	values[0x1]	69790	1			T2	10		T3	288		T4	470
all_pins[1]	transitions[0x0=>0x1]	38370	1			T2	5		T3	138		T4	313
all_pins[1]	transitions[0x1=>0x0]	43542	1			T1	4		T2	3		T3	161
all_pins[2]	values[0x0]	288643	1			T1	15		T2	25		T3	888
all_pins[2]	values[0x1]	69186	1			T2	10		T3	313		T4	461
all_pins[2]	transitions[0x0=>0x1]	37835	1			T2	4		T3	170		T4	219
all_pins[2]	transitions[0x1=>0x0]	38439	1			T2	4		T3	145		T4	228
all_pins[3]	values[0x0]	290687	1			T1	15		T2	25		T3	910
all_pins[3]	values[0x1]	67142	1			T2	10		T3	291		T4	445
all_pins[3]	transitions[0x0=>0x1]	36671	1			T2	4		T3	139		T4	219
all_pins[3]	transitions[0x1=>0x0]	38715	1			T2	4		T3	161		T4	235