Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}
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Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}
SCOREWEIGHTGOALAT LEASTAUTO BIN MAXPRINT MISSING
100.00 1 100 1 64 64


Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv



Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Variables 10 0 10 100.00
Crosses 24 0 24 100.00


Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}
VARIABLEEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTAUTO BIN MAXCOMMENT
cp_intr 4 0 4 100.00 100 1 1 0
cp_intr_en 2 0 2 100.00 100 1 1 2
cp_intr_state 2 0 2 100.00 100 1 1 2
cp_intr_test 2 0 2 100.00 100 1 1 2


Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}
CROSSEXPECTEDUNCOVEREDCOVEREDPERCENTGOALWEIGHTAT LEASTPRINT MISSINGCOMMENT
intr_test_cg_cc 24 0 24 100.00 100 1 1 0


Summary for Variable cp_intr

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
User Defined Bins 4 0 4 100.00


User Defined Bins for cp_intr

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] 272 1 T165 7 T166 4 T239 4
all_values[1] 272 1 T165 7 T166 4 T239 4
all_values[2] 272 1 T165 7 T166 4 T239 4
all_values[3] 272 1 T165 7 T166 4 T239 4



Summary for Variable cp_intr_en

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_en

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 597 1 T165 11 T166 7 T239 7
auto[1] 491 1 T165 17 T166 9 T239 9



Summary for Variable cp_intr_state

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_state

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 437 1 T165 8 T166 2 T239 5
auto[1] 651 1 T165 20 T166 14 T239 11



Summary for Variable cp_intr_test

CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENT
Automatically Generated Bins 2 0 2 100.00


Automatically Generated Bins for cp_intr_test

Bins
NAMECOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
auto[0] 649 1 T165 14 T166 8 T239 9
auto[1] 439 1 T165 14 T166 8 T239 7



Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state
CATEGORYEXPECTEDUNCOVEREDCOVEREDPERCENTMISSING
TOTAL 24 0 24 100.00
Automatically Generated Cross Bins 24 0 24 100.00
User Defined Cross Bins 0 0 0


Automatically Generated Cross Bins for intr_test_cg_cc

Bins
cp_intrcp_intr_testcp_intr_encp_intr_stateCOUNTAT LEASTSTATUSTESTCOUNTTESTCOUNTTESTCOUNT
all_values[0] auto[0] auto[0] auto[0] 62 1 T165 2 T262 1 T348 1
all_values[0] auto[0] auto[0] auto[1] 26 1 T166 1 T349 1 T350 2
all_values[0] auto[0] auto[1] auto[0] 56 1 T165 1 T166 1 T261 1
all_values[0] auto[0] auto[1] auto[1] 28 1 T165 1 T166 1 T239 1
all_values[0] auto[1] auto[0] auto[1] 47 1 T165 2 T239 2 T261 3
all_values[0] auto[1] auto[1] auto[1] 53 1 T165 1 T166 1 T239 1
all_values[1] auto[0] auto[0] auto[0] 63 1 T165 1 T261 2 T348 2
all_values[1] auto[0] auto[0] auto[1] 31 1 T166 1 T239 1 T262 1
all_values[1] auto[0] auto[1] auto[0] 45 1 T165 1 T261 2 T262 2
all_values[1] auto[0] auto[1] auto[1] 27 1 T165 2 T166 1 T239 1
all_values[1] auto[1] auto[0] auto[1] 65 1 T239 1 T261 1 T262 1
all_values[1] auto[1] auto[1] auto[1] 41 1 T165 3 T166 2 T239 1
all_values[2] auto[0] auto[0] auto[0] 60 1 T165 1 T239 2 T261 2
all_values[2] auto[0] auto[0] auto[1] 24 1 T165 1 T166 1 T262 1
all_values[2] auto[0] auto[1] auto[0] 53 1 T239 1 T261 1 T351 1
all_values[2] auto[0] auto[1] auto[1] 25 1 T165 2 T261 2 T348 1
all_values[2] auto[1] auto[0] auto[1] 64 1 T165 2 T166 3 T261 2
all_values[2] auto[1] auto[1] auto[1] 46 1 T165 1 T239 1 T351 1
all_values[3] auto[0] auto[0] auto[0] 58 1 T165 1 T239 1 T261 2
all_values[3] auto[0] auto[0] auto[1] 29 1 T261 1 T351 2 T349 1
all_values[3] auto[0] auto[1] auto[0] 40 1 T165 1 T166 1 T239 1
all_values[3] auto[0] auto[1] auto[1] 22 1 T166 1 T239 1 T352 1
all_values[3] auto[1] auto[0] auto[1] 68 1 T165 1 T166 1 T261 4
all_values[3] auto[1] auto[1] auto[1] 55 1 T165 4 T166 1 T239 1


User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins
NAMECOUNTSTATUS
test_1_state_0 0 Illegal

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