Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	93059	1			T3	498		T5	1143		T17	1608
accum_cnt_1000	232030	1			T3	1154		T4	2213		T7	971
accum_cnt_100	28203	1			T3	68		T4	108		T7	225
accum_cnt_50	63080	1			T2	60		T3	50		T4	159
accum_cnt_10	160462	1			T1	4		T2	58		T3	900
accum_cnt_0	440267	1			T1	24		T2	18		T3	894

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	264378	1			T1	7		T2	34		T3	891
class_index[0x1]	264378	1			T1	7		T2	34		T3	891
class_index[0x2]	264378	1			T1	7		T2	34		T3	891
class_index[0x3]	264378	1			T1	7		T2	34		T3	891

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	28075	1			T5	1073		T17	564		T6	752
class_index[0x0]	accum_cnt_1000	71647	1			T4	1025		T7	553		T5	1358
class_index[0x0]	accum_cnt_100	10803	1			T4	89		T7	71		T5	145
class_index[0x0]	accum_cnt_50	13849	1			T2	18		T4	84		T7	65
class_index[0x0]	accum_cnt_10	39497	1			T1	4		T2	12		T4	46
class_index[0x0]	accum_cnt_0	83653	1			T1	3		T2	4		T3	891
class_index[0x1]	accum_cnt_2000	18613	1			T3	80		T17	546		T6	233
class_index[0x1]	accum_cnt_1000	55428	1			T3	727		T7	418		T5	300
class_index[0x1]	accum_cnt_100	5978	1			T3	41		T4	17		T7	154
class_index[0x1]	accum_cnt_50	19469	1			T2	20		T3	34		T4	38
class_index[0x1]	accum_cnt_10	41977	1			T2	13		T3	8		T4	1240
class_index[0x1]	accum_cnt_0	115020	1			T1	7		T2	1		T3	1
class_index[0x2]	accum_cnt_2000	21676	1			T3	418		T17	498		T6	402
class_index[0x2]	accum_cnt_1000	49354	1			T3	427		T5	119		T17	623
class_index[0x2]	accum_cnt_100	4939	1			T3	27		T5	69		T17	37
class_index[0x2]	accum_cnt_50	12669	1			T2	22		T3	16		T4	4
class_index[0x2]	accum_cnt_10	41745	1			T2	4		T3	1		T4	1218
class_index[0x2]	accum_cnt_0	125600	1			T1	7		T2	8		T3	2
class_index[0x3]	accum_cnt_2000	24695	1			T5	70		T18	13		T6	355
class_index[0x3]	accum_cnt_1000	55601	1			T4	1188		T5	1284		T14	886
class_index[0x3]	accum_cnt_100	6483	1			T4	2		T5	188		T14	79
class_index[0x3]	accum_cnt_50	17093	1			T4	33		T12	19		T5	189
class_index[0x3]	accum_cnt_10	37243	1			T2	29		T3	891		T4	46
class_index[0x3]	accum_cnt_0	115994	1			T1	7		T2	5		T4	56