Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	2464	1			T8	1		T15	1		T6	50
alert[0x1]	3378	1			T15	1		T68	9		T27	142
alert[0x2]	6286	1			T16	1		T61	1		T68	2
alert[0x3]	3644	1			T4	228		T6	129		T64	1
alert[0x4]	5290	1			T4	387		T8	1		T6	211
alert[0x5]	3080	1			T62	1		T67	5		T79	1
alert[0x6]	1562	1			T4	13		T7	1		T6	93
alert[0x7]	2256	1			T8	1		T6	202		T61	1
alert[0x8]	2874	1			T6	15		T64	2		T67	110
alert[0x9]	6856	1			T3	4		T6	2		T67	43
alert[0xa]	3381	1			T5	14		T68	40		T121	8
alert[0xb]	4446	1			T4	452		T61	1		T31	1
alert[0xc]	5987	1			T5	1		T8	1		T6	47
alert[0xd]	4787	1			T6	208		T68	3		T233	83
alert[0xe]	2257	1			T8	1		T67	55		T27	38
alert[0xf]	7081	1			T6	9		T233	41		T27	15
alert[0x10]	3850	1			T8	1		T67	68		T234	1
alert[0x11]	6325	1			T6	970		T68	25		T233	294
alert[0x12]	2425	1			T6	28		T68	4		T31	3
alert[0x13]	5450	1			T17	18		T6	9		T61	1
alert[0x14]	3702	1			T3	2		T4	63		T15	1
alert[0x15]	3384	1			T4	20		T5	4		T8	1
alert[0x16]	10414	1			T6	145		T61	1		T233	4
alert[0x17]	4011	1			T5	33		T8	1		T6	353
alert[0x18]	7764	1			T4	350		T6	404		T67	96
alert[0x19]	4795	1			T4	439		T5	7		T67	327
alert[0x1a]	6620	1			T67	28		T234	1		T76	5
alert[0x1b]	3252	1			T5	13		T67	2		T233	17
alert[0x1c]	8022	1			T4	95		T8	2		T13	1
alert[0x1d]	11654	1			T4	163		T6	292		T61	1
alert[0x1e]	5256	1			T5	3		T67	48		T31	2
alert[0x1f]	6763	1			T4	7		T6	60		T67	49
alert[0x20]	7562	1			T4	18		T8	1		T6	25
alert[0x21]	6702	1			T4	57		T5	49		T6	3647
alert[0x22]	6025	1			T4	263		T6	37		T64	2
alert[0x23]	4169	1			T6	27		T64	2		T67	66
alert[0x24]	6876	1			T15	1		T6	86		T233	2465
alert[0x25]	3915	1			T4	125		T8	1		T67	144
alert[0x26]	5004	1			T5	26		T6	8		T67	427
alert[0x27]	9760	1			T6	116		T67	28		T233	122
alert[0x28]	8120	1			T6	48		T61	1		T235	1
alert[0x29]	5933	1			T6	11		T67	408		T31	7
alert[0x2a]	8523	1			T6	12		T64	2		T241	2
alert[0x2b]	3079	1			T3	1		T4	643		T5	25
alert[0x2c]	5392	1			T4	383		T16	1		T61	2
alert[0x2d]	3597	1			T5	1		T14	1		T6	514
alert[0x2e]	7261	1			T4	105		T5	7		T6	640
alert[0x2f]	4818	1			T3	12		T4	11		T117	31
alert[0x30]	3487	1			T4	21		T5	29		T8	1
alert[0x31]	4660	1			T46	9		T6	121		T79	4
alert[0x32]	8368	1			T4	216		T5	1220		T61	1
alert[0x33]	4895	1			T4	147		T8	1		T61	1
alert[0x34]	3389	1			T8	1		T64	2		T233	63
alert[0x35]	5738	1			T8	1		T15	1		T67	92
alert[0x36]	6954	1			T64	1		T233	33		T31	1
alert[0x37]	5024	1			T4	89		T8	1		T6	119
alert[0x38]	6049	1			T6	193		T61	2		T67	48
alert[0x39]	1993	1			T3	3		T8	1		T15	1
alert[0x3a]	7890	1			T3	2		T4	5		T8	1
alert[0x3b]	3933	1			T4	57		T6	50		T61	1
alert[0x3c]	9579	1			T3	1		T4	263		T46	2
alert[0x3d]	3246	1			T6	40		T61	1		T64	1
alert[0x3e]	3885	1			T4	365		T6	3		T67	59
alert[0x3f]	3053	1			T4	353		T5	1		T67	165
alert[0x40]	1499	1			T6	118		T67	149		T233	51

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	142283	1			T3	8		T7	1		T5	1433
class_i[0x1]	99681	1			T4	46		T14	1		T6	1314
class_i[0x2]	49687	1			T3	14		T4	5292		T13	2
class_i[0x3]	48043	1			T3	3		T8	19		T16	5

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

339066

1

T3

25

T4

5338

T5

1433

alert_ping_fail

628

1

T7

1

T8

19

T13

2

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	2456	1			T6	50		T67	4		T233	10
alert_integrity_fail	alert[0x1]	3371	1			T68	9		T27	142		T80	23
alert_integrity_fail	alert[0x2]	6280	1			T68	2		T79	1		T233	182
alert_integrity_fail	alert[0x3]	3632	1			T4	228		T6	129		T33	9
alert_integrity_fail	alert[0x4]	5279	1			T4	387		T6	211		T67	297
alert_integrity_fail	alert[0x5]	3067	1			T67	5		T79	1		T31	1
alert_integrity_fail	alert[0x6]	1548	1			T4	13		T6	93		T31	2
alert_integrity_fail	alert[0x7]	2242	1			T6	202		T233	26		T220	708
alert_integrity_fail	alert[0x8]	2852	1			T6	15		T67	110		T29	2
alert_integrity_fail	alert[0x9]	6847	1			T3	4		T6	2		T67	43
alert_integrity_fail	alert[0xa]	3369	1			T5	14		T68	40		T121	8
alert_integrity_fail	alert[0xb]	4435	1			T4	452		T31	1		T53	397
alert_integrity_fail	alert[0xc]	5975	1			T5	1		T6	47		T117	63
alert_integrity_fail	alert[0xd]	4781	1			T6	208		T68	3		T233	83
alert_integrity_fail	alert[0xe]	2251	1			T67	55		T27	38		T30	391
alert_integrity_fail	alert[0xf]	7079	1			T6	9		T233	41		T27	15
alert_integrity_fail	alert[0x10]	3841	1			T67	68		T220	274		T30	16
alert_integrity_fail	alert[0x11]	6318	1			T6	970		T68	25		T233	294
alert_integrity_fail	alert[0x12]	2416	1			T6	28		T68	4		T31	3
alert_integrity_fail	alert[0x13]	5443	1			T17	18		T6	9		T220	325
alert_integrity_fail	alert[0x14]	3687	1			T3	2		T4	63		T68	4
alert_integrity_fail	alert[0x15]	3373	1			T4	20		T5	4		T67	80
alert_integrity_fail	alert[0x16]	10398	1			T6	145		T233	4		T31	39
alert_integrity_fail	alert[0x17]	4005	1			T5	33		T6	353		T233	74
alert_integrity_fail	alert[0x18]	7756	1			T4	350		T6	404		T67	96
alert_integrity_fail	alert[0x19]	4783	1			T4	439		T5	7		T67	327
alert_integrity_fail	alert[0x1a]	6615	1			T67	28		T76	5		T302	28
alert_integrity_fail	alert[0x1b]	3246	1			T5	13		T67	2		T233	17
alert_integrity_fail	alert[0x1c]	8012	1			T4	95		T6	11		T31	4
alert_integrity_fail	alert[0x1d]	11641	1			T4	163		T6	292		T79	1
alert_integrity_fail	alert[0x1e]	5252	1			T5	3		T67	48		T31	2
alert_integrity_fail	alert[0x1f]	6751	1			T4	7		T6	60		T67	49
alert_integrity_fail	alert[0x20]	7555	1			T4	18		T6	25		T233	21
alert_integrity_fail	alert[0x21]	6688	1			T4	57		T5	49		T6	3647
alert_integrity_fail	alert[0x22]	6014	1			T4	263		T6	37		T68	13
alert_integrity_fail	alert[0x23]	4161	1			T6	27		T67	66		T68	7
alert_integrity_fail	alert[0x24]	6866	1			T6	86		T233	2465		T31	19
alert_integrity_fail	alert[0x25]	3905	1			T4	125		T67	144		T79	1
alert_integrity_fail	alert[0x26]	4997	1			T5	26		T6	8		T67	427
alert_integrity_fail	alert[0x27]	9756	1			T6	116		T67	28		T233	122
alert_integrity_fail	alert[0x28]	8112	1			T6	48		T220	6		T30	1004
alert_integrity_fail	alert[0x29]	5925	1			T6	11		T67	408		T31	7
alert_integrity_fail	alert[0x2a]	8507	1			T6	12		T220	553		T27	322
alert_integrity_fail	alert[0x2b]	3069	1			T3	1		T4	643		T5	25
alert_integrity_fail	alert[0x2c]	5373	1			T4	383		T67	21		T31	3
alert_integrity_fail	alert[0x2d]	3592	1			T5	1		T6	514		T31	66
alert_integrity_fail	alert[0x2e]	7249	1			T4	105		T5	7		T6	640
alert_integrity_fail	alert[0x2f]	4809	1			T3	12		T4	11		T117	31
alert_integrity_fail	alert[0x30]	3475	1			T4	21		T5	29		T6	65
alert_integrity_fail	alert[0x31]	4648	1			T46	9		T6	121		T79	4
alert_integrity_fail	alert[0x32]	8354	1			T4	216		T5	1220		T220	56
alert_integrity_fail	alert[0x33]	4883	1			T4	147		T67	10		T33	1
alert_integrity_fail	alert[0x34]	3382	1			T233	63		T31	2		T121	1
alert_integrity_fail	alert[0x35]	5728	1			T67	92		T31	1		T220	14
alert_integrity_fail	alert[0x36]	6944	1			T233	33		T31	1		T220	156
alert_integrity_fail	alert[0x37]	5018	1			T4	89		T6	119		T79	2
alert_integrity_fail	alert[0x38]	6043	1			T6	193		T67	48		T233	35
alert_integrity_fail	alert[0x39]	1982	1			T3	3		T6	13		T220	29
alert_integrity_fail	alert[0x3a]	7877	1			T3	2		T4	5		T67	53
alert_integrity_fail	alert[0x3b]	3927	1			T4	57		T6	50		T68	8
alert_integrity_fail	alert[0x3c]	9571	1			T3	1		T4	263		T46	2
alert_integrity_fail	alert[0x3d]	3231	1			T6	40		T67	125		T27	1
alert_integrity_fail	alert[0x3e]	3877	1			T4	365		T6	3		T67	59
alert_integrity_fail	alert[0x3f]	3051	1			T4	353		T5	1		T67	165
alert_integrity_fail	alert[0x40]	1496	1			T6	118		T67	149		T233	51
alert_ping_fail	alert[0x0]	8	1			T8	1		T15	1		T64	1
alert_ping_fail	alert[0x1]	7	1			T15	1		T303	1		T304	1
alert_ping_fail	alert[0x2]	6	1			T16	1		T61	1		T221	1
alert_ping_fail	alert[0x3]	12	1			T64	1		T234	1		T305	1
alert_ping_fail	alert[0x4]	11	1			T8	1		T61	1		T304	1
alert_ping_fail	alert[0x5]	13	1			T62	1		T235	1		T221	1
alert_ping_fail	alert[0x6]	14	1			T7	1		T234	1		T306	1
alert_ping_fail	alert[0x7]	14	1			T8	1		T61	1		T305	1
alert_ping_fail	alert[0x8]	22	1			T64	2		T301	2		T304	2
alert_ping_fail	alert[0x9]	9	1			T307	2		T308	2		T309	1
alert_ping_fail	alert[0xa]	12	1			T271	2		T305	1		T307	2
alert_ping_fail	alert[0xb]	11	1			T61	1		T303	1		T310	1
alert_ping_fail	alert[0xc]	12	1			T8	1		T64	1		T304	1
alert_ping_fail	alert[0xd]	6	1			T304	1		T311	1		T312	1
alert_ping_fail	alert[0xe]	6	1			T8	1		T307	1		T313	1
alert_ping_fail	alert[0xf]	2	1			T307	1		T314	1		-	-
alert_ping_fail	alert[0x10]	9	1			T8	1		T234	1		T315	1
alert_ping_fail	alert[0x11]	7	1			T316	1		T317	1		T310	1
alert_ping_fail	alert[0x12]	9	1			T311	1		T318	1		T319	1
alert_ping_fail	alert[0x13]	7	1			T61	1		T309	1		T320	2
alert_ping_fail	alert[0x14]	15	1			T15	1		T61	1		T234	1
alert_ping_fail	alert[0x15]	11	1			T8	1		T13	1		T16	1
alert_ping_fail	alert[0x16]	16	1			T61	1		T234	1		T241	2
alert_ping_fail	alert[0x17]	6	1			T8	1		T303	2		T310	1
alert_ping_fail	alert[0x18]	8	1			T221	1		T305	2		T321	1
alert_ping_fail	alert[0x19]	12	1			T304	1		T308	1		T311	1
alert_ping_fail	alert[0x1a]	5	1			T234	1		T322	1		T323	1
alert_ping_fail	alert[0x1b]	6	1			T324	1		T325	1		T326	1
alert_ping_fail	alert[0x1c]	10	1			T8	2		T13	1		T16	1
alert_ping_fail	alert[0x1d]	13	1			T61	1		T305	1		T322	1
alert_ping_fail	alert[0x1e]	4	1			T309	1		T326	2		T327	1
alert_ping_fail	alert[0x1f]	12	1			T70	1		T234	1		T328	1
alert_ping_fail	alert[0x20]	7	1			T8	1		T303	1		T329	1
alert_ping_fail	alert[0x21]	14	1			T317	1		T304	1		T310	1
alert_ping_fail	alert[0x22]	11	1			T64	2		T235	1		T316	1
alert_ping_fail	alert[0x23]	8	1			T64	2		T305	1		T311	1
alert_ping_fail	alert[0x24]	10	1			T15	1		T234	1		T303	1
alert_ping_fail	alert[0x25]	10	1			T8	1		T234	1		T303	1
alert_ping_fail	alert[0x26]	7	1			T307	1		T322	1		T311	3
alert_ping_fail	alert[0x27]	4	1			T304	1		T310	1		T320	1
alert_ping_fail	alert[0x28]	8	1			T61	1		T235	1		T238	1
alert_ping_fail	alert[0x29]	8	1			T317	1		T304	1		T330	1
alert_ping_fail	alert[0x2a]	16	1			T64	2		T241	2		T304	1
alert_ping_fail	alert[0x2b]	10	1			T61	1		T321	1		T309	1
alert_ping_fail	alert[0x2c]	19	1			T16	1		T61	2		T62	1
alert_ping_fail	alert[0x2d]	5	1			T14	1		T310	1		T325	1
alert_ping_fail	alert[0x2e]	12	1			T61	1		T62	1		T301	1
alert_ping_fail	alert[0x2f]	9	1			T331	1		T305	1		T304	1
alert_ping_fail	alert[0x30]	12	1			T8	1		T307	1		T311	1
alert_ping_fail	alert[0x31]	12	1			T317	1		T304	1		T307	1
alert_ping_fail	alert[0x32]	14	1			T61	1		T64	1		T234	1
alert_ping_fail	alert[0x33]	12	1			T8	1		T61	1		T303	2
alert_ping_fail	alert[0x34]	7	1			T8	1		T64	2		T312	1
alert_ping_fail	alert[0x35]	10	1			T8	1		T15	1		T221	1
alert_ping_fail	alert[0x36]	10	1			T64	1		T234	1		T324	1
alert_ping_fail	alert[0x37]	6	1			T8	1		T234	1		T307	1
alert_ping_fail	alert[0x38]	6	1			T61	2		T310	1		T324	1
alert_ping_fail	alert[0x39]	11	1			T8	1		T15	1		T303	1
alert_ping_fail	alert[0x3a]	13	1			T8	1		T15	1		T16	1
alert_ping_fail	alert[0x3b]	6	1			T61	1		T234	1		T310	1
alert_ping_fail	alert[0x3c]	8	1			T61	1		T64	2		T303	1
alert_ping_fail	alert[0x3d]	15	1			T61	1		T64	1		T305	1
alert_ping_fail	alert[0x3e]	8	1			T307	1		T313	1		T311	1
alert_ping_fail	alert[0x3f]	2	1			T322	1		T332	1		-	-
alert_ping_fail	alert[0x40]	3	1			T307	1		T333	1		T334	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	142081	1			T3	8		T5	1433		T17	18
alert_integrity_fail	class_i[0x1]	99515	1			T4	46		T6	1314		T67	4418
alert_integrity_fail	class_i[0x2]	49564	1			T3	14		T4	5292		T46	9
alert_integrity_fail	class_i[0x3]	47906	1			T3	3		T67	36		T79	2
alert_ping_fail	class_i[0x0]	202	1			T7	1		T15	7		T61	1
alert_ping_fail	class_i[0x1]	166	1			T14	1		T61	18		T64	20
alert_ping_fail	class_i[0x2]	123	1			T13	2		T61	1		T64	1
alert_ping_fail	class_i[0x3]	137	1			T8	19		T16	5		T235	1