Tests
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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.21 99.99 98.70 97.09 100.00 100.00 99.38 99.32


Total test records in report: 827
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T775 /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.1257817071 Aug 10 04:38:21 PM PDT 24 Aug 10 04:38:31 PM PDT 24 143005129 ps
T776 /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.2829523213 Aug 10 04:38:32 PM PDT 24 Aug 10 04:38:36 PM PDT 24 73177788 ps
T777 /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.3196339938 Aug 10 04:38:30 PM PDT 24 Aug 10 04:38:34 PM PDT 24 140794212 ps
T778 /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.195837803 Aug 10 04:38:57 PM PDT 24 Aug 10 04:38:58 PM PDT 24 9553589 ps
T779 /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.1877193244 Aug 10 04:38:39 PM PDT 24 Aug 10 04:39:16 PM PDT 24 496980597 ps
T780 /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.3172137374 Aug 10 04:38:29 PM PDT 24 Aug 10 04:39:10 PM PDT 24 1043872741 ps
T781 /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.902662666 Aug 10 04:38:35 PM PDT 24 Aug 10 04:38:54 PM PDT 24 256864990 ps
T782 /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.1880749422 Aug 10 04:38:27 PM PDT 24 Aug 10 04:38:50 PM PDT 24 598122604 ps
T783 /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.4031999939 Aug 10 04:38:44 PM PDT 24 Aug 10 04:39:01 PM PDT 24 249311464 ps
T784 /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.93203414 Aug 10 04:38:51 PM PDT 24 Aug 10 04:38:52 PM PDT 24 7781603 ps
T147 /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.1791997136 Aug 10 04:38:56 PM PDT 24 Aug 10 04:56:35 PM PDT 24 15254788585 ps
T169 /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.1338058039 Aug 10 04:38:19 PM PDT 24 Aug 10 04:38:22 PM PDT 24 475339391 ps
T300 /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.1478356415 Aug 10 04:38:33 PM PDT 24 Aug 10 04:39:11 PM PDT 24 652774427 ps
T785 /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.1881832457 Aug 10 04:38:45 PM PDT 24 Aug 10 04:38:46 PM PDT 24 9405529 ps
T786 /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.3384469079 Aug 10 04:38:52 PM PDT 24 Aug 10 04:39:03 PM PDT 24 135725737 ps
T174 /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.2224739113 Aug 10 04:38:51 PM PDT 24 Aug 10 04:38:56 PM PDT 24 89868378 ps
T787 /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.1236052215 Aug 10 04:38:41 PM PDT 24 Aug 10 04:39:07 PM PDT 24 702749145 ps
T788 /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.3805489105 Aug 10 04:38:29 PM PDT 24 Aug 10 04:38:31 PM PDT 24 10008089 ps
T789 /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.2543255873 Aug 10 04:38:50 PM PDT 24 Aug 10 04:38:52 PM PDT 24 25215283 ps
T140 /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.232760749 Aug 10 04:38:38 PM PDT 24 Aug 10 04:43:16 PM PDT 24 4313967405 ps
T133 /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.657875921 Aug 10 04:38:37 PM PDT 24 Aug 10 04:43:32 PM PDT 24 17357391024 ps
T790 /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.2182657838 Aug 10 04:38:49 PM PDT 24 Aug 10 04:39:54 PM PDT 24 1059932846 ps
T791 /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.309802295 Aug 10 04:38:24 PM PDT 24 Aug 10 04:38:32 PM PDT 24 410271617 ps
T792 /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.876189762 Aug 10 04:38:35 PM PDT 24 Aug 10 04:38:37 PM PDT 24 8535753 ps
T793 /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.2614587761 Aug 10 04:38:30 PM PDT 24 Aug 10 04:39:59 PM PDT 24 552289893 ps
T794 /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.2913640739 Aug 10 04:39:01 PM PDT 24 Aug 10 04:39:15 PM PDT 24 501771643 ps
T795 /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.3303409842 Aug 10 04:38:45 PM PDT 24 Aug 10 04:38:53 PM PDT 24 95407363 ps
T796 /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.2488359254 Aug 10 04:38:26 PM PDT 24 Aug 10 04:38:35 PM PDT 24 124045794 ps
T797 /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.2170393505 Aug 10 04:38:33 PM PDT 24 Aug 10 04:38:45 PM PDT 24 351280982 ps
T172 /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.3659855156 Aug 10 04:38:51 PM PDT 24 Aug 10 04:40:18 PM PDT 24 14736366551 ps
T798 /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.3092407188 Aug 10 04:38:50 PM PDT 24 Aug 10 04:39:00 PM PDT 24 171934470 ps
T146 /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.1558075585 Aug 10 04:38:37 PM PDT 24 Aug 10 04:44:08 PM PDT 24 5023586593 ps
T799 /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.4204353184 Aug 10 04:38:35 PM PDT 24 Aug 10 04:39:21 PM PDT 24 2574491021 ps
T800 /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.201835659 Aug 10 04:38:46 PM PDT 24 Aug 10 04:38:48 PM PDT 24 7962782 ps
T801 /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.263327780 Aug 10 04:38:43 PM PDT 24 Aug 10 04:39:18 PM PDT 24 981815764 ps
T154 /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.3181401868 Aug 10 04:38:35 PM PDT 24 Aug 10 04:45:51 PM PDT 24 7001988808 ps
T802 /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.3348430756 Aug 10 04:38:27 PM PDT 24 Aug 10 04:47:36 PM PDT 24 6338184260 ps
T803 /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.2363266405 Aug 10 04:38:35 PM PDT 24 Aug 10 04:38:49 PM PDT 24 250443466 ps
T354 /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.3135598005 Aug 10 04:38:37 PM PDT 24 Aug 10 04:49:18 PM PDT 24 29038127896 ps
T804 /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.3365093651 Aug 10 04:38:45 PM PDT 24 Aug 10 04:38:47 PM PDT 24 34043841 ps
T356 /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.1802815949 Aug 10 04:38:29 PM PDT 24 Aug 10 04:48:05 PM PDT 24 28065486367 ps
T805 /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.1787067189 Aug 10 04:38:39 PM PDT 24 Aug 10 04:38:43 PM PDT 24 52285721 ps
T155 /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.2721173698 Aug 10 04:38:36 PM PDT 24 Aug 10 04:42:06 PM PDT 24 33372068839 ps
T806 /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.2887422308 Aug 10 04:38:37 PM PDT 24 Aug 10 04:38:45 PM PDT 24 680235665 ps
T807 /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.1980003770 Aug 10 04:38:15 PM PDT 24 Aug 10 04:38:24 PM PDT 24 554613017 ps
T808 /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.2461019311 Aug 10 04:38:52 PM PDT 24 Aug 10 04:38:57 PM PDT 24 30949722 ps
T158 /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.547204044 Aug 10 04:38:38 PM PDT 24 Aug 10 04:40:39 PM PDT 24 1156412366 ps
T160 /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.3612774051 Aug 10 04:38:48 PM PDT 24 Aug 10 04:45:16 PM PDT 24 18659303473 ps
T809 /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.2658031191 Aug 10 04:38:36 PM PDT 24 Aug 10 04:38:37 PM PDT 24 6260971 ps
T810 /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.2877421292 Aug 10 04:38:54 PM PDT 24 Aug 10 04:38:56 PM PDT 24 16825577 ps
T811 /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.2121353951 Aug 10 04:38:48 PM PDT 24 Aug 10 04:39:36 PM PDT 24 2373600889 ps
T812 /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.1297552387 Aug 10 04:38:48 PM PDT 24 Aug 10 04:38:50 PM PDT 24 24960459 ps
T161 /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.1057858423 Aug 10 04:38:24 PM PDT 24 Aug 10 04:44:04 PM PDT 24 35036001612 ps
T813 /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.4275565291 Aug 10 04:38:45 PM PDT 24 Aug 10 04:38:47 PM PDT 24 8218970 ps
T157 /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.3598908598 Aug 10 04:38:29 PM PDT 24 Aug 10 04:43:15 PM PDT 24 7891405173 ps
T814 /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.1256230073 Aug 10 04:38:15 PM PDT 24 Aug 10 04:38:34 PM PDT 24 326853577 ps
T815 /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.466797387 Aug 10 04:38:41 PM PDT 24 Aug 10 04:38:54 PM PDT 24 87044726 ps
T816 /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.2211379254 Aug 10 04:38:45 PM PDT 24 Aug 10 04:42:39 PM PDT 24 3247102092 ps
T180 /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.3093564990 Aug 10 04:38:46 PM PDT 24 Aug 10 04:38:48 PM PDT 24 96676985 ps
T159 /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.376900878 Aug 10 04:38:17 PM PDT 24 Aug 10 04:41:10 PM PDT 24 10096375988 ps
T156 /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.3468051753 Aug 10 04:38:29 PM PDT 24 Aug 10 04:41:02 PM PDT 24 8683431686 ps
T817 /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.3419404977 Aug 10 04:38:54 PM PDT 24 Aug 10 04:39:03 PM PDT 24 95807902 ps
T818 /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.3384390374 Aug 10 04:38:30 PM PDT 24 Aug 10 04:39:13 PM PDT 24 695172081 ps
T177 /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.2292774067 Aug 10 04:38:41 PM PDT 24 Aug 10 04:38:45 PM PDT 24 193319890 ps
T819 /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.2634167922 Aug 10 04:38:42 PM PDT 24 Aug 10 04:38:53 PM PDT 24 364756599 ps
T820 /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.2749163816 Aug 10 04:38:33 PM PDT 24 Aug 10 04:40:47 PM PDT 24 7173139024 ps
T821 /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.2867449003 Aug 10 04:38:28 PM PDT 24 Aug 10 04:41:49 PM PDT 24 12933041942 ps
T168 /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.112634532 Aug 10 04:38:08 PM PDT 24 Aug 10 04:39:38 PM PDT 24 11369946298 ps
T822 /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.323597980 Aug 10 04:38:30 PM PDT 24 Aug 10 04:38:51 PM PDT 24 274085785 ps
T176 /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.3769424734 Aug 10 04:38:45 PM PDT 24 Aug 10 04:38:49 PM PDT 24 180358129 ps
T823 /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.756189561 Aug 10 04:38:15 PM PDT 24 Aug 10 04:38:16 PM PDT 24 10333972 ps
T824 /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.2485120340 Aug 10 04:38:35 PM PDT 24 Aug 10 04:38:46 PM PDT 24 551405014 ps
T355 /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.4045189094 Aug 10 04:38:30 PM PDT 24 Aug 10 04:48:54 PM PDT 24 4654704755 ps
T825 /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.4266096208 Aug 10 04:38:46 PM PDT 24 Aug 10 04:38:48 PM PDT 24 14287679 ps
T826 /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.4022762971 Aug 10 04:38:40 PM PDT 24 Aug 10 04:38:45 PM PDT 24 197386056 ps
T827 /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.1786923625 Aug 10 04:38:43 PM PDT 24 Aug 10 04:38:47 PM PDT 24 80157361 ps
T171 /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.2455931056 Aug 10 04:38:36 PM PDT 24 Aug 10 04:38:41 PM PDT 24 215686645 ps

Test location /workspace/coverage/default/45.alert_handler_stress_all_with_rand_reset.3307527727
Short name T5
Test name
Test status
Simulation time 570584964893 ps
CPU time 9512.33 seconds
Started Aug 10 04:40:23 PM PDT 24
Finished Aug 10 07:18:57 PM PDT 24
Peak memory 369528 kb
Host smart-b1566c39-f57f-4152-bb17-5148ed8993de
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3307527727 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.alert_handler_stress_all_with_rand_reset.3307527727
Directory /workspace/45.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.148710030
Short name T17
Test name
Test status
Simulation time 38579236602 ps
CPU time 2286.77 seconds
Started Aug 10 04:39:45 PM PDT 24
Finished Aug 10 05:17:52 PM PDT 24
Peak memory 280956 kb
Host smart-11fd49c6-7505-406b-a804-218d3770eca3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=148710030 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.148710030
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.3666161410
Short name T11
Test name
Test status
Simulation time 1527652059 ps
CPU time 14.28 seconds
Started Aug 10 04:38:54 PM PDT 24
Finished Aug 10 04:39:09 PM PDT 24
Peak memory 277068 kb
Host smart-b597bb80-0045-4127-a233-a15e609b2c3a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3666161410 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.3666161410
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all_with_rand_reset.667364977
Short name T31
Test name
Test status
Simulation time 126432041368 ps
CPU time 2089.49 seconds
Started Aug 10 04:38:54 PM PDT 24
Finished Aug 10 05:13:44 PM PDT 24
Peak memory 288568 kb
Host smart-9f949df9-e071-4ea1-bf47-b2f5f91397b5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=667364977 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 2.alert_handler_stress_all_with_rand_reset.667364977
Directory /workspace/2.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.486984457
Short name T244
Test name
Test status
Simulation time 441696191 ps
CPU time 9.33 seconds
Started Aug 10 04:38:31 PM PDT 24
Finished Aug 10 04:38:40 PM PDT 24
Peak memory 237580 kb
Host smart-73e39ed4-0b81-4e8e-988b-238a39e23cfd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=486984457 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.486984457
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.1469134732
Short name T128
Test name
Test status
Simulation time 4912864360 ps
CPU time 675.91 seconds
Started Aug 10 04:38:38 PM PDT 24
Finished Aug 10 04:49:55 PM PDT 24
Peak memory 265536 kb
Host smart-fbe5bba0-0cfb-4803-b821-62bd83d4f3e2
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469134732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.1469134732
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.3616476808
Short name T236
Test name
Test status
Simulation time 3570405394 ps
CPU time 37.5 seconds
Started Aug 10 04:39:30 PM PDT 24
Finished Aug 10 04:40:08 PM PDT 24
Peak memory 248252 kb
Host smart-57ab53b6-7fe0-4da2-bf17-ce06fdc0e196
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3616476808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.3616476808
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.1203332668
Short name T57
Test name
Test status
Simulation time 23859468657 ps
CPU time 351.19 seconds
Started Aug 10 04:39:23 PM PDT 24
Finished Aug 10 04:45:14 PM PDT 24
Peak memory 256472 kb
Host smart-cf5b0e99-b503-4092-8d7e-48fce81f257c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1203332668 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_ha
ndler_stress_all.1203332668
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.164005296
Short name T52
Test name
Test status
Simulation time 4840746873 ps
CPU time 45.25 seconds
Started Aug 10 04:39:36 PM PDT 24
Finished Aug 10 04:40:22 PM PDT 24
Peak memory 248008 kb
Host smart-151221c9-d298-4a2f-8059-b5f76865d623
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16400
5296 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.164005296
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.3025850006
Short name T235
Test name
Test status
Simulation time 86687741631 ps
CPU time 2530.49 seconds
Started Aug 10 04:38:48 PM PDT 24
Finished Aug 10 05:20:59 PM PDT 24
Peak memory 285592 kb
Host smart-c76ad38b-3d5e-43e8-887a-7335fc71639a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025850006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.3025850006
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.3680601097
Short name T145
Test name
Test status
Simulation time 13030566471 ps
CPU time 211.56 seconds
Started Aug 10 04:38:44 PM PDT 24
Finished Aug 10 04:42:16 PM PDT 24
Peak memory 265568 kb
Host smart-59f7c276-7485-4a7a-ae4a-732484e55dba
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3680601097 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_err
ors.3680601097
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all_with_rand_reset.2930310862
Short name T6
Test name
Test status
Simulation time 209249629878 ps
CPU time 8536.07 seconds
Started Aug 10 04:38:58 PM PDT 24
Finished Aug 10 07:01:15 PM PDT 24
Peak memory 370800 kb
Host smart-bdc5a21a-41b9-40c8-83d9-776a4f76d9c3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2930310862 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.alert_handler_stress_all_with_rand_reset.2930310862
Directory /workspace/3.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.1615813688
Short name T132
Test name
Test status
Simulation time 4389941075 ps
CPU time 638.61 seconds
Started Aug 10 04:38:51 PM PDT 24
Finished Aug 10 04:49:30 PM PDT 24
Peak memory 265472 kb
Host smart-da392db1-8853-4666-ac98-9b134903ddb1
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615813688 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.1615813688
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.1858906826
Short name T106
Test name
Test status
Simulation time 365535680420 ps
CPU time 1885.28 seconds
Started Aug 10 04:40:16 PM PDT 24
Finished Aug 10 05:11:41 PM PDT 24
Peak memory 272224 kb
Host smart-d2a7ac23-0957-47c1-9b03-5330691ec37b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1858906826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.1858906826
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.4155663648
Short name T127
Test name
Test status
Simulation time 18685003360 ps
CPU time 648.04 seconds
Started Aug 10 04:38:27 PM PDT 24
Finished Aug 10 04:49:16 PM PDT 24
Peak memory 265512 kb
Host smart-78390159-d9fd-4cc9-b9fa-5062166f51dc
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4155663648 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.4155663648
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all_with_rand_reset.3167730085
Short name T111
Test name
Test status
Simulation time 517857440011 ps
CPU time 3424.2 seconds
Started Aug 10 04:39:23 PM PDT 24
Finished Aug 10 05:36:28 PM PDT 24
Peak memory 306016 kb
Host smart-212e1754-9ecc-4781-b477-afaa61aeeb53
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3167730085 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.alert_handler_stress_all_with_rand_reset.3167730085
Directory /workspace/13.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.469180814
Short name T107
Test name
Test status
Simulation time 1185548104873 ps
CPU time 3406.25 seconds
Started Aug 10 04:39:57 PM PDT 24
Finished Aug 10 05:36:44 PM PDT 24
Peak memory 288884 kb
Host smart-9aed5b90-bfe6-40a5-a61a-86e567e5508c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=469180814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_han
dler_stress_all.469180814
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.2946341845
Short name T8
Test name
Test status
Simulation time 17179472746 ps
CPU time 636.25 seconds
Started Aug 10 04:39:38 PM PDT 24
Finished Aug 10 04:50:15 PM PDT 24
Peak memory 247128 kb
Host smart-53f9a70c-383a-4fab-8ce0-f5fec47c0a82
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2946341845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.2946341845
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.709424244
Short name T162
Test name
Test status
Simulation time 485666742 ps
CPU time 34.61 seconds
Started Aug 10 04:38:41 PM PDT 24
Finished Aug 10 04:39:15 PM PDT 24
Peak memory 240508 kb
Host smart-a5781dc4-79ae-46e5-9762-e37ec002f546
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=709424244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.709424244
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.1132295923
Short name T271
Test name
Test status
Simulation time 715568324118 ps
CPU time 2525.57 seconds
Started Aug 10 04:39:11 PM PDT 24
Finished Aug 10 05:21:17 PM PDT 24
Peak memory 284116 kb
Host smart-be6dbb84-d796-455a-ae7f-350ee2683593
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1132295923 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.1132295923
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.4200061184
Short name T165
Test name
Test status
Simulation time 10358953 ps
CPU time 1.34 seconds
Started Aug 10 04:38:30 PM PDT 24
Finished Aug 10 04:38:31 PM PDT 24
Peak memory 237596 kb
Host smart-72677405-cfb4-4adb-a3b9-e900ba4cc6d4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4200061184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.4200061184
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.657875921
Short name T133
Test name
Test status
Simulation time 17357391024 ps
CPU time 295.44 seconds
Started Aug 10 04:38:37 PM PDT 24
Finished Aug 10 04:43:32 PM PDT 24
Peak memory 265480 kb
Host smart-c8ce2760-f9af-4e82-8ebf-4b9345ced2d2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=657875921 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_error
s.657875921
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.2334232443
Short name T4
Test name
Test status
Simulation time 23350918258 ps
CPU time 1308.6 seconds
Started Aug 10 04:40:05 PM PDT 24
Finished Aug 10 05:01:54 PM PDT 24
Peak memory 289104 kb
Host smart-f70e33e1-3be9-4745-a9a7-ae01215dcdb0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2334232443 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_ha
ndler_stress_all.2334232443
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.2815318557
Short name T148
Test name
Test status
Simulation time 25028526398 ps
CPU time 749.44 seconds
Started Aug 10 04:38:52 PM PDT 24
Finished Aug 10 04:51:22 PM PDT 24
Peak memory 265492 kb
Host smart-812312a4-280a-49a6-a8f8-65ee21bc5082
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2815318557 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.2815318557
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.1702164887
Short name T70
Test name
Test status
Simulation time 46148298165 ps
CPU time 2734.97 seconds
Started Aug 10 04:40:11 PM PDT 24
Finished Aug 10 05:25:47 PM PDT 24
Peak memory 288468 kb
Host smart-8475880a-cf0b-4879-be85-1efa963a4e77
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1702164887 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.1702164887
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.1778306608
Short name T61
Test name
Test status
Simulation time 27264826146 ps
CPU time 545.61 seconds
Started Aug 10 04:39:57 PM PDT 24
Finished Aug 10 04:49:03 PM PDT 24
Peak memory 248240 kb
Host smart-a4cb3048-e7b1-40f5-86ea-d68bdb497c4d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1778306608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.1778306608
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.2721173698
Short name T155
Test name
Test status
Simulation time 33372068839 ps
CPU time 210.05 seconds
Started Aug 10 04:38:36 PM PDT 24
Finished Aug 10 04:42:06 PM PDT 24
Peak memory 265468 kb
Host smart-f923e00f-9019-4e94-8812-797582a29d7a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2721173698 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_err
ors.2721173698
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.3742767393
Short name T311
Test name
Test status
Simulation time 22112054131 ps
CPU time 562.53 seconds
Started Aug 10 04:39:31 PM PDT 24
Finished Aug 10 04:48:54 PM PDT 24
Peak memory 248068 kb
Host smart-0e4a2ed4-c93b-459c-ae1c-93dd86342e53
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742767393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.3742767393
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.307311428
Short name T7
Test name
Test status
Simulation time 87760003544 ps
CPU time 1300.91 seconds
Started Aug 10 04:40:31 PM PDT 24
Finished Aug 10 05:02:12 PM PDT 24
Peak memory 272108 kb
Host smart-8a90846f-f485-4f71-b1b6-d25a8b867f6e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=307311428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.307311428
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.3175576331
Short name T609
Test name
Test status
Simulation time 69676253208 ps
CPU time 2011.39 seconds
Started Aug 10 04:39:25 PM PDT 24
Finished Aug 10 05:12:57 PM PDT 24
Peak memory 272280 kb
Host smart-3065baef-9fd4-4b45-9664-c5f1feb67a38
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175576331 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.3175576331
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.1967007137
Short name T54
Test name
Test status
Simulation time 17784698121 ps
CPU time 1713.15 seconds
Started Aug 10 04:38:48 PM PDT 24
Finished Aug 10 05:07:21 PM PDT 24
Peak memory 298760 kb
Host smart-c112a7db-3ff3-4d74-be69-1e88559aa79b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1967007137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_han
dler_stress_all.1967007137
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.829509435
Short name T135
Test name
Test status
Simulation time 15563346643 ps
CPU time 288.99 seconds
Started Aug 10 04:38:48 PM PDT 24
Finished Aug 10 04:43:37 PM PDT 24
Peak memory 273620 kb
Host smart-28e820d5-fe3e-4c7d-acc0-68b2d4f421e5
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=829509435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_erro
rs.829509435
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.1830059249
Short name T118
Test name
Test status
Simulation time 171791552742 ps
CPU time 2392.48 seconds
Started Aug 10 04:39:37 PM PDT 24
Finished Aug 10 05:19:30 PM PDT 24
Peak memory 288812 kb
Host smart-bb691d5f-0f38-4914-ad75-a417d301c900
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1830059249 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_ha
ndler_stress_all.1830059249
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.4100160227
Short name T301
Test name
Test status
Simulation time 189103810653 ps
CPU time 2304.19 seconds
Started Aug 10 04:39:37 PM PDT 24
Finished Aug 10 05:18:02 PM PDT 24
Peak memory 272672 kb
Host smart-026adaf9-55c3-473d-909f-b8c8528feabe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4100160227 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.4100160227
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.4062537956
Short name T350
Test name
Test status
Simulation time 19702148 ps
CPU time 1.41 seconds
Started Aug 10 04:38:40 PM PDT 24
Finished Aug 10 04:38:41 PM PDT 24
Peak memory 237608 kb
Host smart-56a9b793-08c2-4348-b6f5-ff9e2edf99ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4062537956 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.4062537956
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.707751194
Short name T304
Test name
Test status
Simulation time 48651072522 ps
CPU time 467.06 seconds
Started Aug 10 04:38:48 PM PDT 24
Finished Aug 10 04:46:35 PM PDT 24
Peak memory 248296 kb
Host smart-a3e6dc1f-7531-4491-9300-da9919d4279d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=707751194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.707751194
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.1730343024
Short name T71
Test name
Test status
Simulation time 232187735 ps
CPU time 26.84 seconds
Started Aug 10 04:39:23 PM PDT 24
Finished Aug 10 04:39:49 PM PDT 24
Peak memory 247708 kb
Host smart-381920e2-bb1b-4d40-8d51-622071f77c17
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17303
43024 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.1730343024
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.3380659899
Short name T33
Test name
Test status
Simulation time 22650471455 ps
CPU time 1928 seconds
Started Aug 10 04:39:48 PM PDT 24
Finished Aug 10 05:11:56 PM PDT 24
Peak memory 301048 kb
Host smart-933e9505-6f7d-44b1-9968-3ba0d859a40f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3380659899 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_ha
ndler_stress_all.3380659899
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.1409756770
Short name T175
Test name
Test status
Simulation time 168262788 ps
CPU time 3.78 seconds
Started Aug 10 04:38:32 PM PDT 24
Finished Aug 10 04:38:36 PM PDT 24
Peak memory 238712 kb
Host smart-e66a38fa-3eab-4f12-a60c-9ddefc746824
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1409756770 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.1409756770
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.400945078
Short name T126
Test name
Test status
Simulation time 9238727942 ps
CPU time 305.02 seconds
Started Aug 10 04:38:42 PM PDT 24
Finished Aug 10 04:43:47 PM PDT 24
Peak memory 265492 kb
Host smart-b747aabe-41f0-4abe-80b0-6448d7d4036a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=400945078 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_erro
rs.400945078
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.4268677675
Short name T241
Test name
Test status
Simulation time 154850311350 ps
CPU time 2387.29 seconds
Started Aug 10 04:39:48 PM PDT 24
Finished Aug 10 05:19:36 PM PDT 24
Peak memory 286652 kb
Host smart-b50acbe8-768b-408c-b9ce-f8649f92e2b9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4268677675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.4268677675
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.4069634344
Short name T240
Test name
Test status
Simulation time 27589005307 ps
CPU time 1812.13 seconds
Started Aug 10 04:40:38 PM PDT 24
Finished Aug 10 05:10:51 PM PDT 24
Peak memory 272764 kb
Host smart-b4955d4c-7717-43f8-9ab6-0c850151904c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4069634344 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.4069634344
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.2686194140
Short name T143
Test name
Test status
Simulation time 12727473624 ps
CPU time 517.97 seconds
Started Aug 10 04:38:34 PM PDT 24
Finished Aug 10 04:47:12 PM PDT 24
Peak memory 265512 kb
Host smart-05f640fe-130f-4463-a543-695053887119
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2686194140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.2686194140
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.3812349121
Short name T141
Test name
Test status
Simulation time 9258417354 ps
CPU time 366.03 seconds
Started Aug 10 04:38:45 PM PDT 24
Finished Aug 10 04:44:51 PM PDT 24
Peak memory 265512 kb
Host smart-2c54c949-6344-45ef-919e-4ed77193a1b0
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3812349121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.3812349121
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.1708041501
Short name T25
Test name
Test status
Simulation time 74655830706 ps
CPU time 4616.13 seconds
Started Aug 10 04:40:06 PM PDT 24
Finished Aug 10 05:57:03 PM PDT 24
Peak memory 304616 kb
Host smart-c16931a9-9f8d-483a-a1dd-84c3d09a4ec2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1708041501 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_ha
ndler_stress_all.1708041501
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.3659527349
Short name T309
Test name
Test status
Simulation time 18818494741 ps
CPU time 233.84 seconds
Started Aug 10 04:39:08 PM PDT 24
Finished Aug 10 04:43:02 PM PDT 24
Peak memory 247140 kb
Host smart-99758eed-3cb9-4071-9c65-83768ee9e94d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659527349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.3659527349
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.3242490694
Short name T265
Test name
Test status
Simulation time 332766269 ps
CPU time 41.54 seconds
Started Aug 10 04:39:09 PM PDT 24
Finished Aug 10 04:39:51 PM PDT 24
Peak memory 248204 kb
Host smart-474bff76-129c-4d03-89fc-204d9bcce579
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32424
90694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.3242490694
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all_with_rand_reset.237738020
Short name T293
Test name
Test status
Simulation time 36051934699 ps
CPU time 2024.4 seconds
Started Aug 10 04:39:23 PM PDT 24
Finished Aug 10 05:13:08 PM PDT 24
Peak memory 283588 kb
Host smart-da3c616e-0f86-472f-a060-4b1ec33b1ab9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=237738020 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 17.alert_handler_stress_all_with_rand_reset.237738020
Directory /workspace/17.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.2631745033
Short name T325
Test name
Test status
Simulation time 13357007995 ps
CPU time 136.14 seconds
Started Aug 10 04:39:24 PM PDT 24
Finished Aug 10 04:41:40 PM PDT 24
Peak memory 247996 kb
Host smart-eda9445e-70ca-441a-9077-7458e9d20cef
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2631745033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.2631745033
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.2079741032
Short name T292
Test name
Test status
Simulation time 419630576 ps
CPU time 27.7 seconds
Started Aug 10 04:39:40 PM PDT 24
Finished Aug 10 04:40:08 PM PDT 24
Peak memory 248312 kb
Host smart-10fa57dc-ea2d-4b16-97c6-cc0a4cd44a4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20797
41032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.2079741032
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all_with_rand_reset.3718104487
Short name T102
Test name
Test status
Simulation time 19769795959 ps
CPU time 1319.79 seconds
Started Aug 10 04:40:00 PM PDT 24
Finished Aug 10 05:02:01 PM PDT 24
Peak memory 273000 kb
Host smart-a059e881-37d3-4737-ad6e-c5fa6b4fdf23
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3718104487 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.alert_handler_stress_all_with_rand_reset.3718104487
Directory /workspace/39.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all_with_rand_reset.1916384678
Short name T27
Test name
Test status
Simulation time 33164431392 ps
CPU time 1765.16 seconds
Started Aug 10 04:39:34 PM PDT 24
Finished Aug 10 05:09:00 PM PDT 24
Peak memory 296984 kb
Host smart-e514456a-5ac3-45a7-9c0a-be240f5694fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916384678 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.alert_handler_stress_all_with_rand_reset.1916384678
Directory /workspace/25.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.1791997136
Short name T147
Test name
Test status
Simulation time 15254788585 ps
CPU time 1059.03 seconds
Started Aug 10 04:38:56 PM PDT 24
Finished Aug 10 04:56:35 PM PDT 24
Peak memory 265616 kb
Host smart-bd19bb1e-0e65-4b09-8daa-329b4dc66504
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1791997136 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.1791997136
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.2313654962
Short name T207
Test name
Test status
Simulation time 112351212 ps
CPU time 3.05 seconds
Started Aug 10 04:38:46 PM PDT 24
Finished Aug 10 04:38:49 PM PDT 24
Peak memory 248480 kb
Host smart-c4348b4e-be87-498e-be01-7f6778ea5efb
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2313654962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.2313654962
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.2331359032
Short name T212
Test name
Test status
Simulation time 80080103 ps
CPU time 3.53 seconds
Started Aug 10 04:38:51 PM PDT 24
Finished Aug 10 04:38:55 PM PDT 24
Peak memory 248456 kb
Host smart-8ebc893e-21fe-4c60-91b6-b2337b4a54e2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2331359032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.2331359032
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.37642902
Short name T208
Test name
Test status
Simulation time 156139953 ps
CPU time 3.82 seconds
Started Aug 10 04:39:23 PM PDT 24
Finished Aug 10 04:39:27 PM PDT 24
Peak memory 248436 kb
Host smart-58f0756e-e699-4d37-a653-a5e9d8352f62
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=37642902 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.37642902
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.3160255732
Short name T205
Test name
Test status
Simulation time 43261997 ps
CPU time 3.45 seconds
Started Aug 10 04:39:17 PM PDT 24
Finished Aug 10 04:39:21 PM PDT 24
Peak memory 248476 kb
Host smart-68aa175d-ab68-4bf9-8805-f0938bd81e50
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3160255732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.3160255732
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.1467171500
Short name T289
Test name
Test status
Simulation time 20685632001 ps
CPU time 1733.38 seconds
Started Aug 10 04:38:49 PM PDT 24
Finished Aug 10 05:07:43 PM PDT 24
Peak memory 288240 kb
Host smart-f3b92755-289d-4c08-9cca-fe0ef407ce40
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1467171500 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_han
dler_stress_all.1467171500
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.3936660772
Short name T343
Test name
Test status
Simulation time 164648982123 ps
CPU time 2038.22 seconds
Started Aug 10 04:38:52 PM PDT 24
Finished Aug 10 05:12:51 PM PDT 24
Peak memory 272520 kb
Host smart-42a519c7-8713-4d18-9111-179cd3c38c86
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3936660772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.3936660772
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.1607250657
Short name T332
Test name
Test status
Simulation time 21865634920 ps
CPU time 236.49 seconds
Started Aug 10 04:39:29 PM PDT 24
Finished Aug 10 04:43:25 PM PDT 24
Peak memory 253996 kb
Host smart-73f67513-f0f4-49d1-8ea4-ed259039a631
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1607250657 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.1607250657
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.2390161853
Short name T307
Test name
Test status
Simulation time 10221841932 ps
CPU time 417.71 seconds
Started Aug 10 04:39:24 PM PDT 24
Finished Aug 10 04:46:22 PM PDT 24
Peak memory 254588 kb
Host smart-063d4180-fdb4-4230-a6ad-4df89a9db70d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390161853 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.2390161853
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.2825704495
Short name T285
Test name
Test status
Simulation time 983635480 ps
CPU time 14.91 seconds
Started Aug 10 04:39:51 PM PDT 24
Finished Aug 10 04:40:06 PM PDT 24
Peak memory 248164 kb
Host smart-1f6a4e7f-1081-4a2f-8f4b-34ae88afb8a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28257
04495 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.2825704495
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all_with_rand_reset.1508213708
Short name T89
Test name
Test status
Simulation time 40415415382 ps
CPU time 2095.07 seconds
Started Aug 10 04:39:50 PM PDT 24
Finished Aug 10 05:14:46 PM PDT 24
Peak memory 289212 kb
Host smart-cf83f835-c218-42bc-95eb-42fc317b19bc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1508213708 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.alert_handler_stress_all_with_rand_reset.1508213708
Directory /workspace/35.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.1019502725
Short name T42
Test name
Test status
Simulation time 304140286 ps
CPU time 22.21 seconds
Started Aug 10 04:39:11 PM PDT 24
Finished Aug 10 04:39:33 PM PDT 24
Peak memory 255860 kb
Host smart-6c98a45a-b76d-414f-96db-e9b6c5053e24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10195
02725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.1019502725
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all_with_rand_reset.4206691861
Short name T80
Test name
Test status
Simulation time 111991395194 ps
CPU time 10374 seconds
Started Aug 10 04:39:37 PM PDT 24
Finished Aug 10 07:32:32 PM PDT 24
Peak memory 411720 kb
Host smart-fe5949c1-0005-4127-860f-38ed8eb676a9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206691861 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.alert_handler_stress_all_with_rand_reset.4206691861
Directory /workspace/30.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.3625407122
Short name T163
Test name
Test status
Simulation time 4294150267 ps
CPU time 42.33 seconds
Started Aug 10 04:38:50 PM PDT 24
Finished Aug 10 04:39:33 PM PDT 24
Peak memory 238108 kb
Host smart-45da8f99-1629-4703-893d-0411f706e778
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3625407122 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.3625407122
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.4045189094
Short name T355
Test name
Test status
Simulation time 4654704755 ps
CPU time 623.65 seconds
Started Aug 10 04:38:30 PM PDT 24
Finished Aug 10 04:48:54 PM PDT 24
Peak memory 265716 kb
Host smart-b919cf87-7033-4491-ad21-ab21fd409dc0
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4045189094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.4045189094
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.3087082158
Short name T733
Test name
Test status
Simulation time 10134236 ps
CPU time 1.33 seconds
Started Aug 10 04:38:27 PM PDT 24
Finished Aug 10 04:38:28 PM PDT 24
Peak memory 235636 kb
Host smart-35c78cb4-a420-4933-9b95-d3dc6e52315d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3087082158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.3087082158
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.3135598005
Short name T354
Test name
Test status
Simulation time 29038127896 ps
CPU time 641.02 seconds
Started Aug 10 04:38:37 PM PDT 24
Finished Aug 10 04:49:18 PM PDT 24
Peak memory 265596 kb
Host smart-836ec028-3290-4429-98c1-d39a4cf03f0a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3135598005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.3135598005
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.1196151261
Short name T18
Test name
Test status
Simulation time 14764004944 ps
CPU time 989.21 seconds
Started Aug 10 04:38:50 PM PDT 24
Finished Aug 10 04:55:20 PM PDT 24
Peak memory 272268 kb
Host smart-7cc64934-2b79-40ab-8915-db2b5c63a787
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1196151261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.1196151261
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.24841130
Short name T485
Test name
Test status
Simulation time 57157828981 ps
CPU time 481.11 seconds
Started Aug 10 04:39:08 PM PDT 24
Finished Aug 10 04:47:09 PM PDT 24
Peak memory 248236 kb
Host smart-46235edd-41b3-4fd4-aa68-7048475ee877
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=24841130 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.24841130
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.226142021
Short name T323
Test name
Test status
Simulation time 3298445117 ps
CPU time 141.46 seconds
Started Aug 10 04:39:09 PM PDT 24
Finished Aug 10 04:41:31 PM PDT 24
Peak memory 248212 kb
Host smart-06d83ff8-3c27-4a7a-a1d1-6fc80a9886ed
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=226142021 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.226142021
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.3316036220
Short name T94
Test name
Test status
Simulation time 3114357228 ps
CPU time 108.79 seconds
Started Aug 10 04:39:16 PM PDT 24
Finished Aug 10 04:41:05 PM PDT 24
Peak memory 256504 kb
Host smart-fbec7897-c681-41c0-8b2a-09b552e94b2a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3316036220 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_ha
ndler_stress_all.3316036220
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.2669819858
Short name T268
Test name
Test status
Simulation time 815112155 ps
CPU time 15.51 seconds
Started Aug 10 04:39:00 PM PDT 24
Finished Aug 10 04:39:16 PM PDT 24
Peak memory 248224 kb
Host smart-668dfa9f-52f2-44a1-89e8-32d970bf365b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26698
19858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.2669819858
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.461085684
Short name T62
Test name
Test status
Simulation time 37635344418 ps
CPU time 2582.92 seconds
Started Aug 10 04:38:47 PM PDT 24
Finished Aug 10 05:21:51 PM PDT 24
Peak memory 288268 kb
Host smart-06f2e2b2-4190-4cdd-8dcf-a0dd232e984a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=461085684 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.461085684
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.3470317361
Short name T296
Test name
Test status
Simulation time 3290627393 ps
CPU time 53.8 seconds
Started Aug 10 04:39:39 PM PDT 24
Finished Aug 10 04:40:33 PM PDT 24
Peak memory 248180 kb
Host smart-142f84c8-39e8-431e-b967-c45e1d162e05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34703
17361 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.3470317361
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.4159314741
Short name T283
Test name
Test status
Simulation time 331372673 ps
CPU time 23.37 seconds
Started Aug 10 04:39:56 PM PDT 24
Finished Aug 10 04:40:20 PM PDT 24
Peak memory 255640 kb
Host smart-e8745922-73f9-4eda-ab98-02b99220acc8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41593
14741 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.4159314741
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.4225520807
Short name T290
Test name
Test status
Simulation time 233587760 ps
CPU time 4.04 seconds
Started Aug 10 04:38:50 PM PDT 24
Finished Aug 10 04:38:54 PM PDT 24
Peak memory 239376 kb
Host smart-da59e024-3fcc-483e-8960-629ae7cdb0a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42255
20807 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.4225520807
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.2786500704
Short name T287
Test name
Test status
Simulation time 1393036254 ps
CPU time 23.63 seconds
Started Aug 10 04:40:14 PM PDT 24
Finished Aug 10 04:40:38 PM PDT 24
Peak memory 248700 kb
Host smart-437036ce-6d08-4ed9-b642-fbf65882d886
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27865
00704 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.2786500704
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.2677912499
Short name T99
Test name
Test status
Simulation time 2543688564 ps
CPU time 43.72 seconds
Started Aug 10 04:40:23 PM PDT 24
Finished Aug 10 04:41:07 PM PDT 24
Peak memory 256168 kb
Host smart-236d4187-2a2d-47f0-86d8-c455ad2bb00a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26779
12499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.2677912499
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.1037321531
Short name T10
Test name
Test status
Simulation time 247714130 ps
CPU time 16.02 seconds
Started Aug 10 04:38:58 PM PDT 24
Finished Aug 10 04:39:14 PM PDT 24
Peak memory 270288 kb
Host smart-6edeae95-db80-43ef-8429-ef3ce194dc73
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1037321531 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.1037321531
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.3659855156
Short name T172
Test name
Test status
Simulation time 14736366551 ps
CPU time 82.49 seconds
Started Aug 10 04:38:51 PM PDT 24
Finished Aug 10 04:40:18 PM PDT 24
Peak memory 238696 kb
Host smart-aff73aaf-9596-4f6b-bd0e-d8ab764ef3f0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3659855156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.3659855156
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.2455931056
Short name T171
Test name
Test status
Simulation time 215686645 ps
CPU time 4.32 seconds
Started Aug 10 04:38:36 PM PDT 24
Finished Aug 10 04:38:41 PM PDT 24
Peak memory 237884 kb
Host smart-628aaa31-6ad6-432c-b713-8b5c6bdfadcd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2455931056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.2455931056
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.2224739113
Short name T174
Test name
Test status
Simulation time 89868378 ps
CPU time 5.39 seconds
Started Aug 10 04:38:51 PM PDT 24
Finished Aug 10 04:38:56 PM PDT 24
Peak memory 237528 kb
Host smart-34bb4e94-927d-446d-90c2-7729f7bb93ec
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2224739113 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.2224739113
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.1338058039
Short name T169
Test name
Test status
Simulation time 475339391 ps
CPU time 2.61 seconds
Started Aug 10 04:38:19 PM PDT 24
Finished Aug 10 04:38:22 PM PDT 24
Peak memory 237632 kb
Host smart-f63bb2a2-3f4d-4634-9a63-6f8c4e5bcc4a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1338058039 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.1338058039
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.2872122015
Short name T170
Test name
Test status
Simulation time 3466017212 ps
CPU time 45.02 seconds
Started Aug 10 04:38:29 PM PDT 24
Finished Aug 10 04:39:14 PM PDT 24
Peak memory 240664 kb
Host smart-c6afcf65-3b63-4fb8-b25d-250c8df492eb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2872122015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.2872122015
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.103462688
Short name T178
Test name
Test status
Simulation time 5678297412 ps
CPU time 91.37 seconds
Started Aug 10 04:38:24 PM PDT 24
Finished Aug 10 04:39:56 PM PDT 24
Peak memory 240628 kb
Host smart-afd18d59-7cb2-4150-b863-973f3e43efca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=103462688 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.103462688
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.2292774067
Short name T177
Test name
Test status
Simulation time 193319890 ps
CPU time 4.64 seconds
Started Aug 10 04:38:41 PM PDT 24
Finished Aug 10 04:38:45 PM PDT 24
Peak memory 238616 kb
Host smart-9f563b92-b4f4-4019-8c3a-f41a503c2cb8
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2292774067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.2292774067
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.2256725784
Short name T173
Test name
Test status
Simulation time 723554091 ps
CPU time 34.09 seconds
Started Aug 10 04:38:08 PM PDT 24
Finished Aug 10 04:38:42 PM PDT 24
Peak memory 240504 kb
Host smart-de7664f9-a5a2-4f4d-bb6b-c410d0ed67c7
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2256725784 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.2256725784
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.112634532
Short name T168
Test name
Test status
Simulation time 11369946298 ps
CPU time 89.54 seconds
Started Aug 10 04:38:08 PM PDT 24
Finished Aug 10 04:39:38 PM PDT 24
Peak memory 238824 kb
Host smart-af2f4a86-2a78-4748-8c19-aec6e927866e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=112634532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.112634532
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.1922712033
Short name T179
Test name
Test status
Simulation time 960691685 ps
CPU time 42.71 seconds
Started Aug 10 04:38:42 PM PDT 24
Finished Aug 10 04:39:24 PM PDT 24
Peak memory 240416 kb
Host smart-ffe68983-a4b5-4224-93ba-296523eb25c9
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1922712033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.1922712033
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.3093564990
Short name T180
Test name
Test status
Simulation time 96676985 ps
CPU time 2.38 seconds
Started Aug 10 04:38:46 PM PDT 24
Finished Aug 10 04:38:48 PM PDT 24
Peak memory 236664 kb
Host smart-10d9b342-feb8-46f0-ac2a-b4b2558fbfef
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3093564990 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.3093564990
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.4154697178
Short name T24
Test name
Test status
Simulation time 18044261848 ps
CPU time 894.88 seconds
Started Aug 10 04:39:38 PM PDT 24
Finished Aug 10 04:54:33 PM PDT 24
Peak memory 282528 kb
Host smart-6de0dd3f-717e-4795-bed7-a59029a0a3c2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4154697178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.4154697178
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.2614587761
Short name T793
Test name
Test status
Simulation time 552289893 ps
CPU time 89 seconds
Started Aug 10 04:38:30 PM PDT 24
Finished Aug 10 04:39:59 PM PDT 24
Peak memory 237584 kb
Host smart-b7e330ba-5531-442c-9680-ee1858affbeb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2614587761 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.2614587761
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.1138936030
Short name T722
Test name
Test status
Simulation time 5813428729 ps
CPU time 425.98 seconds
Started Aug 10 04:38:39 PM PDT 24
Finished Aug 10 04:45:45 PM PDT 24
Peak memory 237704 kb
Host smart-73615947-061c-457f-a565-a650bc77bc35
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1138936030 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.1138936030
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.1719736592
Short name T737
Test name
Test status
Simulation time 182563644 ps
CPU time 7.17 seconds
Started Aug 10 04:38:27 PM PDT 24
Finished Aug 10 04:38:34 PM PDT 24
Peak memory 248688 kb
Host smart-26844aa4-0186-46e5-b4cc-78ef5af70bc0
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1719736592 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.1719736592
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.542086398
Short name T720
Test name
Test status
Simulation time 251021727 ps
CPU time 10.8 seconds
Started Aug 10 04:38:22 PM PDT 24
Finished Aug 10 04:38:33 PM PDT 24
Peak memory 243652 kb
Host smart-c4bc9d40-6207-4ba5-b659-8d400df6a74f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542086398 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 0.alert_handler_csr_mem_rw_with_rand_reset.542086398
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.4007533927
Short name T752
Test name
Test status
Simulation time 208611008 ps
CPU time 8.01 seconds
Started Aug 10 04:38:35 PM PDT 24
Finished Aug 10 04:38:43 PM PDT 24
Peak memory 240480 kb
Host smart-fd75b9d0-2a8b-430c-9747-a65d0ddc8e58
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4007533927 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.4007533927
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.876189762
Short name T792
Test name
Test status
Simulation time 8535753 ps
CPU time 1.34 seconds
Started Aug 10 04:38:35 PM PDT 24
Finished Aug 10 04:38:37 PM PDT 24
Peak memory 237560 kb
Host smart-3089e0a0-c17e-4776-9bae-d8b30c121588
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=876189762 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.876189762
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.1880749422
Short name T782
Test name
Test status
Simulation time 598122604 ps
CPU time 22.41 seconds
Started Aug 10 04:38:27 PM PDT 24
Finished Aug 10 04:38:50 PM PDT 24
Peak memory 245736 kb
Host smart-938df663-62c2-4a80-81b2-768bea42ca63
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1880749422 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_out
standing.1880749422
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.1436690849
Short name T139
Test name
Test status
Simulation time 2250930956 ps
CPU time 153.21 seconds
Started Aug 10 04:38:28 PM PDT 24
Finished Aug 10 04:41:02 PM PDT 24
Peak memory 265528 kb
Host smart-c533bd07-35f9-49b0-ad30-19d7e9f5af67
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1436690849 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_erro
rs.1436690849
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.1980003770
Short name T807
Test name
Test status
Simulation time 554613017 ps
CPU time 9.28 seconds
Started Aug 10 04:38:15 PM PDT 24
Finished Aug 10 04:38:24 PM PDT 24
Peak memory 252504 kb
Host smart-e8ea4c56-3470-42a3-8e00-8ade1c85360a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1980003770 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.1980003770
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.2211379254
Short name T816
Test name
Test status
Simulation time 3247102092 ps
CPU time 234.34 seconds
Started Aug 10 04:38:45 PM PDT 24
Finished Aug 10 04:42:39 PM PDT 24
Peak memory 240556 kb
Host smart-068c6dc4-2d4b-42df-8b2a-1678ce2559f2
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2211379254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.2211379254
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.3535608176
Short name T767
Test name
Test status
Simulation time 3334861445 ps
CPU time 220.88 seconds
Started Aug 10 04:38:19 PM PDT 24
Finished Aug 10 04:42:00 PM PDT 24
Peak memory 237608 kb
Host smart-63f8ca44-d8a8-4a88-abfd-424f71850449
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3535608176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.3535608176
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.1994381429
Short name T167
Test name
Test status
Simulation time 215562786 ps
CPU time 9.68 seconds
Started Aug 10 04:38:27 PM PDT 24
Finished Aug 10 04:38:36 PM PDT 24
Peak memory 249064 kb
Host smart-0abaac49-40aa-4f2e-b101-e2b6074bf023
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1994381429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.1994381429
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.1257817071
Short name T775
Test name
Test status
Simulation time 143005129 ps
CPU time 10.03 seconds
Started Aug 10 04:38:21 PM PDT 24
Finished Aug 10 04:38:31 PM PDT 24
Peak memory 238236 kb
Host smart-1b1dc0ab-fd75-4e13-907a-a735787b4a89
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1257817071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 1.alert_handler_csr_mem_rw_with_rand_reset.1257817071
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.2358220549
Short name T181
Test name
Test status
Simulation time 51177016 ps
CPU time 5.33 seconds
Started Aug 10 04:38:27 PM PDT 24
Finished Aug 10 04:38:32 PM PDT 24
Peak memory 237536 kb
Host smart-58367d3f-ac34-4a3c-8f38-67e77ec02026
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2358220549 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.2358220549
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.300899384
Short name T258
Test name
Test status
Simulation time 4476002455 ps
CPU time 47.17 seconds
Started Aug 10 04:38:28 PM PDT 24
Finished Aug 10 04:39:15 PM PDT 24
Peak memory 245912 kb
Host smart-b431a8f9-661c-4c9e-8164-99d565286a2b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=300899384 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_outs
tanding.300899384
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.3012483512
Short name T130
Test name
Test status
Simulation time 1499435555 ps
CPU time 183.22 seconds
Started Aug 10 04:38:37 PM PDT 24
Finished Aug 10 04:41:40 PM PDT 24
Peak memory 272700 kb
Host smart-3a80c506-144b-45fb-bd8d-828f9d50cebf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3012483512 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_erro
rs.3012483512
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.4158713978
Short name T713
Test name
Test status
Simulation time 41402709 ps
CPU time 6.03 seconds
Started Aug 10 04:38:42 PM PDT 24
Finished Aug 10 04:38:48 PM PDT 24
Peak memory 248844 kb
Host smart-3c1d3b75-2520-4828-a027-d7c0b817b8e8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4158713978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.4158713978
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.2461019311
Short name T808
Test name
Test status
Simulation time 30949722 ps
CPU time 4.54 seconds
Started Aug 10 04:38:52 PM PDT 24
Finished Aug 10 04:38:57 PM PDT 24
Peak memory 240068 kb
Host smart-704243ed-3b10-46ec-ab88-1737c96699a2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2461019311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 10.alert_handler_csr_mem_rw_with_rand_reset.2461019311
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.2923342991
Short name T718
Test name
Test status
Simulation time 794087474 ps
CPU time 8.08 seconds
Started Aug 10 04:38:39 PM PDT 24
Finished Aug 10 04:38:47 PM PDT 24
Peak memory 237408 kb
Host smart-3420e609-1e0b-40c8-872a-cbc90e268c79
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2923342991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.2923342991
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.1074764818
Short name T723
Test name
Test status
Simulation time 20339028 ps
CPU time 1.56 seconds
Started Aug 10 04:38:41 PM PDT 24
Finished Aug 10 04:38:43 PM PDT 24
Peak memory 237588 kb
Host smart-714902e6-fb2e-46d9-ab3a-cf6c12b025c0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1074764818 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.1074764818
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.1236052215
Short name T787
Test name
Test status
Simulation time 702749145 ps
CPU time 25.12 seconds
Started Aug 10 04:38:41 PM PDT 24
Finished Aug 10 04:39:07 PM PDT 24
Peak memory 240484 kb
Host smart-9b28feec-a2c7-4530-b702-15e7cc288ef6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1236052215 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_ou
tstanding.1236052215
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.547204044
Short name T158
Test name
Test status
Simulation time 1156412366 ps
CPU time 120.53 seconds
Started Aug 10 04:38:38 PM PDT 24
Finished Aug 10 04:40:39 PM PDT 24
Peak memory 269568 kb
Host smart-2172f0e2-008f-48f6-b5fc-eae18dc98b17
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=547204044 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_erro
rs.547204044
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.1786923625
Short name T827
Test name
Test status
Simulation time 80157361 ps
CPU time 3.53 seconds
Started Aug 10 04:38:43 PM PDT 24
Finished Aug 10 04:38:47 PM PDT 24
Peak memory 248736 kb
Host smart-ea90ea6d-9e57-4e4d-ba00-a6d1af44d6e3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1786923625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.1786923625
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.2014126976
Short name T259
Test name
Test status
Simulation time 257574297 ps
CPU time 5.5 seconds
Started Aug 10 04:38:43 PM PDT 24
Finished Aug 10 04:38:49 PM PDT 24
Peak memory 252504 kb
Host smart-674ab01c-1b5f-4bb9-8097-676e50c79e63
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2014126976 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.alert_handler_csr_mem_rw_with_rand_reset.2014126976
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.1288740400
Short name T196
Test name
Test status
Simulation time 124505533 ps
CPU time 6.16 seconds
Started Aug 10 04:38:39 PM PDT 24
Finished Aug 10 04:38:46 PM PDT 24
Peak memory 237592 kb
Host smart-740a8e9c-9617-4b06-b891-a9f18b4b305f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1288740400 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.1288740400
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.2637074413
Short name T734
Test name
Test status
Simulation time 6817926 ps
CPU time 1.43 seconds
Started Aug 10 04:38:51 PM PDT 24
Finished Aug 10 04:38:53 PM PDT 24
Peak memory 237524 kb
Host smart-78034c93-279f-4ddc-86cc-ccf9b5644e59
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2637074413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.2637074413
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.127633242
Short name T192
Test name
Test status
Simulation time 182039771 ps
CPU time 23.4 seconds
Started Aug 10 04:38:38 PM PDT 24
Finished Aug 10 04:39:02 PM PDT 24
Peak memory 248660 kb
Host smart-964ef5dd-e8bc-4445-84c8-fdbc60c286f9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=127633242 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_out
standing.127633242
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.600494787
Short name T759
Test name
Test status
Simulation time 258783932 ps
CPU time 19.37 seconds
Started Aug 10 04:38:48 PM PDT 24
Finished Aug 10 04:39:07 PM PDT 24
Peak memory 248800 kb
Host smart-2b00e760-ea72-4bd5-94fa-3e4a006516bf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=600494787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.600494787
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.1478356415
Short name T300
Test name
Test status
Simulation time 652774427 ps
CPU time 37.65 seconds
Started Aug 10 04:38:33 PM PDT 24
Finished Aug 10 04:39:11 PM PDT 24
Peak memory 248648 kb
Host smart-1c7cece9-3c60-4629-a2c5-2af80ab58386
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1478356415 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.1478356415
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.3419404977
Short name T817
Test name
Test status
Simulation time 95807902 ps
CPU time 8.81 seconds
Started Aug 10 04:38:54 PM PDT 24
Finished Aug 10 04:39:03 PM PDT 24
Peak memory 240704 kb
Host smart-315436d0-18c2-41f9-9ab4-8946e9de460b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419404977 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 12.alert_handler_csr_mem_rw_with_rand_reset.3419404977
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.4022762971
Short name T826
Test name
Test status
Simulation time 197386056 ps
CPU time 4.87 seconds
Started Aug 10 04:38:40 PM PDT 24
Finished Aug 10 04:38:45 PM PDT 24
Peak memory 237564 kb
Host smart-2fca4af8-dd38-4715-84d3-ac43ee89be12
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4022762971 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.4022762971
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.4135553520
Short name T741
Test name
Test status
Simulation time 15515624 ps
CPU time 1.4 seconds
Started Aug 10 04:38:48 PM PDT 24
Finished Aug 10 04:38:49 PM PDT 24
Peak memory 237616 kb
Host smart-5775312f-10df-4b1c-85f7-ad880d1587a6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4135553520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.4135553520
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.2634167922
Short name T819
Test name
Test status
Simulation time 364756599 ps
CPU time 11 seconds
Started Aug 10 04:38:42 PM PDT 24
Finished Aug 10 04:38:53 PM PDT 24
Peak memory 245768 kb
Host smart-b3d660e1-e00a-43f7-9a82-20fdd87ae8b1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2634167922 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_ou
tstanding.2634167922
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.3612774051
Short name T160
Test name
Test status
Simulation time 18659303473 ps
CPU time 387.82 seconds
Started Aug 10 04:38:48 PM PDT 24
Finished Aug 10 04:45:16 PM PDT 24
Peak memory 265448 kb
Host smart-287381b3-e197-4774-af88-b10a56d149fd
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3612774051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_err
ors.3612774051
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.1628643062
Short name T142
Test name
Test status
Simulation time 8559788628 ps
CPU time 330.93 seconds
Started Aug 10 04:38:40 PM PDT 24
Finished Aug 10 04:44:11 PM PDT 24
Peak memory 268788 kb
Host smart-25997142-97d1-4d28-a56c-5cf23a83a0c9
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1628643062 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.1628643062
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.94700536
Short name T716
Test name
Test status
Simulation time 561930512 ps
CPU time 9.22 seconds
Started Aug 10 04:38:53 PM PDT 24
Finished Aug 10 04:39:02 PM PDT 24
Peak memory 253792 kb
Host smart-20c0154b-4ca2-4eaf-bd64-4bf0c4d9b974
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=94700536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.94700536
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.3384469079
Short name T786
Test name
Test status
Simulation time 135725737 ps
CPU time 11.5 seconds
Started Aug 10 04:38:52 PM PDT 24
Finished Aug 10 04:39:03 PM PDT 24
Peak memory 256808 kb
Host smart-73f95bff-aa55-4d94-b4f1-a12d7f46072c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3384469079 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 13.alert_handler_csr_mem_rw_with_rand_reset.3384469079
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.867302806
Short name T742
Test name
Test status
Simulation time 32741895 ps
CPU time 5.39 seconds
Started Aug 10 04:38:46 PM PDT 24
Finished Aug 10 04:38:52 PM PDT 24
Peak memory 237548 kb
Host smart-cfa96f79-7970-4e1b-abd7-fa16e31a38ff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=867302806 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.867302806
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.616625525
Short name T727
Test name
Test status
Simulation time 14094545 ps
CPU time 1.34 seconds
Started Aug 10 04:38:40 PM PDT 24
Finished Aug 10 04:38:42 PM PDT 24
Peak memory 237584 kb
Host smart-b0cf6955-89f5-4696-ace2-629ee0bdac46
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=616625525 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.616625525
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.4106981761
Short name T770
Test name
Test status
Simulation time 912000226 ps
CPU time 20.58 seconds
Started Aug 10 04:38:38 PM PDT 24
Finished Aug 10 04:38:59 PM PDT 24
Peak memory 248652 kb
Host smart-6a737f56-bb62-4ecf-94ca-180fbe19e08c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4106981761 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_ou
tstanding.4106981761
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.1336478253
Short name T735
Test name
Test status
Simulation time 198361091 ps
CPU time 7.9 seconds
Started Aug 10 04:38:48 PM PDT 24
Finished Aug 10 04:38:56 PM PDT 24
Peak memory 253888 kb
Host smart-b0a1b5ee-a4be-4a2b-818e-fa48feffb948
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1336478253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.1336478253
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.3428705459
Short name T198
Test name
Test status
Simulation time 49402335 ps
CPU time 2.58 seconds
Started Aug 10 04:38:37 PM PDT 24
Finished Aug 10 04:38:40 PM PDT 24
Peak memory 237756 kb
Host smart-1eac9a22-c516-45f2-bca6-3730ee5a2cfe
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3428705459 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.3428705459
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.2074772106
Short name T774
Test name
Test status
Simulation time 321882306 ps
CPU time 11.64 seconds
Started Aug 10 04:38:39 PM PDT 24
Finished Aug 10 04:38:51 PM PDT 24
Peak memory 242724 kb
Host smart-69e27b01-8eed-4a80-b3b2-8f85438af0fb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074772106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.alert_handler_csr_mem_rw_with_rand_reset.2074772106
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.1787067189
Short name T805
Test name
Test status
Simulation time 52285721 ps
CPU time 4.69 seconds
Started Aug 10 04:38:39 PM PDT 24
Finished Aug 10 04:38:43 PM PDT 24
Peak memory 237588 kb
Host smart-96e12965-a495-46f7-afbb-5d5333778f48
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1787067189 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.1787067189
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.4072065845
Short name T262
Test name
Test status
Simulation time 10762698 ps
CPU time 1.44 seconds
Started Aug 10 04:38:40 PM PDT 24
Finished Aug 10 04:38:41 PM PDT 24
Peak memory 236640 kb
Host smart-0568bae9-7228-43d9-afd3-91bb8288bb20
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4072065845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.4072065845
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.466797387
Short name T815
Test name
Test status
Simulation time 87044726 ps
CPU time 12.38 seconds
Started Aug 10 04:38:41 PM PDT 24
Finished Aug 10 04:38:54 PM PDT 24
Peak memory 240536 kb
Host smart-c2711da0-40b2-4340-bbfb-1786b469dcfb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=466797387 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_out
standing.466797387
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.232760749
Short name T140
Test name
Test status
Simulation time 4313967405 ps
CPU time 277.69 seconds
Started Aug 10 04:38:38 PM PDT 24
Finished Aug 10 04:43:16 PM PDT 24
Peak memory 265476 kb
Host smart-1d6f666d-cfec-4c80-9b17-29e8fa942f2b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=232760749 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_erro
rs.232760749
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.2514940948
Short name T768
Test name
Test status
Simulation time 182615914 ps
CPU time 12.53 seconds
Started Aug 10 04:38:39 PM PDT 24
Finished Aug 10 04:38:52 PM PDT 24
Peak memory 247828 kb
Host smart-b281e079-8ec3-49f2-bc6c-0c4078617946
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2514940948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.2514940948
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.4151069442
Short name T245
Test name
Test status
Simulation time 135533129 ps
CPU time 10.35 seconds
Started Aug 10 04:38:53 PM PDT 24
Finished Aug 10 04:39:03 PM PDT 24
Peak memory 239692 kb
Host smart-d45501ab-e3ab-40ca-9a7f-23bcb1eabfe5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4151069442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 15.alert_handler_csr_mem_rw_with_rand_reset.4151069442
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.2473596890
Short name T766
Test name
Test status
Simulation time 59427489 ps
CPU time 4.76 seconds
Started Aug 10 04:38:45 PM PDT 24
Finished Aug 10 04:38:50 PM PDT 24
Peak memory 236596 kb
Host smart-19f5837c-7b5d-47bb-a79b-52d38cfc3b75
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2473596890 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.2473596890
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.2152487939
Short name T772
Test name
Test status
Simulation time 8568311 ps
CPU time 1.59 seconds
Started Aug 10 04:38:37 PM PDT 24
Finished Aug 10 04:38:39 PM PDT 24
Peak memory 237608 kb
Host smart-49627124-ba1a-4d5b-a66e-d337715d685b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2152487939 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.2152487939
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.1877193244
Short name T779
Test name
Test status
Simulation time 496980597 ps
CPU time 37.36 seconds
Started Aug 10 04:38:39 PM PDT 24
Finished Aug 10 04:39:16 PM PDT 24
Peak memory 248624 kb
Host smart-dd56c16a-f37b-4501-bc59-5e177ca6f6ef
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1877193244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_ou
tstanding.1877193244
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.2121945341
Short name T150
Test name
Test status
Simulation time 8453514998 ps
CPU time 164.5 seconds
Started Aug 10 04:38:58 PM PDT 24
Finished Aug 10 04:41:42 PM PDT 24
Peak memory 265612 kb
Host smart-c2b03897-e6d4-41a5-a8e6-4ff385d495a3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2121945341 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_err
ors.2121945341
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.4236007521
Short name T144
Test name
Test status
Simulation time 5519641208 ps
CPU time 777.67 seconds
Started Aug 10 04:38:52 PM PDT 24
Finished Aug 10 04:51:50 PM PDT 24
Peak memory 273364 kb
Host smart-14355e56-2aa5-48c2-94b8-f6e42a14822c
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4236007521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.4236007521
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.1257441834
Short name T757
Test name
Test status
Simulation time 62700455 ps
CPU time 8.13 seconds
Started Aug 10 04:38:49 PM PDT 24
Finished Aug 10 04:38:57 PM PDT 24
Peak memory 248468 kb
Host smart-35e6604e-8904-4f23-b0dc-1d1cdd5614ce
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1257441834 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.1257441834
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.2791576564
Short name T715
Test name
Test status
Simulation time 580120762 ps
CPU time 5.68 seconds
Started Aug 10 04:38:44 PM PDT 24
Finished Aug 10 04:38:49 PM PDT 24
Peak memory 253888 kb
Host smart-4c1a2e77-4e0b-4bff-b5de-bedae81e1ce8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2791576564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 16.alert_handler_csr_mem_rw_with_rand_reset.2791576564
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.1453903316
Short name T729
Test name
Test status
Simulation time 192449279 ps
CPU time 4.5 seconds
Started Aug 10 04:38:57 PM PDT 24
Finished Aug 10 04:39:01 PM PDT 24
Peak memory 240588 kb
Host smart-b1c40c8f-1ee4-448d-82f8-130a3f8922a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1453903316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.1453903316
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.281305847
Short name T758
Test name
Test status
Simulation time 901144568 ps
CPU time 18.08 seconds
Started Aug 10 04:38:38 PM PDT 24
Finished Aug 10 04:38:56 PM PDT 24
Peak memory 244928 kb
Host smart-3916d589-4209-4847-8ad1-5d07218f6165
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=281305847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_out
standing.281305847
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.2523412020
Short name T151
Test name
Test status
Simulation time 2130319340 ps
CPU time 357.76 seconds
Started Aug 10 04:38:38 PM PDT 24
Finished Aug 10 04:44:36 PM PDT 24
Peak memory 265392 kb
Host smart-80c3f392-8213-4cd1-b58f-52cbcee23cf0
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523412020 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.2523412020
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.1008573000
Short name T771
Test name
Test status
Simulation time 41983832 ps
CPU time 5.65 seconds
Started Aug 10 04:38:38 PM PDT 24
Finished Aug 10 04:38:43 PM PDT 24
Peak memory 247272 kb
Host smart-2a5e0f73-7d00-4b1a-bdd1-c2202d5afef6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1008573000 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.1008573000
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.3838926754
Short name T743
Test name
Test status
Simulation time 37699188 ps
CPU time 5.99 seconds
Started Aug 10 04:38:44 PM PDT 24
Finished Aug 10 04:38:50 PM PDT 24
Peak memory 248776 kb
Host smart-9319172a-9a07-4024-a4a7-1019a994d61c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3838926754 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 17.alert_handler_csr_mem_rw_with_rand_reset.3838926754
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.3260216250
Short name T197
Test name
Test status
Simulation time 531286361 ps
CPU time 4.61 seconds
Started Aug 10 04:38:58 PM PDT 24
Finished Aug 10 04:39:03 PM PDT 24
Peak memory 236700 kb
Host smart-d78625e5-b855-46d2-aacf-8129d1a49f04
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3260216250 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.3260216250
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.815732627
Short name T728
Test name
Test status
Simulation time 15053010 ps
CPU time 1.49 seconds
Started Aug 10 04:38:52 PM PDT 24
Finished Aug 10 04:38:53 PM PDT 24
Peak memory 236608 kb
Host smart-33f3cfec-1974-43c0-b789-c9fcae2e2555
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=815732627 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.815732627
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.4031999939
Short name T783
Test name
Test status
Simulation time 249311464 ps
CPU time 17.02 seconds
Started Aug 10 04:38:44 PM PDT 24
Finished Aug 10 04:39:01 PM PDT 24
Peak memory 244848 kb
Host smart-ede700a7-15d9-4df9-90d6-c2336b1b3e9f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4031999939 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_ou
tstanding.4031999939
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.3181401868
Short name T154
Test name
Test status
Simulation time 7001988808 ps
CPU time 435.98 seconds
Started Aug 10 04:38:35 PM PDT 24
Finished Aug 10 04:45:51 PM PDT 24
Peak memory 265536 kb
Host smart-86719a65-2d0f-4d1d-8058-bd0d88901c50
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3181401868 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_err
ors.3181401868
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.3840761638
Short name T138
Test name
Test status
Simulation time 52301796683 ps
CPU time 1091.81 seconds
Started Aug 10 04:38:39 PM PDT 24
Finished Aug 10 04:56:51 PM PDT 24
Peak memory 265472 kb
Host smart-deb650db-2c6a-422d-a528-e8dc167fbe4e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3840761638 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.3840761638
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.276906370
Short name T717
Test name
Test status
Simulation time 368747841 ps
CPU time 8.34 seconds
Started Aug 10 04:38:39 PM PDT 24
Finished Aug 10 04:38:47 PM PDT 24
Peak memory 248788 kb
Host smart-9e975d76-b8fe-4ee5-924f-c9213e94c14d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=276906370 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.276906370
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.4099498275
Short name T182
Test name
Test status
Simulation time 97652902 ps
CPU time 7.64 seconds
Started Aug 10 04:38:55 PM PDT 24
Finished Aug 10 04:39:03 PM PDT 24
Peak memory 238060 kb
Host smart-d17e59f9-b3bf-4619-b25e-3431a0ecb88f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4099498275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 18.alert_handler_csr_mem_rw_with_rand_reset.4099498275
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.35476341
Short name T256
Test name
Test status
Simulation time 264131540 ps
CPU time 5.46 seconds
Started Aug 10 04:39:01 PM PDT 24
Finished Aug 10 04:39:07 PM PDT 24
Peak memory 240500 kb
Host smart-b4d24b9e-c0da-4aac-b0de-37203404c109
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=35476341 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+co
nd+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.35476341
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.1499428107
Short name T751
Test name
Test status
Simulation time 10638307 ps
CPU time 1.27 seconds
Started Aug 10 04:38:46 PM PDT 24
Finished Aug 10 04:38:47 PM PDT 24
Peak memory 235788 kb
Host smart-521a0e8e-7589-4901-976c-aa1a8bfe61d6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1499428107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.1499428107
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.2913640739
Short name T794
Test name
Test status
Simulation time 501771643 ps
CPU time 13.6 seconds
Started Aug 10 04:39:01 PM PDT 24
Finished Aug 10 04:39:15 PM PDT 24
Peak memory 245768 kb
Host smart-ceb69838-684c-480a-9e41-4bc5f711b0a0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2913640739 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_ou
tstanding.2913640739
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.4003563566
Short name T152
Test name
Test status
Simulation time 3144198988 ps
CPU time 353.48 seconds
Started Aug 10 04:38:39 PM PDT 24
Finished Aug 10 04:44:33 PM PDT 24
Peak memory 265440 kb
Host smart-0a69f1b3-d2ef-4913-9c4c-e8f4687c5ad5
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4003563566 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.4003563566
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.3092407188
Short name T798
Test name
Test status
Simulation time 171934470 ps
CPU time 10.21 seconds
Started Aug 10 04:38:50 PM PDT 24
Finished Aug 10 04:39:00 PM PDT 24
Peak memory 249784 kb
Host smart-89760814-3ab9-4918-9c93-ee325161f7a0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3092407188 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.3092407188
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.3769424734
Short name T176
Test name
Test status
Simulation time 180358129 ps
CPU time 3.82 seconds
Started Aug 10 04:38:45 PM PDT 24
Finished Aug 10 04:38:49 PM PDT 24
Peak memory 237496 kb
Host smart-e984bc7e-c762-4a79-a766-7f0ed718831e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3769424734 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.3769424734
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.3191124954
Short name T246
Test name
Test status
Simulation time 612049347 ps
CPU time 11.66 seconds
Started Aug 10 04:38:44 PM PDT 24
Finished Aug 10 04:38:56 PM PDT 24
Peak memory 249076 kb
Host smart-5c35ada3-3e7d-41bf-868d-e1af7a391b26
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3191124954 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 19.alert_handler_csr_mem_rw_with_rand_reset.3191124954
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.2809340132
Short name T190
Test name
Test status
Simulation time 173514823 ps
CPU time 5.39 seconds
Started Aug 10 04:38:40 PM PDT 24
Finished Aug 10 04:38:45 PM PDT 24
Peak memory 240524 kb
Host smart-536b5d84-caae-42d3-a005-f15bbddd2941
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2809340132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.2809340132
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.3822345118
Short name T763
Test name
Test status
Simulation time 13755259 ps
CPU time 1.33 seconds
Started Aug 10 04:38:46 PM PDT 24
Finished Aug 10 04:38:48 PM PDT 24
Peak memory 237588 kb
Host smart-27d59b04-2c57-4f5a-8209-cecb4eab1d72
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3822345118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.3822345118
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.2121353951
Short name T811
Test name
Test status
Simulation time 2373600889 ps
CPU time 47.81 seconds
Started Aug 10 04:38:48 PM PDT 24
Finished Aug 10 04:39:36 PM PDT 24
Peak memory 245796 kb
Host smart-5f2f5f34-7616-4d72-96ba-ed25bdc07346
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2121353951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_ou
tstanding.2121353951
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.3800490128
Short name T129
Test name
Test status
Simulation time 2105495871 ps
CPU time 157.81 seconds
Started Aug 10 04:38:51 PM PDT 24
Finished Aug 10 04:41:29 PM PDT 24
Peak memory 257396 kb
Host smart-07271a87-cf92-4bc1-8149-f366783ec97a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3800490128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_err
ors.3800490128
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.3967995631
Short name T739
Test name
Test status
Simulation time 632400124 ps
CPU time 12.38 seconds
Started Aug 10 04:38:55 PM PDT 24
Finished Aug 10 04:39:13 PM PDT 24
Peak memory 253948 kb
Host smart-e5ed88c9-0794-4f4e-83e5-90027269cd0d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3967995631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.3967995631
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.2182657838
Short name T790
Test name
Test status
Simulation time 1059932846 ps
CPU time 65.01 seconds
Started Aug 10 04:38:49 PM PDT 24
Finished Aug 10 04:39:54 PM PDT 24
Peak memory 240504 kb
Host smart-6fac1303-f3bd-446b-8db8-ce0216c49ca0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2182657838 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.2182657838
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.2749163816
Short name T820
Test name
Test status
Simulation time 7173139024 ps
CPU time 134.41 seconds
Started Aug 10 04:38:33 PM PDT 24
Finished Aug 10 04:40:47 PM PDT 24
Peak memory 236832 kb
Host smart-17f54cd2-819e-49ba-b53c-73edcff69b9d
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2749163816 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.2749163816
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.2867449003
Short name T821
Test name
Test status
Simulation time 12933041942 ps
CPU time 200.85 seconds
Started Aug 10 04:38:28 PM PDT 24
Finished Aug 10 04:41:49 PM PDT 24
Peak memory 237704 kb
Host smart-3ed177ce-3598-4008-aa4f-7a6e3505bb44
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2867449003 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.2867449003
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.2055798916
Short name T248
Test name
Test status
Simulation time 127355754 ps
CPU time 9.44 seconds
Started Aug 10 04:38:31 PM PDT 24
Finished Aug 10 04:38:41 PM PDT 24
Peak memory 249040 kb
Host smart-d316715a-77cc-4241-9906-00e722ced6b4
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2055798916 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.2055798916
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.3208247281
Short name T769
Test name
Test status
Simulation time 524532645 ps
CPU time 9.19 seconds
Started Aug 10 04:38:31 PM PDT 24
Finished Aug 10 04:38:40 PM PDT 24
Peak memory 239228 kb
Host smart-e19ea2ad-d8f6-4ba5-9dac-2e55f5b64da8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3208247281 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.alert_handler_csr_mem_rw_with_rand_reset.3208247281
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.791257519
Short name T193
Test name
Test status
Simulation time 105075675 ps
CPU time 3.27 seconds
Started Aug 10 04:38:35 PM PDT 24
Finished Aug 10 04:38:39 PM PDT 24
Peak memory 237536 kb
Host smart-02d4c5f9-62e8-4d68-ad5c-3f4152e8a993
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=791257519 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.791257519
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.1256230073
Short name T814
Test name
Test status
Simulation time 326853577 ps
CPU time 18.76 seconds
Started Aug 10 04:38:15 PM PDT 24
Finished Aug 10 04:38:34 PM PDT 24
Peak memory 248660 kb
Host smart-51af2e46-bf52-43de-8ba1-65432a803ffa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1256230073 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_out
standing.1256230073
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.3417955714
Short name T136
Test name
Test status
Simulation time 1098530839 ps
CPU time 127.45 seconds
Started Aug 10 04:38:25 PM PDT 24
Finished Aug 10 04:40:33 PM PDT 24
Peak memory 265416 kb
Host smart-11845e54-bde0-4ebb-a721-773d9654af18
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3417955714 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_erro
rs.3417955714
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.1057858423
Short name T161
Test name
Test status
Simulation time 35036001612 ps
CPU time 339.95 seconds
Started Aug 10 04:38:24 PM PDT 24
Finished Aug 10 04:44:04 PM PDT 24
Peak memory 265496 kb
Host smart-f85c9ecf-1dd9-4c95-8916-527e630a6131
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1057858423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.1057858423
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.3097639588
Short name T260
Test name
Test status
Simulation time 1981977990 ps
CPU time 9.42 seconds
Started Aug 10 04:38:22 PM PDT 24
Finished Aug 10 04:38:31 PM PDT 24
Peak memory 247616 kb
Host smart-5ef0250c-dfd1-4138-89c3-bfc46af88b68
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3097639588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.3097639588
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.863917498
Short name T261
Test name
Test status
Simulation time 31104883 ps
CPU time 1.63 seconds
Started Aug 10 04:38:41 PM PDT 24
Finished Aug 10 04:38:43 PM PDT 24
Peak memory 237596 kb
Host smart-ca73b23a-1940-4383-86d6-8e9b2deef2b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=863917498 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.863917498
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.3896510486
Short name T351
Test name
Test status
Simulation time 8960063 ps
CPU time 1.52 seconds
Started Aug 10 04:38:40 PM PDT 24
Finished Aug 10 04:38:41 PM PDT 24
Peak memory 237704 kb
Host smart-27adf7c7-fb75-4069-9e34-019bd6d90d30
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3896510486 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.3896510486
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.28323817
Short name T753
Test name
Test status
Simulation time 17003935 ps
CPU time 1.4 seconds
Started Aug 10 04:38:55 PM PDT 24
Finished Aug 10 04:39:02 PM PDT 24
Peak memory 237660 kb
Host smart-7639527d-2bf4-480d-9f61-d37f2fbcc85e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=28323817 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.28323817
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.4266096208
Short name T825
Test name
Test status
Simulation time 14287679 ps
CPU time 1.39 seconds
Started Aug 10 04:38:46 PM PDT 24
Finished Aug 10 04:38:48 PM PDT 24
Peak memory 237448 kb
Host smart-0e4a52e3-d635-4037-8e4e-7f2442637138
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4266096208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.4266096208
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.3547174347
Short name T721
Test name
Test status
Simulation time 8811365 ps
CPU time 1.5 seconds
Started Aug 10 04:38:42 PM PDT 24
Finished Aug 10 04:38:44 PM PDT 24
Peak memory 237532 kb
Host smart-80e98d74-649c-485b-9127-8c1e10850be2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3547174347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.3547174347
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.3621066886
Short name T756
Test name
Test status
Simulation time 9742364 ps
CPU time 1.65 seconds
Started Aug 10 04:38:55 PM PDT 24
Finished Aug 10 04:38:57 PM PDT 24
Peak memory 237548 kb
Host smart-7c099fe1-f041-46cf-b5bb-69256e4dd249
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3621066886 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.3621066886
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.2522064544
Short name T760
Test name
Test status
Simulation time 12765093 ps
CPU time 1.43 seconds
Started Aug 10 04:39:03 PM PDT 24
Finished Aug 10 04:39:05 PM PDT 24
Peak memory 236676 kb
Host smart-655390c3-a8ba-4b0f-a005-de91326b473a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2522064544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.2522064544
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.2895772504
Short name T736
Test name
Test status
Simulation time 13610254 ps
CPU time 1.33 seconds
Started Aug 10 04:38:36 PM PDT 24
Finished Aug 10 04:38:38 PM PDT 24
Peak memory 235612 kb
Host smart-7c08384c-27f1-46e1-a7a9-a18746e4dcfb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2895772504 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.2895772504
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.2877421292
Short name T810
Test name
Test status
Simulation time 16825577 ps
CPU time 1.48 seconds
Started Aug 10 04:38:54 PM PDT 24
Finished Aug 10 04:38:56 PM PDT 24
Peak memory 237572 kb
Host smart-89bde1b1-fd26-4ae6-9425-2608b3112702
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2877421292 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.2877421292
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.2543255873
Short name T789
Test name
Test status
Simulation time 25215283 ps
CPU time 1.46 seconds
Started Aug 10 04:38:50 PM PDT 24
Finished Aug 10 04:38:52 PM PDT 24
Peak memory 237576 kb
Host smart-a34bfe0f-30dc-4b93-9159-f1aa69064715
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2543255873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.2543255873
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.1147956785
Short name T195
Test name
Test status
Simulation time 4707340792 ps
CPU time 342.66 seconds
Started Aug 10 04:38:37 PM PDT 24
Finished Aug 10 04:44:20 PM PDT 24
Peak memory 240700 kb
Host smart-9ac5aa63-2450-41bc-810a-65b3b2fdb640
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1147956785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.1147956785
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.568616548
Short name T191
Test name
Test status
Simulation time 94986865706 ps
CPU time 387.16 seconds
Started Aug 10 04:38:29 PM PDT 24
Finished Aug 10 04:44:57 PM PDT 24
Peak memory 240700 kb
Host smart-d898eeab-67d2-49f8-9937-37dea23cda1e
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=568616548 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.568616548
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.1941265074
Short name T749
Test name
Test status
Simulation time 340893942 ps
CPU time 10.45 seconds
Started Aug 10 04:38:10 PM PDT 24
Finished Aug 10 04:38:20 PM PDT 24
Peak memory 249100 kb
Host smart-5ff2362c-f4bc-4eb5-b4d5-30d2bfee602c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1941265074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.1941265074
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.1249740528
Short name T719
Test name
Test status
Simulation time 156810792 ps
CPU time 6.24 seconds
Started Aug 10 04:38:12 PM PDT 24
Finished Aug 10 04:38:18 PM PDT 24
Peak memory 240660 kb
Host smart-53c0e788-9efa-4434-a62a-a8667dce7231
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1249740528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.alert_handler_csr_mem_rw_with_rand_reset.1249740528
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.2829523213
Short name T776
Test name
Test status
Simulation time 73177788 ps
CPU time 4.44 seconds
Started Aug 10 04:38:32 PM PDT 24
Finished Aug 10 04:38:36 PM PDT 24
Peak memory 237572 kb
Host smart-4cc3888c-3022-4dd6-a662-5e163b0a7d15
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2829523213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.2829523213
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.2709358038
Short name T730
Test name
Test status
Simulation time 19059072 ps
CPU time 1.32 seconds
Started Aug 10 04:38:29 PM PDT 24
Finished Aug 10 04:38:31 PM PDT 24
Peak memory 237644 kb
Host smart-bd8445f1-f9d2-4b40-a076-40e06d78d486
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2709358038 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.2709358038
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.3550593373
Short name T765
Test name
Test status
Simulation time 254945136 ps
CPU time 18.56 seconds
Started Aug 10 04:38:26 PM PDT 24
Finished Aug 10 04:38:44 PM PDT 24
Peak memory 244904 kb
Host smart-fa6f6e31-1bf2-4409-a498-df679cf3aab8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3550593373 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_out
standing.3550593373
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.3598908598
Short name T157
Test name
Test status
Simulation time 7891405173 ps
CPU time 285.9 seconds
Started Aug 10 04:38:29 PM PDT 24
Finished Aug 10 04:43:15 PM PDT 24
Peak memory 265564 kb
Host smart-5996e79b-1cb9-4fa4-871e-943b9dbeb47c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3598908598 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_erro
rs.3598908598
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.1593630765
Short name T131
Test name
Test status
Simulation time 24130656568 ps
CPU time 1006.28 seconds
Started Aug 10 04:38:09 PM PDT 24
Finished Aug 10 04:54:55 PM PDT 24
Peak memory 265696 kb
Host smart-94f4ee58-cd5b-4516-92a4-3358dc780ebf
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1593630765 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.1593630765
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.1138016016
Short name T257
Test name
Test status
Simulation time 320344015 ps
CPU time 21.14 seconds
Started Aug 10 04:38:06 PM PDT 24
Finished Aug 10 04:38:27 PM PDT 24
Peak memory 255412 kb
Host smart-a28b8176-34a1-4dd1-a965-235a1c5250ee
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1138016016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.1138016016
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.472868652
Short name T732
Test name
Test status
Simulation time 9770803 ps
CPU time 1.6 seconds
Started Aug 10 04:38:49 PM PDT 24
Finished Aug 10 04:38:51 PM PDT 24
Peak memory 235700 kb
Host smart-edf6c799-cea7-47e9-9302-1b286e514164
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=472868652 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.472868652
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.1883605774
Short name T761
Test name
Test status
Simulation time 10851035 ps
CPU time 1.31 seconds
Started Aug 10 04:38:55 PM PDT 24
Finished Aug 10 04:38:56 PM PDT 24
Peak memory 236552 kb
Host smart-7bb09c58-4748-481d-a40d-dbc5b13a9086
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1883605774 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.1883605774
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.3765044171
Short name T239
Test name
Test status
Simulation time 9837988 ps
CPU time 1.33 seconds
Started Aug 10 04:38:49 PM PDT 24
Finished Aug 10 04:38:51 PM PDT 24
Peak memory 236668 kb
Host smart-23da598c-6182-4209-994a-fe05465e407d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3765044171 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.3765044171
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.2335580749
Short name T740
Test name
Test status
Simulation time 24567582 ps
CPU time 1.25 seconds
Started Aug 10 04:38:53 PM PDT 24
Finished Aug 10 04:38:55 PM PDT 24
Peak memory 237440 kb
Host smart-669e1711-d557-41a9-8211-ab4cc886da03
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2335580749 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.2335580749
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.2686655461
Short name T352
Test name
Test status
Simulation time 20397716 ps
CPU time 1.45 seconds
Started Aug 10 04:38:46 PM PDT 24
Finished Aug 10 04:38:47 PM PDT 24
Peak memory 236600 kb
Host smart-c511ffc4-a97f-4a87-8efb-33aa76d9f28b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2686655461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.2686655461
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.567160265
Short name T746
Test name
Test status
Simulation time 45744989 ps
CPU time 1.35 seconds
Started Aug 10 04:38:49 PM PDT 24
Finished Aug 10 04:38:50 PM PDT 24
Peak memory 235460 kb
Host smart-77287e1f-0b86-44ce-b8dd-e40b0a9159f1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=567160265 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.567160265
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.4275565291
Short name T813
Test name
Test status
Simulation time 8218970 ps
CPU time 1.39 seconds
Started Aug 10 04:38:45 PM PDT 24
Finished Aug 10 04:38:47 PM PDT 24
Peak memory 237512 kb
Host smart-6221c62a-420b-4a08-a72e-60d450aaef0a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4275565291 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.4275565291
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.3365093651
Short name T804
Test name
Test status
Simulation time 34043841 ps
CPU time 1.26 seconds
Started Aug 10 04:38:45 PM PDT 24
Finished Aug 10 04:38:47 PM PDT 24
Peak memory 237452 kb
Host smart-9e690111-890c-449b-a40e-988c02d4555b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3365093651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.3365093651
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.2166863922
Short name T745
Test name
Test status
Simulation time 10726375 ps
CPU time 1.65 seconds
Started Aug 10 04:39:02 PM PDT 24
Finished Aug 10 04:39:04 PM PDT 24
Peak memory 236728 kb
Host smart-e56b2023-3436-40b4-9a48-30fc99ab221e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2166863922 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.2166863922
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.201835659
Short name T800
Test name
Test status
Simulation time 7962782 ps
CPU time 1.37 seconds
Started Aug 10 04:38:46 PM PDT 24
Finished Aug 10 04:38:48 PM PDT 24
Peak memory 236668 kb
Host smart-41cb0b60-900f-4ed4-b991-7aa6d54098d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=201835659 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.201835659
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.4247255991
Short name T731
Test name
Test status
Simulation time 1149039094 ps
CPU time 157.4 seconds
Started Aug 10 04:38:08 PM PDT 24
Finished Aug 10 04:40:45 PM PDT 24
Peak memory 239728 kb
Host smart-585c8b7f-e458-4e75-bba9-d676369714f0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4247255991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.4247255991
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.913440831
Short name T353
Test name
Test status
Simulation time 3334817952 ps
CPU time 245.11 seconds
Started Aug 10 04:38:43 PM PDT 24
Finished Aug 10 04:42:48 PM PDT 24
Peak memory 237588 kb
Host smart-dade2d2a-946c-4493-b755-bf4a1a860cd4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=913440831 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.913440831
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.2757057290
Short name T247
Test name
Test status
Simulation time 498786561 ps
CPU time 10.38 seconds
Started Aug 10 04:38:22 PM PDT 24
Finished Aug 10 04:38:32 PM PDT 24
Peak memory 249220 kb
Host smart-d37b38ad-4700-4ef5-9bf2-e5f799d7e813
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2757057290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.2757057290
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.284071542
Short name T750
Test name
Test status
Simulation time 103951043 ps
CPU time 8.74 seconds
Started Aug 10 04:38:25 PM PDT 24
Finished Aug 10 04:38:33 PM PDT 24
Peak memory 251812 kb
Host smart-25cfa5ec-7b6a-41d2-973a-cb8c3209d47f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=284071542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 4.alert_handler_csr_mem_rw_with_rand_reset.284071542
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.2363266405
Short name T803
Test name
Test status
Simulation time 250443466 ps
CPU time 9.42 seconds
Started Aug 10 04:38:35 PM PDT 24
Finished Aug 10 04:38:49 PM PDT 24
Peak memory 240512 kb
Host smart-4304b8f2-c266-4b2c-b890-fbb6697cac41
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2363266405 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.2363266405
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.756189561
Short name T823
Test name
Test status
Simulation time 10333972 ps
CPU time 1.2 seconds
Started Aug 10 04:38:15 PM PDT 24
Finished Aug 10 04:38:16 PM PDT 24
Peak memory 237652 kb
Host smart-501beb6f-38d2-48c7-a48d-df3b69589cb3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=756189561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.756189561
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.3384390374
Short name T818
Test name
Test status
Simulation time 695172081 ps
CPU time 43.12 seconds
Started Aug 10 04:38:30 PM PDT 24
Finished Aug 10 04:39:13 PM PDT 24
Peak memory 245788 kb
Host smart-648c9786-b381-4fe5-a468-2a6b2b2d9f91
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3384390374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_out
standing.3384390374
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.3519820741
Short name T134
Test name
Test status
Simulation time 1096036220 ps
CPU time 109.41 seconds
Started Aug 10 04:38:37 PM PDT 24
Finished Aug 10 04:40:27 PM PDT 24
Peak memory 257192 kb
Host smart-ae897c0f-9b57-4595-9e82-0902bb482e36
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3519820741 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_erro
rs.3519820741
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.177426518
Short name T137
Test name
Test status
Simulation time 62481540216 ps
CPU time 1200.47 seconds
Started Aug 10 04:38:21 PM PDT 24
Finished Aug 10 04:58:21 PM PDT 24
Peak memory 273492 kb
Host smart-e31f8320-416e-486e-a2ec-ded86d4d95d2
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=177426518 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.177426518
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.3196339938
Short name T777
Test name
Test status
Simulation time 140794212 ps
CPU time 4.67 seconds
Started Aug 10 04:38:30 PM PDT 24
Finished Aug 10 04:38:34 PM PDT 24
Peak memory 253936 kb
Host smart-892cc38a-6e07-4610-b9c3-10129cca00a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3196339938 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.3196339938
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.1297552387
Short name T812
Test name
Test status
Simulation time 24960459 ps
CPU time 1.33 seconds
Started Aug 10 04:38:48 PM PDT 24
Finished Aug 10 04:38:50 PM PDT 24
Peak memory 236568 kb
Host smart-77e9aa21-66c8-41a6-ab75-a5320b44b010
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1297552387 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.1297552387
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.804738515
Short name T725
Test name
Test status
Simulation time 12197562 ps
CPU time 1.69 seconds
Started Aug 10 04:38:47 PM PDT 24
Finished Aug 10 04:38:49 PM PDT 24
Peak memory 236656 kb
Host smart-b4489f62-273d-46b4-a996-386a6374967a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=804738515 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.804738515
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.1988811696
Short name T348
Test name
Test status
Simulation time 11119657 ps
CPU time 1.3 seconds
Started Aug 10 04:38:57 PM PDT 24
Finished Aug 10 04:38:58 PM PDT 24
Peak memory 237560 kb
Host smart-3d61807d-ca17-44a4-9296-5c5d6f46ba0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1988811696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.1988811696
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.373833404
Short name T762
Test name
Test status
Simulation time 9324011 ps
CPU time 1.67 seconds
Started Aug 10 04:38:46 PM PDT 24
Finished Aug 10 04:38:48 PM PDT 24
Peak memory 237704 kb
Host smart-54d1b49a-0c6a-4073-9307-421da4307630
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=373833404 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.373833404
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.195837803
Short name T778
Test name
Test status
Simulation time 9553589 ps
CPU time 1.35 seconds
Started Aug 10 04:38:57 PM PDT 24
Finished Aug 10 04:38:58 PM PDT 24
Peak memory 237544 kb
Host smart-9ff801de-7600-4b43-b183-bf42b6b503f2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=195837803 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.195837803
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.723229096
Short name T773
Test name
Test status
Simulation time 10454375 ps
CPU time 1.58 seconds
Started Aug 10 04:38:42 PM PDT 24
Finished Aug 10 04:38:44 PM PDT 24
Peak memory 236548 kb
Host smart-8b41ab2d-104f-42f2-90c5-827baaa7a5b0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=723229096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.723229096
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.1881832457
Short name T785
Test name
Test status
Simulation time 9405529 ps
CPU time 1.55 seconds
Started Aug 10 04:38:45 PM PDT 24
Finished Aug 10 04:38:46 PM PDT 24
Peak memory 235616 kb
Host smart-c04403cb-f227-475b-b663-3feadf90154e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1881832457 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.1881832457
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.4089612300
Short name T747
Test name
Test status
Simulation time 11651116 ps
CPU time 1.3 seconds
Started Aug 10 04:38:52 PM PDT 24
Finished Aug 10 04:38:53 PM PDT 24
Peak memory 237556 kb
Host smart-489e7aa6-0e91-4981-8c4a-0a422d4add40
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4089612300 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.4089612300
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.93203414
Short name T784
Test name
Test status
Simulation time 7781603 ps
CPU time 1.39 seconds
Started Aug 10 04:38:51 PM PDT 24
Finished Aug 10 04:38:52 PM PDT 24
Peak memory 237540 kb
Host smart-75ec1c73-6c2e-4224-afa9-2e248ff584ac
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=93203414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.93203414
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.3235692818
Short name T166
Test name
Test status
Simulation time 10334552 ps
CPU time 1.25 seconds
Started Aug 10 04:38:53 PM PDT 24
Finished Aug 10 04:38:55 PM PDT 24
Peak memory 236668 kb
Host smart-36238ddd-d33a-4185-8267-7db021e8813f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3235692818 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.3235692818
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.3303409842
Short name T795
Test name
Test status
Simulation time 95407363 ps
CPU time 7.94 seconds
Started Aug 10 04:38:45 PM PDT 24
Finished Aug 10 04:38:53 PM PDT 24
Peak memory 240212 kb
Host smart-20b9466a-7ada-4bfe-8f00-b33dd46160bd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3303409842 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 5.alert_handler_csr_mem_rw_with_rand_reset.3303409842
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.2485120340
Short name T824
Test name
Test status
Simulation time 551405014 ps
CPU time 10.41 seconds
Started Aug 10 04:38:35 PM PDT 24
Finished Aug 10 04:38:46 PM PDT 24
Peak memory 237348 kb
Host smart-d9218a54-9ee7-4680-9a58-bf57796e3f92
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2485120340 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.2485120340
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.2658031191
Short name T809
Test name
Test status
Simulation time 6260971 ps
CPU time 1.46 seconds
Started Aug 10 04:38:36 PM PDT 24
Finished Aug 10 04:38:37 PM PDT 24
Peak memory 237584 kb
Host smart-288c488e-52df-43e2-97f1-aab4e4b5c589
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2658031191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.2658031191
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.902662666
Short name T781
Test name
Test status
Simulation time 256864990 ps
CPU time 18.78 seconds
Started Aug 10 04:38:35 PM PDT 24
Finished Aug 10 04:38:54 PM PDT 24
Peak memory 245792 kb
Host smart-eff210d2-cade-4477-a484-c80ea8bd682f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=902662666 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_outs
tanding.902662666
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.1802815949
Short name T356
Test name
Test status
Simulation time 28065486367 ps
CPU time 575.05 seconds
Started Aug 10 04:38:29 PM PDT 24
Finished Aug 10 04:48:05 PM PDT 24
Peak memory 265452 kb
Host smart-d3923b38-4d4c-4a35-8abb-527881bb02c7
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802815949 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.1802815949
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.309802295
Short name T791
Test name
Test status
Simulation time 410271617 ps
CPU time 8.21 seconds
Started Aug 10 04:38:24 PM PDT 24
Finished Aug 10 04:38:32 PM PDT 24
Peak memory 248744 kb
Host smart-fcbdc0be-911a-4c0e-ba5a-a00d2bd2fc99
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=309802295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.309802295
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.4204353184
Short name T799
Test name
Test status
Simulation time 2574491021 ps
CPU time 44.94 seconds
Started Aug 10 04:38:35 PM PDT 24
Finished Aug 10 04:39:21 PM PDT 24
Peak memory 240552 kb
Host smart-fa42d481-518e-4554-99e4-72de41563a20
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4204353184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.4204353184
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.1557222084
Short name T714
Test name
Test status
Simulation time 304822244 ps
CPU time 10.13 seconds
Started Aug 10 04:38:45 PM PDT 24
Finished Aug 10 04:38:55 PM PDT 24
Peak memory 256664 kb
Host smart-341486e7-ea30-44e5-abc9-5cf7d424850d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557222084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.alert_handler_csr_mem_rw_with_rand_reset.1557222084
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.2331035051
Short name T349
Test name
Test status
Simulation time 9542303 ps
CPU time 1.26 seconds
Started Aug 10 04:38:26 PM PDT 24
Finished Aug 10 04:38:27 PM PDT 24
Peak memory 235920 kb
Host smart-8c189dfa-a320-4ccb-b10c-c177b349dfef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2331035051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.2331035051
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.2863671290
Short name T194
Test name
Test status
Simulation time 1491270916 ps
CPU time 24.36 seconds
Started Aug 10 04:38:37 PM PDT 24
Finished Aug 10 04:39:01 PM PDT 24
Peak memory 245688 kb
Host smart-730b55ed-c989-47e1-a918-1d07303dc310
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2863671290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_out
standing.2863671290
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.1558075585
Short name T146
Test name
Test status
Simulation time 5023586593 ps
CPU time 331.11 seconds
Started Aug 10 04:38:37 PM PDT 24
Finished Aug 10 04:44:08 PM PDT 24
Peak memory 265432 kb
Host smart-ebf1c1b6-4cd0-4e4b-a615-659ef30a3d26
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1558075585 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_erro
rs.1558075585
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.2488359254
Short name T796
Test name
Test status
Simulation time 124045794 ps
CPU time 8.89 seconds
Started Aug 10 04:38:26 PM PDT 24
Finished Aug 10 04:38:35 PM PDT 24
Peak memory 249916 kb
Host smart-1fbc3ba6-e0d0-475c-8e3a-0ae321a0d2c9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2488359254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.2488359254
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.2452599481
Short name T764
Test name
Test status
Simulation time 39948603 ps
CPU time 6 seconds
Started Aug 10 04:38:25 PM PDT 24
Finished Aug 10 04:38:31 PM PDT 24
Peak memory 255908 kb
Host smart-aa453e9d-a621-4204-a7b4-96905f0e5051
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2452599481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 7.alert_handler_csr_mem_rw_with_rand_reset.2452599481
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.3218554530
Short name T748
Test name
Test status
Simulation time 185952307 ps
CPU time 7.65 seconds
Started Aug 10 04:38:32 PM PDT 24
Finished Aug 10 04:38:40 PM PDT 24
Peak memory 237504 kb
Host smart-395d4f97-07bc-45ed-98fb-c626a540d08b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3218554530 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.3218554530
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.3853017559
Short name T755
Test name
Test status
Simulation time 11290640 ps
CPU time 1.59 seconds
Started Aug 10 04:38:28 PM PDT 24
Finished Aug 10 04:38:30 PM PDT 24
Peak memory 235568 kb
Host smart-f8fd132c-764b-4117-8a7c-24e165a28e6f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3853017559 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.3853017559
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.263327780
Short name T801
Test name
Test status
Simulation time 981815764 ps
CPU time 35.54 seconds
Started Aug 10 04:38:43 PM PDT 24
Finished Aug 10 04:39:18 PM PDT 24
Peak memory 245012 kb
Host smart-4380bfbc-a1fe-478f-8e30-f99b0ddd5e9e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=263327780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_outs
tanding.263327780
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.376900878
Short name T159
Test name
Test status
Simulation time 10096375988 ps
CPU time 172.55 seconds
Started Aug 10 04:38:17 PM PDT 24
Finished Aug 10 04:41:10 PM PDT 24
Peak memory 265620 kb
Host smart-16c2ee58-833a-47f8-a329-9b1cd660bc9b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=376900878 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_error
s.376900878
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.3209756942
Short name T153
Test name
Test status
Simulation time 2722279829 ps
CPU time 432.34 seconds
Started Aug 10 04:38:41 PM PDT 24
Finished Aug 10 04:45:53 PM PDT 24
Peak memory 265404 kb
Host smart-e748699d-5c91-44a7-9618-2e7b154ffd78
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3209756942 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.3209756942
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.2170393505
Short name T797
Test name
Test status
Simulation time 351280982 ps
CPU time 11.51 seconds
Started Aug 10 04:38:33 PM PDT 24
Finished Aug 10 04:38:45 PM PDT 24
Peak memory 248520 kb
Host smart-917ea93e-4f8f-48eb-afce-6141a58252fb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2170393505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.2170393505
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.1666593997
Short name T724
Test name
Test status
Simulation time 126510617 ps
CPU time 9.14 seconds
Started Aug 10 04:38:33 PM PDT 24
Finished Aug 10 04:38:43 PM PDT 24
Peak memory 253212 kb
Host smart-577af574-d97b-4b36-8152-67c26abf0f03
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1666593997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.alert_handler_csr_mem_rw_with_rand_reset.1666593997
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.1613574599
Short name T754
Test name
Test status
Simulation time 477402695 ps
CPU time 9.71 seconds
Started Aug 10 04:38:36 PM PDT 24
Finished Aug 10 04:38:46 PM PDT 24
Peak memory 237688 kb
Host smart-87da9e2b-f77b-4c66-a4ac-f5919a00f6a8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1613574599 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.1613574599
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.3805489105
Short name T788
Test name
Test status
Simulation time 10008089 ps
CPU time 1.59 seconds
Started Aug 10 04:38:29 PM PDT 24
Finished Aug 10 04:38:31 PM PDT 24
Peak memory 237524 kb
Host smart-874fc197-7589-4b66-afec-9d0a0abb49ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3805489105 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.3805489105
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.323597980
Short name T822
Test name
Test status
Simulation time 274085785 ps
CPU time 20.2 seconds
Started Aug 10 04:38:30 PM PDT 24
Finished Aug 10 04:38:51 PM PDT 24
Peak memory 245776 kb
Host smart-11a96d10-ba81-428a-80d1-d483c80a9ae6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=323597980 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_outs
tanding.323597980
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.1710070598
Short name T149
Test name
Test status
Simulation time 10594774251 ps
CPU time 368.58 seconds
Started Aug 10 04:38:38 PM PDT 24
Finished Aug 10 04:44:46 PM PDT 24
Peak memory 265468 kb
Host smart-edff6263-e5bf-45c3-8a8e-a1585152f001
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1710070598 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_erro
rs.1710070598
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.3348430756
Short name T802
Test name
Test status
Simulation time 6338184260 ps
CPU time 549.54 seconds
Started Aug 10 04:38:27 PM PDT 24
Finished Aug 10 04:47:36 PM PDT 24
Peak memory 270052 kb
Host smart-1abb2cd7-2db2-48f4-84cb-88797758105d
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348430756 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.3348430756
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.2986513579
Short name T712
Test name
Test status
Simulation time 325042925 ps
CPU time 25.86 seconds
Started Aug 10 04:38:35 PM PDT 24
Finished Aug 10 04:39:02 PM PDT 24
Peak memory 248792 kb
Host smart-dff00c62-9fef-4c34-b2ff-5ecaf4449d18
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2986513579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.2986513579
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.2404454726
Short name T164
Test name
Test status
Simulation time 1799439868 ps
CPU time 65.75 seconds
Started Aug 10 04:38:34 PM PDT 24
Finished Aug 10 04:39:40 PM PDT 24
Peak memory 240504 kb
Host smart-cc4d9d60-cff9-40a2-80ae-8ef3a95f79fa
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2404454726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.2404454726
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.2201948971
Short name T726
Test name
Test status
Simulation time 116023467 ps
CPU time 5.17 seconds
Started Aug 10 04:38:26 PM PDT 24
Finished Aug 10 04:38:31 PM PDT 24
Peak memory 240192 kb
Host smart-6e0a461b-c3ee-4468-ad05-b41346159b34
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2201948971 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.alert_handler_csr_mem_rw_with_rand_reset.2201948971
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.2887422308
Short name T806
Test name
Test status
Simulation time 680235665 ps
CPU time 7.23 seconds
Started Aug 10 04:38:37 PM PDT 24
Finished Aug 10 04:38:45 PM PDT 24
Peak memory 236656 kb
Host smart-a0281d30-dc14-4ae8-aa8e-3fc34828e203
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2887422308 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.2887422308
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.883622604
Short name T738
Test name
Test status
Simulation time 11045946 ps
CPU time 1.63 seconds
Started Aug 10 04:38:26 PM PDT 24
Finished Aug 10 04:38:28 PM PDT 24
Peak memory 236680 kb
Host smart-9b14b21c-90d4-47bd-9f21-387c4a472cf7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=883622604 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.883622604
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.3172137374
Short name T780
Test name
Test status
Simulation time 1043872741 ps
CPU time 41.4 seconds
Started Aug 10 04:38:29 PM PDT 24
Finished Aug 10 04:39:10 PM PDT 24
Peak memory 248712 kb
Host smart-f2b0916d-9abb-449e-9e16-ca5e5e1ef5de
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3172137374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_out
standing.3172137374
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.3468051753
Short name T156
Test name
Test status
Simulation time 8683431686 ps
CPU time 152.78 seconds
Started Aug 10 04:38:29 PM PDT 24
Finished Aug 10 04:41:02 PM PDT 24
Peak memory 265608 kb
Host smart-d4e84993-0736-4c03-bce9-462ffab201eb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3468051753 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_erro
rs.3468051753
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.853310091
Short name T744
Test name
Test status
Simulation time 249348728 ps
CPU time 8.31 seconds
Started Aug 10 04:38:20 PM PDT 24
Finished Aug 10 04:38:29 PM PDT 24
Peak memory 248616 kb
Host smart-12cae36b-21f3-4b57-8e22-cf80aaa09271
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=853310091 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.853310091
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.3962939038
Short name T29
Test name
Test status
Simulation time 31807570269 ps
CPU time 1706.91 seconds
Started Aug 10 04:38:46 PM PDT 24
Finished Aug 10 05:07:13 PM PDT 24
Peak memory 272780 kb
Host smart-a4bac4a6-e28c-4982-8bbe-a8e3d1e5c992
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962939038 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.3962939038
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.2278869464
Short name T631
Test name
Test status
Simulation time 273702217 ps
CPU time 12.83 seconds
Started Aug 10 04:38:58 PM PDT 24
Finished Aug 10 04:39:11 PM PDT 24
Peak memory 248208 kb
Host smart-088298e9-1599-4199-af15-c919f9270239
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2278869464 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.2278869464
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.1530333257
Short name T630
Test name
Test status
Simulation time 36970977 ps
CPU time 5.77 seconds
Started Aug 10 04:38:55 PM PDT 24
Finished Aug 10 04:39:01 PM PDT 24
Peak memory 252976 kb
Host smart-96adbf89-0d74-45b4-9b37-627f12bfca16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15303
33257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.1530333257
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.1807306729
Short name T620
Test name
Test status
Simulation time 1182498044 ps
CPU time 14.19 seconds
Started Aug 10 04:38:52 PM PDT 24
Finished Aug 10 04:39:06 PM PDT 24
Peak memory 252720 kb
Host smart-5b2c8b90-d2fb-49f1-a78b-f5796e6f5cee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18073
06729 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.1807306729
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.1642908238
Short name T606
Test name
Test status
Simulation time 40433662899 ps
CPU time 2354.65 seconds
Started Aug 10 04:38:49 PM PDT 24
Finished Aug 10 05:18:04 PM PDT 24
Peak memory 288428 kb
Host smart-03d68452-e522-4695-b093-608e77219a77
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1642908238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.1642908238
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.1304348386
Short name T483
Test name
Test status
Simulation time 814302979 ps
CPU time 48.2 seconds
Started Aug 10 04:38:47 PM PDT 24
Finished Aug 10 04:39:35 PM PDT 24
Peak memory 255592 kb
Host smart-5692e6fd-7e54-4ba2-96f0-043a18a45038
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13043
48386 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.1304348386
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.824360738
Short name T624
Test name
Test status
Simulation time 461976512 ps
CPU time 23.68 seconds
Started Aug 10 04:38:42 PM PDT 24
Finished Aug 10 04:39:06 PM PDT 24
Peak memory 247808 kb
Host smart-dfa506ab-b022-4fce-9ed6-999ff2d4092d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82436
0738 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.824360738
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.1338748582
Short name T367
Test name
Test status
Simulation time 627832395 ps
CPU time 17.13 seconds
Started Aug 10 04:38:45 PM PDT 24
Finished Aug 10 04:39:02 PM PDT 24
Peak memory 247980 kb
Host smart-5a7dceee-b6cf-4f58-abd1-47a8865ebdf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13387
48582 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.1338748582
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.1164290896
Short name T542
Test name
Test status
Simulation time 652293510 ps
CPU time 42.78 seconds
Started Aug 10 04:38:44 PM PDT 24
Finished Aug 10 04:39:27 PM PDT 24
Peak memory 248252 kb
Host smart-bb1dac5e-4914-44c9-98dd-76344df33e58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11642
90896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.1164290896
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all_with_rand_reset.1332680118
Short name T297
Test name
Test status
Simulation time 77237315124 ps
CPU time 6778.06 seconds
Started Aug 10 04:38:45 PM PDT 24
Finished Aug 10 06:31:44 PM PDT 24
Peak memory 354296 kb
Host smart-3195d8d7-2559-4d75-885f-100c1b1fbab8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1332680118 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.alert_handler_stress_all_with_rand_reset.1332680118
Directory /workspace/0.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.3582878779
Short name T3
Test name
Test status
Simulation time 43940730970 ps
CPU time 1023.93 seconds
Started Aug 10 04:38:42 PM PDT 24
Finished Aug 10 04:55:47 PM PDT 24
Peak memory 272836 kb
Host smart-b3af5d26-3a68-4875-aba4-c64f6c195622
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3582878779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.3582878779
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.3619492581
Short name T426
Test name
Test status
Simulation time 1713232490 ps
CPU time 9.83 seconds
Started Aug 10 04:38:52 PM PDT 24
Finished Aug 10 04:39:02 PM PDT 24
Peak memory 248156 kb
Host smart-1bd62c1b-67f5-437b-b593-d930ac4c5924
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3619492581 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.3619492581
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.1341387150
Short name T45
Test name
Test status
Simulation time 6883383854 ps
CPU time 112.07 seconds
Started Aug 10 04:38:54 PM PDT 24
Finished Aug 10 04:40:46 PM PDT 24
Peak memory 256036 kb
Host smart-fcba2068-e015-4e21-93e7-d10a5b4058ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13413
87150 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.1341387150
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.503004338
Short name T83
Test name
Test status
Simulation time 280131909 ps
CPU time 10.42 seconds
Started Aug 10 04:38:45 PM PDT 24
Finished Aug 10 04:38:55 PM PDT 24
Peak memory 247800 kb
Host smart-1ae2f5c1-da09-4403-809c-32885f703406
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50300
4338 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.503004338
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.2227785669
Short name T429
Test name
Test status
Simulation time 21989284690 ps
CPU time 1113.92 seconds
Started Aug 10 04:38:46 PM PDT 24
Finished Aug 10 04:57:20 PM PDT 24
Peak memory 282604 kb
Host smart-7f364407-24b4-4ca6-9c9b-b7424857c01d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2227785669 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.2227785669
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.1980730337
Short name T686
Test name
Test status
Simulation time 3714776082 ps
CPU time 52.74 seconds
Started Aug 10 04:38:55 PM PDT 24
Finished Aug 10 04:39:48 PM PDT 24
Peak memory 248328 kb
Host smart-2fab5ff2-824c-4eea-84d4-f3cf19252c28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19807
30337 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.1980730337
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.3406623858
Short name T114
Test name
Test status
Simulation time 2537024255 ps
CPU time 39.5 seconds
Started Aug 10 04:38:46 PM PDT 24
Finished Aug 10 04:39:26 PM PDT 24
Peak memory 255992 kb
Host smart-90b07ee1-e181-40da-a0da-4a001f6d6cac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34066
23858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.3406623858
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.1419667412
Short name T476
Test name
Test status
Simulation time 2856638819 ps
CPU time 47.14 seconds
Started Aug 10 04:39:07 PM PDT 24
Finished Aug 10 04:39:54 PM PDT 24
Peak memory 248208 kb
Host smart-7e7a6bc7-2d5f-4702-ba86-decdad0921cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14196
67412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.1419667412
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.841336932
Short name T638
Test name
Test status
Simulation time 698692055 ps
CPU time 30.42 seconds
Started Aug 10 04:38:59 PM PDT 24
Finished Aug 10 04:39:30 PM PDT 24
Peak memory 256472 kb
Host smart-24ce9696-1932-4094-9273-dcaa8d697f45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84133
6932 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.841336932
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.1378348677
Short name T465
Test name
Test status
Simulation time 27070961710 ps
CPU time 1337.94 seconds
Started Aug 10 04:38:54 PM PDT 24
Finished Aug 10 05:01:17 PM PDT 24
Peak memory 281012 kb
Host smart-35a4b12d-045a-4eff-a71a-d1a05070e20d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1378348677 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_han
dler_stress_all.1378348677
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all_with_rand_reset.498865839
Short name T622
Test name
Test status
Simulation time 84848483888 ps
CPU time 2035.02 seconds
Started Aug 10 04:38:53 PM PDT 24
Finished Aug 10 05:12:48 PM PDT 24
Peak memory 305000 kb
Host smart-aae60bbb-de75-4c55-8222-42fe4cd6df55
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=498865839 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 1.alert_handler_stress_all_with_rand_reset.498865839
Directory /workspace/1.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.2997109505
Short name T209
Test name
Test status
Simulation time 102520080 ps
CPU time 2.97 seconds
Started Aug 10 04:39:19 PM PDT 24
Finished Aug 10 04:39:22 PM PDT 24
Peak memory 248512 kb
Host smart-dd506de0-07e0-4c4a-af65-d69c09175ca4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2997109505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.2997109505
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.631113554
Short name T501
Test name
Test status
Simulation time 6400235151 ps
CPU time 662.3 seconds
Started Aug 10 04:39:06 PM PDT 24
Finished Aug 10 04:50:08 PM PDT 24
Peak memory 264636 kb
Host smart-72b90a77-ff33-413b-969d-ed0ef4daa18b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=631113554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.631113554
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.3068052854
Short name T386
Test name
Test status
Simulation time 2059001761 ps
CPU time 44.84 seconds
Started Aug 10 04:39:15 PM PDT 24
Finished Aug 10 04:40:00 PM PDT 24
Peak memory 248284 kb
Host smart-5a051ae9-7e12-42ec-91da-94710a7bfa15
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3068052854 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.3068052854
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.2993491047
Short name T403
Test name
Test status
Simulation time 464279840 ps
CPU time 27.3 seconds
Started Aug 10 04:39:07 PM PDT 24
Finished Aug 10 04:39:35 PM PDT 24
Peak memory 247536 kb
Host smart-5db96de8-e4f7-4ea7-8d84-280d328c1b98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29934
91047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.2993491047
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.3248244530
Short name T380
Test name
Test status
Simulation time 121538967 ps
CPU time 6.07 seconds
Started Aug 10 04:39:14 PM PDT 24
Finished Aug 10 04:39:25 PM PDT 24
Peak memory 248124 kb
Host smart-107615d9-d55a-48ee-9b3c-7fda3adc46f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32482
44530 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.3248244530
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.3014942060
Short name T116
Test name
Test status
Simulation time 34555586750 ps
CPU time 2373.11 seconds
Started Aug 10 04:39:01 PM PDT 24
Finished Aug 10 05:18:34 PM PDT 24
Peak memory 288052 kb
Host smart-a71258ef-5af6-40d8-ac54-09667c9ca4e0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3014942060 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.3014942060
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.3470698141
Short name T540
Test name
Test status
Simulation time 98624408 ps
CPU time 9.34 seconds
Started Aug 10 04:39:12 PM PDT 24
Finished Aug 10 04:39:21 PM PDT 24
Peak memory 248224 kb
Host smart-48bf3b3e-3cce-4bc6-ba5e-f347a57244f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34706
98141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.3470698141
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.3616603732
Short name T446
Test name
Test status
Simulation time 1060136816 ps
CPU time 31.98 seconds
Started Aug 10 04:39:15 PM PDT 24
Finished Aug 10 04:39:47 PM PDT 24
Peak memory 256248 kb
Host smart-fd57d22c-bc0a-4168-b026-e494581ca4bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36166
03732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.3616603732
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.1786134979
Short name T710
Test name
Test status
Simulation time 435553232 ps
CPU time 27.09 seconds
Started Aug 10 04:39:13 PM PDT 24
Finished Aug 10 04:39:40 PM PDT 24
Peak memory 247756 kb
Host smart-6d4b9d25-9163-4915-adc3-96d28ccca235
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17861
34979 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.1786134979
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.2567136071
Short name T404
Test name
Test status
Simulation time 310363968 ps
CPU time 11.15 seconds
Started Aug 10 04:39:08 PM PDT 24
Finished Aug 10 04:39:20 PM PDT 24
Peak memory 248164 kb
Host smart-70bf915a-0520-4b63-a94b-1dd5ce9decb1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25671
36071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.2567136071
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.2407969406
Short name T499
Test name
Test status
Simulation time 4386633732 ps
CPU time 257.79 seconds
Started Aug 10 04:39:08 PM PDT 24
Finished Aug 10 04:43:26 PM PDT 24
Peak memory 256476 kb
Host smart-94edea6c-56b3-4b58-8789-c3315264171e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2407969406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_ha
ndler_stress_all.2407969406
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.466380588
Short name T119
Test name
Test status
Simulation time 17780172025 ps
CPU time 844.95 seconds
Started Aug 10 04:39:18 PM PDT 24
Finished Aug 10 04:53:24 PM PDT 24
Peak memory 272820 kb
Host smart-b85cd73b-0a1a-43f9-8e29-4aff540f5e45
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=466380588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.466380588
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.2505829372
Short name T428
Test name
Test status
Simulation time 366337390 ps
CPU time 9.97 seconds
Started Aug 10 04:39:13 PM PDT 24
Finished Aug 10 04:39:23 PM PDT 24
Peak memory 248108 kb
Host smart-c03f4351-0bf4-4980-92d3-c1a6b4775bd8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2505829372 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.2505829372
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.2762536633
Short name T423
Test name
Test status
Simulation time 209893850 ps
CPU time 12.22 seconds
Started Aug 10 04:39:21 PM PDT 24
Finished Aug 10 04:39:33 PM PDT 24
Peak memory 254384 kb
Host smart-4bfa2b57-2386-4aff-8451-a8bd1b58008a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27625
36633 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.2762536633
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.4014109952
Short name T371
Test name
Test status
Simulation time 179412941 ps
CPU time 12.01 seconds
Started Aug 10 04:39:06 PM PDT 24
Finished Aug 10 04:39:18 PM PDT 24
Peak memory 247920 kb
Host smart-e4f5f57c-44f1-495d-9386-a999d92c5d5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40141
09952 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.4014109952
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.2082209282
Short name T231
Test name
Test status
Simulation time 12856729382 ps
CPU time 1154.48 seconds
Started Aug 10 04:39:17 PM PDT 24
Finished Aug 10 04:58:31 PM PDT 24
Peak memory 281032 kb
Host smart-a982b433-cffd-4a64-8998-875a77ab3521
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2082209282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.2082209282
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.2211386879
Short name T486
Test name
Test status
Simulation time 54135023063 ps
CPU time 1418.59 seconds
Started Aug 10 04:39:12 PM PDT 24
Finished Aug 10 05:02:51 PM PDT 24
Peak memory 267724 kb
Host smart-c969a5fe-dab9-4220-96d7-eff22e8f2eaf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211386879 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.2211386879
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.1228389533
Short name T319
Test name
Test status
Simulation time 58562559293 ps
CPU time 279.43 seconds
Started Aug 10 04:39:09 PM PDT 24
Finished Aug 10 04:43:49 PM PDT 24
Peak memory 254244 kb
Host smart-a7c84160-0155-45ff-aaf7-4ede45082a24
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1228389533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.1228389533
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.3653744524
Short name T613
Test name
Test status
Simulation time 1828098654 ps
CPU time 57 seconds
Started Aug 10 04:39:23 PM PDT 24
Finished Aug 10 04:40:21 PM PDT 24
Peak memory 255620 kb
Host smart-ddd95035-82b5-4111-90d0-ece7e615ede0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36537
44524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.3653744524
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.2157731464
Short name T12
Test name
Test status
Simulation time 5122514493 ps
CPU time 73.01 seconds
Started Aug 10 04:39:14 PM PDT 24
Finished Aug 10 04:40:27 PM PDT 24
Peak memory 248168 kb
Host smart-e334e2ca-131e-4158-8ee1-409e912bdedd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21577
31464 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.2157731464
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.811179755
Short name T524
Test name
Test status
Simulation time 437774083 ps
CPU time 8.3 seconds
Started Aug 10 04:39:07 PM PDT 24
Finished Aug 10 04:39:16 PM PDT 24
Peak memory 248164 kb
Host smart-07ee522a-0b0c-43a0-bcd0-c4ffaf5bf5ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81117
9755 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.811179755
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.4231604039
Short name T681
Test name
Test status
Simulation time 72023238412 ps
CPU time 2535.78 seconds
Started Aug 10 04:39:07 PM PDT 24
Finished Aug 10 05:21:23 PM PDT 24
Peak memory 288560 kb
Host smart-d212855c-5d05-415b-a241-a30a3782cf6f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4231604039 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_ha
ndler_stress_all.4231604039
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all_with_rand_reset.3142036222
Short name T288
Test name
Test status
Simulation time 109063928117 ps
CPU time 4777.99 seconds
Started Aug 10 04:39:09 PM PDT 24
Finished Aug 10 05:58:47 PM PDT 24
Peak memory 338332 kb
Host smart-48373ecc-9c7d-40ef-a4c9-2fbd67a02116
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142036222 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.alert_handler_stress_all_with_rand_reset.3142036222
Directory /workspace/11.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.372380084
Short name T204
Test name
Test status
Simulation time 59181238 ps
CPU time 3.23 seconds
Started Aug 10 04:39:15 PM PDT 24
Finished Aug 10 04:39:18 PM PDT 24
Peak memory 248492 kb
Host smart-28d8e246-bf34-4650-901e-4e7cac988876
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=372380084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.372380084
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.3078831985
Short name T37
Test name
Test status
Simulation time 20407343232 ps
CPU time 1106.47 seconds
Started Aug 10 04:39:06 PM PDT 24
Finished Aug 10 04:57:33 PM PDT 24
Peak memory 264660 kb
Host smart-84ef5f41-b1aa-419c-8ec3-5f70c56a272a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3078831985 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.3078831985
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.2944141437
Short name T389
Test name
Test status
Simulation time 3140026861 ps
CPU time 36.41 seconds
Started Aug 10 04:39:02 PM PDT 24
Finished Aug 10 04:39:38 PM PDT 24
Peak memory 248212 kb
Host smart-e6f9047c-bc3b-4a6a-9884-4659d27cb026
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2944141437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.2944141437
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.430445429
Short name T225
Test name
Test status
Simulation time 1119514590 ps
CPU time 66.92 seconds
Started Aug 10 04:39:01 PM PDT 24
Finished Aug 10 04:40:08 PM PDT 24
Peak memory 256372 kb
Host smart-658ad247-aa08-4dd0-b0ee-774dfec4458e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43044
5429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.430445429
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.1928467537
Short name T294
Test name
Test status
Simulation time 170471327 ps
CPU time 13.61 seconds
Started Aug 10 04:39:14 PM PDT 24
Finished Aug 10 04:39:28 PM PDT 24
Peak memory 256364 kb
Host smart-558b07c8-65b2-4984-a865-4e9c1ea6bd35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19284
67537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.1928467537
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.134814991
Short name T691
Test name
Test status
Simulation time 6571277924 ps
CPU time 661.32 seconds
Started Aug 10 04:39:05 PM PDT 24
Finished Aug 10 04:50:07 PM PDT 24
Peak memory 272080 kb
Host smart-9420bccb-1980-405f-8e84-d4943f1fbe61
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134814991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.134814991
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.2506121723
Short name T219
Test name
Test status
Simulation time 27086564481 ps
CPU time 1417.35 seconds
Started Aug 10 04:39:20 PM PDT 24
Finished Aug 10 05:02:58 PM PDT 24
Peak memory 264740 kb
Host smart-95e53b71-83ea-463f-bd79-70af1770d928
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2506121723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.2506121723
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.3603740655
Short name T493
Test name
Test status
Simulation time 1613151897 ps
CPU time 43.01 seconds
Started Aug 10 04:38:59 PM PDT 24
Finished Aug 10 04:39:42 PM PDT 24
Peak memory 248216 kb
Host smart-1642e21c-4289-4b8d-8164-d57637542547
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36037
40655 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.3603740655
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.1836084700
Short name T523
Test name
Test status
Simulation time 3195038873 ps
CPU time 13.41 seconds
Started Aug 10 04:39:15 PM PDT 24
Finished Aug 10 04:39:29 PM PDT 24
Peak memory 254628 kb
Host smart-39558811-b94a-4b44-9209-6c4277094033
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18360
84700 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.1836084700
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.3078887325
Short name T39
Test name
Test status
Simulation time 810402294 ps
CPU time 51.1 seconds
Started Aug 10 04:39:07 PM PDT 24
Finished Aug 10 04:39:58 PM PDT 24
Peak memory 256232 kb
Host smart-930c5a59-dd7d-47f2-a310-db09b4c3cf94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30788
87325 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.3078887325
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.2096805307
Short name T566
Test name
Test status
Simulation time 18649706614 ps
CPU time 1010.29 seconds
Started Aug 10 04:39:14 PM PDT 24
Finished Aug 10 04:56:04 PM PDT 24
Peak memory 288512 kb
Host smart-045b62c1-a3fc-47bf-b6a9-1afa30326088
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2096805307 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_ha
ndler_stress_all.2096805307
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all_with_rand_reset.3176643767
Short name T539
Test name
Test status
Simulation time 53499911683 ps
CPU time 1821.98 seconds
Started Aug 10 04:39:04 PM PDT 24
Finished Aug 10 05:09:26 PM PDT 24
Peak memory 289300 kb
Host smart-0002ba5c-5ded-4775-a221-13b733e03f21
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3176643767 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.alert_handler_stress_all_with_rand_reset.3176643767
Directory /workspace/12.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.1391333673
Short name T215
Test name
Test status
Simulation time 68268023 ps
CPU time 2.96 seconds
Started Aug 10 04:39:26 PM PDT 24
Finished Aug 10 04:39:29 PM PDT 24
Peak memory 248436 kb
Host smart-340dbf5b-350a-49e7-9e3b-07e409643084
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1391333673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.1391333673
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.2872176797
Short name T584
Test name
Test status
Simulation time 120438401584 ps
CPU time 2112.76 seconds
Started Aug 10 04:39:34 PM PDT 24
Finished Aug 10 05:14:47 PM PDT 24
Peak memory 281000 kb
Host smart-57d8c023-0e0d-44be-8d5e-f566c88eab5d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872176797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.2872176797
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.2462231274
Short name T463
Test name
Test status
Simulation time 146436567 ps
CPU time 9.9 seconds
Started Aug 10 04:39:24 PM PDT 24
Finished Aug 10 04:39:34 PM PDT 24
Peak memory 248104 kb
Host smart-879498f3-e570-49a4-9df3-c00d093e3a0c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2462231274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.2462231274
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.1829821246
Short name T627
Test name
Test status
Simulation time 5667288603 ps
CPU time 195.5 seconds
Started Aug 10 04:39:05 PM PDT 24
Finished Aug 10 04:42:21 PM PDT 24
Peak memory 256004 kb
Host smart-a72dfe3b-ef6d-49dd-8527-95f80c08e9f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18298
21246 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.1829821246
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.818361760
Short name T552
Test name
Test status
Simulation time 371405394 ps
CPU time 31.5 seconds
Started Aug 10 04:39:16 PM PDT 24
Finished Aug 10 04:39:48 PM PDT 24
Peak memory 248212 kb
Host smart-b01f6660-b20d-44fc-b3dc-002610591d3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81836
1760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.818361760
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.2892955212
Short name T679
Test name
Test status
Simulation time 63963177798 ps
CPU time 1911.9 seconds
Started Aug 10 04:39:18 PM PDT 24
Finished Aug 10 05:11:10 PM PDT 24
Peak memory 284820 kb
Host smart-a7c9d33a-d9a3-429e-891c-4f35c1b060c8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2892955212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.2892955212
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.1619666877
Short name T538
Test name
Test status
Simulation time 152251981240 ps
CPU time 1650.48 seconds
Started Aug 10 04:39:18 PM PDT 24
Finished Aug 10 05:06:49 PM PDT 24
Peak memory 272312 kb
Host smart-b2f2cb46-0026-47ec-8482-0a4dbb748eef
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1619666877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.1619666877
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.4025610498
Short name T551
Test name
Test status
Simulation time 6266376501 ps
CPU time 249.41 seconds
Started Aug 10 04:39:22 PM PDT 24
Finished Aug 10 04:43:32 PM PDT 24
Peak memory 254896 kb
Host smart-b31c0158-3fd1-4c22-8f08-9dacffb3f5a1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025610498 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.4025610498
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.2751277550
Short name T511
Test name
Test status
Simulation time 68155470 ps
CPU time 3.46 seconds
Started Aug 10 04:39:18 PM PDT 24
Finished Aug 10 04:39:21 PM PDT 24
Peak memory 248128 kb
Host smart-c8469021-69d6-40c8-b4a3-975252c9a8cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27512
77550 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.2751277550
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.3426930972
Short name T684
Test name
Test status
Simulation time 1126763484 ps
CPU time 31.8 seconds
Started Aug 10 04:39:07 PM PDT 24
Finished Aug 10 04:39:39 PM PDT 24
Peak memory 247752 kb
Host smart-b9882b63-2d96-43ec-b413-3274d7d9ed7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34269
30972 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.3426930972
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.3429294628
Short name T690
Test name
Test status
Simulation time 495211742 ps
CPU time 13.96 seconds
Started Aug 10 04:39:26 PM PDT 24
Finished Aug 10 04:39:40 PM PDT 24
Peak memory 255688 kb
Host smart-33f70d47-b045-4491-b2c6-c0bc1ff6f5d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34292
94628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.3429294628
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.181358212
Short name T500
Test name
Test status
Simulation time 1274864619 ps
CPU time 36.74 seconds
Started Aug 10 04:39:20 PM PDT 24
Finished Aug 10 04:39:57 PM PDT 24
Peak memory 248148 kb
Host smart-854be5f0-fc3e-4d89-891d-151e610e33ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18135
8212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.181358212
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.2499147182
Short name T616
Test name
Test status
Simulation time 52791475185 ps
CPU time 1493.42 seconds
Started Aug 10 04:39:25 PM PDT 24
Finished Aug 10 05:04:18 PM PDT 24
Peak memory 282680 kb
Host smart-2a39036e-3ba5-4ba3-b744-527774e456e0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499147182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_ha
ndler_stress_all.2499147182
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.3197382742
Short name T438
Test name
Test status
Simulation time 62844301063 ps
CPU time 1545.43 seconds
Started Aug 10 04:39:30 PM PDT 24
Finished Aug 10 05:05:16 PM PDT 24
Peak memory 272500 kb
Host smart-c621c8e5-d4be-47ad-a0f4-f01c9482c7c6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3197382742 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.3197382742
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.3548111343
Short name T362
Test name
Test status
Simulation time 378607240 ps
CPU time 19.28 seconds
Started Aug 10 04:39:18 PM PDT 24
Finished Aug 10 04:39:38 PM PDT 24
Peak memory 248532 kb
Host smart-b9aaf92c-0cf5-4f6d-b68d-7c5827e96209
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3548111343 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.3548111343
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.2818663875
Short name T594
Test name
Test status
Simulation time 8071752726 ps
CPU time 217.33 seconds
Started Aug 10 04:39:21 PM PDT 24
Finished Aug 10 04:42:59 PM PDT 24
Peak memory 255812 kb
Host smart-af90a4ae-2576-4c7f-8725-2101632e7da9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28186
63875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.2818663875
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.1791661854
Short name T592
Test name
Test status
Simulation time 1146990291 ps
CPU time 31.42 seconds
Started Aug 10 04:39:26 PM PDT 24
Finished Aug 10 04:39:57 PM PDT 24
Peak memory 247812 kb
Host smart-657bf3de-e398-43d7-96e5-6d2ebc65f015
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17916
61854 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.1791661854
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.2077810334
Short name T424
Test name
Test status
Simulation time 186764074657 ps
CPU time 1077.25 seconds
Started Aug 10 04:39:27 PM PDT 24
Finished Aug 10 04:57:24 PM PDT 24
Peak memory 272072 kb
Host smart-59ca6467-1367-47b7-b30e-663592a78b13
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2077810334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.2077810334
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.1534067094
Short name T628
Test name
Test status
Simulation time 30035479689 ps
CPU time 1381.28 seconds
Started Aug 10 04:39:31 PM PDT 24
Finished Aug 10 05:02:33 PM PDT 24
Peak memory 281000 kb
Host smart-737f99f2-2852-4e27-8f3f-4095c8ffc98a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1534067094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.1534067094
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.3590667975
Short name T313
Test name
Test status
Simulation time 32838208735 ps
CPU time 204.86 seconds
Started Aug 10 04:39:15 PM PDT 24
Finished Aug 10 04:42:40 PM PDT 24
Peak memory 248332 kb
Host smart-a19e62db-3624-4e04-bf05-81811c613a43
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3590667975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.3590667975
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.82731180
Short name T502
Test name
Test status
Simulation time 2075540391 ps
CPU time 27.19 seconds
Started Aug 10 04:39:25 PM PDT 24
Finished Aug 10 04:39:52 PM PDT 24
Peak memory 255916 kb
Host smart-12960912-33e8-48c4-8ccd-8447e54b5150
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82731
180 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.82731180
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.898750140
Short name T113
Test name
Test status
Simulation time 1751094311 ps
CPU time 20.16 seconds
Started Aug 10 04:39:30 PM PDT 24
Finished Aug 10 04:39:50 PM PDT 24
Peak memory 247648 kb
Host smart-641fc2a5-b898-4aee-835e-0c0c4e988e87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89875
0140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.898750140
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.1919210514
Short name T504
Test name
Test status
Simulation time 2860758666 ps
CPU time 31.82 seconds
Started Aug 10 04:39:18 PM PDT 24
Finished Aug 10 04:39:50 PM PDT 24
Peak memory 247772 kb
Host smart-adebeca4-b7c5-49b2-82ee-f9593e5c089b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19192
10514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.1919210514
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.3206658976
Short name T479
Test name
Test status
Simulation time 343485012 ps
CPU time 14.08 seconds
Started Aug 10 04:39:30 PM PDT 24
Finished Aug 10 04:39:44 PM PDT 24
Peak memory 255536 kb
Host smart-210ae752-9c3d-4337-890b-ee7e15928999
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32066
58976 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.3206658976
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.1732257417
Short name T586
Test name
Test status
Simulation time 53018501090 ps
CPU time 1251.93 seconds
Started Aug 10 04:39:19 PM PDT 24
Finished Aug 10 05:00:11 PM PDT 24
Peak memory 287124 kb
Host smart-967411ae-1024-441f-bc3d-f2f523f86b94
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1732257417 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_ha
ndler_stress_all.1732257417
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.1994423531
Short name T210
Test name
Test status
Simulation time 20925870 ps
CPU time 2.9 seconds
Started Aug 10 04:39:15 PM PDT 24
Finished Aug 10 04:39:18 PM PDT 24
Peak memory 248436 kb
Host smart-6b621b38-7e26-4d78-9416-d2729ec27237
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1994423531 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.1994423531
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.3339419938
Short name T280
Test name
Test status
Simulation time 89920346663 ps
CPU time 1346.62 seconds
Started Aug 10 04:39:22 PM PDT 24
Finished Aug 10 05:01:48 PM PDT 24
Peak memory 271164 kb
Host smart-3ce2acb8-d3c7-4e10-ab1c-ec73034fff90
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3339419938 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.3339419938
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.2445160957
Short name T503
Test name
Test status
Simulation time 1171000128 ps
CPU time 49.21 seconds
Started Aug 10 04:39:23 PM PDT 24
Finished Aug 10 04:40:13 PM PDT 24
Peak memory 248148 kb
Host smart-fd0e07c4-e650-4809-9c84-acb9416ded15
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2445160957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.2445160957
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.1878910574
Short name T366
Test name
Test status
Simulation time 3458958222 ps
CPU time 192.3 seconds
Started Aug 10 04:39:36 PM PDT 24
Finished Aug 10 04:42:48 PM PDT 24
Peak memory 255592 kb
Host smart-f66e6a59-687c-4769-9679-baa4535ab7db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18789
10574 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.1878910574
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.2666007120
Short name T382
Test name
Test status
Simulation time 131162852 ps
CPU time 14.34 seconds
Started Aug 10 04:39:15 PM PDT 24
Finished Aug 10 04:39:30 PM PDT 24
Peak memory 255688 kb
Host smart-00c8d283-b00f-4b5e-9c2e-c7e671396013
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26660
07120 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.2666007120
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.3760924201
Short name T617
Test name
Test status
Simulation time 134957839404 ps
CPU time 2258.91 seconds
Started Aug 10 04:39:15 PM PDT 24
Finished Aug 10 05:16:55 PM PDT 24
Peak memory 280472 kb
Host smart-e8c202ac-1fc9-43ab-ad20-24e5de4c211b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3760924201 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.3760924201
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.3974823431
Short name T555
Test name
Test status
Simulation time 43465858750 ps
CPU time 1205.43 seconds
Started Aug 10 04:39:26 PM PDT 24
Finished Aug 10 04:59:31 PM PDT 24
Peak memory 282840 kb
Host smart-34287a82-a588-40f2-895c-16750e765273
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3974823431 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.3974823431
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.3054476542
Short name T655
Test name
Test status
Simulation time 72910135993 ps
CPU time 728.64 seconds
Started Aug 10 04:39:25 PM PDT 24
Finished Aug 10 04:51:34 PM PDT 24
Peak memory 248236 kb
Host smart-5734a1a6-9799-4a9b-b98d-9a7b8cc5e3ba
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3054476542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.3054476542
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.2467968996
Short name T706
Test name
Test status
Simulation time 839176998 ps
CPU time 69.24 seconds
Started Aug 10 04:39:30 PM PDT 24
Finished Aug 10 04:40:39 PM PDT 24
Peak memory 248164 kb
Host smart-d3e24fe0-e439-46e0-bfd8-9d98a21b30f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24679
68996 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.2467968996
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.3863524791
Short name T521
Test name
Test status
Simulation time 918414167 ps
CPU time 32.29 seconds
Started Aug 10 04:39:29 PM PDT 24
Finished Aug 10 04:40:01 PM PDT 24
Peak memory 255468 kb
Host smart-ba582383-9581-48c8-bfc8-cc647e117ac6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38635
24791 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.3863524791
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.1908028369
Short name T567
Test name
Test status
Simulation time 92504852 ps
CPU time 7.63 seconds
Started Aug 10 04:39:22 PM PDT 24
Finished Aug 10 04:39:30 PM PDT 24
Peak memory 248336 kb
Host smart-f5083f02-1021-4815-a22e-c9223668a0cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19080
28369 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.1908028369
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.1656336565
Short name T595
Test name
Test status
Simulation time 2967876424 ps
CPU time 45.14 seconds
Started Aug 10 04:39:29 PM PDT 24
Finished Aug 10 04:40:14 PM PDT 24
Peak memory 248204 kb
Host smart-104a2890-bec4-409b-af75-b51dc93ac934
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16563
36565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.1656336565
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all_with_rand_reset.1819632616
Short name T68
Test name
Test status
Simulation time 35879167437 ps
CPU time 3764.18 seconds
Started Aug 10 04:39:25 PM PDT 24
Finished Aug 10 05:42:10 PM PDT 24
Peak memory 321908 kb
Host smart-8023a2fc-cdd4-4f6b-af84-fa6572adba4d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1819632616 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.alert_handler_stress_all_with_rand_reset.1819632616
Directory /workspace/15.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.4090076090
Short name T201
Test name
Test status
Simulation time 34719045 ps
CPU time 2.44 seconds
Started Aug 10 04:39:35 PM PDT 24
Finished Aug 10 04:39:38 PM PDT 24
Peak memory 248500 kb
Host smart-d34631cb-bb35-4f07-ad2a-2fd56ef7aedd
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4090076090 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.4090076090
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.1577445473
Short name T530
Test name
Test status
Simulation time 17200217833 ps
CPU time 1185.7 seconds
Started Aug 10 04:39:25 PM PDT 24
Finished Aug 10 04:59:11 PM PDT 24
Peak memory 272432 kb
Host smart-ab0d0728-61a0-4808-8e3b-d386df6e2fea
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1577445473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.1577445473
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.1291223853
Short name T417
Test name
Test status
Simulation time 3858136151 ps
CPU time 39.45 seconds
Started Aug 10 04:39:26 PM PDT 24
Finished Aug 10 04:40:06 PM PDT 24
Peak memory 248272 kb
Host smart-c1f2fe62-4850-40ff-8e27-31e2e3731599
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1291223853 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.1291223853
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.1349782334
Short name T509
Test name
Test status
Simulation time 2209356003 ps
CPU time 96.58 seconds
Started Aug 10 04:39:17 PM PDT 24
Finished Aug 10 04:40:53 PM PDT 24
Peak memory 256460 kb
Host smart-57572609-9ea8-4e31-92d6-7d58fbe5cde9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13497
82334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.1349782334
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.3513512021
Short name T699
Test name
Test status
Simulation time 2729434473 ps
CPU time 22.86 seconds
Started Aug 10 04:39:16 PM PDT 24
Finished Aug 10 04:39:39 PM PDT 24
Peak memory 255768 kb
Host smart-0b2fab76-762d-4ab2-b3dd-776f63cb0acf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35135
12021 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.3513512021
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.2529649879
Short name T337
Test name
Test status
Simulation time 31397243926 ps
CPU time 1927.58 seconds
Started Aug 10 04:39:19 PM PDT 24
Finished Aug 10 05:11:26 PM PDT 24
Peak memory 284468 kb
Host smart-a3fcaab7-7e9f-45ed-a7d6-5f08fc7e2965
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2529649879 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.2529649879
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.1986184983
Short name T467
Test name
Test status
Simulation time 11800236190 ps
CPU time 1021.41 seconds
Started Aug 10 04:39:31 PM PDT 24
Finished Aug 10 04:56:33 PM PDT 24
Peak memory 283156 kb
Host smart-7c1a0434-1f95-4398-8bdd-e076a2dd9523
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1986184983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.1986184983
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.3668424435
Short name T308
Test name
Test status
Simulation time 23229531431 ps
CPU time 243.97 seconds
Started Aug 10 04:39:20 PM PDT 24
Finished Aug 10 04:43:24 PM PDT 24
Peak memory 254912 kb
Host smart-15eeb842-8a84-41ff-8e80-47cca5683807
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3668424435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.3668424435
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.1482879129
Short name T469
Test name
Test status
Simulation time 333274068 ps
CPU time 22.17 seconds
Started Aug 10 04:39:29 PM PDT 24
Finished Aug 10 04:39:52 PM PDT 24
Peak memory 248232 kb
Host smart-8ba54e3f-c1a3-44f2-b448-93868b4c93aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14828
79129 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.1482879129
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.1579549827
Short name T611
Test name
Test status
Simulation time 445355996 ps
CPU time 17.01 seconds
Started Aug 10 04:39:21 PM PDT 24
Finished Aug 10 04:39:38 PM PDT 24
Peak memory 247676 kb
Host smart-d71c1de9-3416-4fc7-8f2e-444cfb305874
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15795
49827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.1579549827
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.1749004214
Short name T264
Test name
Test status
Simulation time 95456715 ps
CPU time 8.67 seconds
Started Aug 10 04:39:21 PM PDT 24
Finished Aug 10 04:39:29 PM PDT 24
Peak memory 247608 kb
Host smart-93bef5e0-d8fa-4b83-9b8d-85a0a38bb7ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17490
04214 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.1749004214
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.498668512
Short name T19
Test name
Test status
Simulation time 3334720444 ps
CPU time 42.75 seconds
Started Aug 10 04:39:23 PM PDT 24
Finished Aug 10 04:40:06 PM PDT 24
Peak memory 256476 kb
Host smart-c924ba95-922a-4a76-bedc-98c5d064520e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49866
8512 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.498668512
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.4185567344
Short name T598
Test name
Test status
Simulation time 11540843278 ps
CPU time 702.35 seconds
Started Aug 10 04:39:18 PM PDT 24
Finished Aug 10 04:51:00 PM PDT 24
Peak memory 269548 kb
Host smart-1cc17c6f-55cf-457d-bf50-eb83385eb2a0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185567344 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_ha
ndler_stress_all.4185567344
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all_with_rand_reset.2236068753
Short name T676
Test name
Test status
Simulation time 24123000830 ps
CPU time 2728.93 seconds
Started Aug 10 04:39:17 PM PDT 24
Finished Aug 10 05:24:46 PM PDT 24
Peak memory 305788 kb
Host smart-9cf0dfbe-a2a0-4054-a5b8-41f552649eb8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2236068753 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.alert_handler_stress_all_with_rand_reset.2236068753
Directory /workspace/16.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.10465272
Short name T199
Test name
Test status
Simulation time 15685470 ps
CPU time 3.15 seconds
Started Aug 10 04:39:29 PM PDT 24
Finished Aug 10 04:39:33 PM PDT 24
Peak memory 248508 kb
Host smart-c6dcfe5e-3037-4056-9742-5913348de87f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=10465272 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.10465272
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.1061152084
Short name T462
Test name
Test status
Simulation time 27334130881 ps
CPU time 1451.58 seconds
Started Aug 10 04:39:35 PM PDT 24
Finished Aug 10 05:03:47 PM PDT 24
Peak memory 272376 kb
Host smart-09498207-b026-4eb3-a7be-868b172d35ac
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061152084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.1061152084
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.4215687843
Short name T450
Test name
Test status
Simulation time 1994720133 ps
CPU time 22.52 seconds
Started Aug 10 04:39:26 PM PDT 24
Finished Aug 10 04:39:49 PM PDT 24
Peak memory 248432 kb
Host smart-49314b8f-67f0-41e1-a3a2-5c4c3ef665d5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4215687843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.4215687843
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.3618096271
Short name T667
Test name
Test status
Simulation time 3979152949 ps
CPU time 225.11 seconds
Started Aug 10 04:39:17 PM PDT 24
Finished Aug 10 04:43:02 PM PDT 24
Peak memory 256444 kb
Host smart-e66369c3-34a0-4833-81d7-88690ebff830
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36180
96271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.3618096271
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.3595893995
Short name T101
Test name
Test status
Simulation time 373063187 ps
CPU time 26.25 seconds
Started Aug 10 04:39:25 PM PDT 24
Finished Aug 10 04:39:51 PM PDT 24
Peak memory 256336 kb
Host smart-bc83237c-4f3b-4829-90a3-98337401feb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35958
93995 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.3595893995
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.4038100899
Short name T518
Test name
Test status
Simulation time 36988367814 ps
CPU time 1486.63 seconds
Started Aug 10 04:39:35 PM PDT 24
Finished Aug 10 05:04:22 PM PDT 24
Peak memory 289068 kb
Host smart-2deb58cd-31df-47eb-a15d-f1d4abb8bc7a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038100899 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.4038100899
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.2658229417
Short name T51
Test name
Test status
Simulation time 144867119 ps
CPU time 15.92 seconds
Started Aug 10 04:39:16 PM PDT 24
Finished Aug 10 04:39:32 PM PDT 24
Peak memory 256380 kb
Host smart-f1517355-ea5b-4265-836e-a153cf9cfa34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26582
29417 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.2658229417
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.1625635996
Short name T680
Test name
Test status
Simulation time 501373260 ps
CPU time 16.06 seconds
Started Aug 10 04:39:31 PM PDT 24
Finished Aug 10 04:39:47 PM PDT 24
Peak memory 255272 kb
Host smart-7ffa41a3-16af-48aa-9f3f-883a1a653a39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16256
35996 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.1625635996
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.2953444208
Short name T581
Test name
Test status
Simulation time 1388563985 ps
CPU time 19.62 seconds
Started Aug 10 04:39:36 PM PDT 24
Finished Aug 10 04:39:56 PM PDT 24
Peak memory 256412 kb
Host smart-587888cd-fb9b-4691-bf27-4714ac1a72b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29534
44208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.2953444208
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.1680161039
Short name T560
Test name
Test status
Simulation time 30013600 ps
CPU time 3.01 seconds
Started Aug 10 04:39:24 PM PDT 24
Finished Aug 10 04:39:27 PM PDT 24
Peak memory 248252 kb
Host smart-a27db607-8531-4944-92b3-9fb0bbec6bb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16801
61039 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.1680161039
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.1191004137
Short name T272
Test name
Test status
Simulation time 14886205434 ps
CPU time 1270.96 seconds
Started Aug 10 04:39:25 PM PDT 24
Finished Aug 10 05:00:37 PM PDT 24
Peak memory 283860 kb
Host smart-6fffe730-556c-4f27-bbcb-2d81646c8e9a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1191004137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_ha
ndler_stress_all.1191004137
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.1164423549
Short name T200
Test name
Test status
Simulation time 30515752 ps
CPU time 3.32 seconds
Started Aug 10 04:39:25 PM PDT 24
Finished Aug 10 04:39:28 PM PDT 24
Peak memory 248392 kb
Host smart-379cd203-d83a-4bc2-a717-35c971f74e64
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1164423549 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.1164423549
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.255119289
Short name T618
Test name
Test status
Simulation time 38981738958 ps
CPU time 951.11 seconds
Started Aug 10 04:39:29 PM PDT 24
Finished Aug 10 04:55:20 PM PDT 24
Peak memory 284044 kb
Host smart-2ef07d43-44bc-42cd-8682-b1a51e1c5f7d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=255119289 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.255119289
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.1370375358
Short name T227
Test name
Test status
Simulation time 396190596 ps
CPU time 20.74 seconds
Started Aug 10 04:39:25 PM PDT 24
Finished Aug 10 04:39:46 PM PDT 24
Peak memory 248108 kb
Host smart-93ed57ec-6f12-42ea-8382-22b84dbef10d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1370375358 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.1370375358
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.3145499500
Short name T360
Test name
Test status
Simulation time 8928099171 ps
CPU time 115.61 seconds
Started Aug 10 04:39:41 PM PDT 24
Finished Aug 10 04:41:37 PM PDT 24
Peak memory 256260 kb
Host smart-dea1688f-d935-4a14-8804-fd070e70a534
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31454
99500 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.3145499500
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.1221770291
Short name T84
Test name
Test status
Simulation time 278416336 ps
CPU time 20.07 seconds
Started Aug 10 04:39:38 PM PDT 24
Finished Aug 10 04:39:58 PM PDT 24
Peak memory 248192 kb
Host smart-66c0cc14-c6b5-4045-be44-7fecc05c6b24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12217
70291 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.1221770291
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.1539478922
Short name T497
Test name
Test status
Simulation time 15719516402 ps
CPU time 1406.9 seconds
Started Aug 10 04:39:29 PM PDT 24
Finished Aug 10 05:02:57 PM PDT 24
Peak memory 287948 kb
Host smart-ae31b61c-8f9d-40f9-b107-1f9b2f88c633
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1539478922 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.1539478922
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.915490880
Short name T535
Test name
Test status
Simulation time 45779821489 ps
CPU time 1403.51 seconds
Started Aug 10 04:39:33 PM PDT 24
Finished Aug 10 05:02:56 PM PDT 24
Peak memory 287572 kb
Host smart-6c3ad8f6-533a-4d11-b847-68dc5e4fa8b6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=915490880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.915490880
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.87075142
Short name T316
Test name
Test status
Simulation time 17218677699 ps
CPU time 185.03 seconds
Started Aug 10 04:39:24 PM PDT 24
Finished Aug 10 04:42:29 PM PDT 24
Peak memory 255636 kb
Host smart-29859f7f-6816-4fe9-826c-36cb617cb93d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=87075142 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.87075142
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.4231020904
Short name T675
Test name
Test status
Simulation time 720911319 ps
CPU time 19.29 seconds
Started Aug 10 04:39:34 PM PDT 24
Finished Aug 10 04:39:53 PM PDT 24
Peak memory 256032 kb
Host smart-a1c1ab70-5dc9-4af1-b655-5c12922b4a54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42310
20904 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.4231020904
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.1761805476
Short name T435
Test name
Test status
Simulation time 1977000293 ps
CPU time 53.39 seconds
Started Aug 10 04:39:21 PM PDT 24
Finished Aug 10 04:40:15 PM PDT 24
Peak memory 256324 kb
Host smart-0e819cf1-4755-44c1-8d94-33311933a2ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17618
05476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.1761805476
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.2376165819
Short name T46
Test name
Test status
Simulation time 106169082 ps
CPU time 12.2 seconds
Started Aug 10 04:39:27 PM PDT 24
Finished Aug 10 04:39:39 PM PDT 24
Peak memory 247560 kb
Host smart-9a8bc8a1-7344-42ed-adef-cc3da5b514b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23761
65819 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.2376165819
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.1823613993
Short name T185
Test name
Test status
Simulation time 1639477596 ps
CPU time 34.23 seconds
Started Aug 10 04:39:29 PM PDT 24
Finished Aug 10 04:40:03 PM PDT 24
Peak memory 255684 kb
Host smart-3d1e25b8-b7dc-4d61-ae69-78f027493f3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18236
13993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.1823613993
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.78298868
Short name T525
Test name
Test status
Simulation time 17453223656 ps
CPU time 1147.84 seconds
Started Aug 10 04:39:24 PM PDT 24
Finished Aug 10 04:58:32 PM PDT 24
Peak memory 284932 kb
Host smart-9f03f8d2-9aa5-49bc-8eb2-957912d30c2e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78298868 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_hand
ler_stress_all.78298868
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all_with_rand_reset.2769060611
Short name T104
Test name
Test status
Simulation time 21423982244 ps
CPU time 245.13 seconds
Started Aug 10 04:39:34 PM PDT 24
Finished Aug 10 04:43:39 PM PDT 24
Peak memory 265908 kb
Host smart-7701a158-6185-4aaf-9aec-021a1043c7ca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2769060611 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.alert_handler_stress_all_with_rand_reset.2769060611
Directory /workspace/18.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.3431585355
Short name T213
Test name
Test status
Simulation time 83878130 ps
CPU time 2.49 seconds
Started Aug 10 04:39:35 PM PDT 24
Finished Aug 10 04:39:38 PM PDT 24
Peak memory 248580 kb
Host smart-429a2c15-4ec7-48e2-abed-64821c6ccc7d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3431585355 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.3431585355
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.444750507
Short name T697
Test name
Test status
Simulation time 96346467299 ps
CPU time 1713.72 seconds
Started Aug 10 04:39:43 PM PDT 24
Finished Aug 10 05:08:17 PM PDT 24
Peak memory 271136 kb
Host smart-a160597c-377d-474c-9369-5ba5a199a9b9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=444750507 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.444750507
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.4090690591
Short name T218
Test name
Test status
Simulation time 240416337 ps
CPU time 7.19 seconds
Started Aug 10 04:39:26 PM PDT 24
Finished Aug 10 04:39:33 PM PDT 24
Peak memory 248172 kb
Host smart-1ee7e537-eb64-409b-b287-1ba96d898b09
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4090690591 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.4090690591
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.2269341490
Short name T398
Test name
Test status
Simulation time 796428373 ps
CPU time 63.07 seconds
Started Aug 10 04:39:38 PM PDT 24
Finished Aug 10 04:40:42 PM PDT 24
Peak memory 255872 kb
Host smart-2851b5d1-47fd-4e24-b87d-777f2b229bd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22693
41490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.2269341490
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.2206597671
Short name T85
Test name
Test status
Simulation time 780191736 ps
CPU time 55.03 seconds
Started Aug 10 04:39:34 PM PDT 24
Finished Aug 10 04:40:29 PM PDT 24
Peak memory 254956 kb
Host smart-a7280e6a-0663-4782-87ed-c944a243e850
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22065
97671 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.2206597671
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.3405018884
Short name T238
Test name
Test status
Simulation time 128012076172 ps
CPU time 2085.95 seconds
Started Aug 10 04:39:38 PM PDT 24
Finished Aug 10 05:14:24 PM PDT 24
Peak memory 272832 kb
Host smart-3bb4c711-2f2b-480d-a17f-930988e01182
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3405018884 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.3405018884
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.4003778154
Short name T406
Test name
Test status
Simulation time 294576849079 ps
CPU time 1529.7 seconds
Started Aug 10 04:39:35 PM PDT 24
Finished Aug 10 05:05:05 PM PDT 24
Peak memory 286940 kb
Host smart-5c8c4bcf-3de3-4ef8-9652-b43553203f79
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4003778154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.4003778154
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.3607224185
Short name T188
Test name
Test status
Simulation time 568026899 ps
CPU time 6.46 seconds
Started Aug 10 04:39:23 PM PDT 24
Finished Aug 10 04:39:29 PM PDT 24
Peak memory 254152 kb
Host smart-d249215b-6cd1-4dff-9782-1216cdf72c1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36072
24185 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.3607224185
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.675315454
Short name T224
Test name
Test status
Simulation time 507070327 ps
CPU time 34.41 seconds
Started Aug 10 04:39:39 PM PDT 24
Finished Aug 10 04:40:14 PM PDT 24
Peak memory 247784 kb
Host smart-60c7e99a-6c25-4cb2-a270-abcd1ede5737
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67531
5454 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.675315454
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.1469594101
Short name T376
Test name
Test status
Simulation time 316515250 ps
CPU time 20.15 seconds
Started Aug 10 04:39:36 PM PDT 24
Finished Aug 10 04:39:56 PM PDT 24
Peak memory 255624 kb
Host smart-d8b642de-08e8-4d22-9082-163ab95630c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14695
94101 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.1469594101
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.2281822306
Short name T670
Test name
Test status
Simulation time 2609512698 ps
CPU time 38.28 seconds
Started Aug 10 04:39:20 PM PDT 24
Finished Aug 10 04:39:59 PM PDT 24
Peak memory 248744 kb
Host smart-4be6fb95-01c9-4a19-bd76-fc1cc4d369e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22818
22306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.2281822306
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all_with_rand_reset.3090277037
Short name T189
Test name
Test status
Simulation time 471493272851 ps
CPU time 10602.2 seconds
Started Aug 10 04:39:30 PM PDT 24
Finished Aug 10 07:36:13 PM PDT 24
Peak memory 403080 kb
Host smart-81a77b4c-201d-4c07-a5a7-4e9ca032f1e3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3090277037 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.alert_handler_stress_all_with_rand_reset.3090277037
Directory /workspace/19.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.3009061479
Short name T206
Test name
Test status
Simulation time 177375391 ps
CPU time 3.82 seconds
Started Aug 10 04:38:57 PM PDT 24
Finished Aug 10 04:39:01 PM PDT 24
Peak memory 248444 kb
Host smart-79f9d4ef-4292-4d9c-994c-30db597710f5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3009061479 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.3009061479
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.866436832
Short name T603
Test name
Test status
Simulation time 35191157390 ps
CPU time 2024.97 seconds
Started Aug 10 04:38:50 PM PDT 24
Finished Aug 10 05:12:35 PM PDT 24
Peak memory 285768 kb
Host smart-cca96741-308c-4aba-b36e-60a33c8c09d3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=866436832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.866436832
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.2469937457
Short name T649
Test name
Test status
Simulation time 140147208 ps
CPU time 8.75 seconds
Started Aug 10 04:38:56 PM PDT 24
Finished Aug 10 04:39:05 PM PDT 24
Peak memory 247860 kb
Host smart-0c8adb1b-a436-4d3b-ba9b-41f4502d6c9f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2469937457 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.2469937457
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.4004360885
Short name T604
Test name
Test status
Simulation time 223170734 ps
CPU time 7.85 seconds
Started Aug 10 04:39:06 PM PDT 24
Finished Aug 10 04:39:14 PM PDT 24
Peak memory 255160 kb
Host smart-a5cd7918-723e-4a5f-9d22-2c9811208507
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40043
60885 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.4004360885
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.2094692187
Short name T694
Test name
Test status
Simulation time 614359488 ps
CPU time 14.08 seconds
Started Aug 10 04:38:57 PM PDT 24
Finished Aug 10 04:39:11 PM PDT 24
Peak memory 247712 kb
Host smart-0ce87f43-441f-4207-8173-841d4662d40e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20946
92187 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.2094692187
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.1914010882
Short name T338
Test name
Test status
Simulation time 37214265577 ps
CPU time 2496.33 seconds
Started Aug 10 04:39:00 PM PDT 24
Finished Aug 10 05:20:36 PM PDT 24
Peak memory 288664 kb
Host smart-0ce73176-a1d9-4880-ab5d-bf3e414e46e9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914010882 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.1914010882
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.2532307465
Short name T394
Test name
Test status
Simulation time 36160252692 ps
CPU time 2544.53 seconds
Started Aug 10 04:38:53 PM PDT 24
Finished Aug 10 05:21:18 PM PDT 24
Peak memory 288904 kb
Host smart-50cc0dd6-0df6-4068-bfb6-2725da3e2202
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2532307465 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.2532307465
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.2722100179
Short name T334
Test name
Test status
Simulation time 8564015877 ps
CPU time 104.77 seconds
Started Aug 10 04:39:00 PM PDT 24
Finished Aug 10 04:40:45 PM PDT 24
Peak memory 248236 kb
Host smart-f3ee5e86-79db-47f5-8566-61f43480698f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2722100179 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.2722100179
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.513602849
Short name T488
Test name
Test status
Simulation time 541106531 ps
CPU time 21.94 seconds
Started Aug 10 04:38:48 PM PDT 24
Finished Aug 10 04:39:10 PM PDT 24
Peak memory 248316 kb
Host smart-acc5353d-49c3-4865-9b03-c204949ac742
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51360
2849 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.513602849
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.2455169310
Short name T34
Test name
Test status
Simulation time 177337866 ps
CPU time 11.97 seconds
Started Aug 10 04:38:49 PM PDT 24
Finished Aug 10 04:39:01 PM PDT 24
Peak memory 270544 kb
Host smart-6a42fa46-31ce-4423-9362-86321b2adc3e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2455169310 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.2455169310
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.28432318
Short name T267
Test name
Test status
Simulation time 3179790880 ps
CPU time 20.02 seconds
Started Aug 10 04:38:52 PM PDT 24
Finished Aug 10 04:39:12 PM PDT 24
Peak memory 248224 kb
Host smart-b14a3b34-82bb-43ec-a54d-d96c0b9acca6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28432
318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.28432318
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.1577302158
Short name T645
Test name
Test status
Simulation time 4374713113 ps
CPU time 64.96 seconds
Started Aug 10 04:38:58 PM PDT 24
Finished Aug 10 04:40:03 PM PDT 24
Peak memory 248372 kb
Host smart-02a81294-2807-4e00-9ba0-2c737aa2688e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15773
02158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.1577302158
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.2624054957
Short name T279
Test name
Test status
Simulation time 63437264594 ps
CPU time 1622.3 seconds
Started Aug 10 04:38:50 PM PDT 24
Finished Aug 10 05:05:53 PM PDT 24
Peak memory 289096 kb
Host smart-17d2b692-dab8-4c9d-b505-f175459a584b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2624054957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_han
dler_stress_all.2624054957
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.796459713
Short name T253
Test name
Test status
Simulation time 106184084419 ps
CPU time 1818.78 seconds
Started Aug 10 04:39:37 PM PDT 24
Finished Aug 10 05:09:56 PM PDT 24
Peak memory 281036 kb
Host smart-97b5036a-3375-4ff1-9d7a-6f400fca3b1b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=796459713 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.796459713
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.443952528
Short name T443
Test name
Test status
Simulation time 3753954809 ps
CPU time 252.44 seconds
Started Aug 10 04:39:23 PM PDT 24
Finished Aug 10 04:43:36 PM PDT 24
Peak memory 256400 kb
Host smart-b4955f4e-0bf9-4a80-b900-6ddfb3cac139
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44395
2528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.443952528
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.2905309689
Short name T232
Test name
Test status
Simulation time 47427279 ps
CPU time 4.15 seconds
Started Aug 10 04:39:25 PM PDT 24
Finished Aug 10 04:39:29 PM PDT 24
Peak memory 239464 kb
Host smart-b2b44ecb-2b6f-4681-9238-156af6725147
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29053
09689 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.2905309689
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.2796895345
Short name T419
Test name
Test status
Simulation time 23317044302 ps
CPU time 620.48 seconds
Started Aug 10 04:39:24 PM PDT 24
Finished Aug 10 04:49:44 PM PDT 24
Peak memory 272552 kb
Host smart-5ee0bf0a-72ff-48ee-b2b3-140268440255
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796895345 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.2796895345
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.3815292522
Short name T688
Test name
Test status
Simulation time 68783834056 ps
CPU time 1836.85 seconds
Started Aug 10 04:39:41 PM PDT 24
Finished Aug 10 05:10:18 PM PDT 24
Peak memory 281040 kb
Host smart-0e06c623-70c1-4f51-af26-7779788ae074
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3815292522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.3815292522
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.1052053178
Short name T270
Test name
Test status
Simulation time 143825516219 ps
CPU time 523.41 seconds
Started Aug 10 04:39:23 PM PDT 24
Finished Aug 10 04:48:07 PM PDT 24
Peak memory 248120 kb
Host smart-ad51a976-6463-4bb4-890b-3b189c3b7b92
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1052053178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.1052053178
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.2763916826
Short name T368
Test name
Test status
Simulation time 613891407 ps
CPU time 44.34 seconds
Started Aug 10 04:39:35 PM PDT 24
Finished Aug 10 04:40:19 PM PDT 24
Peak memory 255696 kb
Host smart-52a6e6b0-93a8-4847-a016-2a97e380245e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27639
16826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.2763916826
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.1609024027
Short name T49
Test name
Test status
Simulation time 637506051 ps
CPU time 38.74 seconds
Started Aug 10 04:39:36 PM PDT 24
Finished Aug 10 04:40:15 PM PDT 24
Peak memory 255784 kb
Host smart-0478243f-7dce-467f-8b5b-e1e3ace9f50d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16090
24027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.1609024027
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.2561344910
Short name T633
Test name
Test status
Simulation time 991468196 ps
CPU time 23.77 seconds
Started Aug 10 04:39:26 PM PDT 24
Finished Aug 10 04:39:50 PM PDT 24
Peak memory 247516 kb
Host smart-e30a2bd7-875c-4a10-aa42-ce78ed0910aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25613
44910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.2561344910
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.3101470322
Short name T1
Test name
Test status
Simulation time 419322856 ps
CPU time 30.15 seconds
Started Aug 10 04:39:24 PM PDT 24
Finished Aug 10 04:39:55 PM PDT 24
Peak memory 256176 kb
Host smart-e9c40b67-3968-4a01-82e0-dcb858f61c0c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31014
70322 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.3101470322
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.1438208400
Short name T59
Test name
Test status
Simulation time 234503560414 ps
CPU time 3384.4 seconds
Started Aug 10 04:39:23 PM PDT 24
Finished Aug 10 05:35:47 PM PDT 24
Peak memory 289244 kb
Host smart-b6196db4-aebe-4feb-9cdd-c93dcbf9aa21
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1438208400 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_ha
ndler_stress_all.1438208400
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all_with_rand_reset.2659333393
Short name T103
Test name
Test status
Simulation time 111982317156 ps
CPU time 3111.35 seconds
Started Aug 10 04:39:18 PM PDT 24
Finished Aug 10 05:31:10 PM PDT 24
Peak memory 338160 kb
Host smart-01afae5c-8599-4d73-8ac1-cb5a5662c34c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2659333393 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 20.alert_handler_stress_all_with_rand_reset.2659333393
Directory /workspace/20.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.2154244946
Short name T456
Test name
Test status
Simulation time 78429721895 ps
CPU time 2215.77 seconds
Started Aug 10 04:39:23 PM PDT 24
Finished Aug 10 05:16:19 PM PDT 24
Peak memory 284800 kb
Host smart-334e6230-7ce6-4a3c-994a-da891f4fe357
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2154244946 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.2154244946
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.4282728034
Short name T707
Test name
Test status
Simulation time 2393567803 ps
CPU time 37.46 seconds
Started Aug 10 04:39:27 PM PDT 24
Finished Aug 10 04:40:05 PM PDT 24
Peak memory 255856 kb
Host smart-d46315de-8138-4cd2-a707-0ec1e690c8af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42827
28034 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.4282728034
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.363579951
Short name T661
Test name
Test status
Simulation time 969323693 ps
CPU time 14.66 seconds
Started Aug 10 04:39:38 PM PDT 24
Finished Aug 10 04:39:54 PM PDT 24
Peak memory 247732 kb
Host smart-322f31c5-b2b6-4d01-ad71-009d1c50bdce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36357
9951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.363579951
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.528035501
Short name T344
Test name
Test status
Simulation time 26073728980 ps
CPU time 1498.41 seconds
Started Aug 10 04:39:41 PM PDT 24
Finished Aug 10 05:04:39 PM PDT 24
Peak memory 272056 kb
Host smart-bb38c974-78a7-4a0a-83e9-1404d159446b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=528035501 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.528035501
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.2803303664
Short name T559
Test name
Test status
Simulation time 28485616574 ps
CPU time 1981.54 seconds
Started Aug 10 04:39:34 PM PDT 24
Finished Aug 10 05:12:36 PM PDT 24
Peak memory 288956 kb
Host smart-142823f9-8aba-4908-acb3-d3755f1111bc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2803303664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.2803303664
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.37517486
Short name T320
Test name
Test status
Simulation time 98451593501 ps
CPU time 554.87 seconds
Started Aug 10 04:39:34 PM PDT 24
Finished Aug 10 04:48:49 PM PDT 24
Peak memory 248272 kb
Host smart-480d3845-3738-45f1-a452-3f281df248f5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=37517486 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.37517486
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.1695314729
Short name T615
Test name
Test status
Simulation time 1999165610 ps
CPU time 63.55 seconds
Started Aug 10 04:39:28 PM PDT 24
Finished Aug 10 04:40:32 PM PDT 24
Peak memory 255588 kb
Host smart-407d57bd-650f-495b-9ef5-d41dbb240602
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16953
14729 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.1695314729
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.2735183786
Short name T506
Test name
Test status
Simulation time 3652793609 ps
CPU time 56.22 seconds
Started Aug 10 04:39:34 PM PDT 24
Finished Aug 10 04:40:30 PM PDT 24
Peak memory 248196 kb
Host smart-8f34af75-3d33-4454-9be6-377e6f556d11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27351
83786 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.2735183786
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.3118703615
Short name T708
Test name
Test status
Simulation time 1060474276 ps
CPU time 17.64 seconds
Started Aug 10 04:39:27 PM PDT 24
Finished Aug 10 04:39:45 PM PDT 24
Peak memory 255940 kb
Host smart-d784f37b-1fda-4ea5-9ed0-4ec0ae35092f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31187
03615 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.3118703615
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.2169656502
Short name T43
Test name
Test status
Simulation time 95434436 ps
CPU time 4.44 seconds
Started Aug 10 04:39:37 PM PDT 24
Finished Aug 10 04:39:41 PM PDT 24
Peak memory 248184 kb
Host smart-ec994b63-d2ad-436c-aa24-82a56cfa875e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21696
56502 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.2169656502
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.3305349701
Short name T646
Test name
Test status
Simulation time 7841460239 ps
CPU time 217.53 seconds
Started Aug 10 04:39:30 PM PDT 24
Finished Aug 10 04:43:08 PM PDT 24
Peak memory 253172 kb
Host smart-e567a460-4869-4c29-8201-0d2b3fb1ae14
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3305349701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_ha
ndler_stress_all.3305349701
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all_with_rand_reset.65214527
Short name T105
Test name
Test status
Simulation time 62998957818 ps
CPU time 3943.69 seconds
Started Aug 10 04:39:33 PM PDT 24
Finished Aug 10 05:45:17 PM PDT 24
Peak memory 315508 kb
Host smart-8d20bac3-dc88-4c5e-a4c4-79cde98cb00c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65214527 -assert nopostproc +UVM_TESTNAME=alert_
handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -c
m_log /dev/null -cm_name 21.alert_handler_stress_all_with_rand_reset.65214527
Directory /workspace/21.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.1207816090
Short name T117
Test name
Test status
Simulation time 49380805758 ps
CPU time 844.71 seconds
Started Aug 10 04:39:26 PM PDT 24
Finished Aug 10 04:53:31 PM PDT 24
Peak memory 264812 kb
Host smart-c0ae4f0d-8130-48cb-b792-c0d0e1a7521a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1207816090 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.1207816090
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.1252507224
Short name T553
Test name
Test status
Simulation time 4762773760 ps
CPU time 154.41 seconds
Started Aug 10 04:39:28 PM PDT 24
Finished Aug 10 04:42:02 PM PDT 24
Peak memory 255976 kb
Host smart-5fd65630-df61-46d8-b889-a7ebb0351422
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12525
07224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.1252507224
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.2935378421
Short name T602
Test name
Test status
Simulation time 221024374 ps
CPU time 14.6 seconds
Started Aug 10 04:39:36 PM PDT 24
Finished Aug 10 04:39:50 PM PDT 24
Peak memory 252720 kb
Host smart-f75903fa-129b-4fb5-978b-acda0f55ef8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29353
78421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.2935378421
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.3753334906
Short name T14
Test name
Test status
Simulation time 209218917885 ps
CPU time 1983.87 seconds
Started Aug 10 04:39:28 PM PDT 24
Finished Aug 10 05:12:33 PM PDT 24
Peak memory 281836 kb
Host smart-0c6ada16-406e-44ab-b63c-709401eb163b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753334906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.3753334906
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.268684623
Short name T237
Test name
Test status
Simulation time 44323548703 ps
CPU time 1378.63 seconds
Started Aug 10 04:39:30 PM PDT 24
Finished Aug 10 05:02:29 PM PDT 24
Peak memory 272632 kb
Host smart-4db193c4-c90c-4277-a5d7-eca74ef1d96d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=268684623 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.268684623
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.3841091275
Short name T64
Test name
Test status
Simulation time 62521456536 ps
CPU time 654.31 seconds
Started Aug 10 04:39:24 PM PDT 24
Finished Aug 10 04:50:19 PM PDT 24
Peak memory 255288 kb
Host smart-e4d46963-a632-430f-a961-caf6ee9ea18e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3841091275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.3841091275
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.1407995423
Short name T599
Test name
Test status
Simulation time 920937753 ps
CPU time 29.9 seconds
Started Aug 10 04:39:27 PM PDT 24
Finished Aug 10 04:39:57 PM PDT 24
Peak memory 248220 kb
Host smart-5fefc875-f1e7-4643-814d-3f5f8dcb13db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14079
95423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.1407995423
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.2547710323
Short name T48
Test name
Test status
Simulation time 1389817990 ps
CPU time 39.82 seconds
Started Aug 10 04:39:30 PM PDT 24
Finished Aug 10 04:40:11 PM PDT 24
Peak memory 247756 kb
Host smart-63baad34-8475-4255-adb7-d56b16d9402c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25477
10323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.2547710323
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.4248867551
Short name T695
Test name
Test status
Simulation time 70590582 ps
CPU time 9.87 seconds
Started Aug 10 04:39:37 PM PDT 24
Finished Aug 10 04:39:47 PM PDT 24
Peak memory 247624 kb
Host smart-87e6326c-5f28-4630-bfbd-a7c907d70434
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42488
67551 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.4248867551
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.456170587
Short name T357
Test name
Test status
Simulation time 165192227 ps
CPU time 16.32 seconds
Started Aug 10 04:39:25 PM PDT 24
Finished Aug 10 04:39:42 PM PDT 24
Peak memory 255584 kb
Host smart-aa6856a5-69c6-4f2f-add9-b99dbb75fa4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45617
0587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.456170587
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.508542707
Short name T299
Test name
Test status
Simulation time 43345772423 ps
CPU time 2622.69 seconds
Started Aug 10 04:39:29 PM PDT 24
Finished Aug 10 05:23:12 PM PDT 24
Peak memory 287008 kb
Host smart-5ffe8f2a-3fc6-40ce-9b1b-8ef619dce7aa
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=508542707 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_han
dler_stress_all.508542707
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all_with_rand_reset.1630814079
Short name T651
Test name
Test status
Simulation time 112044429863 ps
CPU time 2716.81 seconds
Started Aug 10 04:39:35 PM PDT 24
Finished Aug 10 05:24:52 PM PDT 24
Peak memory 305724 kb
Host smart-e5c1c2cb-0037-494e-88b1-eda24bd6be23
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1630814079 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.alert_handler_stress_all_with_rand_reset.1630814079
Directory /workspace/22.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.2550161163
Short name T220
Test name
Test status
Simulation time 32908120515 ps
CPU time 743.28 seconds
Started Aug 10 04:39:46 PM PDT 24
Finished Aug 10 04:52:10 PM PDT 24
Peak memory 272152 kb
Host smart-ce9c38a3-4454-415d-a459-3b96dac82de6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2550161163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.2550161163
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.3432747530
Short name T363
Test name
Test status
Simulation time 19374598792 ps
CPU time 285.83 seconds
Started Aug 10 04:39:33 PM PDT 24
Finished Aug 10 04:44:19 PM PDT 24
Peak memory 255936 kb
Host smart-539d27ed-a9b7-4b48-82cf-192433573a2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34327
47530 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.3432747530
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.1262912457
Short name T693
Test name
Test status
Simulation time 428527983 ps
CPU time 30.81 seconds
Started Aug 10 04:39:38 PM PDT 24
Finished Aug 10 04:40:09 PM PDT 24
Peak memory 248100 kb
Host smart-569bcb72-aa7f-4d17-b048-4ca3a1a0410b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12629
12457 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.1262912457
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.3533768547
Short name T339
Test name
Test status
Simulation time 41783376362 ps
CPU time 1374.07 seconds
Started Aug 10 04:39:38 PM PDT 24
Finished Aug 10 05:02:32 PM PDT 24
Peak memory 272036 kb
Host smart-20480768-a5c8-40d1-b0e3-ecda2a7facc6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3533768547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.3533768547
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.4175980143
Short name T375
Test name
Test status
Simulation time 58782420522 ps
CPU time 1241.92 seconds
Started Aug 10 04:39:42 PM PDT 24
Finished Aug 10 05:00:25 PM PDT 24
Peak memory 272380 kb
Host smart-b9606270-5914-49cf-95e9-7fecddc9e475
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4175980143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.4175980143
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.1110215800
Short name T508
Test name
Test status
Simulation time 36557541633 ps
CPU time 373.11 seconds
Started Aug 10 04:39:36 PM PDT 24
Finished Aug 10 04:45:49 PM PDT 24
Peak memory 248244 kb
Host smart-d323d04a-7913-46b7-a801-79ca1fb4c37b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1110215800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.1110215800
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.2441921360
Short name T441
Test name
Test status
Simulation time 81080636 ps
CPU time 3.41 seconds
Started Aug 10 04:39:31 PM PDT 24
Finished Aug 10 04:39:34 PM PDT 24
Peak memory 239876 kb
Host smart-a899019e-d23e-4904-9ade-0e8f9aad553c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24419
21360 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.2441921360
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.588603618
Short name T377
Test name
Test status
Simulation time 22168005 ps
CPU time 3.31 seconds
Started Aug 10 04:39:34 PM PDT 24
Finished Aug 10 04:39:38 PM PDT 24
Peak memory 239556 kb
Host smart-6d37f4d4-8966-4cc6-b7a5-4732f1628614
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58860
3618 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.588603618
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.3346461404
Short name T533
Test name
Test status
Simulation time 1785174264 ps
CPU time 26.59 seconds
Started Aug 10 04:39:32 PM PDT 24
Finished Aug 10 04:39:59 PM PDT 24
Peak memory 256096 kb
Host smart-a591bdfa-6589-47ac-81f2-fd9bcbc1c8d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33464
61404 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.3346461404
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all_with_rand_reset.2120712800
Short name T480
Test name
Test status
Simulation time 121872007516 ps
CPU time 5886.96 seconds
Started Aug 10 04:39:48 PM PDT 24
Finished Aug 10 06:17:55 PM PDT 24
Peak memory 354748 kb
Host smart-9e146171-9979-4803-9b42-acc0582d17a8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2120712800 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.alert_handler_stress_all_with_rand_reset.2120712800
Directory /workspace/23.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.2678803557
Short name T639
Test name
Test status
Simulation time 77850492814 ps
CPU time 1309.01 seconds
Started Aug 10 04:39:25 PM PDT 24
Finished Aug 10 05:01:14 PM PDT 24
Peak memory 286712 kb
Host smart-cb1c3ac2-7910-446e-b4e4-36104a7289fe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678803557 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.2678803557
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.2364452233
Short name T263
Test name
Test status
Simulation time 298191959 ps
CPU time 24.98 seconds
Started Aug 10 04:39:48 PM PDT 24
Finished Aug 10 04:40:14 PM PDT 24
Peak memory 256052 kb
Host smart-965538c8-2dfa-48d6-82a8-6c0837d9f40c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23644
52233 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.2364452233
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.3865249244
Short name T183
Test name
Test status
Simulation time 7927842190 ps
CPU time 36.54 seconds
Started Aug 10 04:39:46 PM PDT 24
Finished Aug 10 04:40:23 PM PDT 24
Peak memory 256208 kb
Host smart-213c8a6c-9152-46f4-919f-e3ab02815ecd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38652
49244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.3865249244
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.779858892
Short name T473
Test name
Test status
Simulation time 93681611132 ps
CPU time 1421.98 seconds
Started Aug 10 04:39:34 PM PDT 24
Finished Aug 10 05:03:16 PM PDT 24
Peak memory 271312 kb
Host smart-f31582ed-8f49-411f-b5e1-b53248a47664
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=779858892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.779858892
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.3437765496
Short name T250
Test name
Test status
Simulation time 28445123358 ps
CPU time 1170.92 seconds
Started Aug 10 04:39:36 PM PDT 24
Finished Aug 10 04:59:07 PM PDT 24
Peak memory 281036 kb
Host smart-ae1c55ff-6699-45b3-abba-0f2da817e02a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3437765496 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.3437765496
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.3828801173
Short name T315
Test name
Test status
Simulation time 4462311860 ps
CPU time 198.78 seconds
Started Aug 10 04:39:39 PM PDT 24
Finished Aug 10 04:42:58 PM PDT 24
Peak memory 247052 kb
Host smart-33bf6d7c-3f43-455c-a0f1-55373ca7f244
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828801173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.3828801173
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.577845047
Short name T442
Test name
Test status
Simulation time 129010028 ps
CPU time 7.98 seconds
Started Aug 10 04:39:35 PM PDT 24
Finished Aug 10 04:39:44 PM PDT 24
Peak memory 248240 kb
Host smart-57d11e94-e9a9-432a-951c-e33d4ac71b80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57784
5047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.577845047
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.689404314
Short name T90
Test name
Test status
Simulation time 1049490840 ps
CPU time 25.73 seconds
Started Aug 10 04:39:45 PM PDT 24
Finished Aug 10 04:40:11 PM PDT 24
Peak memory 248196 kb
Host smart-90c5dac3-44b7-4993-8895-81b59b9f6f07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68940
4314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.689404314
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.1986803721
Short name T709
Test name
Test status
Simulation time 231800494 ps
CPU time 28.04 seconds
Started Aug 10 04:39:38 PM PDT 24
Finished Aug 10 04:40:06 PM PDT 24
Peak memory 247820 kb
Host smart-26778586-89d1-4b19-8b17-cbbf69174a37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19868
03721 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.1986803721
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.695211423
Short name T563
Test name
Test status
Simulation time 260419023 ps
CPU time 24.68 seconds
Started Aug 10 04:39:49 PM PDT 24
Finished Aug 10 04:40:14 PM PDT 24
Peak memory 248592 kb
Host smart-2aa08351-8f02-4658-86b4-22e80473b091
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69521
1423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.695211423
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.1161926686
Short name T91
Test name
Test status
Simulation time 23691051325 ps
CPU time 2328.26 seconds
Started Aug 10 04:39:36 PM PDT 24
Finished Aug 10 05:18:25 PM PDT 24
Peak memory 305268 kb
Host smart-4a8480a5-09d7-44cf-afbd-9aed241e16ae
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1161926686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_ha
ndler_stress_all.1161926686
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.2824462623
Short name T79
Test name
Test status
Simulation time 24325887073 ps
CPU time 1524.25 seconds
Started Aug 10 04:39:45 PM PDT 24
Finished Aug 10 05:05:09 PM PDT 24
Peak memory 272896 kb
Host smart-aacd6229-1b8b-4e3c-8f80-d8880b148068
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2824462623 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.2824462623
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.4036467353
Short name T430
Test name
Test status
Simulation time 14214870411 ps
CPU time 227.91 seconds
Started Aug 10 04:39:24 PM PDT 24
Finished Aug 10 04:43:12 PM PDT 24
Peak memory 251292 kb
Host smart-1164dc09-eb62-450f-852f-c172c74ebd3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40364
67353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.4036467353
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.453422340
Short name T124
Test name
Test status
Simulation time 1085110696 ps
CPU time 24.71 seconds
Started Aug 10 04:39:39 PM PDT 24
Finished Aug 10 04:40:04 PM PDT 24
Peak memory 248200 kb
Host smart-6522f002-18be-4c3b-ada6-a11511a5138d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45342
2340 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.453422340
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.14824491
Short name T346
Test name
Test status
Simulation time 209775729726 ps
CPU time 2755.11 seconds
Started Aug 10 04:39:33 PM PDT 24
Finished Aug 10 05:25:29 PM PDT 24
Peak memory 286860 kb
Host smart-0b664f4c-5571-4c95-9a98-28ace3e4b117
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14824491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.14824491
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.3459482452
Short name T519
Test name
Test status
Simulation time 57259380783 ps
CPU time 3357.75 seconds
Started Aug 10 04:39:43 PM PDT 24
Finished Aug 10 05:35:41 PM PDT 24
Peak memory 289464 kb
Host smart-db96f93a-573d-41b9-b7ad-5ebf3aa38e65
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459482452 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.3459482452
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.2429237748
Short name T303
Test name
Test status
Simulation time 48409186935 ps
CPU time 481.44 seconds
Started Aug 10 04:39:31 PM PDT 24
Finished Aug 10 04:47:32 PM PDT 24
Peak memory 248104 kb
Host smart-9cb7e732-cd8f-4331-a469-2cb70b3fd98a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2429237748 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.2429237748
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.3430039637
Short name T405
Test name
Test status
Simulation time 3846032669 ps
CPU time 62.38 seconds
Started Aug 10 04:39:37 PM PDT 24
Finished Aug 10 04:40:40 PM PDT 24
Peak memory 248212 kb
Host smart-1b4431b5-4bf3-4ba6-ad57-5edb2993b17a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34300
39637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.3430039637
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.2826011326
Short name T390
Test name
Test status
Simulation time 239706325 ps
CPU time 19.35 seconds
Started Aug 10 04:39:39 PM PDT 24
Finished Aug 10 04:39:58 PM PDT 24
Peak memory 247780 kb
Host smart-397e9f9a-00db-484e-85df-fa5792397abd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28260
11326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.2826011326
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.3465645827
Short name T588
Test name
Test status
Simulation time 69771019 ps
CPU time 3.59 seconds
Started Aug 10 04:39:34 PM PDT 24
Finished Aug 10 04:39:38 PM PDT 24
Peak memory 239448 kb
Host smart-76154891-171d-4436-8450-d6fd51c91d25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34656
45827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.3465645827
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.996029964
Short name T668
Test name
Test status
Simulation time 133071421 ps
CPU time 15.42 seconds
Started Aug 10 04:39:35 PM PDT 24
Finished Aug 10 04:39:51 PM PDT 24
Peak memory 248376 kb
Host smart-c2740aca-8aff-4d4c-90d5-25866a1fce59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99602
9964 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.996029964
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.1232063807
Short name T60
Test name
Test status
Simulation time 69150972891 ps
CPU time 1439 seconds
Started Aug 10 04:39:42 PM PDT 24
Finished Aug 10 05:03:42 PM PDT 24
Peak memory 288220 kb
Host smart-590206bc-ee57-4c1c-99da-5bf7e1a46a76
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232063807 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_ha
ndler_stress_all.1232063807
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.582590684
Short name T579
Test name
Test status
Simulation time 42203893017 ps
CPU time 1460.26 seconds
Started Aug 10 04:39:39 PM PDT 24
Finished Aug 10 05:03:59 PM PDT 24
Peak memory 272768 kb
Host smart-b4a6ad42-3b68-4714-a47d-a433e4a8b4ee
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=582590684 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.582590684
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.699533459
Short name T269
Test name
Test status
Simulation time 1544351568 ps
CPU time 169.52 seconds
Started Aug 10 04:39:36 PM PDT 24
Finished Aug 10 04:42:25 PM PDT 24
Peak memory 256388 kb
Host smart-559aca1c-2c3b-44b7-9ee9-ca182ac57393
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69953
3459 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.699533459
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.4174600654
Short name T414
Test name
Test status
Simulation time 336144115 ps
CPU time 45.03 seconds
Started Aug 10 04:39:34 PM PDT 24
Finished Aug 10 04:40:19 PM PDT 24
Peak memory 248228 kb
Host smart-d6173da9-8ae3-443a-9475-b2b36b68bc53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41746
00654 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.4174600654
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.2804691969
Short name T689
Test name
Test status
Simulation time 81967982956 ps
CPU time 2551.89 seconds
Started Aug 10 04:39:34 PM PDT 24
Finished Aug 10 05:22:06 PM PDT 24
Peak memory 288496 kb
Host smart-c80a9295-e723-4ba1-808d-37f11ea6f55a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804691969 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.2804691969
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.2585552960
Short name T666
Test name
Test status
Simulation time 55868841229 ps
CPU time 3404.36 seconds
Started Aug 10 04:39:44 PM PDT 24
Finished Aug 10 05:36:30 PM PDT 24
Peak memory 289060 kb
Host smart-76234d6f-ed2f-4496-9a69-f5065c90c907
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2585552960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.2585552960
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.1860634877
Short name T532
Test name
Test status
Simulation time 1217719012 ps
CPU time 39.36 seconds
Started Aug 10 04:39:39 PM PDT 24
Finished Aug 10 04:40:18 PM PDT 24
Peak memory 256264 kb
Host smart-329770f1-b0d3-44d7-8861-e8ff787bc1d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18606
34877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.1860634877
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.3001301229
Short name T612
Test name
Test status
Simulation time 1713466682 ps
CPU time 33.05 seconds
Started Aug 10 04:39:46 PM PDT 24
Finished Aug 10 04:40:19 PM PDT 24
Peak memory 255232 kb
Host smart-95da75b5-8664-4076-8ec0-f79713ec2d25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30013
01229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.3001301229
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.3610958689
Short name T635
Test name
Test status
Simulation time 1557488890 ps
CPU time 22.8 seconds
Started Aug 10 04:39:41 PM PDT 24
Finished Aug 10 04:40:04 PM PDT 24
Peak memory 248152 kb
Host smart-193cb21c-6ba0-4e43-958c-b559b978b456
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36109
58689 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.3610958689
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.732344464
Short name T75
Test name
Test status
Simulation time 109823206302 ps
CPU time 3175.07 seconds
Started Aug 10 04:39:31 PM PDT 24
Finished Aug 10 05:32:26 PM PDT 24
Peak memory 288808 kb
Host smart-b0d627bd-6b08-423a-bdd4-6c42887709b8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732344464 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_han
dler_stress_all.732344464
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.1006984953
Short name T399
Test name
Test status
Simulation time 91177879902 ps
CPU time 1480.89 seconds
Started Aug 10 04:39:34 PM PDT 24
Finished Aug 10 05:04:15 PM PDT 24
Peak memory 272024 kb
Host smart-3dacc13b-d045-4799-8e6e-35ddeaa1af12
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1006984953 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.1006984953
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.780826487
Short name T381
Test name
Test status
Simulation time 3023811227 ps
CPU time 185.63 seconds
Started Aug 10 04:39:41 PM PDT 24
Finished Aug 10 04:42:47 PM PDT 24
Peak memory 256448 kb
Host smart-0137ae71-bfe5-451c-beb5-1d76728cf95e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78082
6487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.780826487
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.477921142
Short name T531
Test name
Test status
Simulation time 1071055878 ps
CPU time 12.57 seconds
Started Aug 10 04:39:41 PM PDT 24
Finished Aug 10 04:39:53 PM PDT 24
Peak memory 254420 kb
Host smart-db9d0fd9-2a97-4d63-a9b3-9f901055ea01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47792
1142 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.477921142
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.513092827
Short name T329
Test name
Test status
Simulation time 134781476587 ps
CPU time 2069.85 seconds
Started Aug 10 04:39:45 PM PDT 24
Finished Aug 10 05:14:15 PM PDT 24
Peak memory 282536 kb
Host smart-6a416e78-0cac-431b-8428-bd2b177802fd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=513092827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.513092827
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.3753713709
Short name T527
Test name
Test status
Simulation time 166690289230 ps
CPU time 2697.59 seconds
Started Aug 10 04:39:40 PM PDT 24
Finished Aug 10 05:24:37 PM PDT 24
Peak memory 284864 kb
Host smart-ee463086-f33f-4953-bd79-9ada6f3f89e2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3753713709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.3753713709
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.1873488212
Short name T20
Test name
Test status
Simulation time 1708143805 ps
CPU time 26.47 seconds
Started Aug 10 04:39:46 PM PDT 24
Finished Aug 10 04:40:13 PM PDT 24
Peak memory 248124 kb
Host smart-f31bdda0-9eca-4a66-b309-be94a92faf4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18734
88212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.1873488212
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.3921671856
Short name T372
Test name
Test status
Simulation time 159001566 ps
CPU time 10.25 seconds
Started Aug 10 04:39:27 PM PDT 24
Finished Aug 10 04:39:37 PM PDT 24
Peak memory 247776 kb
Host smart-cc26064c-bf7d-4548-9e22-ae94baab5fbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39216
71856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.3921671856
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.2594392018
Short name T395
Test name
Test status
Simulation time 1539163627 ps
CPU time 48.53 seconds
Started Aug 10 04:39:37 PM PDT 24
Finished Aug 10 04:40:26 PM PDT 24
Peak memory 255672 kb
Host smart-784dfb6c-c5da-4f8f-92c9-57ee51c209d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25943
92018 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.2594392018
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.2351690617
Short name T522
Test name
Test status
Simulation time 1361618174 ps
CPU time 26.75 seconds
Started Aug 10 04:39:31 PM PDT 24
Finished Aug 10 04:39:58 PM PDT 24
Peak memory 256032 kb
Host smart-be944579-f5b1-4fe5-83f8-1cffcce83eea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23516
90617 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.2351690617
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.1236980607
Short name T81
Test name
Test status
Simulation time 165697858952 ps
CPU time 2323.72 seconds
Started Aug 10 04:39:46 PM PDT 24
Finished Aug 10 05:18:30 PM PDT 24
Peak memory 288768 kb
Host smart-fe5ca1af-592a-42cc-abdd-4df3e421a65e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1236980607 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_ha
ndler_stress_all.1236980607
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.2023700068
Short name T478
Test name
Test status
Simulation time 128792706873 ps
CPU time 2006.64 seconds
Started Aug 10 04:39:43 PM PDT 24
Finished Aug 10 05:13:10 PM PDT 24
Peak memory 287772 kb
Host smart-6caf305d-dc75-41a9-91f4-2c2e8f702d0f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2023700068 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.2023700068
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.3441583969
Short name T489
Test name
Test status
Simulation time 2674764614 ps
CPU time 121.88 seconds
Started Aug 10 04:39:42 PM PDT 24
Finished Aug 10 04:41:44 PM PDT 24
Peak memory 249160 kb
Host smart-9404f9a9-2613-4b08-8c6e-43ca215bd474
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34415
83969 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.3441583969
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.180344602
Short name T440
Test name
Test status
Simulation time 3322571117 ps
CPU time 29.54 seconds
Started Aug 10 04:39:36 PM PDT 24
Finished Aug 10 04:40:06 PM PDT 24
Peak memory 247828 kb
Host smart-475c470b-e5b3-475d-9796-874c98104484
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18034
4602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.180344602
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.2991969745
Short name T340
Test name
Test status
Simulation time 347977672540 ps
CPU time 1805.33 seconds
Started Aug 10 04:39:39 PM PDT 24
Finished Aug 10 05:09:45 PM PDT 24
Peak memory 272640 kb
Host smart-10b9fffc-e47b-4556-a107-98b7746ccfc1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2991969745 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.2991969745
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.1042834135
Short name T600
Test name
Test status
Simulation time 36097199604 ps
CPU time 2174.23 seconds
Started Aug 10 04:39:46 PM PDT 24
Finished Aug 10 05:16:01 PM PDT 24
Peak memory 271544 kb
Host smart-7569f1e9-ae78-467e-9773-648891527d33
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1042834135 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.1042834135
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.2739060124
Short name T36
Test name
Test status
Simulation time 699454404 ps
CPU time 28.13 seconds
Started Aug 10 04:39:47 PM PDT 24
Finished Aug 10 04:40:16 PM PDT 24
Peak memory 255520 kb
Host smart-efec6e1f-f357-4822-aaea-00e5bc05ed3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27390
60124 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.2739060124
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.2033431915
Short name T614
Test name
Test status
Simulation time 357094501 ps
CPU time 13.2 seconds
Started Aug 10 04:39:46 PM PDT 24
Finished Aug 10 04:40:00 PM PDT 24
Peak memory 252244 kb
Host smart-909eea95-c3c3-4d79-b7d8-fc2e8c252a40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20334
31915 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.2033431915
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.4264608783
Short name T38
Test name
Test status
Simulation time 345007207 ps
CPU time 14.18 seconds
Started Aug 10 04:39:45 PM PDT 24
Finished Aug 10 04:40:00 PM PDT 24
Peak memory 247976 kb
Host smart-9cdd3a03-b75d-413c-97af-05477f30f88f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42646
08783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.4264608783
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.2958214446
Short name T656
Test name
Test status
Simulation time 303252611 ps
CPU time 22.86 seconds
Started Aug 10 04:39:44 PM PDT 24
Finished Aug 10 04:40:07 PM PDT 24
Peak memory 256240 kb
Host smart-ed00abd2-7b54-4924-ad39-b8a3fab39539
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29582
14446 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.2958214446
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.1158165558
Short name T422
Test name
Test status
Simulation time 75249041986 ps
CPU time 2775.28 seconds
Started Aug 10 04:39:41 PM PDT 24
Finished Aug 10 05:25:57 PM PDT 24
Peak memory 289000 kb
Host smart-bfc32f73-18f5-443d-8a5e-c3af46124bc4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158165558 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_ha
ndler_stress_all.1158165558
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all_with_rand_reset.3225400016
Short name T56
Test name
Test status
Simulation time 66238375487 ps
CPU time 4062.18 seconds
Started Aug 10 04:39:37 PM PDT 24
Finished Aug 10 05:47:20 PM PDT 24
Peak memory 305192 kb
Host smart-b37415a2-5230-4955-9758-fc589cd58472
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225400016 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.alert_handler_stress_all_with_rand_reset.3225400016
Directory /workspace/28.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.561755337
Short name T534
Test name
Test status
Simulation time 264187352 ps
CPU time 16.26 seconds
Started Aug 10 04:39:46 PM PDT 24
Finished Aug 10 04:40:02 PM PDT 24
Peak memory 253904 kb
Host smart-fdb95e70-913d-42f6-8c7b-02d67f523917
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56175
5337 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.561755337
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.4020494872
Short name T574
Test name
Test status
Simulation time 2446139553 ps
CPU time 45.66 seconds
Started Aug 10 04:39:45 PM PDT 24
Finished Aug 10 04:40:31 PM PDT 24
Peak memory 248124 kb
Host smart-bf0afe8e-dec4-46e2-bd83-14b537e26431
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40204
94872 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.4020494872
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.2541563313
Short name T341
Test name
Test status
Simulation time 31387661296 ps
CPU time 1716.05 seconds
Started Aug 10 04:39:42 PM PDT 24
Finished Aug 10 05:08:18 PM PDT 24
Peak memory 272076 kb
Host smart-849a9414-bc46-44e2-85bf-608bc9312043
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2541563313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.2541563313
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.4188139623
Short name T641
Test name
Test status
Simulation time 61427086835 ps
CPU time 1969.92 seconds
Started Aug 10 04:39:46 PM PDT 24
Finished Aug 10 05:12:36 PM PDT 24
Peak memory 283492 kb
Host smart-5241f5b7-2e6c-4b31-94e1-f1967e5183a2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4188139623 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.4188139623
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.2629882831
Short name T317
Test name
Test status
Simulation time 5352441508 ps
CPU time 216.55 seconds
Started Aug 10 04:39:35 PM PDT 24
Finished Aug 10 04:43:12 PM PDT 24
Peak memory 248060 kb
Host smart-51fc2f91-ac93-4e65-ac3a-761b7c3f4cb6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2629882831 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.2629882831
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.3552331011
Short name T230
Test name
Test status
Simulation time 295312492 ps
CPU time 35.53 seconds
Started Aug 10 04:39:45 PM PDT 24
Finished Aug 10 04:40:21 PM PDT 24
Peak memory 248104 kb
Host smart-e4abd412-92bc-4831-8a9c-a61fbe1cc884
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35523
31011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.3552331011
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.1110129774
Short name T284
Test name
Test status
Simulation time 730748156 ps
CPU time 50.86 seconds
Started Aug 10 04:39:37 PM PDT 24
Finished Aug 10 04:40:28 PM PDT 24
Peak memory 255900 kb
Host smart-4d41f5b9-b6f2-49cf-88b1-6fecfab87077
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11101
29774 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.1110129774
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.1911050608
Short name T358
Test name
Test status
Simulation time 28041286 ps
CPU time 3.31 seconds
Started Aug 10 04:39:30 PM PDT 24
Finished Aug 10 04:39:33 PM PDT 24
Peak memory 239952 kb
Host smart-81d2a294-3fa1-48ae-b063-13a2760c0ec8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19110
50608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.1911050608
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.2801410947
Short name T672
Test name
Test status
Simulation time 38787609 ps
CPU time 4.87 seconds
Started Aug 10 04:39:38 PM PDT 24
Finished Aug 10 04:39:44 PM PDT 24
Peak memory 250808 kb
Host smart-393f5c1d-4e0c-439e-8dde-b3a8bdf92714
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28014
10947 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.2801410947
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.3218191255
Short name T53
Test name
Test status
Simulation time 246352940859 ps
CPU time 1481.68 seconds
Started Aug 10 04:39:47 PM PDT 24
Finished Aug 10 05:04:29 PM PDT 24
Peak memory 297188 kb
Host smart-e6cd305b-8ab6-42e4-aec7-b7e51a0c731a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3218191255 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_ha
ndler_stress_all.3218191255
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.594231438
Short name T211
Test name
Test status
Simulation time 38165392 ps
CPU time 3.57 seconds
Started Aug 10 04:38:51 PM PDT 24
Finished Aug 10 04:38:55 PM PDT 24
Peak memory 248308 kb
Host smart-fad2e3d2-4dce-4db4-8f2b-203c61094364
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=594231438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.594231438
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.556869511
Short name T110
Test name
Test status
Simulation time 50371971393 ps
CPU time 2931.66 seconds
Started Aug 10 04:38:58 PM PDT 24
Finished Aug 10 05:27:50 PM PDT 24
Peak memory 289080 kb
Host smart-3727b042-05e3-4122-a5d0-9823f9defd63
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=556869511 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.556869511
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.660291681
Short name T529
Test name
Test status
Simulation time 250328499 ps
CPU time 8.7 seconds
Started Aug 10 04:38:51 PM PDT 24
Finished Aug 10 04:39:00 PM PDT 24
Peak memory 248140 kb
Host smart-51aa174c-41a0-4d96-9081-d81f1787dbdb
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=660291681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.660291681
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.231370435
Short name T449
Test name
Test status
Simulation time 719264925 ps
CPU time 31.37 seconds
Started Aug 10 04:38:47 PM PDT 24
Finished Aug 10 04:39:18 PM PDT 24
Peak memory 255924 kb
Host smart-524cace6-21e0-4606-a250-efe8c9c9b8f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23137
0435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.231370435
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.3443914048
Short name T69
Test name
Test status
Simulation time 2081274039 ps
CPU time 36.88 seconds
Started Aug 10 04:38:47 PM PDT 24
Finished Aug 10 04:39:24 PM PDT 24
Peak memory 247604 kb
Host smart-fcaaba87-e219-4eb8-8612-13a83163c7ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34439
14048 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.3443914048
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.1892007311
Short name T564
Test name
Test status
Simulation time 15441077493 ps
CPU time 1614.87 seconds
Started Aug 10 04:38:51 PM PDT 24
Finished Aug 10 05:05:46 PM PDT 24
Peak memory 288532 kb
Host smart-6249613d-e7a0-4387-8737-41274aca78f8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1892007311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.1892007311
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.1715018550
Short name T657
Test name
Test status
Simulation time 3040216876 ps
CPU time 125.85 seconds
Started Aug 10 04:38:57 PM PDT 24
Finished Aug 10 04:41:03 PM PDT 24
Peak memory 248076 kb
Host smart-893d2578-4928-4835-be9a-cb8987644aaa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1715018550 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.1715018550
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.3746918381
Short name T557
Test name
Test status
Simulation time 375253658 ps
CPU time 23.37 seconds
Started Aug 10 04:38:52 PM PDT 24
Finished Aug 10 04:39:21 PM PDT 24
Peak memory 255576 kb
Host smart-cbc70c26-8644-41d8-8b1a-74cba538a67b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37469
18381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.3746918381
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.1291027374
Short name T122
Test name
Test status
Simulation time 434584374 ps
CPU time 22.07 seconds
Started Aug 10 04:38:49 PM PDT 24
Finished Aug 10 04:39:12 PM PDT 24
Peak memory 247380 kb
Host smart-ece30e62-589a-4299-92c9-cef557d34ae4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12910
27374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.1291027374
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.2657824537
Short name T9
Test name
Test status
Simulation time 441042947 ps
CPU time 24.27 seconds
Started Aug 10 04:39:02 PM PDT 24
Finished Aug 10 04:39:26 PM PDT 24
Peak memory 269700 kb
Host smart-5135f721-16f3-4f32-8b7c-e55cc6d8cd00
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2657824537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.2657824537
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.320739977
Short name T431
Test name
Test status
Simulation time 213156557 ps
CPU time 15.26 seconds
Started Aug 10 04:38:43 PM PDT 24
Finished Aug 10 04:38:58 PM PDT 24
Peak memory 248144 kb
Host smart-c10e8be2-6ca4-44c8-b9ac-f4b112e1dbe1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32073
9977 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.320739977
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.2666244386
Short name T186
Test name
Test status
Simulation time 279230679 ps
CPU time 8.5 seconds
Started Aug 10 04:39:07 PM PDT 24
Finished Aug 10 04:39:15 PM PDT 24
Peak memory 254988 kb
Host smart-510883c9-c196-459b-a597-0f72f11d83b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26662
44386 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.2666244386
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.1706080441
Short name T281
Test name
Test status
Simulation time 82146013755 ps
CPU time 1541.75 seconds
Started Aug 10 04:39:36 PM PDT 24
Finished Aug 10 05:05:18 PM PDT 24
Peak memory 272596 kb
Host smart-37061cbd-67b6-454e-93c5-1588ae599ed4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1706080441 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.1706080441
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.961734462
Short name T420
Test name
Test status
Simulation time 6338671906 ps
CPU time 148.78 seconds
Started Aug 10 04:39:38 PM PDT 24
Finished Aug 10 04:42:07 PM PDT 24
Peak memory 255596 kb
Host smart-d8b1b51d-d5db-411b-b32d-18008cfaf036
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96173
4462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.961734462
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.228372832
Short name T464
Test name
Test status
Simulation time 51074177 ps
CPU time 2.62 seconds
Started Aug 10 04:39:49 PM PDT 24
Finished Aug 10 04:39:51 PM PDT 24
Peak memory 239572 kb
Host smart-75f40fba-6c10-4c66-8b31-77bcb135ef14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22837
2832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.228372832
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.2650493232
Short name T662
Test name
Test status
Simulation time 13312847712 ps
CPU time 1171.1 seconds
Started Aug 10 04:39:43 PM PDT 24
Finished Aug 10 04:59:15 PM PDT 24
Peak memory 282848 kb
Host smart-7a28d638-7059-42e9-a70f-0ba4cd1d0539
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2650493232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.2650493232
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.579982419
Short name T318
Test name
Test status
Simulation time 45708805491 ps
CPU time 449.69 seconds
Started Aug 10 04:39:38 PM PDT 24
Finished Aug 10 04:47:08 PM PDT 24
Peak memory 248240 kb
Host smart-0988e972-115d-496b-b1ae-c75fe251e34f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=579982419 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.579982419
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.2348011154
Short name T23
Test name
Test status
Simulation time 2838318026 ps
CPU time 47.39 seconds
Started Aug 10 04:39:43 PM PDT 24
Finished Aug 10 04:40:30 PM PDT 24
Peak memory 255676 kb
Host smart-8058d759-7f6e-468d-a6b1-21cde7e43bd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23480
11154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.2348011154
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.433159796
Short name T282
Test name
Test status
Simulation time 10058794131 ps
CPU time 64.17 seconds
Started Aug 10 04:39:37 PM PDT 24
Finished Aug 10 04:40:41 PM PDT 24
Peak memory 255792 kb
Host smart-f9656478-9c53-47f0-9767-801cd68e6282
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43315
9796 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.433159796
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.775107165
Short name T589
Test name
Test status
Simulation time 127033250 ps
CPU time 14.53 seconds
Started Aug 10 04:39:39 PM PDT 24
Finished Aug 10 04:39:54 PM PDT 24
Peak memory 247624 kb
Host smart-dceaab95-adf2-43c8-b284-ad0632f079a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77510
7165 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.775107165
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.3948726568
Short name T637
Test name
Test status
Simulation time 833386758 ps
CPU time 45.96 seconds
Started Aug 10 04:39:42 PM PDT 24
Finished Aug 10 04:40:28 PM PDT 24
Peak memory 256340 kb
Host smart-10d06036-f785-4a22-8120-8cf7b6057b3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39487
26568 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.3948726568
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.3788559567
Short name T412
Test name
Test status
Simulation time 147504096602 ps
CPU time 1973.13 seconds
Started Aug 10 04:39:37 PM PDT 24
Finished Aug 10 05:12:30 PM PDT 24
Peak memory 284532 kb
Host smart-8cb5a6af-df6f-45e9-866f-b878c4e467fd
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3788559567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_ha
ndler_stress_all.3788559567
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.3942422309
Short name T361
Test name
Test status
Simulation time 1921731600 ps
CPU time 75.91 seconds
Started Aug 10 04:39:44 PM PDT 24
Finished Aug 10 04:41:00 PM PDT 24
Peak memory 255736 kb
Host smart-180241af-eaf7-4039-96a4-4066d3e8ca7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39424
22309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.3942422309
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.43364603
Short name T254
Test name
Test status
Simulation time 375031028 ps
CPU time 23.44 seconds
Started Aug 10 04:39:40 PM PDT 24
Finished Aug 10 04:40:04 PM PDT 24
Peak memory 247948 kb
Host smart-5bda2144-46e7-4479-a65d-7381c03ae546
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43364
603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.43364603
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.3723072414
Short name T621
Test name
Test status
Simulation time 56254703090 ps
CPU time 1212.42 seconds
Started Aug 10 04:39:36 PM PDT 24
Finished Aug 10 04:59:49 PM PDT 24
Peak memory 288884 kb
Host smart-b9b0b05a-ccc4-48b8-8868-6c0d2b795266
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3723072414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.3723072414
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.429287678
Short name T401
Test name
Test status
Simulation time 113201740579 ps
CPU time 2035.28 seconds
Started Aug 10 04:39:45 PM PDT 24
Finished Aug 10 05:13:40 PM PDT 24
Peak memory 282668 kb
Host smart-5a1086df-625c-4bba-907a-2476e5b1d23b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429287678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.429287678
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.2312370320
Short name T505
Test name
Test status
Simulation time 5694223218 ps
CPU time 113.36 seconds
Started Aug 10 04:39:44 PM PDT 24
Finished Aug 10 04:41:38 PM PDT 24
Peak memory 248240 kb
Host smart-90a17867-ae3e-4807-81c5-ddb35f4ac7a3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312370320 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.2312370320
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.1936542198
Short name T549
Test name
Test status
Simulation time 108540107 ps
CPU time 12.87 seconds
Started Aug 10 04:39:46 PM PDT 24
Finished Aug 10 04:39:59 PM PDT 24
Peak memory 248220 kb
Host smart-c60f6cbb-750e-42f9-ae59-75fb12d51f50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19365
42198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.1936542198
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.379008682
Short name T63
Test name
Test status
Simulation time 1025181081 ps
CPU time 24.35 seconds
Started Aug 10 04:39:41 PM PDT 24
Finished Aug 10 04:40:06 PM PDT 24
Peak memory 247704 kb
Host smart-33d8f5d6-d59a-4821-92e5-7942a55d4735
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37900
8682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.379008682
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.3725465856
Short name T86
Test name
Test status
Simulation time 681746428 ps
CPU time 42.12 seconds
Started Aug 10 04:39:38 PM PDT 24
Finished Aug 10 04:40:21 PM PDT 24
Peak memory 247404 kb
Host smart-5620fab2-3052-4fdc-8a99-45172e8095ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37254
65856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.3725465856
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.2596798556
Short name T582
Test name
Test status
Simulation time 526030730 ps
CPU time 26.17 seconds
Started Aug 10 04:39:46 PM PDT 24
Finished Aug 10 04:40:13 PM PDT 24
Peak memory 256340 kb
Host smart-a30ca147-4063-467c-bdb1-f9c1e1f6b248
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25967
98556 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.2596798556
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.3177137033
Short name T397
Test name
Test status
Simulation time 70121830505 ps
CPU time 2402.4 seconds
Started Aug 10 04:39:44 PM PDT 24
Finished Aug 10 05:19:47 PM PDT 24
Peak memory 288580 kb
Host smart-a2e11f91-8b6b-4734-b00e-dbb356a53a59
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3177137033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.3177137033
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.1493295824
Short name T409
Test name
Test status
Simulation time 2754252935 ps
CPU time 179.4 seconds
Started Aug 10 04:39:45 PM PDT 24
Finished Aug 10 04:42:45 PM PDT 24
Peak memory 255828 kb
Host smart-a22b9174-cfcb-46b5-b748-61cdc170399c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14932
95824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.1493295824
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.1170961423
Short name T703
Test name
Test status
Simulation time 1249625573 ps
CPU time 13.76 seconds
Started Aug 10 04:39:54 PM PDT 24
Finished Aug 10 04:40:08 PM PDT 24
Peak memory 248036 kb
Host smart-82c6f095-c87b-4058-a395-fab3a4057a77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11709
61423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.1170961423
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.191148756
Short name T328
Test name
Test status
Simulation time 48329456452 ps
CPU time 1504.96 seconds
Started Aug 10 04:39:43 PM PDT 24
Finished Aug 10 05:04:49 PM PDT 24
Peak memory 272212 kb
Host smart-15cfffe1-29c3-44e5-afe4-d8dfca4824dd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191148756 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.191148756
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.2664650353
Short name T72
Test name
Test status
Simulation time 380282425147 ps
CPU time 1903.19 seconds
Started Aug 10 04:39:43 PM PDT 24
Finished Aug 10 05:11:27 PM PDT 24
Peak memory 272556 kb
Host smart-e4a31f66-b14f-458d-ab94-aeddddafadd5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2664650353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.2664650353
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.2120440052
Short name T537
Test name
Test status
Simulation time 86439210615 ps
CPU time 477.77 seconds
Started Aug 10 04:39:46 PM PDT 24
Finished Aug 10 04:47:44 PM PDT 24
Peak memory 256408 kb
Host smart-6b92ee3c-313f-4c9d-ab89-6ef8737f15fc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2120440052 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.2120440052
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.3394139204
Short name T455
Test name
Test status
Simulation time 2449407487 ps
CPU time 78.5 seconds
Started Aug 10 04:39:31 PM PDT 24
Finished Aug 10 04:40:50 PM PDT 24
Peak memory 256072 kb
Host smart-db29d722-c748-4e6c-b373-998166b3afcf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33941
39204 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.3394139204
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.481653154
Short name T50
Test name
Test status
Simulation time 1626511417 ps
CPU time 31.12 seconds
Started Aug 10 04:39:39 PM PDT 24
Finished Aug 10 04:40:10 PM PDT 24
Peak memory 255756 kb
Host smart-84b10510-ce6c-43a0-9209-eb52d0d0e279
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48165
3154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.481653154
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.1842085518
Short name T439
Test name
Test status
Simulation time 360269130 ps
CPU time 23.73 seconds
Started Aug 10 04:39:43 PM PDT 24
Finished Aug 10 04:40:07 PM PDT 24
Peak memory 248532 kb
Host smart-da51a4a9-91bd-4f67-97e4-75a837926dde
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18420
85518 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.1842085518
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.1582479227
Short name T448
Test name
Test status
Simulation time 6596328262 ps
CPU time 43.24 seconds
Started Aug 10 04:39:41 PM PDT 24
Finished Aug 10 04:40:25 PM PDT 24
Peak memory 248236 kb
Host smart-179a90ae-abf1-4a2f-a58b-d18c291d3ef9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15824
79227 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.1582479227
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all_with_rand_reset.728092213
Short name T410
Test name
Test status
Simulation time 57277978366 ps
CPU time 2789 seconds
Started Aug 10 04:39:50 PM PDT 24
Finished Aug 10 05:26:19 PM PDT 24
Peak memory 322080 kb
Host smart-8fb93c3e-c970-46bb-a7b1-e872f06e9dac
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=728092213 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 32.alert_handler_stress_all_with_rand_reset.728092213
Directory /workspace/32.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.365778107
Short name T576
Test name
Test status
Simulation time 29962500696 ps
CPU time 730.07 seconds
Started Aug 10 04:39:52 PM PDT 24
Finished Aug 10 04:52:02 PM PDT 24
Peak memory 264536 kb
Host smart-e49ccf75-8367-40f4-b6c3-953cb2224cb5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=365778107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.365778107
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.518307924
Short name T698
Test name
Test status
Simulation time 4415020923 ps
CPU time 52.3 seconds
Started Aug 10 04:39:51 PM PDT 24
Finished Aug 10 04:40:43 PM PDT 24
Peak memory 256444 kb
Host smart-6c10446a-a705-4bb7-b606-6d76b7a943ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51830
7924 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.518307924
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.3809193895
Short name T516
Test name
Test status
Simulation time 395390634 ps
CPU time 10.84 seconds
Started Aug 10 04:39:44 PM PDT 24
Finished Aug 10 04:39:55 PM PDT 24
Peak memory 247836 kb
Host smart-01a7ffe2-4231-4dea-b9a5-fc2a335303a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38091
93895 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.3809193895
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.1187312042
Short name T648
Test name
Test status
Simulation time 19934244319 ps
CPU time 1193.81 seconds
Started Aug 10 04:39:45 PM PDT 24
Finished Aug 10 04:59:39 PM PDT 24
Peak memory 272680 kb
Host smart-a1156265-b6e8-4293-a6d6-1dbec40538c3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1187312042 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.1187312042
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.1891763632
Short name T565
Test name
Test status
Simulation time 23509932454 ps
CPU time 1625.38 seconds
Started Aug 10 04:39:48 PM PDT 24
Finished Aug 10 05:06:54 PM PDT 24
Peak memory 273164 kb
Host smart-16e14ee1-5881-4ce4-b3ec-40970333d732
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1891763632 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.1891763632
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.1144825106
Short name T601
Test name
Test status
Simulation time 14058525368 ps
CPU time 577.52 seconds
Started Aug 10 04:39:51 PM PDT 24
Finished Aug 10 04:49:29 PM PDT 24
Peak memory 254804 kb
Host smart-42c2012f-27d8-42e0-8b59-4d2c6e0fa796
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1144825106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.1144825106
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.4093256551
Short name T593
Test name
Test status
Simulation time 793235070 ps
CPU time 45.26 seconds
Started Aug 10 04:39:48 PM PDT 24
Finished Aug 10 04:40:33 PM PDT 24
Peak memory 248168 kb
Host smart-5802ac89-3d61-442a-8187-5290cd3ce0cb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40932
56551 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.4093256551
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.3273136769
Short name T421
Test name
Test status
Simulation time 1164547389 ps
CPU time 16.7 seconds
Started Aug 10 04:39:48 PM PDT 24
Finished Aug 10 04:40:05 PM PDT 24
Peak memory 255172 kb
Host smart-2a939434-586f-401b-8708-ee084a118704
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32731
36769 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.3273136769
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.3855196319
Short name T21
Test name
Test status
Simulation time 12091740950 ps
CPU time 57.69 seconds
Started Aug 10 04:39:49 PM PDT 24
Finished Aug 10 04:40:47 PM PDT 24
Peak memory 255384 kb
Host smart-d947e275-af2d-46be-8eaf-74de3cfd017d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38551
96319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.3855196319
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.2462027019
Short name T295
Test name
Test status
Simulation time 179785828879 ps
CPU time 2339.3 seconds
Started Aug 10 04:39:45 PM PDT 24
Finished Aug 10 05:18:45 PM PDT 24
Peak memory 289088 kb
Host smart-e774d426-e11e-4fa3-9347-1d8363a79fcc
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2462027019 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_ha
ndler_stress_all.2462027019
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all_with_rand_reset.3432362861
Short name T76
Test name
Test status
Simulation time 17999252708 ps
CPU time 1806.67 seconds
Started Aug 10 04:39:49 PM PDT 24
Finished Aug 10 05:09:56 PM PDT 24
Peak memory 305436 kb
Host smart-71e645e7-9e65-4e3a-bee0-2284f4350500
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3432362861 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.alert_handler_stress_all_with_rand_reset.3432362861
Directory /workspace/33.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.1533682549
Short name T66
Test name
Test status
Simulation time 48901150417 ps
CPU time 1454.37 seconds
Started Aug 10 04:39:43 PM PDT 24
Finished Aug 10 05:03:58 PM PDT 24
Peak memory 284524 kb
Host smart-39cb7acb-3fe8-44a3-ba87-8311a107fad8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1533682549 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.1533682549
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.1644156517
Short name T711
Test name
Test status
Simulation time 5742509690 ps
CPU time 313.77 seconds
Started Aug 10 04:39:42 PM PDT 24
Finished Aug 10 04:44:56 PM PDT 24
Peak memory 256544 kb
Host smart-2e230320-fe91-457d-947c-bdc95391e325
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16441
56517 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.1644156517
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.3659162386
Short name T447
Test name
Test status
Simulation time 87561486541 ps
CPU time 1306.13 seconds
Started Aug 10 04:39:47 PM PDT 24
Finished Aug 10 05:01:34 PM PDT 24
Peak memory 272768 kb
Host smart-7d165936-4d4a-4b74-92a8-0c131c850c7d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3659162386 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.3659162386
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.133989686
Short name T407
Test name
Test status
Simulation time 13431955809 ps
CPU time 1043.57 seconds
Started Aug 10 04:39:44 PM PDT 24
Finished Aug 10 04:57:08 PM PDT 24
Peak memory 284500 kb
Host smart-59208291-14ef-41bd-aa89-a32fcabc8360
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=133989686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.133989686
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.2355712026
Short name T322
Test name
Test status
Simulation time 9480627263 ps
CPU time 267.55 seconds
Started Aug 10 04:39:45 PM PDT 24
Finished Aug 10 04:44:13 PM PDT 24
Peak memory 248304 kb
Host smart-995dac65-7717-4155-972a-9a3e275990d9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355712026 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.2355712026
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.3350156271
Short name T229
Test name
Test status
Simulation time 2102665025 ps
CPU time 68.1 seconds
Started Aug 10 04:39:45 PM PDT 24
Finished Aug 10 04:40:54 PM PDT 24
Peak memory 248232 kb
Host smart-a3c493e9-6277-4696-b274-cd52614a5a30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33501
56271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.3350156271
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.625146649
Short name T632
Test name
Test status
Simulation time 289775855 ps
CPU time 18.27 seconds
Started Aug 10 04:39:52 PM PDT 24
Finished Aug 10 04:40:10 PM PDT 24
Peak memory 247472 kb
Host smart-b87f5766-ae17-44a6-a40a-8ac871e7eb82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62514
6649 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.625146649
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.688762752
Short name T416
Test name
Test status
Simulation time 232506759 ps
CPU time 20.88 seconds
Started Aug 10 04:39:54 PM PDT 24
Finished Aug 10 04:40:15 PM PDT 24
Peak memory 256332 kb
Host smart-a690fb11-bbf0-4b39-8499-9889a7262778
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68876
2752 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.688762752
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.2038737529
Short name T112
Test name
Test status
Simulation time 9067005470 ps
CPU time 298.34 seconds
Started Aug 10 04:39:52 PM PDT 24
Finished Aug 10 04:44:50 PM PDT 24
Peak memory 256424 kb
Host smart-4a5b4dab-d48f-4e3d-be13-0a8bba94bfea
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2038737529 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_ha
ndler_stress_all.2038737529
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.3085264027
Short name T109
Test name
Test status
Simulation time 27446470296 ps
CPU time 1871.36 seconds
Started Aug 10 04:39:51 PM PDT 24
Finished Aug 10 05:11:03 PM PDT 24
Peak memory 280788 kb
Host smart-77aa500e-ee81-476b-89ae-d073ed3fe12f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085264027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.3085264027
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.2374794809
Short name T590
Test name
Test status
Simulation time 1618095510 ps
CPU time 107.15 seconds
Started Aug 10 04:39:46 PM PDT 24
Finished Aug 10 04:41:34 PM PDT 24
Peak memory 256440 kb
Host smart-e94f9cd0-ffd7-4204-831e-444213e25f46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23747
94809 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.2374794809
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.3653436545
Short name T433
Test name
Test status
Simulation time 5186936824 ps
CPU time 43.18 seconds
Started Aug 10 04:39:46 PM PDT 24
Finished Aug 10 04:40:30 PM PDT 24
Peak memory 256084 kb
Host smart-67db1e53-de82-4d68-a92e-107f781b84d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36534
36545 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.3653436545
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.3348578341
Short name T331
Test name
Test status
Simulation time 41683333954 ps
CPU time 2470.02 seconds
Started Aug 10 04:39:50 PM PDT 24
Finished Aug 10 05:21:00 PM PDT 24
Peak memory 272848 kb
Host smart-e8102db4-a6da-4c83-bce6-d4b15fcaf679
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3348578341 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.3348578341
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.3085026819
Short name T623
Test name
Test status
Simulation time 400685456680 ps
CPU time 2355.28 seconds
Started Aug 10 04:39:54 PM PDT 24
Finished Aug 10 05:19:09 PM PDT 24
Peak memory 282820 kb
Host smart-b2587a3f-f0bd-4368-844d-3a3ec1fa432d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3085026819 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.3085026819
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.2355812891
Short name T15
Test name
Test status
Simulation time 16593638987 ps
CPU time 219.65 seconds
Started Aug 10 04:39:45 PM PDT 24
Finished Aug 10 04:43:25 PM PDT 24
Peak memory 248208 kb
Host smart-41a812b3-5a81-4f2e-9d8d-1e9265e97843
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2355812891 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.2355812891
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.3790065275
Short name T44
Test name
Test status
Simulation time 168302901 ps
CPU time 12.81 seconds
Started Aug 10 04:39:50 PM PDT 24
Finished Aug 10 04:40:03 PM PDT 24
Peak memory 248536 kb
Host smart-e5bdf835-7994-4ef0-aec0-a4ec2f356d41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37900
65275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.3790065275
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.3573249773
Short name T98
Test name
Test status
Simulation time 2092000922 ps
CPU time 33.44 seconds
Started Aug 10 04:39:50 PM PDT 24
Finished Aug 10 04:40:24 PM PDT 24
Peak memory 247592 kb
Host smart-62b434d9-cfca-47f3-baaf-468f86e28c65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35732
49773 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.3573249773
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.3448449173
Short name T427
Test name
Test status
Simulation time 478864641 ps
CPU time 32.04 seconds
Started Aug 10 04:39:45 PM PDT 24
Finished Aug 10 04:40:18 PM PDT 24
Peak memory 255944 kb
Host smart-221e9cfe-45c6-44be-a991-19f398665363
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34484
49173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.3448449173
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.986964722
Short name T411
Test name
Test status
Simulation time 2472757351 ps
CPU time 74.46 seconds
Started Aug 10 04:39:53 PM PDT 24
Finished Aug 10 04:41:08 PM PDT 24
Peak memory 255396 kb
Host smart-b7daf373-9082-4c2e-8b35-896db981797a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98696
4722 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.986964722
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.2650330526
Short name T453
Test name
Test status
Simulation time 28949670907 ps
CPU time 1607.45 seconds
Started Aug 10 04:39:51 PM PDT 24
Finished Aug 10 05:06:39 PM PDT 24
Peak memory 300964 kb
Host smart-dc754534-8d79-4e0d-a63f-c4a02d0e7014
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650330526 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_ha
ndler_stress_all.2650330526
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.3127334951
Short name T444
Test name
Test status
Simulation time 28085605943 ps
CPU time 835.42 seconds
Started Aug 10 04:39:47 PM PDT 24
Finished Aug 10 04:53:42 PM PDT 24
Peak memory 272256 kb
Host smart-773a5e62-ef71-4d9c-a6d5-77065bbfb86b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3127334951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.3127334951
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.1129825220
Short name T222
Test name
Test status
Simulation time 2815431359 ps
CPU time 87.2 seconds
Started Aug 10 04:39:48 PM PDT 24
Finished Aug 10 04:41:15 PM PDT 24
Peak memory 256488 kb
Host smart-1c6267ff-ede2-4704-8196-c7e580dcdfbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11298
25220 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.1129825220
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.432909160
Short name T291
Test name
Test status
Simulation time 678374071 ps
CPU time 40.26 seconds
Started Aug 10 04:39:47 PM PDT 24
Finished Aug 10 04:40:28 PM PDT 24
Peak memory 248080 kb
Host smart-746842dc-de3f-4535-bd33-c0e537083b16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43290
9160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.432909160
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.3298263753
Short name T251
Test name
Test status
Simulation time 52577694701 ps
CPU time 2568.56 seconds
Started Aug 10 04:39:54 PM PDT 24
Finished Aug 10 05:22:43 PM PDT 24
Peak memory 288396 kb
Host smart-a85952fa-6999-48ef-aecf-41fb6ea0c337
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298263753 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.3298263753
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.2456347096
Short name T634
Test name
Test status
Simulation time 5454264177 ps
CPU time 216.9 seconds
Started Aug 10 04:39:47 PM PDT 24
Finished Aug 10 04:43:24 PM PDT 24
Peak memory 254576 kb
Host smart-a4515bc2-fd7d-4358-a9f1-fe73b2c599f5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2456347096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.2456347096
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.1154318882
Short name T276
Test name
Test status
Simulation time 1092865695 ps
CPU time 16.7 seconds
Started Aug 10 04:39:55 PM PDT 24
Finished Aug 10 04:40:11 PM PDT 24
Peak memory 248160 kb
Host smart-f3cc8f42-f707-435f-aa6f-f966ad389c05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11543
18882 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.1154318882
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.1672112822
Short name T97
Test name
Test status
Simulation time 464095373 ps
CPU time 43.77 seconds
Started Aug 10 04:39:45 PM PDT 24
Finished Aug 10 04:40:30 PM PDT 24
Peak memory 247828 kb
Host smart-6673c69a-468e-4931-b238-51e4b30d7e59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16721
12822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.1672112822
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.1915361697
Short name T275
Test name
Test status
Simulation time 1066472986 ps
CPU time 27.72 seconds
Started Aug 10 04:39:51 PM PDT 24
Finished Aug 10 04:40:18 PM PDT 24
Peak memory 248752 kb
Host smart-01692c92-8762-4550-a9cb-35bc1d0e21f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19153
61697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.1915361697
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.3101013307
Short name T385
Test name
Test status
Simulation time 153326572 ps
CPU time 11.56 seconds
Started Aug 10 04:39:48 PM PDT 24
Finished Aug 10 04:40:00 PM PDT 24
Peak memory 254416 kb
Host smart-5ab62137-472b-45f8-9b92-f865be1b21dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31010
13307 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.3101013307
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.4185575674
Short name T654
Test name
Test status
Simulation time 2203813304 ps
CPU time 255.83 seconds
Started Aug 10 04:39:52 PM PDT 24
Finished Aug 10 04:44:08 PM PDT 24
Peak memory 256548 kb
Host smart-fa1af70f-9dc6-4fcf-bd90-beb44a749577
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4185575674 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_ha
ndler_stress_all.4185575674
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.3722861507
Short name T393
Test name
Test status
Simulation time 398741610733 ps
CPU time 1660.37 seconds
Started Aug 10 04:39:46 PM PDT 24
Finished Aug 10 05:07:27 PM PDT 24
Peak memory 272708 kb
Host smart-5a05e73f-2f7c-47d1-af2b-f919e3af44c9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3722861507 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.3722861507
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.2729935910
Short name T585
Test name
Test status
Simulation time 8107929197 ps
CPU time 263.25 seconds
Started Aug 10 04:39:48 PM PDT 24
Finished Aug 10 04:44:12 PM PDT 24
Peak memory 256464 kb
Host smart-b1d4efac-5d62-4283-aef2-6b7f862e13a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27299
35910 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.2729935910
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.1072648760
Short name T702
Test name
Test status
Simulation time 4280095897 ps
CPU time 45.54 seconds
Started Aug 10 04:39:45 PM PDT 24
Finished Aug 10 04:40:31 PM PDT 24
Peak memory 248068 kb
Host smart-2a996e1e-3b14-48e7-b798-243f274958c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10726
48760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.1072648760
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.2746850354
Short name T658
Test name
Test status
Simulation time 109335509983 ps
CPU time 1695.71 seconds
Started Aug 10 04:39:49 PM PDT 24
Finished Aug 10 05:08:05 PM PDT 24
Peak memory 272164 kb
Host smart-b830133c-df9c-4b76-842b-9f48bc656bae
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2746850354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.2746850354
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.2612982238
Short name T573
Test name
Test status
Simulation time 11326331721 ps
CPU time 1213.42 seconds
Started Aug 10 04:39:56 PM PDT 24
Finished Aug 10 05:00:10 PM PDT 24
Peak memory 289020 kb
Host smart-0a5fe927-158c-4888-aede-743233c6b1df
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2612982238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.2612982238
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.2588376096
Short name T310
Test name
Test status
Simulation time 8935478269 ps
CPU time 380.17 seconds
Started Aug 10 04:39:54 PM PDT 24
Finished Aug 10 04:46:14 PM PDT 24
Peak memory 248056 kb
Host smart-83b1347c-8d01-47a8-8c0c-27f8895bb984
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2588376096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.2588376096
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.780239424
Short name T605
Test name
Test status
Simulation time 1691604224 ps
CPU time 62.51 seconds
Started Aug 10 04:39:54 PM PDT 24
Finished Aug 10 04:40:56 PM PDT 24
Peak memory 255704 kb
Host smart-752ca388-3831-463c-b5d6-e3a4524fa98f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=78023
9424 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.780239424
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.4059959744
Short name T466
Test name
Test status
Simulation time 315170431 ps
CPU time 23.66 seconds
Started Aug 10 04:39:48 PM PDT 24
Finished Aug 10 04:40:12 PM PDT 24
Peak memory 248012 kb
Host smart-a95627b4-d08b-4f0d-a139-9732fc18ed7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40599
59744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.4059959744
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.3906368705
Short name T82
Test name
Test status
Simulation time 529122660 ps
CPU time 10.57 seconds
Started Aug 10 04:39:48 PM PDT 24
Finished Aug 10 04:39:58 PM PDT 24
Peak memory 252608 kb
Host smart-054d9141-0c3b-44e0-9c68-9a301ca1c5d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39063
68705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.3906368705
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.3972218392
Short name T495
Test name
Test status
Simulation time 491536063 ps
CPU time 35.42 seconds
Started Aug 10 04:39:47 PM PDT 24
Finished Aug 10 04:40:23 PM PDT 24
Peak memory 256508 kb
Host smart-27a72ebc-7ff6-4a97-86cf-dcd71f1ec110
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39722
18392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.3972218392
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.2619279636
Short name T242
Test name
Test status
Simulation time 8703113661 ps
CPU time 766.16 seconds
Started Aug 10 04:39:55 PM PDT 24
Finished Aug 10 04:52:41 PM PDT 24
Peak memory 272760 kb
Host smart-6d9e2344-9c41-4897-b056-d7d2e0d6a739
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2619279636 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_ha
ndler_stress_all.2619279636
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.2148504865
Short name T629
Test name
Test status
Simulation time 11792981245 ps
CPU time 1043.19 seconds
Started Aug 10 04:39:58 PM PDT 24
Finished Aug 10 04:57:21 PM PDT 24
Peak memory 280396 kb
Host smart-414189c6-422e-4110-a802-0f45786c3660
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148504865 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.2148504865
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.3703603281
Short name T556
Test name
Test status
Simulation time 1060745712 ps
CPU time 69.33 seconds
Started Aug 10 04:40:01 PM PDT 24
Finished Aug 10 04:41:10 PM PDT 24
Peak memory 249264 kb
Host smart-3c323e42-d871-4534-afcc-e7c7deeb7868
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37036
03281 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.3703603281
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.338578167
Short name T482
Test name
Test status
Simulation time 124606085 ps
CPU time 9.31 seconds
Started Aug 10 04:39:53 PM PDT 24
Finished Aug 10 04:40:02 PM PDT 24
Peak memory 254404 kb
Host smart-a004bac3-de8d-43ef-8ef4-e08489ccbaaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33857
8167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.338578167
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.4280896805
Short name T223
Test name
Test status
Simulation time 21016718792 ps
CPU time 938.49 seconds
Started Aug 10 04:39:57 PM PDT 24
Finished Aug 10 04:55:36 PM PDT 24
Peak memory 272832 kb
Host smart-d9ac015a-7f38-4aa0-83c3-b457a98564dc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4280896805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.4280896805
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.1628704037
Short name T558
Test name
Test status
Simulation time 8944039833 ps
CPU time 692.25 seconds
Started Aug 10 04:39:57 PM PDT 24
Finished Aug 10 04:51:29 PM PDT 24
Peak memory 272764 kb
Host smart-91953c61-2c00-40aa-8a72-4ba9e0488d6c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1628704037 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.1628704037
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.3745289040
Short name T365
Test name
Test status
Simulation time 852744015 ps
CPU time 50.36 seconds
Started Aug 10 04:39:57 PM PDT 24
Finished Aug 10 04:40:48 PM PDT 24
Peak memory 255816 kb
Host smart-761cadc4-c3ba-4031-8137-24e001d37905
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37452
89040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.3745289040
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.2662230816
Short name T481
Test name
Test status
Simulation time 747526634 ps
CPU time 15.32 seconds
Started Aug 10 04:39:56 PM PDT 24
Finished Aug 10 04:40:12 PM PDT 24
Peak memory 253956 kb
Host smart-fc3eb1fa-0887-4310-9a33-b05f4195e0a8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26622
30816 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.2662230816
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.2261136819
Short name T673
Test name
Test status
Simulation time 1890546035 ps
CPU time 28.16 seconds
Started Aug 10 04:39:59 PM PDT 24
Finished Aug 10 04:40:27 PM PDT 24
Peak memory 256308 kb
Host smart-c850b0da-c453-4391-b5a0-7c84d8b9107f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22611
36819 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.2261136819
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.573756170
Short name T187
Test name
Test status
Simulation time 232217501 ps
CPU time 18.55 seconds
Started Aug 10 04:39:59 PM PDT 24
Finished Aug 10 04:40:18 PM PDT 24
Peak memory 255484 kb
Host smart-d6187c2a-31af-446f-9d29-eca61268dc6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57375
6170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.573756170
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.3501149456
Short name T255
Test name
Test status
Simulation time 117400104925 ps
CPU time 663.72 seconds
Started Aug 10 04:39:58 PM PDT 24
Finished Aug 10 04:51:01 PM PDT 24
Peak memory 256440 kb
Host smart-8de4c07c-8d1a-454b-8d22-6a1eb73294ed
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3501149456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_ha
ndler_stress_all.3501149456
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.744107577
Short name T451
Test name
Test status
Simulation time 25387538131 ps
CPU time 1587.32 seconds
Started Aug 10 04:39:57 PM PDT 24
Finished Aug 10 05:06:25 PM PDT 24
Peak memory 273160 kb
Host smart-2ecd58ef-63d7-4b42-881a-39d5ec3a6348
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=744107577 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.744107577
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.3821063665
Short name T647
Test name
Test status
Simulation time 2651677398 ps
CPU time 55.19 seconds
Started Aug 10 04:39:55 PM PDT 24
Finished Aug 10 04:40:50 PM PDT 24
Peak memory 256040 kb
Host smart-269d716d-52a4-4438-92cc-568b8e47f75f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38210
63665 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.3821063665
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.3956786639
Short name T640
Test name
Test status
Simulation time 7887595383 ps
CPU time 54.86 seconds
Started Aug 10 04:39:56 PM PDT 24
Finished Aug 10 04:40:51 PM PDT 24
Peak memory 248044 kb
Host smart-b9ff22bf-df50-41a5-a8c3-3bd9bfa53068
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39567
86639 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.3956786639
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.212949833
Short name T345
Test name
Test status
Simulation time 123768818756 ps
CPU time 1725.53 seconds
Started Aug 10 04:39:56 PM PDT 24
Finished Aug 10 05:08:42 PM PDT 24
Peak memory 272152 kb
Host smart-006b4eb9-600b-4a18-8386-12451b222411
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=212949833 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.212949833
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.3926933846
Short name T678
Test name
Test status
Simulation time 82148531036 ps
CPU time 1387.57 seconds
Started Aug 10 04:39:56 PM PDT 24
Finished Aug 10 05:03:03 PM PDT 24
Peak memory 286792 kb
Host smart-730a50a6-bbcf-4271-b695-fc1a51ed9ae6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3926933846 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.3926933846
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.2976172650
Short name T312
Test name
Test status
Simulation time 20787749249 ps
CPU time 408.17 seconds
Started Aug 10 04:39:57 PM PDT 24
Finished Aug 10 04:46:45 PM PDT 24
Peak memory 248180 kb
Host smart-9df9178c-3412-40e9-b5c7-9864caed6c0f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976172650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.2976172650
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.1081077738
Short name T513
Test name
Test status
Simulation time 3429414931 ps
CPU time 59.43 seconds
Started Aug 10 04:39:55 PM PDT 24
Finished Aug 10 04:40:55 PM PDT 24
Peak memory 256476 kb
Host smart-8ad7b46f-8b45-4b05-88db-e8157abdf1d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10810
77738 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.1081077738
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.285453238
Short name T58
Test name
Test status
Simulation time 1328868722 ps
CPU time 9.46 seconds
Started Aug 10 04:39:54 PM PDT 24
Finished Aug 10 04:40:04 PM PDT 24
Peak memory 247812 kb
Host smart-3227cbde-2c4e-4e4f-9312-51f1c4ef903e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28545
3238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.285453238
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.1681206004
Short name T507
Test name
Test status
Simulation time 852236570 ps
CPU time 12.01 seconds
Started Aug 10 04:39:57 PM PDT 24
Finished Aug 10 04:40:09 PM PDT 24
Peak memory 248220 kb
Host smart-eb7964a4-9104-4485-a1a6-bbfe818d2181
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16812
06004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.1681206004
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.876701322
Short name T202
Test name
Test status
Simulation time 84690601 ps
CPU time 3.86 seconds
Started Aug 10 04:39:03 PM PDT 24
Finished Aug 10 04:39:07 PM PDT 24
Peak memory 248176 kb
Host smart-6381097a-be9f-4be0-b9ef-9525c8aa6f54
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=876701322 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.876701322
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.2671070330
Short name T468
Test name
Test status
Simulation time 175006134233 ps
CPU time 2561.79 seconds
Started Aug 10 04:39:03 PM PDT 24
Finished Aug 10 05:21:45 PM PDT 24
Peak memory 288228 kb
Host smart-1005adb1-043d-410d-94aa-4f1ac60b94de
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671070330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.2671070330
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.2465199339
Short name T596
Test name
Test status
Simulation time 88019495 ps
CPU time 6.41 seconds
Started Aug 10 04:38:50 PM PDT 24
Finished Aug 10 04:38:57 PM PDT 24
Peak memory 248152 kb
Host smart-3d7b5d0f-2f5c-4fb0-9960-5872a3d316e7
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2465199339 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.2465199339
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.3769812077
Short name T484
Test name
Test status
Simulation time 18301828585 ps
CPU time 258.53 seconds
Started Aug 10 04:38:58 PM PDT 24
Finished Aug 10 04:43:16 PM PDT 24
Peak memory 255908 kb
Host smart-9d72f95d-1b0b-4494-b1a7-445a39ebc151
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37698
12077 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.3769812077
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.1558588992
Short name T577
Test name
Test status
Simulation time 283454554 ps
CPU time 14.51 seconds
Started Aug 10 04:38:48 PM PDT 24
Finished Aug 10 04:39:03 PM PDT 24
Peak memory 256448 kb
Host smart-a2ea5b57-120e-4344-8288-64a1e21fdf21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15585
88992 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.1558588992
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.2651426132
Short name T392
Test name
Test status
Simulation time 37376087792 ps
CPU time 735.85 seconds
Started Aug 10 04:38:50 PM PDT 24
Finished Aug 10 04:51:07 PM PDT 24
Peak memory 272176 kb
Host smart-012fcbef-bff1-47ea-8e1d-85c7b9b19e5d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2651426132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.2651426132
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.4056255688
Short name T652
Test name
Test status
Simulation time 17904390485 ps
CPU time 396.79 seconds
Started Aug 10 04:38:57 PM PDT 24
Finished Aug 10 04:45:34 PM PDT 24
Peak memory 248220 kb
Host smart-b4c9ada0-dfb5-4a42-bfaf-3d492742bf1b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4056255688 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.4056255688
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.2145039097
Short name T626
Test name
Test status
Simulation time 894808768 ps
CPU time 38.22 seconds
Started Aug 10 04:38:49 PM PDT 24
Finished Aug 10 04:39:27 PM PDT 24
Peak memory 248228 kb
Host smart-be3c0937-1de7-4392-aaef-eda186761f52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21450
39097 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.2145039097
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.2036658098
Short name T458
Test name
Test status
Simulation time 1640915484 ps
CPU time 43.34 seconds
Started Aug 10 04:39:00 PM PDT 24
Finished Aug 10 04:39:44 PM PDT 24
Peak memory 256396 kb
Host smart-929aa124-2df7-4238-b913-8daa1195173f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20366
58098 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.2036658098
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.1177032593
Short name T35
Test name
Test status
Simulation time 401296254 ps
CPU time 14.03 seconds
Started Aug 10 04:38:53 PM PDT 24
Finished Aug 10 04:39:08 PM PDT 24
Peak memory 269416 kb
Host smart-0cdec095-1a43-4147-9f97-5a991f277356
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1177032593 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.1177032593
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.2629423431
Short name T387
Test name
Test status
Simulation time 2578191621 ps
CPU time 45.01 seconds
Started Aug 10 04:38:50 PM PDT 24
Finished Aug 10 04:39:35 PM PDT 24
Peak memory 256432 kb
Host smart-3bcfd979-938e-4153-89ee-2875cc25791a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26294
23431 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.2629423431
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.2892456926
Short name T298
Test name
Test status
Simulation time 347523028981 ps
CPU time 3217.89 seconds
Started Aug 10 04:38:52 PM PDT 24
Finished Aug 10 05:32:31 PM PDT 24
Peak memory 288424 kb
Host smart-a12b1540-17f9-4639-9e43-8d087c7888ff
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2892456926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_han
dler_stress_all.2892456926
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.943944735
Short name T510
Test name
Test status
Simulation time 21854044144 ps
CPU time 1690.82 seconds
Started Aug 10 04:40:03 PM PDT 24
Finished Aug 10 05:08:14 PM PDT 24
Peak memory 288336 kb
Host smart-75f53060-d4b9-4532-80b6-8cbd596390d1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943944735 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.943944735
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.286447299
Short name T41
Test name
Test status
Simulation time 4231584984 ps
CPU time 32.03 seconds
Started Aug 10 04:40:06 PM PDT 24
Finished Aug 10 04:40:38 PM PDT 24
Peak memory 256376 kb
Host smart-ec3f3e27-e797-405b-8c08-084b328acf59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28644
7299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.286447299
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.2271016479
Short name T445
Test name
Test status
Simulation time 6573616043 ps
CPU time 57.4 seconds
Started Aug 10 04:40:05 PM PDT 24
Finished Aug 10 04:41:03 PM PDT 24
Peak memory 248264 kb
Host smart-d9854a6b-61dd-4de8-8287-7d1be14e4e01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22710
16479 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.2271016479
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.724263998
Short name T73
Test name
Test status
Simulation time 61388551959 ps
CPU time 1757 seconds
Started Aug 10 04:40:06 PM PDT 24
Finished Aug 10 05:09:24 PM PDT 24
Peak memory 271976 kb
Host smart-44e33dcf-5c14-4d82-9e24-41e3f077e1dd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724263998 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.724263998
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.810809754
Short name T383
Test name
Test status
Simulation time 53255586096 ps
CPU time 955.06 seconds
Started Aug 10 04:40:10 PM PDT 24
Finished Aug 10 04:56:05 PM PDT 24
Peak memory 284408 kb
Host smart-5b9b75b5-4802-4eba-b691-7dd073ca2b4a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=810809754 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.810809754
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.4191663407
Short name T305
Test name
Test status
Simulation time 7839483891 ps
CPU time 346.93 seconds
Started Aug 10 04:40:04 PM PDT 24
Finished Aug 10 04:45:51 PM PDT 24
Peak memory 254900 kb
Host smart-52c5bf82-5cd8-4f95-bebf-cf586f762fb9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4191663407 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.4191663407
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.1556972590
Short name T26
Test name
Test status
Simulation time 724598500 ps
CPU time 35.55 seconds
Started Aug 10 04:39:57 PM PDT 24
Finished Aug 10 04:40:33 PM PDT 24
Peak memory 248164 kb
Host smart-8e7d239a-56a7-42b3-91b0-2c51a74cc63a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15569
72590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.1556972590
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.1706559252
Short name T547
Test name
Test status
Simulation time 674683668 ps
CPU time 24.05 seconds
Started Aug 10 04:40:04 PM PDT 24
Finished Aug 10 04:40:28 PM PDT 24
Peak memory 255988 kb
Host smart-c468c2fa-1e01-4149-8ded-6f2f5bb23cd1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17065
59252 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.1706559252
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.1697896009
Short name T120
Test name
Test status
Simulation time 2626162949 ps
CPU time 26.73 seconds
Started Aug 10 04:40:06 PM PDT 24
Finished Aug 10 04:40:33 PM PDT 24
Peak memory 248888 kb
Host smart-ca6e561d-35df-4f92-bab8-33196178cb72
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16978
96009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.1697896009
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.1525508996
Short name T642
Test name
Test status
Simulation time 3948015934 ps
CPU time 63.27 seconds
Started Aug 10 04:39:54 PM PDT 24
Finished Aug 10 04:40:57 PM PDT 24
Peak memory 248788 kb
Host smart-16f3ded6-50a3-4d75-a243-c636728aae24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15255
08996 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.1525508996
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all_with_rand_reset.4269670251
Short name T492
Test name
Test status
Simulation time 45364564140 ps
CPU time 3293.41 seconds
Started Aug 10 04:40:05 PM PDT 24
Finished Aug 10 05:34:59 PM PDT 24
Peak memory 304956 kb
Host smart-56b3cb6a-be07-4a56-97eb-de035da44783
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4269670251 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.alert_handler_stress_all_with_rand_reset.4269670251
Directory /workspace/40.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.4033957672
Short name T570
Test name
Test status
Simulation time 128214171988 ps
CPU time 1922.84 seconds
Started Aug 10 04:40:05 PM PDT 24
Finished Aug 10 05:12:09 PM PDT 24
Peak memory 272712 kb
Host smart-c9ca11a6-29fd-4bdf-9b11-c02637d969a5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4033957672 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.4033957672
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.2002641975
Short name T47
Test name
Test status
Simulation time 1157913447 ps
CPU time 93.75 seconds
Started Aug 10 04:40:06 PM PDT 24
Finished Aug 10 04:41:40 PM PDT 24
Peak memory 255800 kb
Host smart-1c025158-a50f-43d0-a9be-9b28fc82b2be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20026
41975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.2002641975
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.4085001924
Short name T432
Test name
Test status
Simulation time 116923435 ps
CPU time 5.12 seconds
Started Aug 10 04:40:03 PM PDT 24
Finished Aug 10 04:40:09 PM PDT 24
Peak memory 251028 kb
Host smart-af32f6de-00eb-45a8-982e-820b3e19460a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40850
01924 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.4085001924
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.3635678582
Short name T342
Test name
Test status
Simulation time 308695729392 ps
CPU time 2767.09 seconds
Started Aug 10 04:40:06 PM PDT 24
Finished Aug 10 05:26:13 PM PDT 24
Peak memory 288496 kb
Host smart-7a69af72-2b81-4b12-b83d-123e5fb25053
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3635678582 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.3635678582
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.3928225677
Short name T696
Test name
Test status
Simulation time 24202969131 ps
CPU time 1330.39 seconds
Started Aug 10 04:40:04 PM PDT 24
Finished Aug 10 05:02:15 PM PDT 24
Peak memory 272288 kb
Host smart-56487276-8746-44c4-83ae-cca3e78044d5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3928225677 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.3928225677
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.4186554850
Short name T321
Test name
Test status
Simulation time 5498005451 ps
CPU time 225.23 seconds
Started Aug 10 04:40:03 PM PDT 24
Finished Aug 10 04:43:49 PM PDT 24
Peak memory 248256 kb
Host smart-46c031dd-f52e-46a1-acdc-7a8079ff836f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4186554850 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.4186554850
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.1220936222
Short name T575
Test name
Test status
Simulation time 2610968171 ps
CPU time 38.68 seconds
Started Aug 10 04:40:05 PM PDT 24
Finished Aug 10 04:40:44 PM PDT 24
Peak memory 256276 kb
Host smart-c0767f96-25e5-4d18-a65a-7d7d5ea921f6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12209
36222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.1220936222
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.2769176009
Short name T108
Test name
Test status
Simulation time 1105545694 ps
CPU time 32.45 seconds
Started Aug 10 04:40:03 PM PDT 24
Finished Aug 10 04:40:35 PM PDT 24
Peak memory 248232 kb
Host smart-859feaab-f84c-4d05-b6c3-e7aef5a80f53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27691
76009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.2769176009
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.4007208430
Short name T123
Test name
Test status
Simulation time 742444563 ps
CPU time 15.89 seconds
Started Aug 10 04:40:05 PM PDT 24
Finished Aug 10 04:40:21 PM PDT 24
Peak memory 247584 kb
Host smart-a12fdf26-4ae2-46a8-aac8-bf05cb9eda79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40072
08430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.4007208430
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.2152938002
Short name T669
Test name
Test status
Simulation time 1366399139 ps
CPU time 40.21 seconds
Started Aug 10 04:40:04 PM PDT 24
Finished Aug 10 04:40:45 PM PDT 24
Peak memory 255476 kb
Host smart-6569364b-14e6-4684-8e39-7c65bbef93a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21529
38002 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.2152938002
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all_with_rand_reset.3721625590
Short name T30
Test name
Test status
Simulation time 313508575084 ps
CPU time 7191.76 seconds
Started Aug 10 04:40:05 PM PDT 24
Finished Aug 10 06:39:57 PM PDT 24
Peak memory 394556 kb
Host smart-2f84b517-fa3b-475f-bfb9-7b2edd0fcd20
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721625590 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.alert_handler_stress_all_with_rand_reset.3721625590
Directory /workspace/41.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.3686935858
Short name T705
Test name
Test status
Simulation time 96698779662 ps
CPU time 1315.88 seconds
Started Aug 10 04:40:13 PM PDT 24
Finished Aug 10 05:02:09 PM PDT 24
Peak memory 272128 kb
Host smart-4d108f92-67d9-480c-9134-921540e21c76
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3686935858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.3686935858
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.1831195947
Short name T226
Test name
Test status
Simulation time 915735751 ps
CPU time 4.74 seconds
Started Aug 10 04:40:04 PM PDT 24
Finished Aug 10 04:40:09 PM PDT 24
Peak memory 239568 kb
Host smart-69f53ea7-c470-4fa1-b542-4b49191bbfed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18311
95947 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.1831195947
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.4035543670
Short name T571
Test name
Test status
Simulation time 23791903 ps
CPU time 2.82 seconds
Started Aug 10 04:40:03 PM PDT 24
Finished Aug 10 04:40:06 PM PDT 24
Peak memory 239972 kb
Host smart-d92725a5-6959-45a4-8b9d-dce83238d515
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40355
43670 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.4035543670
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.3677207476
Short name T692
Test name
Test status
Simulation time 104193708622 ps
CPU time 1642.41 seconds
Started Aug 10 04:40:15 PM PDT 24
Finished Aug 10 05:07:38 PM PDT 24
Peak memory 272936 kb
Host smart-0f712413-66ed-4541-bfff-18af35fd289f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3677207476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.3677207476
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.1664250665
Short name T543
Test name
Test status
Simulation time 19768613459 ps
CPU time 192.72 seconds
Started Aug 10 04:40:12 PM PDT 24
Finished Aug 10 04:43:25 PM PDT 24
Peak memory 247144 kb
Host smart-53ce766f-4f3d-46b9-9790-ad0e10eae56b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664250665 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.1664250665
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.4089711921
Short name T607
Test name
Test status
Simulation time 241390801 ps
CPU time 16.88 seconds
Started Aug 10 04:40:06 PM PDT 24
Finished Aug 10 04:40:23 PM PDT 24
Peak memory 248184 kb
Host smart-329fc5ec-af2a-429e-af92-90122154ae87
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40897
11921 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.4089711921
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.437737413
Short name T78
Test name
Test status
Simulation time 1252494387 ps
CPU time 39.78 seconds
Started Aug 10 04:40:07 PM PDT 24
Finished Aug 10 04:40:47 PM PDT 24
Peak memory 248172 kb
Host smart-abf25ee8-7e45-4e67-9ea6-c63b0c42eaee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43773
7413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.437737413
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.3882645539
Short name T87
Test name
Test status
Simulation time 455384420 ps
CPU time 29.59 seconds
Started Aug 10 04:40:04 PM PDT 24
Finished Aug 10 04:40:34 PM PDT 24
Peak memory 255876 kb
Host smart-64a50900-55cb-40aa-b002-21fbd4749db5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38826
45539 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.3882645539
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.1905408299
Short name T418
Test name
Test status
Simulation time 297725072 ps
CPU time 34.08 seconds
Started Aug 10 04:40:06 PM PDT 24
Finished Aug 10 04:40:40 PM PDT 24
Peak memory 248236 kb
Host smart-70b2c2c1-da78-4c76-9be8-72e8aa76bbf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19054
08299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.1905408299
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.981115297
Short name T580
Test name
Test status
Simulation time 49452023672 ps
CPU time 1829.05 seconds
Started Aug 10 04:40:13 PM PDT 24
Finished Aug 10 05:10:42 PM PDT 24
Peak memory 272896 kb
Host smart-7b9f1a86-6389-41fe-be1f-3ed0325025b2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=981115297 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_han
dler_stress_all.981115297
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.2775610258
Short name T121
Test name
Test status
Simulation time 90057003898 ps
CPU time 2347.49 seconds
Started Aug 10 04:40:13 PM PDT 24
Finished Aug 10 05:19:21 PM PDT 24
Peak memory 286436 kb
Host smart-a89fe3a3-273e-4529-a65c-37cadd1cde24
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2775610258 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.2775610258
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.668570919
Short name T391
Test name
Test status
Simulation time 5549576379 ps
CPU time 292.29 seconds
Started Aug 10 04:40:12 PM PDT 24
Finished Aug 10 04:45:05 PM PDT 24
Peak memory 255988 kb
Host smart-821d6f38-2163-432e-a2c3-83b88b9d79ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66857
0919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.668570919
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.3703217624
Short name T459
Test name
Test status
Simulation time 2192203767 ps
CPU time 35.32 seconds
Started Aug 10 04:40:14 PM PDT 24
Finished Aug 10 04:40:49 PM PDT 24
Peak memory 248164 kb
Host smart-ed26259a-d708-43a3-a7d9-fe9c854c7f30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37032
17624 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.3703217624
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.2274275456
Short name T243
Test name
Test status
Simulation time 36886833874 ps
CPU time 2206.64 seconds
Started Aug 10 04:40:12 PM PDT 24
Finished Aug 10 05:16:59 PM PDT 24
Peak memory 288204 kb
Host smart-c0bcd1bc-d70c-4f26-bfa6-9f37b05ddf4b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2274275456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.2274275456
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.3560123797
Short name T326
Test name
Test status
Simulation time 11328288467 ps
CPU time 443.48 seconds
Started Aug 10 04:40:13 PM PDT 24
Finished Aug 10 04:47:37 PM PDT 24
Peak memory 248320 kb
Host smart-01d39d63-77c0-4696-a459-0807066f444f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3560123797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.3560123797
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.3755955950
Short name T474
Test name
Test status
Simulation time 929244006 ps
CPU time 18.71 seconds
Started Aug 10 04:40:11 PM PDT 24
Finished Aug 10 04:40:30 PM PDT 24
Peak memory 248200 kb
Host smart-7db3a5cc-171d-4e67-848e-e70d4b7fc10e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37559
55950 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.3755955950
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.2146193450
Short name T636
Test name
Test status
Simulation time 35055441 ps
CPU time 3.76 seconds
Started Aug 10 04:40:13 PM PDT 24
Finished Aug 10 04:40:17 PM PDT 24
Peak memory 239524 kb
Host smart-bab1161d-7bb1-4f5d-bb32-fe237666f24e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21461
93450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.2146193450
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.647980794
Short name T515
Test name
Test status
Simulation time 918100644 ps
CPU time 46.52 seconds
Started Aug 10 04:40:12 PM PDT 24
Finished Aug 10 04:40:59 PM PDT 24
Peak memory 255916 kb
Host smart-210e7c41-c18e-4d07-86eb-2a279fec9d78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64798
0794 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.647980794
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.667292289
Short name T436
Test name
Test status
Simulation time 120812326 ps
CPU time 12.09 seconds
Started Aug 10 04:40:16 PM PDT 24
Finished Aug 10 04:40:28 PM PDT 24
Peak memory 255036 kb
Host smart-4945b65e-dd98-44f1-9646-0d4152adf076
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66729
2289 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.667292289
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.2496659973
Short name T700
Test name
Test status
Simulation time 10227800147 ps
CPU time 326.16 seconds
Started Aug 10 04:40:14 PM PDT 24
Finished Aug 10 04:45:40 PM PDT 24
Peak memory 256480 kb
Host smart-293e7a0b-a2be-4a63-9083-7f47ae821e85
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2496659973 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_ha
ndler_stress_all.2496659973
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.3621296529
Short name T233
Test name
Test status
Simulation time 7584902825 ps
CPU time 877.29 seconds
Started Aug 10 04:40:14 PM PDT 24
Finished Aug 10 04:54:52 PM PDT 24
Peak memory 288076 kb
Host smart-a91b49bb-249a-471b-b122-05a1e96c301b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3621296529 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.3621296529
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.2233909414
Short name T65
Test name
Test status
Simulation time 21380750772 ps
CPU time 294.86 seconds
Started Aug 10 04:40:12 PM PDT 24
Finished Aug 10 04:45:07 PM PDT 24
Peak memory 256452 kb
Host smart-220ab74c-f88a-4a6c-8735-1a1a6eed0e4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22339
09414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.2233909414
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.177249111
Short name T665
Test name
Test status
Simulation time 55687464 ps
CPU time 7.14 seconds
Started Aug 10 04:40:13 PM PDT 24
Finished Aug 10 04:40:20 PM PDT 24
Peak memory 254096 kb
Host smart-910fee87-2897-4834-bd79-85c90628d4c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17724
9111 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.177249111
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.391375372
Short name T561
Test name
Test status
Simulation time 32424868948 ps
CPU time 1348.03 seconds
Started Aug 10 04:40:12 PM PDT 24
Finished Aug 10 05:02:41 PM PDT 24
Peak memory 272088 kb
Host smart-9bf65788-05cc-4593-9408-2ccce5491750
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=391375372 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.391375372
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.1940141158
Short name T496
Test name
Test status
Simulation time 56782451656 ps
CPU time 1312.36 seconds
Started Aug 10 04:40:14 PM PDT 24
Finished Aug 10 05:02:06 PM PDT 24
Peak memory 281284 kb
Host smart-e1df1602-1292-49e7-87f4-abe1d60cf248
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1940141158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.1940141158
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.4887906
Short name T333
Test name
Test status
Simulation time 8807272219 ps
CPU time 377.8 seconds
Started Aug 10 04:40:13 PM PDT 24
Finished Aug 10 04:46:31 PM PDT 24
Peak memory 248104 kb
Host smart-5080493b-7d1b-4011-a02c-ff8933af9c32
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4887906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.4887906
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.4031494244
Short name T664
Test name
Test status
Simulation time 817410149 ps
CPU time 18.4 seconds
Started Aug 10 04:40:14 PM PDT 24
Finished Aug 10 04:40:33 PM PDT 24
Peak memory 255764 kb
Host smart-54f0350c-c079-4347-9868-fc5e6735a672
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40314
94244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.4031494244
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.2731079136
Short name T477
Test name
Test status
Simulation time 209514263 ps
CPU time 11.25 seconds
Started Aug 10 04:40:13 PM PDT 24
Finished Aug 10 04:40:24 PM PDT 24
Peak memory 247500 kb
Host smart-65cb04db-c77d-4d95-9c60-0592cfe0796b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27310
79136 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.2731079136
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.141240721
Short name T359
Test name
Test status
Simulation time 594604158 ps
CPU time 27.11 seconds
Started Aug 10 04:40:16 PM PDT 24
Finished Aug 10 04:40:43 PM PDT 24
Peak memory 248428 kb
Host smart-568fcaa5-8ee0-4e1c-9adc-4ddde5b03e58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14124
0721 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.141240721
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.2474541192
Short name T460
Test name
Test status
Simulation time 3898975857 ps
CPU time 95.52 seconds
Started Aug 10 04:40:12 PM PDT 24
Finished Aug 10 04:41:48 PM PDT 24
Peak memory 256412 kb
Host smart-828ea017-52c8-4433-a53e-9dc300531704
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474541192 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_ha
ndler_stress_all.2474541192
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.4025728043
Short name T96
Test name
Test status
Simulation time 32673287128 ps
CPU time 1142.61 seconds
Started Aug 10 04:40:21 PM PDT 24
Finished Aug 10 04:59:24 PM PDT 24
Peak memory 281100 kb
Host smart-4ec3ffea-9b50-4e8f-9dcb-718b55a93b49
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025728043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.4025728043
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.2109701000
Short name T374
Test name
Test status
Simulation time 9488242119 ps
CPU time 121.01 seconds
Started Aug 10 04:40:25 PM PDT 24
Finished Aug 10 04:42:27 PM PDT 24
Peak memory 255544 kb
Host smart-6d0bf512-453c-471c-b093-3032ac735b81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21097
01000 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.2109701000
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.2995113315
Short name T526
Test name
Test status
Simulation time 2601223019 ps
CPU time 36.35 seconds
Started Aug 10 04:40:22 PM PDT 24
Finished Aug 10 04:40:58 PM PDT 24
Peak memory 247900 kb
Host smart-6ef82b15-70b4-40a4-a28b-3e8a1f67d2ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29951
13315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.2995113315
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.1061906389
Short name T306
Test name
Test status
Simulation time 32638412405 ps
CPU time 2058.77 seconds
Started Aug 10 04:40:22 PM PDT 24
Finished Aug 10 05:14:41 PM PDT 24
Peak memory 282456 kb
Host smart-26d0ab58-bf6a-4e43-8928-dfdf1bfbc40c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061906389 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.1061906389
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.2302509403
Short name T517
Test name
Test status
Simulation time 20580270372 ps
CPU time 1571.86 seconds
Started Aug 10 04:40:22 PM PDT 24
Finished Aug 10 05:06:34 PM PDT 24
Peak memory 289188 kb
Host smart-4864e816-1574-4475-8669-387d618fc7d3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2302509403 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.2302509403
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.3919666767
Short name T514
Test name
Test status
Simulation time 26418692904 ps
CPU time 154.38 seconds
Started Aug 10 04:40:22 PM PDT 24
Finished Aug 10 04:42:56 PM PDT 24
Peak memory 256408 kb
Host smart-f40ddec4-5e2a-4b00-802a-1ee71b085a70
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3919666767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.3919666767
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.974180085
Short name T471
Test name
Test status
Simulation time 1317735676 ps
CPU time 10.68 seconds
Started Aug 10 04:40:13 PM PDT 24
Finished Aug 10 04:40:23 PM PDT 24
Peak memory 248304 kb
Host smart-61b0cb3e-f544-4699-8052-17d89d74c863
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97418
0085 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.974180085
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.2058248597
Short name T100
Test name
Test status
Simulation time 649485527 ps
CPU time 42.5 seconds
Started Aug 10 04:40:21 PM PDT 24
Finished Aug 10 04:41:04 PM PDT 24
Peak memory 256416 kb
Host smart-45982074-6854-4c63-b2de-1ddf1cc84c45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20582
48597 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.2058248597
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.2559601332
Short name T659
Test name
Test status
Simulation time 93503231 ps
CPU time 5.68 seconds
Started Aug 10 04:40:14 PM PDT 24
Finished Aug 10 04:40:20 PM PDT 24
Peak memory 250808 kb
Host smart-9fd086ac-9479-4dcd-8c7b-e775feee870d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25596
01332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.2559601332
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.661637649
Short name T568
Test name
Test status
Simulation time 12259771613 ps
CPU time 1195.64 seconds
Started Aug 10 04:40:23 PM PDT 24
Finished Aug 10 05:00:19 PM PDT 24
Peak memory 286584 kb
Host smart-a1ad42a5-c81d-48ca-96e2-dfdd259c0eb4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=661637649 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_han
dler_stress_all.661637649
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.228598611
Short name T32
Test name
Test status
Simulation time 39190988153 ps
CPU time 2811.91 seconds
Started Aug 10 04:40:22 PM PDT 24
Finished Aug 10 05:27:14 PM PDT 24
Peak memory 288820 kb
Host smart-5be2ce2a-a9be-48a9-9887-bff1c3505bf1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=228598611 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.228598611
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.2390742162
Short name T520
Test name
Test status
Simulation time 17987864925 ps
CPU time 274.37 seconds
Started Aug 10 04:40:21 PM PDT 24
Finished Aug 10 04:44:56 PM PDT 24
Peak memory 256316 kb
Host smart-aad69573-dcc3-4ce6-b733-e451983302d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23907
42162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.2390742162
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.1114212338
Short name T22
Test name
Test status
Simulation time 1408268918 ps
CPU time 24.77 seconds
Started Aug 10 04:40:25 PM PDT 24
Finished Aug 10 04:40:50 PM PDT 24
Peak memory 247948 kb
Host smart-cdc83026-0ea6-4ba3-a554-2dede4d25cad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11142
12338 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.1114212338
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.2016685337
Short name T336
Test name
Test status
Simulation time 212218049673 ps
CPU time 2727.87 seconds
Started Aug 10 04:40:26 PM PDT 24
Finished Aug 10 05:25:54 PM PDT 24
Peak memory 285504 kb
Host smart-d66831a4-33b3-4021-8c2f-3d3cb7aff48e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2016685337 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.2016685337
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.2677484505
Short name T273
Test name
Test status
Simulation time 7284429481 ps
CPU time 718.54 seconds
Started Aug 10 04:40:23 PM PDT 24
Finished Aug 10 04:52:21 PM PDT 24
Peak memory 264656 kb
Host smart-251cf776-5f81-4c72-b20a-a90a59d8cbf0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2677484505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.2677484505
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.4139276244
Short name T16
Test name
Test status
Simulation time 3826237718 ps
CPU time 159.93 seconds
Started Aug 10 04:40:21 PM PDT 24
Finished Aug 10 04:43:02 PM PDT 24
Peak memory 254492 kb
Host smart-1a154ec1-1072-432a-89f5-f3d086c441d9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139276244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.4139276244
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.345128374
Short name T400
Test name
Test status
Simulation time 464540635 ps
CPU time 26.04 seconds
Started Aug 10 04:40:22 PM PDT 24
Finished Aug 10 04:40:49 PM PDT 24
Peak memory 255696 kb
Host smart-c7a1b083-923c-4988-a188-5f016fe32f76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34512
8374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.345128374
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.4004681502
Short name T578
Test name
Test status
Simulation time 799188888 ps
CPU time 45.91 seconds
Started Aug 10 04:40:23 PM PDT 24
Finished Aug 10 04:41:09 PM PDT 24
Peak memory 255920 kb
Host smart-edb5cc37-ea63-4cc0-8d8f-23869c7c3608
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40046
81502 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.4004681502
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.241694636
Short name T487
Test name
Test status
Simulation time 491387934 ps
CPU time 17.7 seconds
Started Aug 10 04:40:22 PM PDT 24
Finished Aug 10 04:40:39 PM PDT 24
Peak memory 255780 kb
Host smart-6758fe37-85e8-4ea4-9486-f1b1872ad890
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24169
4636 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.241694636
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.3617001520
Short name T490
Test name
Test status
Simulation time 2888244827 ps
CPU time 44.08 seconds
Started Aug 10 04:40:23 PM PDT 24
Finished Aug 10 04:41:08 PM PDT 24
Peak memory 248472 kb
Host smart-83c351a3-bced-4bca-966f-2001e8575315
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36170
01520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.3617001520
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.154886040
Short name T528
Test name
Test status
Simulation time 51443218160 ps
CPU time 1335.22 seconds
Started Aug 10 04:40:26 PM PDT 24
Finished Aug 10 05:02:41 PM PDT 24
Peak memory 288332 kb
Host smart-0b1263df-417c-42f1-80cb-c93968c61762
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=154886040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_han
dler_stress_all.154886040
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.1061124429
Short name T302
Test name
Test status
Simulation time 26519826078 ps
CPU time 1470.89 seconds
Started Aug 10 04:40:30 PM PDT 24
Finished Aug 10 05:05:02 PM PDT 24
Peak memory 272596 kb
Host smart-c679d49b-9f83-4a06-83ce-7831a01fabed
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1061124429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.1061124429
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.1435276851
Short name T583
Test name
Test status
Simulation time 3087658664 ps
CPU time 96.45 seconds
Started Aug 10 04:40:30 PM PDT 24
Finished Aug 10 04:42:06 PM PDT 24
Peak memory 255576 kb
Host smart-9c61728a-f208-43fc-b886-1e1e996b0b9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14352
76851 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.1435276851
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.949169355
Short name T2
Test name
Test status
Simulation time 718513010 ps
CPU time 52.55 seconds
Started Aug 10 04:40:30 PM PDT 24
Finished Aug 10 04:41:22 PM PDT 24
Peak memory 247996 kb
Host smart-1ba4a424-c84f-4ffd-84b1-88a944afb673
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94916
9355 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.949169355
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.2233641658
Short name T572
Test name
Test status
Simulation time 8088608813 ps
CPU time 764.62 seconds
Started Aug 10 04:40:29 PM PDT 24
Finished Aug 10 04:53:14 PM PDT 24
Peak memory 272624 kb
Host smart-c563941b-bcc2-43c6-b565-eae9f2f4e98d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2233641658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.2233641658
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.1935345824
Short name T92
Test name
Test status
Simulation time 38180534319 ps
CPU time 1080.07 seconds
Started Aug 10 04:40:30 PM PDT 24
Finished Aug 10 04:58:31 PM PDT 24
Peak memory 283380 kb
Host smart-ba3897c8-6f8b-427b-9925-2fd859857419
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1935345824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.1935345824
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.1375305319
Short name T544
Test name
Test status
Simulation time 7113694289 ps
CPU time 284.43 seconds
Started Aug 10 04:40:31 PM PDT 24
Finished Aug 10 04:45:16 PM PDT 24
Peak memory 248056 kb
Host smart-e33459cb-2931-42bd-bf7d-33627cf18bef
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1375305319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.1375305319
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.149838909
Short name T685
Test name
Test status
Simulation time 1813098075 ps
CPU time 26.38 seconds
Started Aug 10 04:40:21 PM PDT 24
Finished Aug 10 04:40:47 PM PDT 24
Peak memory 255656 kb
Host smart-a88c8d37-47a3-493e-888d-75a78303915e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14983
8909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.149838909
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.1603380108
Short name T388
Test name
Test status
Simulation time 738361380 ps
CPU time 53.77 seconds
Started Aug 10 04:40:22 PM PDT 24
Finished Aug 10 04:41:16 PM PDT 24
Peak memory 248080 kb
Host smart-5d50c443-f0fc-4f8a-8b90-a97ca179c81f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16033
80108 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.1603380108
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.3242936202
Short name T413
Test name
Test status
Simulation time 2693268382 ps
CPU time 44.19 seconds
Started Aug 10 04:40:31 PM PDT 24
Finished Aug 10 04:41:16 PM PDT 24
Peak memory 255452 kb
Host smart-2b8425bd-1aa2-4166-85d6-cd17786415ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32429
36202 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.3242936202
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.2008549391
Short name T701
Test name
Test status
Simulation time 183839868 ps
CPU time 20.7 seconds
Started Aug 10 04:40:22 PM PDT 24
Finished Aug 10 04:40:43 PM PDT 24
Peak memory 255612 kb
Host smart-bce70459-a758-42f2-bfde-3e93cd5feba9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20085
49391 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.2008549391
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.3092237519
Short name T591
Test name
Test status
Simulation time 67877129817 ps
CPU time 3870 seconds
Started Aug 10 04:40:31 PM PDT 24
Finished Aug 10 05:45:02 PM PDT 24
Peak memory 298368 kb
Host smart-c9cfb225-ef9b-4a8f-bfc7-46218b047cdd
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3092237519 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_ha
ndler_stress_all.3092237519
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.3188492171
Short name T95
Test name
Test status
Simulation time 65544247029 ps
CPU time 2724.1 seconds
Started Aug 10 04:40:31 PM PDT 24
Finished Aug 10 05:25:55 PM PDT 24
Peak memory 288944 kb
Host smart-b84dc15a-3c1f-4b62-97cf-db3308afebd1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3188492171 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.3188492171
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.2681245419
Short name T653
Test name
Test status
Simulation time 16480917383 ps
CPU time 253.54 seconds
Started Aug 10 04:40:32 PM PDT 24
Finished Aug 10 04:44:46 PM PDT 24
Peak memory 256440 kb
Host smart-2519cdbc-c267-488d-b273-da79660dd4f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26812
45419 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.2681245419
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.741790122
Short name T650
Test name
Test status
Simulation time 457977374 ps
CPU time 20.6 seconds
Started Aug 10 04:40:32 PM PDT 24
Finished Aug 10 04:40:53 PM PDT 24
Peak memory 247876 kb
Host smart-c3fd028d-2163-44c8-a039-6ded7a519ded
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=74179
0122 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.741790122
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.3544455127
Short name T364
Test name
Test status
Simulation time 61815775734 ps
CPU time 1733.44 seconds
Started Aug 10 04:40:31 PM PDT 24
Finished Aug 10 05:09:24 PM PDT 24
Peak memory 272580 kb
Host smart-86a945fa-4387-4d30-9c68-6402d0434a01
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544455127 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.3544455127
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.3083854078
Short name T314
Test name
Test status
Simulation time 22783142819 ps
CPU time 141.99 seconds
Started Aug 10 04:40:31 PM PDT 24
Finished Aug 10 04:42:53 PM PDT 24
Peak memory 248284 kb
Host smart-d666a1f0-bf54-4faa-b01e-fb197fd2f1a1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3083854078 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.3083854078
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.1747014532
Short name T536
Test name
Test status
Simulation time 402359011 ps
CPU time 24.25 seconds
Started Aug 10 04:40:30 PM PDT 24
Finished Aug 10 04:40:54 PM PDT 24
Peak memory 255360 kb
Host smart-9bcde600-9b28-40e7-8900-4805a4df6e96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17470
14532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.1747014532
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.1314617503
Short name T396
Test name
Test status
Simulation time 635522589 ps
CPU time 33.44 seconds
Started Aug 10 04:40:31 PM PDT 24
Finished Aug 10 04:41:05 PM PDT 24
Peak memory 255948 kb
Host smart-0af99dbb-7a7b-4f26-943f-1dddcf9d262b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13146
17503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.1314617503
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.2976371553
Short name T677
Test name
Test status
Simulation time 281677723 ps
CPU time 32.87 seconds
Started Aug 10 04:40:32 PM PDT 24
Finished Aug 10 04:41:06 PM PDT 24
Peak memory 247720 kb
Host smart-57a1a799-5dcd-4282-b7cf-0447e6c23c0f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29763
71553 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.2976371553
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.115841209
Short name T373
Test name
Test status
Simulation time 2324107898 ps
CPU time 41.69 seconds
Started Aug 10 04:40:31 PM PDT 24
Finished Aug 10 04:41:13 PM PDT 24
Peak memory 248720 kb
Host smart-81547661-8af5-437a-8b17-7df45f9ba6c0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11584
1209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.115841209
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.1873462705
Short name T704
Test name
Test status
Simulation time 3353610159 ps
CPU time 54.47 seconds
Started Aug 10 04:40:32 PM PDT 24
Finished Aug 10 04:41:27 PM PDT 24
Peak memory 248356 kb
Host smart-1be4d43c-8747-4a3c-82be-85c3a925b222
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873462705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_ha
ndler_stress_all.1873462705
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.2376503608
Short name T369
Test name
Test status
Simulation time 145951108 ps
CPU time 10.85 seconds
Started Aug 10 04:40:38 PM PDT 24
Finished Aug 10 04:40:49 PM PDT 24
Peak memory 253440 kb
Host smart-1bcacaa8-ecb6-406a-974b-1ffa36a03325
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23765
03608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.2376503608
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.1257856792
Short name T660
Test name
Test status
Simulation time 808190523 ps
CPU time 44.79 seconds
Started Aug 10 04:40:32 PM PDT 24
Finished Aug 10 04:41:17 PM PDT 24
Peak memory 255580 kb
Host smart-0dc4591a-42cb-464d-881e-49a1a896412a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12578
56792 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.1257856792
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.2764427352
Short name T13
Test name
Test status
Simulation time 10612458806 ps
CPU time 904.31 seconds
Started Aug 10 04:40:38 PM PDT 24
Finished Aug 10 04:55:43 PM PDT 24
Peak memory 272824 kb
Host smart-a098a2f1-e02a-4e31-b009-d379d9f7f114
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2764427352 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.2764427352
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.752572827
Short name T619
Test name
Test status
Simulation time 9307620004 ps
CPU time 1084 seconds
Started Aug 10 04:40:42 PM PDT 24
Finished Aug 10 04:58:47 PM PDT 24
Peak memory 288952 kb
Host smart-99565751-bcfc-446f-9536-4533d9de182f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752572827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.752572827
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.912328080
Short name T498
Test name
Test status
Simulation time 7371637717 ps
CPU time 324.74 seconds
Started Aug 10 04:40:43 PM PDT 24
Finished Aug 10 04:46:08 PM PDT 24
Peak memory 248256 kb
Host smart-4ea1ec8b-1a66-4aca-bc62-3e5e2ea91707
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=912328080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.912328080
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.4201021504
Short name T437
Test name
Test status
Simulation time 906585802 ps
CPU time 16.85 seconds
Started Aug 10 04:40:32 PM PDT 24
Finished Aug 10 04:40:49 PM PDT 24
Peak memory 254716 kb
Host smart-c4f493db-c628-4f31-8ea3-e476b331cc98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42010
21504 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.4201021504
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.791554080
Short name T402
Test name
Test status
Simulation time 664820545 ps
CPU time 16.79 seconds
Started Aug 10 04:40:32 PM PDT 24
Finished Aug 10 04:40:49 PM PDT 24
Peak memory 247732 kb
Host smart-9fba1d75-2cf0-409d-a1b7-ecf494896740
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=79155
4080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.791554080
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.3117186002
Short name T228
Test name
Test status
Simulation time 72559006 ps
CPU time 9.64 seconds
Started Aug 10 04:40:41 PM PDT 24
Finished Aug 10 04:40:51 PM PDT 24
Peak memory 255320 kb
Host smart-632bb961-cd40-4aa6-b0f7-d080646a26f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31171
86002 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.3117186002
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.3755586574
Short name T554
Test name
Test status
Simulation time 1071466659 ps
CPU time 25.8 seconds
Started Aug 10 04:40:30 PM PDT 24
Finished Aug 10 04:40:56 PM PDT 24
Peak memory 255304 kb
Host smart-62f0a628-443d-466e-a154-c35559991279
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37555
86574 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.3755586574
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.2632227764
Short name T67
Test name
Test status
Simulation time 15581301780 ps
CPU time 1455.15 seconds
Started Aug 10 04:40:44 PM PDT 24
Finished Aug 10 05:04:59 PM PDT 24
Peak memory 288480 kb
Host smart-8375a275-623f-4f7f-8692-2704bd467c8d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632227764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_ha
ndler_stress_all.2632227764
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.3216001347
Short name T217
Test name
Test status
Simulation time 529011865 ps
CPU time 3.33 seconds
Started Aug 10 04:39:03 PM PDT 24
Finished Aug 10 04:39:06 PM PDT 24
Peak memory 253304 kb
Host smart-f85861c4-9650-43df-8310-2bfc39edf721
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3216001347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.3216001347
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.4232359385
Short name T457
Test name
Test status
Simulation time 60194398162 ps
CPU time 1206.4 seconds
Started Aug 10 04:39:15 PM PDT 24
Finished Aug 10 04:59:22 PM PDT 24
Peak memory 288124 kb
Host smart-2fd3c724-ba7a-4d2d-af65-afb514ee4391
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4232359385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.4232359385
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.1779281159
Short name T249
Test name
Test status
Simulation time 856423000 ps
CPU time 37.59 seconds
Started Aug 10 04:39:16 PM PDT 24
Finished Aug 10 04:39:53 PM PDT 24
Peak memory 248284 kb
Host smart-37cd3daf-ba84-445f-97e6-1d91a4fd60b2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1779281159 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.1779281159
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.3676190101
Short name T494
Test name
Test status
Simulation time 15148581358 ps
CPU time 137.32 seconds
Started Aug 10 04:39:06 PM PDT 24
Finished Aug 10 04:41:23 PM PDT 24
Peak memory 255968 kb
Host smart-fc52d479-292e-4443-b7d3-268f76909b3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36761
90101 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.3676190101
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.4135727164
Short name T470
Test name
Test status
Simulation time 416369297 ps
CPU time 23.53 seconds
Started Aug 10 04:38:46 PM PDT 24
Finished Aug 10 04:39:10 PM PDT 24
Peak memory 247964 kb
Host smart-10c20247-b4f5-436d-a94b-c744a2654644
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41357
27164 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.4135727164
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.3149128887
Short name T347
Test name
Test status
Simulation time 61672908802 ps
CPU time 1869.08 seconds
Started Aug 10 04:39:04 PM PDT 24
Finished Aug 10 05:10:14 PM PDT 24
Peak memory 272144 kb
Host smart-3eb342f0-7792-4f64-8b2a-d2040fa4e4a4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149128887 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.3149128887
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.826834569
Short name T28
Test name
Test status
Simulation time 84390799449 ps
CPU time 2382.94 seconds
Started Aug 10 04:39:09 PM PDT 24
Finished Aug 10 05:18:52 PM PDT 24
Peak memory 288612 kb
Host smart-d0f77d8e-5775-4455-8c3f-19917de0f228
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=826834569 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.826834569
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.816416757
Short name T234
Test name
Test status
Simulation time 33659554151 ps
CPU time 368.31 seconds
Started Aug 10 04:38:52 PM PDT 24
Finished Aug 10 04:45:01 PM PDT 24
Peak memory 248240 kb
Host smart-7323768d-3442-4296-b7c1-b2bfb70b92d9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=816416757 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.816416757
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.532201450
Short name T541
Test name
Test status
Simulation time 1762293993 ps
CPU time 37.51 seconds
Started Aug 10 04:38:46 PM PDT 24
Finished Aug 10 04:39:24 PM PDT 24
Peak memory 248228 kb
Host smart-45fc0157-34bb-4069-b4aa-961d1099f225
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53220
1450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.532201450
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.879662663
Short name T461
Test name
Test status
Simulation time 1184008996 ps
CPU time 34.71 seconds
Started Aug 10 04:38:57 PM PDT 24
Finished Aug 10 04:39:32 PM PDT 24
Peak memory 247892 kb
Host smart-29858119-337f-43cd-a224-7d9b1e06b9a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87966
2663 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.879662663
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.1838442970
Short name T125
Test name
Test status
Simulation time 278812938 ps
CPU time 29.8 seconds
Started Aug 10 04:38:48 PM PDT 24
Finished Aug 10 04:39:18 PM PDT 24
Peak memory 248196 kb
Host smart-228a1fb0-9e6f-456c-a9c3-e15879b8b913
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18384
42970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.1838442970
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.62813684
Short name T548
Test name
Test status
Simulation time 1675727459 ps
CPU time 46.91 seconds
Started Aug 10 04:38:52 PM PDT 24
Finished Aug 10 04:39:39 PM PDT 24
Peak memory 248140 kb
Host smart-97d58e79-8d92-4b18-98aa-424637d9acd7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62813
684 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.62813684
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.2623820762
Short name T278
Test name
Test status
Simulation time 15751394643 ps
CPU time 338.24 seconds
Started Aug 10 04:39:02 PM PDT 24
Finished Aug 10 04:44:41 PM PDT 24
Peak memory 256400 kb
Host smart-6d6b9c76-26a9-431e-a89c-d5c0d72b14ec
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2623820762 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_han
dler_stress_all.2623820762
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.1731125239
Short name T216
Test name
Test status
Simulation time 113463256 ps
CPU time 3.55 seconds
Started Aug 10 04:39:08 PM PDT 24
Finished Aug 10 04:39:11 PM PDT 24
Peak memory 248528 kb
Host smart-2e802681-4c89-4d22-b7a8-b1be947880b1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1731125239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.1731125239
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.1635686429
Short name T55
Test name
Test status
Simulation time 77410270604 ps
CPU time 1683.25 seconds
Started Aug 10 04:39:04 PM PDT 24
Finished Aug 10 05:07:08 PM PDT 24
Peak memory 281036 kb
Host smart-b0eeb071-4bc8-408b-88ec-8ec1e28dea09
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1635686429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.1635686429
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.2792320111
Short name T452
Test name
Test status
Simulation time 1126639384 ps
CPU time 16.11 seconds
Started Aug 10 04:39:17 PM PDT 24
Finished Aug 10 04:39:33 PM PDT 24
Peak memory 248184 kb
Host smart-93823eef-2276-44fc-a754-817c82517587
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2792320111 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.2792320111
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.4002637842
Short name T569
Test name
Test status
Simulation time 2231764143 ps
CPU time 46.08 seconds
Started Aug 10 04:38:58 PM PDT 24
Finished Aug 10 04:39:44 PM PDT 24
Peak memory 249188 kb
Host smart-e760c2a2-cb94-4c01-910b-ec5c8519f156
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40026
37842 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.4002637842
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.3970516157
Short name T643
Test name
Test status
Simulation time 196311438 ps
CPU time 9.16 seconds
Started Aug 10 04:39:03 PM PDT 24
Finished Aug 10 04:39:12 PM PDT 24
Peak memory 248160 kb
Host smart-02132091-fe33-44cd-a10c-2f938f6fc8ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39705
16157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.3970516157
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.480562911
Short name T252
Test name
Test status
Simulation time 68626001741 ps
CPU time 2162.73 seconds
Started Aug 10 04:39:01 PM PDT 24
Finished Aug 10 05:15:04 PM PDT 24
Peak memory 288704 kb
Host smart-a79212cd-619a-4bce-be98-4476b019a23a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480562911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.480562911
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.1433030637
Short name T415
Test name
Test status
Simulation time 105060828995 ps
CPU time 1377.19 seconds
Started Aug 10 04:39:15 PM PDT 24
Finished Aug 10 05:02:13 PM PDT 24
Peak memory 265596 kb
Host smart-41d9619b-4ee9-4013-ad0e-1fa84862e20c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1433030637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.1433030637
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.1829900932
Short name T327
Test name
Test status
Simulation time 20855658463 ps
CPU time 239.53 seconds
Started Aug 10 04:38:59 PM PDT 24
Finished Aug 10 04:42:59 PM PDT 24
Peak memory 248504 kb
Host smart-2bef7818-e677-4f69-baa2-3e0c47e60952
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1829900932 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.1829900932
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.3175266371
Short name T550
Test name
Test status
Simulation time 124491319 ps
CPU time 7.75 seconds
Started Aug 10 04:38:59 PM PDT 24
Finished Aug 10 04:39:07 PM PDT 24
Peak memory 248156 kb
Host smart-dbc6517e-128f-4bd8-8c1c-a0e4d64fe4a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31752
66371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.3175266371
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.848021519
Short name T545
Test name
Test status
Simulation time 699037274 ps
CPU time 28.63 seconds
Started Aug 10 04:38:58 PM PDT 24
Finished Aug 10 04:39:26 PM PDT 24
Peak memory 256348 kb
Host smart-636223d4-f9ea-4110-8cb4-747e394cd843
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84802
1519 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.848021519
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.4260751324
Short name T384
Test name
Test status
Simulation time 1172793428 ps
CPU time 21.05 seconds
Started Aug 10 04:39:14 PM PDT 24
Finished Aug 10 04:39:35 PM PDT 24
Peak memory 254888 kb
Host smart-d92c574c-8c2c-40a5-a824-2f12f788c068
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42607
51324 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.4260751324
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.1241817865
Short name T608
Test name
Test status
Simulation time 2109958394 ps
CPU time 23.85 seconds
Started Aug 10 04:39:00 PM PDT 24
Finished Aug 10 04:39:24 PM PDT 24
Peak memory 248376 kb
Host smart-ec79647b-00d4-4d5c-9bc6-610928f2a643
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12418
17865 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.1241817865
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.3950188045
Short name T683
Test name
Test status
Simulation time 2877824873 ps
CPU time 91.51 seconds
Started Aug 10 04:39:12 PM PDT 24
Finished Aug 10 04:40:43 PM PDT 24
Peak memory 256468 kb
Host smart-deac05d8-c5bb-4025-b1ce-32de93d8a1c4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3950188045 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_han
dler_stress_all.3950188045
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all_with_rand_reset.1299555928
Short name T674
Test name
Test status
Simulation time 34321971958 ps
CPU time 3503.78 seconds
Started Aug 10 04:39:10 PM PDT 24
Finished Aug 10 05:37:35 PM PDT 24
Peak memory 337824 kb
Host smart-c0953db6-00e3-4a5c-be83-307ffcbe6c3f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1299555928 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.alert_handler_stress_all_with_rand_reset.1299555928
Directory /workspace/6.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.891999438
Short name T214
Test name
Test status
Simulation time 56134849 ps
CPU time 4.47 seconds
Started Aug 10 04:39:07 PM PDT 24
Finished Aug 10 04:39:12 PM PDT 24
Peak memory 248352 kb
Host smart-004955c5-033e-402e-b1e7-25c06dc2ab89
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=891999438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.891999438
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.1903855291
Short name T277
Test name
Test status
Simulation time 19753400550 ps
CPU time 864.88 seconds
Started Aug 10 04:39:00 PM PDT 24
Finished Aug 10 04:53:25 PM PDT 24
Peak memory 272760 kb
Host smart-3a8ad7dd-a81a-4861-b778-3a98ded3ef29
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1903855291 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.1903855291
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.141766945
Short name T546
Test name
Test status
Simulation time 1700233581 ps
CPU time 20.3 seconds
Started Aug 10 04:39:17 PM PDT 24
Finished Aug 10 04:39:38 PM PDT 24
Peak memory 248116 kb
Host smart-28e1a3b4-80fc-44ba-95c7-e74a8f8b9132
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=141766945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.141766945
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.3979335177
Short name T610
Test name
Test status
Simulation time 2197868501 ps
CPU time 117.65 seconds
Started Aug 10 04:39:00 PM PDT 24
Finished Aug 10 04:40:58 PM PDT 24
Peak memory 255932 kb
Host smart-b87fe9fc-89a0-4e15-8193-84a37e15c91a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39793
35177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.3979335177
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.3504279221
Short name T88
Test name
Test status
Simulation time 2608076562 ps
CPU time 42.19 seconds
Started Aug 10 04:39:13 PM PDT 24
Finished Aug 10 04:39:56 PM PDT 24
Peak memory 248328 kb
Host smart-4fa9316f-4a1d-4098-90b5-173e2aae4693
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35042
79221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.3504279221
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.2289907554
Short name T335
Test name
Test status
Simulation time 85806053488 ps
CPU time 2569.18 seconds
Started Aug 10 04:38:56 PM PDT 24
Finished Aug 10 05:21:46 PM PDT 24
Peak memory 281472 kb
Host smart-3c997cb7-e118-492a-93cf-018046919a86
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289907554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.2289907554
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.633429294
Short name T512
Test name
Test status
Simulation time 11367511539 ps
CPU time 1415.23 seconds
Started Aug 10 04:39:07 PM PDT 24
Finished Aug 10 05:02:43 PM PDT 24
Peak memory 288480 kb
Host smart-9ae567f8-4209-45d1-9227-cc2727665e55
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633429294 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.633429294
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.1226981747
Short name T330
Test name
Test status
Simulation time 3493987437 ps
CPU time 131.7 seconds
Started Aug 10 04:39:13 PM PDT 24
Finished Aug 10 04:41:25 PM PDT 24
Peak memory 248208 kb
Host smart-bcb308d2-66be-47a5-a869-fd42853b8a4e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1226981747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.1226981747
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.2913351608
Short name T370
Test name
Test status
Simulation time 1257337065 ps
CPU time 67.29 seconds
Started Aug 10 04:39:12 PM PDT 24
Finished Aug 10 04:40:20 PM PDT 24
Peak memory 248200 kb
Host smart-b0cc66d1-103e-4b71-bf1a-6292e90e096e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29133
51608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.2913351608
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.111433269
Short name T425
Test name
Test status
Simulation time 617299795 ps
CPU time 12.97 seconds
Started Aug 10 04:39:03 PM PDT 24
Finished Aug 10 04:39:17 PM PDT 24
Peak memory 255008 kb
Host smart-5ab5b572-d7d9-4f4b-ae54-02c9d5e657cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11143
3269 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.111433269
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.3044340108
Short name T587
Test name
Test status
Simulation time 421103304 ps
CPU time 9.05 seconds
Started Aug 10 04:39:16 PM PDT 24
Finished Aug 10 04:39:25 PM PDT 24
Peak memory 247660 kb
Host smart-fdc80e35-6bad-4235-bc8e-ecba343cf592
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30443
40108 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.3044340108
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.3660012904
Short name T93
Test name
Test status
Simulation time 2332719448 ps
CPU time 66.8 seconds
Started Aug 10 04:39:06 PM PDT 24
Finished Aug 10 04:40:13 PM PDT 24
Peak memory 255432 kb
Host smart-7525bdc3-56b3-442c-a879-d80019d62daa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36600
12904 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.3660012904
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.1538338773
Short name T597
Test name
Test status
Simulation time 37623242389 ps
CPU time 1579.1 seconds
Started Aug 10 04:38:57 PM PDT 24
Finished Aug 10 05:05:17 PM PDT 24
Peak memory 288888 kb
Host smart-0433f92b-57ce-4c43-9bb5-e02977bdc17b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1538338773 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_han
dler_stress_all.1538338773
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all_with_rand_reset.1796154997
Short name T687
Test name
Test status
Simulation time 62735342868 ps
CPU time 1047.51 seconds
Started Aug 10 04:39:04 PM PDT 24
Finished Aug 10 04:56:32 PM PDT 24
Peak memory 281172 kb
Host smart-5d1d9871-9f42-44c6-ab45-f40d12ce5334
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1796154997 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.alert_handler_stress_all_with_rand_reset.1796154997
Directory /workspace/7.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.3193388853
Short name T203
Test name
Test status
Simulation time 106381781 ps
CPU time 2.8 seconds
Started Aug 10 04:38:57 PM PDT 24
Finished Aug 10 04:39:00 PM PDT 24
Peak memory 248440 kb
Host smart-bdaac13f-f2be-43f4-9bec-8a087c5dbf5c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3193388853 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.3193388853
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.911972626
Short name T663
Test name
Test status
Simulation time 24646003423 ps
CPU time 1534.27 seconds
Started Aug 10 04:39:06 PM PDT 24
Finished Aug 10 05:04:41 PM PDT 24
Peak memory 272832 kb
Host smart-d1001e27-01b8-4df9-aab5-1f89b58a85ef
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=911972626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.911972626
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.1816282738
Short name T644
Test name
Test status
Simulation time 547192800 ps
CPU time 25.33 seconds
Started Aug 10 04:39:03 PM PDT 24
Finished Aug 10 04:39:28 PM PDT 24
Peak memory 248188 kb
Host smart-67b0ee15-6654-4374-8ee8-1de150d812dc
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1816282738 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.1816282738
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.997220503
Short name T266
Test name
Test status
Simulation time 1222509521 ps
CPU time 92.94 seconds
Started Aug 10 04:39:04 PM PDT 24
Finished Aug 10 04:40:37 PM PDT 24
Peak memory 255828 kb
Host smart-d8617fd3-0be5-4fb4-9e37-41b386080b40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99722
0503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.997220503
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.1275536545
Short name T491
Test name
Test status
Simulation time 77372685 ps
CPU time 6.65 seconds
Started Aug 10 04:39:02 PM PDT 24
Finished Aug 10 04:39:14 PM PDT 24
Peak memory 250872 kb
Host smart-ab7d4dfb-877c-4f77-8ba4-6d41a2fd7173
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12755
36545 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.1275536545
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.1097495338
Short name T682
Test name
Test status
Simulation time 33464219422 ps
CPU time 829.81 seconds
Started Aug 10 04:38:57 PM PDT 24
Finished Aug 10 04:52:47 PM PDT 24
Peak memory 272772 kb
Host smart-26545325-f9ea-4755-a452-498bbcaacf12
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097495338 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.1097495338
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.1832190797
Short name T74
Test name
Test status
Simulation time 63951314717 ps
CPU time 583.08 seconds
Started Aug 10 04:39:09 PM PDT 24
Finished Aug 10 04:48:53 PM PDT 24
Peak memory 264640 kb
Host smart-dd21b463-b1cf-4d02-8d5c-63f3243a0447
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1832190797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.1832190797
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.4214378397
Short name T324
Test name
Test status
Simulation time 32624555682 ps
CPU time 313.28 seconds
Started Aug 10 04:39:15 PM PDT 24
Finished Aug 10 04:44:29 PM PDT 24
Peak memory 254884 kb
Host smart-515d114e-b471-43f3-8d37-553e3f367fe4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4214378397 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.4214378397
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.875284414
Short name T408
Test name
Test status
Simulation time 88219142 ps
CPU time 10.68 seconds
Started Aug 10 04:38:58 PM PDT 24
Finished Aug 10 04:39:09 PM PDT 24
Peak memory 248160 kb
Host smart-7cb3f625-9a6c-4e45-978a-3ffa973d6a2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87528
4414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.875284414
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.610614289
Short name T454
Test name
Test status
Simulation time 149008672 ps
CPU time 15.57 seconds
Started Aug 10 04:39:04 PM PDT 24
Finished Aug 10 04:39:20 PM PDT 24
Peak memory 256444 kb
Host smart-ed6a803e-ebb8-4b24-9edd-833aea08091c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61061
4289 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.610614289
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.4249570765
Short name T286
Test name
Test status
Simulation time 2026027514 ps
CPU time 62.94 seconds
Started Aug 10 04:39:09 PM PDT 24
Finished Aug 10 04:40:12 PM PDT 24
Peak memory 248540 kb
Host smart-4b1a0d83-7269-42bc-a610-31755e32d8a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42495
70765 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.4249570765
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.2783789684
Short name T40
Test name
Test status
Simulation time 3435293833 ps
CPU time 51.47 seconds
Started Aug 10 04:39:09 PM PDT 24
Finished Aug 10 04:40:01 PM PDT 24
Peak memory 248588 kb
Host smart-deab057a-3e39-47b7-bd1c-7d5a34d41dc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27837
89684 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.2783789684
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.2798095626
Short name T472
Test name
Test status
Simulation time 96619146267 ps
CPU time 1166.01 seconds
Started Aug 10 04:39:02 PM PDT 24
Finished Aug 10 04:58:29 PM PDT 24
Peak memory 281684 kb
Host smart-8f33d9e9-d177-4163-8342-b1fc5ca38313
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2798095626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_han
dler_stress_all.2798095626
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.2864355532
Short name T184
Test name
Test status
Simulation time 56361686 ps
CPU time 4.72 seconds
Started Aug 10 04:39:00 PM PDT 24
Finished Aug 10 04:39:05 PM PDT 24
Peak memory 248504 kb
Host smart-10c32877-a58e-406c-a165-81a67a150774
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2864355532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.2864355532
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.2325228441
Short name T434
Test name
Test status
Simulation time 158640026173 ps
CPU time 1087.65 seconds
Started Aug 10 04:39:13 PM PDT 24
Finished Aug 10 04:57:21 PM PDT 24
Peak memory 287852 kb
Host smart-f3e17c8a-cc0b-4e3d-80fa-7887f1293f3a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325228441 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.2325228441
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.3220201818
Short name T625
Test name
Test status
Simulation time 4294986577 ps
CPU time 109.6 seconds
Started Aug 10 04:39:08 PM PDT 24
Finished Aug 10 04:41:02 PM PDT 24
Peak memory 256532 kb
Host smart-6fe09b9d-75b9-4a53-a428-a6eb675eb25a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32202
01818 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.3220201818
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.323487640
Short name T475
Test name
Test status
Simulation time 89648182 ps
CPU time 3.8 seconds
Started Aug 10 04:39:14 PM PDT 24
Finished Aug 10 04:39:17 PM PDT 24
Peak memory 239672 kb
Host smart-c010955f-3b95-4854-973e-9fcbc67e039e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32348
7640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.323487640
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.2680526947
Short name T671
Test name
Test status
Simulation time 15199119093 ps
CPU time 1446.75 seconds
Started Aug 10 04:39:05 PM PDT 24
Finished Aug 10 05:03:12 PM PDT 24
Peak memory 287576 kb
Host smart-a77beee0-fecc-4237-973d-e7b77c97e3dd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680526947 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.2680526947
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.1426613722
Short name T378
Test name
Test status
Simulation time 167753441699 ps
CPU time 2595.96 seconds
Started Aug 10 04:38:53 PM PDT 24
Finished Aug 10 05:22:09 PM PDT 24
Peak memory 281036 kb
Host smart-6d5a5e4b-6964-4bd9-8884-70a477418525
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1426613722 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.1426613722
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.3751492474
Short name T221
Test name
Test status
Simulation time 9947147132 ps
CPU time 110.43 seconds
Started Aug 10 04:39:12 PM PDT 24
Finished Aug 10 04:41:02 PM PDT 24
Peak memory 248240 kb
Host smart-e3a21c89-b52d-4a71-9659-e1de334331fe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3751492474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.3751492474
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.3209545773
Short name T77
Test name
Test status
Simulation time 3617491631 ps
CPU time 49.77 seconds
Started Aug 10 04:38:59 PM PDT 24
Finished Aug 10 04:39:49 PM PDT 24
Peak memory 255768 kb
Host smart-e11c5cf2-4fd0-4e21-b857-d9667336bd48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32095
45773 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.3209545773
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.4208099001
Short name T274
Test name
Test status
Simulation time 213732145 ps
CPU time 13.28 seconds
Started Aug 10 04:39:19 PM PDT 24
Finished Aug 10 04:39:32 PM PDT 24
Peak memory 252612 kb
Host smart-abf33607-7f01-415f-b6b2-693cbacf2aa5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42080
99001 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.4208099001
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.4024787266
Short name T562
Test name
Test status
Simulation time 1186992819 ps
CPU time 20.52 seconds
Started Aug 10 04:39:08 PM PDT 24
Finished Aug 10 04:39:29 PM PDT 24
Peak memory 255420 kb
Host smart-45b692fa-24ca-4bf5-aa41-afc9821b3a15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40247
87266 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.4024787266
Directory /workspace/9.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.594285061
Short name T379
Test name
Test status
Simulation time 1430401178 ps
CPU time 21.26 seconds
Started Aug 10 04:39:26 PM PDT 24
Finished Aug 10 04:39:47 PM PDT 24
Peak memory 255120 kb
Host smart-502fa3f4-e6af-4d81-843a-0e4a0ca0917d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=594285061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_hand
ler_stress_all.594285061
Directory /workspace/9.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all_with_rand_reset.2100760059
Short name T115
Test name
Test status
Simulation time 1035711915907 ps
CPU time 7939.02 seconds
Started Aug 10 04:39:14 PM PDT 24
Finished Aug 10 06:51:34 PM PDT 24
Peak memory 338560 kb
Host smart-4ae76351-69fc-4192-a92e-c9ecb6557be9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2100760059 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.alert_handler_stress_all_with_rand_reset.2100760059
Directory /workspace/9.alert_handler_stress_all_with_rand_reset/latest
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