Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	81761	1			T4	202		T16	2531		T5	3887
class_i[0x1]	41673	1			T4	2369		T5	1		T20	6
class_i[0x2]	69377	1			T5	19		T25	403		T6	502
class_i[0x3]	64690	1			T4	5240		T5	10		T20	3280

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	63066	1			T4	1914		T16	694		T5	994
alert[0x1]	66995	1			T4	1908		T16	642		T5	967
alert[0x2]	64556	1			T4	2011		T16	616		T5	927
alert[0x3]	62884	1			T4	1978		T16	579		T5	1029

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

257246

1

T4

7811

T16

2531

T5

3917

esc_ping_fail

255

1

T13

2

T14

8

T15

6

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	62991	1			T4	1914		T16	694		T5	994
esc_integrity_fail	alert[0x1]	66935	1			T4	1908		T16	642		T5	967
esc_integrity_fail	alert[0x2]	64493	1			T4	2011		T16	616		T5	927
esc_integrity_fail	alert[0x3]	62827	1			T4	1978		T16	579		T5	1029
esc_ping_fail	alert[0x0]	75	1			T13	2		T14	2		T15	1
esc_ping_fail	alert[0x1]	60	1			T14	2		T15	2		T317	1
esc_ping_fail	alert[0x2]	63	1			T14	1		T15	2		T317	1
esc_ping_fail	alert[0x3]	57	1			T14	3		T15	1		T317	2

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	81693	1			T4	202		T16	2531		T5	3887
esc_integrity_fail	class_i[0x1]	41628	1			T4	2369		T5	1		T20	6
esc_integrity_fail	class_i[0x2]	69281	1			T5	19		T25	403		T6	502
esc_integrity_fail	class_i[0x3]	64644	1			T4	5240		T5	10		T20	3280
esc_ping_fail	class_i[0x0]	68	1			T317	5		T327	6		T329	1
esc_ping_fail	class_i[0x1]	45	1			T13	1		T14	1		T321	1
esc_ping_fail	class_i[0x2]	96	1			T14	7		T15	5		T321	4
esc_ping_fail	class_i[0x3]	46	1			T13	1		T15	1		T321	1