Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	705589305	0	0	631
tb.dut.u_edn_req.u_prim_packer_fifo.ValidOPairedWithReadyI_A	0	0	705589305	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AckPKnownO_A	0	0	705589305	705430251	0	0
tb.dut.CheckAccuCntDw	0	0	631	631	0	0
tb.dut.CheckEscCntDw	0	0	631	631	0	0
tb.dut.CheckNAlerts	0	0	631	631	0	0
tb.dut.CheckNClasses	0	0	631	631	0	0
tb.dut.CheckNEscSev	0	0	631	631	0	0
tb.dut.CrashdumpKnownO_A	0	0	705589305	705430251	0	0
tb.dut.EdnKnownO_A	0	0	705589305	705430251	0	0
tb.dut.EscPKnownO_A	0	0	705589305	705430251	0	0
tb.dut.FpvSecCmPingTimerCnterCheck_A	0	0	705589305	70	0	0
tb.dut.FpvSecCmPingTimerDoubleLfsrCheck_A	0	0	705589305	70	0	0
tb.dut.FpvSecCmPingTimerEscCnterCheck_A	0	0	705589305	70	0	0
tb.dut.FpvSecCmPingTimerFsmCheck_A	0	0	705589305	70	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	705589305	70	0	0
tb.dut.IrqAKnownO_A	0	0	705589305	705430251	0	0
tb.dut.IrqBKnownO_A	0	0	705589305	705430251	0	0
tb.dut.IrqCKnownO_A	0	0	705589305	705430251	0	0
tb.dut.IrqDKnownO_A	0	0	705589305	705430251	0	0
tb.dut.TlAReadyKnownO_A	0	0	705589305	705430251	0	0
tb.dut.TlDValidKnownO_A	0	0	705589305	705430251	0	0
tb.dut.alert_handler_csr_assert.TlulOOBAddrErr_A	0	0	730933303	3678068	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_0_rd_A	0	0	730933303	16386	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_10_rd_A	0	0	730933303	14565	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_11_rd_A	0	0	730933303	16361	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_12_rd_A	0	0	730933303	17978	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_13_rd_A	0	0	730933303	14348	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_14_rd_A	0	0	730933303	15562	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_15_rd_A	0	0	730933303	16801	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_16_rd_A	0	0	730933303	15703	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_17_rd_A	0	0	730933303	15227	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_18_rd_A	0	0	730933303	14556	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_19_rd_A	0	0	730933303	16644	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_1_rd_A	0	0	730933303	15425	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_20_rd_A	0	0	730933303	14440	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_21_rd_A	0	0	730933303	16682	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_22_rd_A	0	0	730933303	14716	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_23_rd_A	0	0	730933303	15636	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_24_rd_A	0	0	730933303	18087	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_25_rd_A	0	0	730933303	14216	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_26_rd_A	0	0	730933303	15537	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_27_rd_A	0	0	730933303	16512	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_28_rd_A	0	0	730933303	16865	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_29_rd_A	0	0	730933303	14119	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_2_rd_A	0	0	730933303	15755	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_30_rd_A	0	0	730933303	16283	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_31_rd_A	0	0	730933303	16302	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_32_rd_A	0	0	730933303	15458	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_33_rd_A	0	0	730933303	15520	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_34_rd_A	0	0	730933303	15703	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_35_rd_A	0	0	730933303	15987	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_36_rd_A	0	0	730933303	15658	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_37_rd_A	0	0	730933303	17104	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_38_rd_A	0	0	730933303	14384	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_39_rd_A	0	0	730933303	14086	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_3_rd_A	0	0	730933303	16779	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_40_rd_A	0	0	730933303	17728	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_41_rd_A	0	0	730933303	16531	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_42_rd_A	0	0	730933303	13973	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_43_rd_A	0	0	730933303	15557	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_44_rd_A	0	0	730933303	15128	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_45_rd_A	0	0	730933303	15304	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_46_rd_A	0	0	730933303	15687	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_47_rd_A	0	0	730933303	16503	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_48_rd_A	0	0	730933303	15841	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_49_rd_A	0	0	730933303	16839	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_4_rd_A	0	0	730933303	17851	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_50_rd_A	0	0	730933303	14155	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_51_rd_A	0	0	730933303	15378	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_52_rd_A	0	0	730933303	14582	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_53_rd_A	0	0	730933303	15380	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_54_rd_A	0	0	730933303	17392	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_55_rd_A	0	0	730933303	15574	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_56_rd_A	0	0	730933303	14566	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_57_rd_A	0	0	730933303	16594	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_58_rd_A	0	0	730933303	15459	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_59_rd_A	0	0	730933303	16557	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_5_rd_A	0	0	730933303	16671	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_60_rd_A	0	0	730933303	15834	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_61_rd_A	0	0	730933303	14510	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_62_rd_A	0	0	730933303	16830	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_63_rd_A	0	0	730933303	15426	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_64_rd_A	0	0	730933303	15434	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_6_rd_A	0	0	730933303	16652	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_7_rd_A	0	0	730933303	15581	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_8_rd_A	0	0	730933303	16179	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_9_rd_A	0	0	730933303	15508	0	0
tb.dut.alert_handler_csr_assert.classa_regwen_rd_A	0	0	730933303	15720	0	0
tb.dut.alert_handler_csr_assert.classb_regwen_rd_A	0	0	730933303	14543	0	0
tb.dut.alert_handler_csr_assert.classc_regwen_rd_A	0	0	730933303	15448	0	0
tb.dut.alert_handler_csr_assert.classd_regwen_rd_A	0	0	730933303	15391	0	0
tb.dut.alert_handler_csr_assert.intr_enable_rd_A	0	0	730933303	27347	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_0_rd_A	0	0	730933303	16638	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_1_rd_A	0	0	730933303	14412	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_2_rd_A	0	0	730933303	15479	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_3_rd_A	0	0	730933303	14297	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_4_rd_A	0	0	730933303	14629	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_5_rd_A	0	0	730933303	14413	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_6_rd_A	0	0	730933303	15447	0	0
tb.dut.alert_handler_csr_assert.ping_timer_regwen_rd_A	0	0	730933303	17919	0	0
tb.dut.gen_classes[0].FpvSecCmAccuCnterCheck_A	0	0	705589305	70	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerCnterCheck_A	0	0	705589305	70	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerFsmCheck_A	0	0	705589305	70	0	0
tb.dut.gen_classes[0].u_accu.CountSaturateStable_A	0	0	705589305	5643	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigBkwd_A	0	0	705589305	204964	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigFwd_A	0	0	705589305	353444186	0	0
tb.dut.gen_classes[0].u_esc_timer.AccuFailToFsmError_A	0	0	705589305	187	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig0_A	0	0	705589305	867	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig1_A	0	0	705589305	53	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckClr_A	0	0	705589305	429	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckEn_A	0	0	705349533	256665916	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase0_A	0	0	705589305	963	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase1_A	0	0	705589305	942	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase2_A	0	0	705589305	922	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase3_A	0	0	705589305	905	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeout0_A	0	0	705589305	1034	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt1_A	0	0	705589305	109828	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt2_A	0	0	705589305	915	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutStTrig_A	0	0	705589305	64	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStAllEscAsserted_A	0	0	705589305	1148	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStIsTerminal_A	0	0	705589305	938	0	0
tb.dut.gen_classes[0].u_esc_timer.EscStateOut_A	0	0	705347966	705278712	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs.AssertConnected_A	0	0	631	631	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs_A	0	0	705589305	705430251	0	0
tb.dut.gen_classes[1].FpvSecCmAccuCnterCheck_A	0	0	705589305	70	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerCnterCheck_A	0	0	705589305	70	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerFsmCheck_A	0	0	705589305	70	0	0
tb.dut.gen_classes[1].u_accu.CountSaturateStable_A	0	0	705589305	3522	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigBkwd_A	0	0	705589305	193392	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigFwd_A	0	0	705589305	409362187	0	0
tb.dut.gen_classes[1].u_esc_timer.AccuFailToFsmError_A	0	0	705589305	207	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig0_A	0	0	705589305	570	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig1_A	0	0	705589305	26	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckClr_A	0	0	705589305	284	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckEn_A	0	0	705349533	320159566	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase0_A	0	0	705589305	646	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase1_A	0	0	705589305	638	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase2_A	0	0	705589305	625	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase3_A	0	0	705589305	616	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeout0_A	0	0	705589305	1473	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt1_A	0	0	705589305	129278	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt2_A	0	0	705589305	1377	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutStTrig_A	0	0	705589305	66	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStAllEscAsserted_A	0	0	705589305	1144	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStIsTerminal_A	0	0	705589305	934	0	0
tb.dut.gen_classes[1].u_esc_timer.EscStateOut_A	0	0	705347966	705278712	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs.AssertConnected_A	0	0	631	631	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs_A	0	0	705589305	705430251	0	0
tb.dut.gen_classes[2].FpvSecCmAccuCnterCheck_A	0	0	705589305	70	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerCnterCheck_A	0	0	705589305	70	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerFsmCheck_A	0	0	705589305	70	0	0
tb.dut.gen_classes[2].u_accu.CountSaturateStable_A	0	0	705589305	4087	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigBkwd_A	0	0	705589305	182119	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigFwd_A	0	0	705589305	451093985	0	0
tb.dut.gen_classes[2].u_esc_timer.AccuFailToFsmError_A	0	0	705589305	242	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig0_A	0	0	705589305	505	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig1_A	0	0	705589305	26	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckClr_A	0	0	705589305	212	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckEn_A	0	0	705349533	339859225	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase0_A	0	0	705589305	581	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase1_A	0	0	705589305	575	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase2_A	0	0	705589305	562	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase3_A	0	0	705589305	553	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeout0_A	0	0	705589305	822	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt1_A	0	0	705589305	94504	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt2_A	0	0	705589305	738	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutStTrig_A	0	0	705589305	56	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStAllEscAsserted_A	0	0	705589305	1165	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStIsTerminal_A	0	0	705589305	955	0	0
tb.dut.gen_classes[2].u_esc_timer.EscStateOut_A	0	0	705347966	705278712	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs.AssertConnected_A	0	0	631	631	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs_A	0	0	705589305	705430251	0	0
tb.dut.gen_classes[3].FpvSecCmAccuCnterCheck_A	0	0	705589305	70	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerCnterCheck_A	0	0	705589305	70	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerFsmCheck_A	0	0	705589305	70	0	0
tb.dut.gen_classes[3].u_accu.CountSaturateStable_A	0	0	705589305	2049	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigBkwd_A	0	0	705589305	162901	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigFwd_A	0	0	705589305	418899336	0	0
tb.dut.gen_classes[3].u_esc_timer.AccuFailToFsmError_A	0	0	705589305	218	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig0_A	0	0	705589305	509	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig1_A	0	0	705589305	28	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckClr_A	0	0	705589305	232	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckEn_A	0	0	705349533	321623729	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase0_A	0	0	705589305	597	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase1_A	0	0	705589305	575	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase2_A	0	0	705589305	560	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase3_A	0	0	705589305	546	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeout0_A	0	0	705589305	1080	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt1_A	0	0	705589305	103559	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt2_A	0	0	705589305	983	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutStTrig_A	0	0	705589305	66	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStAllEscAsserted_A	0	0	705589305	1101	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStIsTerminal_A	0	0	705589305	891	0	0
tb.dut.gen_classes[3].u_esc_timer.EscStateOut_A	0	0	705347966	705278712	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs.AssertConnected_A	0	0	631	631	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs_A	0	0	705589305	705430251	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	730933303	144628099	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	730933303	730268742	0	0
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