Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.30	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	2	38	95.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	2	38	95.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	64	1			T5	1		T6	1		T64	1
class_index[0x1]	66	1			T5	1		T25	1		T6	1
class_index[0x2]	56	1			T5	1		T19	1		T68	1
class_index[0x3]	66	1			T5	1		T64	1		T68	1

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	107	1			T5	1		T19	1		T6	1
intr_timeout_cnt[1]	54	1			T5	1		T25	1		T64	1
intr_timeout_cnt[2]	17	1			T88	1		T133	2		T23	1
intr_timeout_cnt[3]	13	1			T5	1		T113	1		T104	1
intr_timeout_cnt[4]	14	1			T68	1		T132	1		T52	1
intr_timeout_cnt[5]	13	1			T5	1		T65	1		T103	1
intr_timeout_cnt[6]	14	1			T30	1		T292	1		T133	1
intr_timeout_cnt[7]	10	1			T27	1		T52	1		T103	1
intr_timeout_cnt[8]	4	1			T6	1		T293	1		T257	1
intr_timeout_cnt[9]	6	1			T81	1		T113	1		T294	1

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	2	38	95.00	2

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x0]]	[intr_timeout_cnt[8]]	0	1	1
[class_index[0x2]]	[intr_timeout_cnt[8]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	19	1			T6	1		T29	1		T27	1
class_index[0x0]	intr_timeout_cnt[1]	14	1			T64	1		T27	1		T80	1
class_index[0x0]	intr_timeout_cnt[2]	6	1			T88	1		T23	1		T295	1
class_index[0x0]	intr_timeout_cnt[3]	4	1			T113	1		T104	1		T296	1
class_index[0x0]	intr_timeout_cnt[4]	2	1			T297	1		T298	1		-	-
class_index[0x0]	intr_timeout_cnt[5]	8	1			T5	1		T65	1		T115	1
class_index[0x0]	intr_timeout_cnt[6]	5	1			T133	1		T299	1		T300	1
class_index[0x0]	intr_timeout_cnt[7]	5	1			T103	1		T256	1		T257	3
class_index[0x0]	intr_timeout_cnt[9]	1	1			T294	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[0]	31	1			T5	1		T78	1		T29	1
class_index[0x1]	intr_timeout_cnt[1]	16	1			T25	1		T301	1		T302	1
class_index[0x1]	intr_timeout_cnt[2]	4	1			T133	2		T303	1		T258	1
class_index[0x1]	intr_timeout_cnt[3]	1	1			T304	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[4]	3	1			T305	1		T306	1		T121	1
class_index[0x1]	intr_timeout_cnt[5]	2	1			T293	1		T300	1		-	-
class_index[0x1]	intr_timeout_cnt[6]	3	1			T30	1		T292	1		T307	1
class_index[0x1]	intr_timeout_cnt[7]	1	1			T52	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[8]	3	1			T6	1		T257	1		T308	1
class_index[0x1]	intr_timeout_cnt[9]	2	1			T81	1		T113	1		-	-
class_index[0x2]	intr_timeout_cnt[0]	21	1			T19	1		T68	1		T86	1
class_index[0x2]	intr_timeout_cnt[1]	15	1			T5	1		T83	1		T89	1
class_index[0x2]	intr_timeout_cnt[2]	5	1			T54	1		T309	2		T299	1
class_index[0x2]	intr_timeout_cnt[3]	3	1			T293	1		T310	2		-	-
class_index[0x2]	intr_timeout_cnt[4]	2	1			T104	1		T303	1		-	-
class_index[0x2]	intr_timeout_cnt[5]	1	1			T121	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[6]	5	1			T300	4		T311	1		-	-
class_index[0x2]	intr_timeout_cnt[7]	2	1			T27	1		T58	1		-	-
class_index[0x2]	intr_timeout_cnt[9]	2	1			T256	1		T300	1		-	-
class_index[0x3]	intr_timeout_cnt[0]	36	1			T64	1		T69	1		T91	1
class_index[0x3]	intr_timeout_cnt[1]	9	1			T85	1		T53	1		T289	1
class_index[0x3]	intr_timeout_cnt[2]	2	1			T294	1		T307	1		-	-
class_index[0x3]	intr_timeout_cnt[3]	5	1			T5	1		T312	1		T313	1
class_index[0x3]	intr_timeout_cnt[4]	7	1			T68	1		T132	1		T52	1
class_index[0x3]	intr_timeout_cnt[5]	2	1			T103	1		T314	1		-	-
class_index[0x3]	intr_timeout_cnt[6]	1	1			T300	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[7]	2	1			T116	1		T315	1		-	-
class_index[0x3]	intr_timeout_cnt[8]	1	1			T293	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[9]	1	1			T293	1		-	-		-	-