Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	362875	1			T1	1501		T2	13		T3	1089
all_values[1]	362875	1			T1	1501		T2	13		T3	1089
all_values[2]	362875	1			T1	1501		T2	13		T3	1089
all_values[3]	362875	1			T1	1501		T2	13		T3	1089

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

721965

1

T1

3074

T2

24

T3

2129

auto[1]

729535

1

T1

2930

T2

28

T3

2227

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

863710

1

T1

4924

T2

28

T3

3131

auto[1]

587790

1

T1

1080

T2

24

T3

1225

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	103485	1			T1	443		T2	3		T3	393
all_values[0]	auto[0]	auto[1]	77098	1			T1	369		T2	2		T3	132
all_values[0]	auto[1]	auto[0]	105172	1			T1	381		T2	4		T3	424
all_values[0]	auto[1]	auto[1]	77120	1			T1	308		T2	4		T3	140
all_values[1]	auto[0]	auto[0]	108163	1			T1	746		T2	4		T3	334
all_values[1]	auto[0]	auto[1]	72054	1			T1	4		T2	4		T3	188
all_values[1]	auto[1]	auto[0]	110207	1			T1	750		T2	3		T3	350
all_values[1]	auto[1]	auto[1]	72451	1			T1	1		T2	2		T3	217
all_values[2]	auto[0]	auto[0]	108330	1			T1	573		T2	4		T3	404
all_values[2]	auto[0]	auto[1]	72007	1			T1	204		T2	3		T3	143
all_values[2]	auto[1]	auto[0]	109901	1			T1	538		T2	3		T3	397
all_values[2]	auto[1]	auto[1]	72637	1			T1	186		T2	3		T3	145
all_values[3]	auto[0]	auto[0]	108532	1			T1	732		T2	2		T3	410
all_values[3]	auto[0]	auto[1]	72296	1			T1	3		T2	2		T3	125
all_values[3]	auto[1]	auto[0]	109920	1			T1	761		T2	5		T3	419
all_values[3]	auto[1]	auto[1]	72127	1			T1	5		T2	4		T3	135