Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	362875	1			T1	1501		T2	13		T3	1089
all_pins[1]	362875	1			T1	1501		T2	13		T3	1089
all_pins[2]	362875	1			T1	1501		T2	13		T3	1089
all_pins[3]	362875	1			T1	1501		T2	13		T3	1089

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	1157165	1			T1	5504		T2	39		T3	3719
values[0x1]	294335	1			T1	500		T2	13		T3	637
transitions[0x0=>0x1]	195262	1			T1	498		T2	10		T3	496
transitions[0x1=>0x0]	195511	1			T1	499		T2	11		T3	496

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	285755	1			T1	1193		T2	9		T3	949
all_pins[0]	values[0x1]	77120	1			T1	308		T2	4		T3	140
all_pins[0]	transitions[0x0=>0x1]	76410	1			T1	307		T2	3		T3	140
all_pins[0]	transitions[0x1=>0x0]	71666	1			T1	5		T2	4		T3	135
all_pins[1]	values[0x0]	290424	1			T1	1500		T2	11		T3	872
all_pins[1]	values[0x1]	72451	1			T1	1		T2	2		T3	217
all_pins[1]	transitions[0x0=>0x1]	38957	1			T1	1		T2	1		T3	162
all_pins[1]	transitions[0x1=>0x0]	43626	1			T1	308		T2	3		T3	85
all_pins[2]	values[0x0]	290238	1			T1	1315		T2	10		T3	944
all_pins[2]	values[0x1]	72637	1			T1	186		T2	3		T3	145
all_pins[2]	transitions[0x0=>0x1]	40082	1			T1	186		T2	3		T3	95
all_pins[2]	transitions[0x1=>0x0]	39896	1			T1	1		T2	2		T3	167
all_pins[3]	values[0x0]	290748	1			T1	1496		T2	9		T3	954
all_pins[3]	values[0x1]	72127	1			T1	5		T2	4		T3	135
all_pins[3]	transitions[0x0=>0x1]	39813	1			T1	4		T2	3		T3	99
all_pins[3]	transitions[0x1=>0x0]	40323	1			T1	185		T2	2		T3	109