Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	290	1			T173	4		T174	4		T175	7
all_values[1]	290	1			T173	4		T174	4		T175	7
all_values[2]	290	1			T173	4		T174	4		T175	7
all_values[3]	290	1			T173	4		T174	4		T175	7

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

636

1

T173

11

T174

10

T175

14

auto[1]

524

1

T173

5

T174

6

T175

14

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

460

1

T173

9

T174

2

T175

15

auto[1]

700

1

T173

7

T174

14

T175

13

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

689

1

T173

12

T174

9

T175

17

auto[1]

471

1

T173

4

T174

7

T175

11

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	24	0	24	100.00
Automatically Generated Cross Bins	24	0	24	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

78

1

T173

1

T174

1

T175

3

all_values[0]

auto[0]

auto[0]

auto[1]

27

1

T174

1

T355

1

T356

2

all_values[0]

auto[0]

auto[1]

auto[0]

57

1

T175

2

T357

4

T356

1

all_values[0]

auto[0]

auto[1]

auto[1]

23

1

T173

2

T175

1

T357

1

all_values[0]

auto[1]

auto[0]

auto[1]

58

1

T175

1

T355

1

T356

2

all_values[0]

auto[1]

auto[1]

auto[1]

47

1

T173

1

T174

2

T357

1

all_values[1]

auto[0]

auto[0]

auto[0]

70

1

T173

4

T175

3

T356

1

all_values[1]

auto[0]

auto[0]

auto[1]

28

1

T174

1

T175

1

T357

1

all_values[1]

auto[0]

auto[1]

auto[0]

38

1

T357

5

T355

1

T358

2

all_values[1]

auto[0]

auto[1]

auto[1]

29

1

T174

1

T355

2

T359

1

all_values[1]

auto[1]

auto[0]

auto[1]

76

1

T174

1

T175

3

T357

1

all_values[1]

auto[1]

auto[1]

auto[1]

49

1

T174

1

T355

1

T356

1

all_values[2]

auto[0]

auto[0]

auto[0]

65

1

T173

2

T174

1

T175

1

all_values[2]

auto[0]

auto[0]

auto[1]

25

1

T174

1

T355

1

T358

1

all_values[2]

auto[0]

auto[1]

auto[0]

51

1

T173

1

T175

3

T357

1

all_values[2]

auto[0]

auto[1]

auto[1]

36

1

T174

1

T357

1

T358

1

all_values[2]

auto[1]

auto[0]

auto[1]

64

1

T357

1

T355

3

T356

2

all_values[2]

auto[1]

auto[1]

auto[1]

49

1

T173

1

T174

1

T175

3

all_values[3]

auto[0]

auto[0]

auto[0]

46

1

T173

1

T175

1

T356

3

all_values[3]

auto[0]

auto[0]

auto[1]

31

1

T173

1

T174

2

T355

2

all_values[3]

auto[0]

auto[1]

auto[0]

55

1

T175

2

T357

3

T356

2

all_values[3]

auto[0]

auto[1]

auto[1]

30

1

T355

2

T360

1

T361

2

all_values[3]

auto[1]

auto[0]

auto[1]

68

1

T173

2

T174

2

T175

1

all_values[3]

auto[1]

auto[1]

auto[1]

60

1

T175

3

T357

4

T355

1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal