Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	87391	1			T7	223		T4	589		T16	226
accum_cnt_1000	226463	1			T1	1821		T3	448		T7	986
accum_cnt_100	27965	1			T1	200		T3	165		T7	55
accum_cnt_50	70642	1			T1	163		T2	6		T3	145
accum_cnt_10	194644	1			T1	47		T2	27		T3	34
accum_cnt_0	431649	1			T1	2249		T2	15		T3	2420

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	268183	1			T1	1120		T2	12		T3	803
class_index[0x1]	268183	1			T1	1120		T2	12		T3	803
class_index[0x2]	268183	1			T1	1120		T2	12		T3	803
class_index[0x3]	268183	1			T1	1120		T2	12		T3	803

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	25913	1			T4	279		T16	226		T5	308
class_index[0x0]	accum_cnt_1000	61947	1			T1	1005		T3	448		T11	11
class_index[0x0]	accum_cnt_100	9098	1			T1	63		T3	165		T11	28
class_index[0x0]	accum_cnt_50	24309	1			T1	38		T3	145		T11	21
class_index[0x0]	accum_cnt_10	46271	1			T1	11		T2	12		T3	34
class_index[0x0]	accum_cnt_0	90927	1			T1	3		T3	11		T7	1323
class_index[0x1]	accum_cnt_2000	21378	1			T7	223		T4	310		T20	96
class_index[0x1]	accum_cnt_1000	57547	1			T7	986		T11	24		T4	657
class_index[0x1]	accum_cnt_100	6228	1			T7	55		T11	20		T4	42
class_index[0x1]	accum_cnt_50	15489	1			T2	4		T7	45		T11	16
class_index[0x1]	accum_cnt_10	43451	1			T2	6		T7	12		T11	6
class_index[0x1]	accum_cnt_0	114468	1			T1	1120		T2	2		T3	803
class_index[0x2]	accum_cnt_2000	20805	1			T19	413		T20	20		T74	680
class_index[0x2]	accum_cnt_1000	51138	1			T1	816		T5	281		T19	443
class_index[0x2]	accum_cnt_100	6419	1			T1	137		T5	67		T19	21
class_index[0x2]	accum_cnt_50	17467	1			T1	125		T4	493		T5	55
class_index[0x2]	accum_cnt_10	57119	1			T1	36		T2	3		T7	1321
class_index[0x2]	accum_cnt_0	107427	1			T1	6		T2	9		T3	803
class_index[0x3]	accum_cnt_2000	19295	1			T19	344		T20	193		T95	489
class_index[0x3]	accum_cnt_1000	55831	1			T4	928		T5	1141		T19	503
class_index[0x3]	accum_cnt_100	6220	1			T4	127		T5	176		T19	25
class_index[0x3]	accum_cnt_50	13377	1			T2	2		T4	116		T5	138
class_index[0x3]	accum_cnt_10	47803	1			T2	6		T7	1319		T11	2
class_index[0x3]	accum_cnt_0	118827	1			T1	1120		T2	4		T3	803