Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	2987	1			T27	21		T251	634		T254	269
alert[0x1]	2580	1			T16	39		T19	28		T20	111
alert[0x2]	6426	1			T4	133		T19	1118		T20	23
alert[0x3]	5882	1			T19	11		T20	503		T29	3
alert[0x4]	2162	1			T4	61		T20	15		T6	3
alert[0x5]	2500	1			T16	151		T25	12		T20	85
alert[0x6]	5240	1			T7	2		T16	1357		T5	1
alert[0x7]	4918	1			T4	14		T5	9		T19	64
alert[0x8]	10277	1			T7	1		T16	77		T25	2
alert[0x9]	4164	1			T4	16		T16	43		T5	2
alert[0xa]	7994	1			T7	1		T4	16		T19	206
alert[0xb]	10950	1			T16	956		T19	109		T6	141
alert[0xc]	3275	1			T4	18		T6	41		T43	1
alert[0xd]	2548	1			T4	11		T16	141		T44	1
alert[0xe]	11116	1			T4	1		T16	55		T19	335
alert[0xf]	1797	1			T16	37		T68	3		T76	1
alert[0x10]	5703	1			T19	752		T20	15		T76	10
alert[0x11]	6957	1			T16	663		T5	5		T29	1
alert[0x12]	3518	1			T44	8		T254	1474		T36	7
alert[0x13]	2277	1			T16	57		T19	2		T43	1
alert[0x14]	8110	1			T3	1		T16	2127		T25	1
alert[0x15]	3367	1			T19	197		T25	2		T29	2
alert[0x16]	3353	1			T1	1		T7	1		T16	201
alert[0x17]	3586	1			T4	708		T5	1		T19	12
alert[0x18]	3381	1			T4	5		T5	35		T6	13
alert[0x19]	3166	1			T5	3		T19	19		T14	2
alert[0x1a]	3698	1			T20	17		T29	14		T27	1
alert[0x1b]	5521	1			T5	6		T19	44		T20	102
alert[0x1c]	5607	1			T1	1		T16	8		T6	70
alert[0x1d]	3682	1			T20	878		T43	39		T68	4
alert[0x1e]	4496	1			T4	7		T5	21		T6	15
alert[0x1f]	17927	1			T1	1		T4	7		T16	23
alert[0x20]	6502	1			T4	14		T16	17		T25	26
alert[0x21]	2133	1			T5	10		T20	139		T44	28
alert[0x22]	2186	1			T16	21		T19	49		T20	19
alert[0x23]	6780	1			T19	8		T25	2		T20	173
alert[0x24]	3556	1			T16	5		T19	78		T13	1
alert[0x25]	5098	1			T16	81		T19	21		T43	2
alert[0x26]	4354	1			T4	32		T16	23		T19	199
alert[0x27]	3554	1			T16	6		T19	69		T20	8
alert[0x28]	2174	1			T19	56		T68	43		T251	30
alert[0x29]	4808	1			T4	48		T16	2151		T19	40
alert[0x2a]	2249	1			T16	206		T19	25		T20	11
alert[0x2b]	2440	1			T16	26		T5	2		T20	25
alert[0x2c]	7036	1			T4	23		T25	1		T29	77
alert[0x2d]	3160	1			T6	4		T29	24		T65	6
alert[0x2e]	2055	1			T4	2		T19	46		T25	2
alert[0x2f]	4047	1			T16	185		T14	1		T251	504
alert[0x30]	4899	1			T4	259		T20	29		T6	7
alert[0x31]	2497	1			T4	2		T16	31		T19	13
alert[0x32]	2105	1			T25	2		T68	10		T27	7
alert[0x33]	13019	1			T5	255		T19	12		T6	9
alert[0x34]	5098	1			T16	698		T19	191		T44	1
alert[0x35]	3814	1			T6	30		T14	1		T44	1
alert[0x36]	6593	1			T20	231		T6	1044		T27	1
alert[0x37]	8382	1			T16	55		T20	4		T6	92
alert[0x38]	4919	1			T14	1		T29	71		T65	3
alert[0x39]	5459	1			T4	5		T19	216		T20	13
alert[0x3a]	4852	1			T20	2		T76	6		T252	1
alert[0x3b]	7384	1			T5	17		T20	223		T43	16
alert[0x3c]	9654	1			T4	67		T5	11		T19	80
alert[0x3d]	2720	1			T16	11		T19	2		T20	289
alert[0x3e]	9077	1			T16	14		T25	4		T76	97
alert[0x3f]	3304	1			T16	11		T19	53		T20	1301
alert[0x40]	1819	1			T16	375		T20	27		T6	676

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	73038	1			T4	1181		T6	571		T13	5
class_i[0x1]	89195	1			T7	5		T5	3		T19	4682
class_i[0x2]	77869	1			T3	1		T5	363		T44	66
class_i[0x3]	86790	1			T1	3		T4	268		T16	9851

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

326224

1

T4

1449

T16

9851

T5

378

alert_ping_fail

668

1

T1

3

T3

1

T7

5

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	2977	1			T27	21		T251	634		T254	269
alert_integrity_fail	alert[0x1]	2574	1			T16	39		T19	28		T20	111
alert_integrity_fail	alert[0x2]	6419	1			T4	133		T19	1118		T20	23
alert_integrity_fail	alert[0x3]	5878	1			T19	11		T20	503		T29	3
alert_integrity_fail	alert[0x4]	2154	1			T4	61		T20	15		T6	3
alert_integrity_fail	alert[0x5]	2490	1			T16	151		T25	12		T20	85
alert_integrity_fail	alert[0x6]	5224	1			T16	1357		T5	1		T19	3
alert_integrity_fail	alert[0x7]	4903	1			T4	14		T5	9		T19	64
alert_integrity_fail	alert[0x8]	10265	1			T16	77		T25	2		T43	33
alert_integrity_fail	alert[0x9]	4159	1			T4	16		T16	43		T5	2
alert_integrity_fail	alert[0xa]	7977	1			T4	16		T19	206		T254	5
alert_integrity_fail	alert[0xb]	10935	1			T16	956		T19	109		T6	141
alert_integrity_fail	alert[0xc]	3267	1			T4	18		T6	41		T43	1
alert_integrity_fail	alert[0xd]	2536	1			T4	11		T16	141		T44	1
alert_integrity_fail	alert[0xe]	11106	1			T4	1		T16	55		T19	335
alert_integrity_fail	alert[0xf]	1785	1			T16	37		T68	3		T76	1
alert_integrity_fail	alert[0x10]	5693	1			T19	752		T20	15		T76	10
alert_integrity_fail	alert[0x11]	6950	1			T16	663		T5	5		T29	1
alert_integrity_fail	alert[0x12]	3513	1			T44	8		T254	1474		T36	7
alert_integrity_fail	alert[0x13]	2262	1			T16	57		T19	2		T43	1
alert_integrity_fail	alert[0x14]	8098	1			T16	2127		T25	1		T20	1087
alert_integrity_fail	alert[0x15]	3356	1			T19	197		T25	2		T29	2
alert_integrity_fail	alert[0x16]	3343	1			T16	201		T19	552		T44	6
alert_integrity_fail	alert[0x17]	3574	1			T4	708		T5	1		T19	12
alert_integrity_fail	alert[0x18]	3368	1			T4	5		T5	35		T6	13
alert_integrity_fail	alert[0x19]	3154	1			T5	3		T19	19		T251	55
alert_integrity_fail	alert[0x1a]	3689	1			T20	17		T29	14		T27	1
alert_integrity_fail	alert[0x1b]	5507	1			T5	6		T19	44		T20	102
alert_integrity_fail	alert[0x1c]	5596	1			T16	8		T6	70		T44	3
alert_integrity_fail	alert[0x1d]	3676	1			T20	878		T43	39		T68	4
alert_integrity_fail	alert[0x1e]	4486	1			T4	7		T5	21		T6	15
alert_integrity_fail	alert[0x1f]	17921	1			T4	7		T16	23		T43	6
alert_integrity_fail	alert[0x20]	6487	1			T4	14		T16	17		T25	26
alert_integrity_fail	alert[0x21]	2123	1			T5	10		T20	139		T44	28
alert_integrity_fail	alert[0x22]	2174	1			T16	21		T19	49		T20	19
alert_integrity_fail	alert[0x23]	6775	1			T19	8		T25	2		T20	173
alert_integrity_fail	alert[0x24]	3550	1			T16	5		T19	78		T43	1
alert_integrity_fail	alert[0x25]	5086	1			T16	81		T19	21		T43	2
alert_integrity_fail	alert[0x26]	4345	1			T4	32		T16	23		T19	199
alert_integrity_fail	alert[0x27]	3541	1			T16	6		T19	69		T20	8
alert_integrity_fail	alert[0x28]	2155	1			T19	56		T68	43		T251	30
alert_integrity_fail	alert[0x29]	4803	1			T4	48		T16	2151		T19	40
alert_integrity_fail	alert[0x2a]	2242	1			T16	206		T19	25		T20	11
alert_integrity_fail	alert[0x2b]	2434	1			T16	26		T5	2		T20	25
alert_integrity_fail	alert[0x2c]	7023	1			T4	23		T25	1		T29	77
alert_integrity_fail	alert[0x2d]	3148	1			T6	4		T29	24		T65	6
alert_integrity_fail	alert[0x2e]	2041	1			T4	2		T19	46		T25	2
alert_integrity_fail	alert[0x2f]	4030	1			T16	185		T251	504		T254	401
alert_integrity_fail	alert[0x30]	4886	1			T4	259		T20	29		T6	7
alert_integrity_fail	alert[0x31]	2491	1			T4	2		T16	31		T19	13
alert_integrity_fail	alert[0x32]	2098	1			T25	2		T68	10		T27	7
alert_integrity_fail	alert[0x33]	13006	1			T5	255		T19	12		T6	9
alert_integrity_fail	alert[0x34]	5088	1			T16	698		T19	191		T44	1
alert_integrity_fail	alert[0x35]	3799	1			T6	30		T44	1		T29	86
alert_integrity_fail	alert[0x36]	6579	1			T20	231		T6	1044		T27	1
alert_integrity_fail	alert[0x37]	8371	1			T16	55		T20	4		T6	92
alert_integrity_fail	alert[0x38]	4906	1			T29	71		T65	3		T76	3
alert_integrity_fail	alert[0x39]	5451	1			T4	5		T19	216		T20	13
alert_integrity_fail	alert[0x3a]	4842	1			T20	2		T76	6		T252	1
alert_integrity_fail	alert[0x3b]	7375	1			T5	17		T20	223		T43	16
alert_integrity_fail	alert[0x3c]	9644	1			T4	67		T5	11		T19	80
alert_integrity_fail	alert[0x3d]	2710	1			T16	11		T19	2		T20	289
alert_integrity_fail	alert[0x3e]	9069	1			T16	14		T25	4		T76	97
alert_integrity_fail	alert[0x3f]	3300	1			T16	11		T19	53		T20	1301
alert_integrity_fail	alert[0x40]	1817	1			T16	375		T20	27		T6	676
alert_ping_fail	alert[0x0]	10	1			T317	1		T318	2		T319	1
alert_ping_fail	alert[0x1]	6	1			T15	1		T320	1		T201	1
alert_ping_fail	alert[0x2]	7	1			T321	1		T322	1		T323	1
alert_ping_fail	alert[0x3]	4	1			T317	1		T324	1		T325	1
alert_ping_fail	alert[0x4]	8	1			T317	1		T320	1		T326	1
alert_ping_fail	alert[0x5]	10	1			T327	1		T328	1		T247	1
alert_ping_fail	alert[0x6]	16	1			T7	2		T324	1		T239	2
alert_ping_fail	alert[0x7]	15	1			T14	1		T329	2		T316	1
alert_ping_fail	alert[0x8]	12	1			T7	1		T41	1		T321	1
alert_ping_fail	alert[0x9]	5	1			T201	1		T330	1		T331	2
alert_ping_fail	alert[0xa]	17	1			T7	1		T41	1		T15	1
alert_ping_fail	alert[0xb]	15	1			T14	1		T324	1		T239	1
alert_ping_fail	alert[0xc]	8	1			T329	1		T320	1		T247	1
alert_ping_fail	alert[0xd]	12	1			T15	1		T327	1		T332	1
alert_ping_fail	alert[0xe]	10	1			T14	1		T247	2		T323	1
alert_ping_fail	alert[0xf]	12	1			T321	2		T324	1		T320	1
alert_ping_fail	alert[0x10]	10	1			T328	1		T332	2		T322	1
alert_ping_fail	alert[0x11]	7	1			T290	1		T333	1		T334	2
alert_ping_fail	alert[0x12]	5	1			T332	1		T318	1		T330	1
alert_ping_fail	alert[0x13]	15	1			T14	1		T284	1		T239	1
alert_ping_fail	alert[0x14]	12	1			T3	1		T14	1		T321	1
alert_ping_fail	alert[0x15]	11	1			T276	1		T316	1		T324	1
alert_ping_fail	alert[0x16]	10	1			T1	1		T7	1		T335	1
alert_ping_fail	alert[0x17]	12	1			T317	1		T290	1		T325	1
alert_ping_fail	alert[0x18]	13	1			T15	1		T317	1		T329	1
alert_ping_fail	alert[0x19]	12	1			T14	2		T15	1		T327	2
alert_ping_fail	alert[0x1a]	9	1			T327	1		T329	1		T332	1
alert_ping_fail	alert[0x1b]	14	1			T13	2		T324	1		T201	1
alert_ping_fail	alert[0x1c]	11	1			T1	1		T14	1		T15	1
alert_ping_fail	alert[0x1d]	6	1			T332	1		T336	1		T326	1
alert_ping_fail	alert[0x1e]	10	1			T329	1		T320	1		T333	1
alert_ping_fail	alert[0x1f]	6	1			T1	1		T265	1		T337	1
alert_ping_fail	alert[0x20]	15	1			T324	1		T328	1		T290	1
alert_ping_fail	alert[0x21]	10	1			T327	1		T247	1		T338	1
alert_ping_fail	alert[0x22]	12	1			T41	1		T24	1		T339	2
alert_ping_fail	alert[0x23]	5	1			T318	1		T319	1		T331	2
alert_ping_fail	alert[0x24]	6	1			T13	1		T290	1		T322	1
alert_ping_fail	alert[0x25]	12	1			T14	1		T321	1		T329	1
alert_ping_fail	alert[0x26]	9	1			T15	1		T324	2		T201	1
alert_ping_fail	alert[0x27]	13	1			T329	1		T338	1		T201	1
alert_ping_fail	alert[0x28]	19	1			T329	1		T328	1		T239	1
alert_ping_fail	alert[0x29]	5	1			T327	2		T336	1		T340	1
alert_ping_fail	alert[0x2a]	7	1			T201	1		T331	1		T341	1
alert_ping_fail	alert[0x2b]	6	1			T325	1		T326	1		T323	1
alert_ping_fail	alert[0x2c]	13	1			T329	1		T24	1		T320	1
alert_ping_fail	alert[0x2d]	12	1			T324	1		T328	1		T323	1
alert_ping_fail	alert[0x2e]	14	1			T14	1		T317	1		T328	1
alert_ping_fail	alert[0x2f]	17	1			T14	1		T327	1		T342	1
alert_ping_fail	alert[0x30]	13	1			T342	1		T324	1		T337	1
alert_ping_fail	alert[0x31]	6	1			T239	1		T247	2		T341	1
alert_ping_fail	alert[0x32]	7	1			T317	1		T324	1		T338	1
alert_ping_fail	alert[0x33]	13	1			T13	1		T328	1		T335	1
alert_ping_fail	alert[0x34]	10	1			T329	1		T320	1		T335	1
alert_ping_fail	alert[0x35]	15	1			T14	1		T317	2		T329	2
alert_ping_fail	alert[0x36]	14	1			T15	1		T317	1		T327	2
alert_ping_fail	alert[0x37]	11	1			T317	1		T332	1		T325	1
alert_ping_fail	alert[0x38]	13	1			T14	1		T321	1		T324	2
alert_ping_fail	alert[0x39]	8	1			T325	1		T322	1		T318	1
alert_ping_fail	alert[0x3a]	10	1			T247	1		T201	1		T323	1
alert_ping_fail	alert[0x3b]	9	1			T15	1		T239	1		T247	1
alert_ping_fail	alert[0x3c]	10	1			T327	1		T324	1		T335	1
alert_ping_fail	alert[0x3d]	10	1			T13	1		T332	1		T247	1
alert_ping_fail	alert[0x3e]	8	1			T327	1		T332	1		T336	1
alert_ping_fail	alert[0x3f]	4	1			T319	1		T343	1		T344	1
alert_ping_fail	alert[0x40]	2	1			T201	1		T319	1		-	-

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	72863	1			T4	1181		T6	571		T43	1
alert_integrity_fail	class_i[0x1]	89037	1			T5	3		T19	4682		T20	12068
alert_integrity_fail	class_i[0x2]	77670	1			T5	363		T44	66		T29	1630
alert_integrity_fail	class_i[0x3]	86654	1			T4	268		T16	9851		T5	12
alert_ping_fail	class_i[0x0]	175	1			T13	5		T14	1		T276	1
alert_ping_fail	class_i[0x1]	158	1			T7	5		T41	3		T14	12
alert_ping_fail	class_i[0x2]	199	1			T3	1		T265	1		T342	2
alert_ping_fail	class_i[0x3]	136	1			T1	3		T284	1		T329	1