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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.24 99.99 98.70 97.09 100.00 100.00 99.38 99.52


Total test records in report: 836
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T184 /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.1746333599 Aug 11 04:52:42 PM PDT 24 Aug 11 04:52:46 PM PDT 24 70365507 ps
T769 /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.1814854998 Aug 11 04:53:00 PM PDT 24 Aug 11 04:53:02 PM PDT 24 19272917 ps
T159 /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.3408454772 Aug 11 04:52:57 PM PDT 24 Aug 11 04:58:52 PM PDT 24 5039388813 ps
T770 /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.3557109606 Aug 11 04:52:55 PM PDT 24 Aug 11 04:56:13 PM PDT 24 16795547339 ps
T771 /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.3632940580 Aug 11 04:53:07 PM PDT 24 Aug 11 04:53:09 PM PDT 24 6435054 ps
T772 /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.2713355750 Aug 11 04:52:56 PM PDT 24 Aug 11 04:52:58 PM PDT 24 9456091 ps
T773 /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.366904783 Aug 11 04:52:54 PM PDT 24 Aug 11 04:53:03 PM PDT 24 234105756 ps
T155 /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.4252729508 Aug 11 04:53:03 PM PDT 24 Aug 11 05:09:51 PM PDT 24 25166917338 ps
T156 /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.1528940745 Aug 11 04:52:50 PM PDT 24 Aug 11 05:05:50 PM PDT 24 4352610738 ps
T774 /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.3348998511 Aug 11 04:53:00 PM PDT 24 Aug 11 04:53:02 PM PDT 24 10849159 ps
T775 /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.658623709 Aug 11 04:52:53 PM PDT 24 Aug 11 04:52:58 PM PDT 24 117749634 ps
T776 /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.1580327840 Aug 11 04:53:00 PM PDT 24 Aug 11 04:53:02 PM PDT 24 9693658 ps
T154 /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.53317224 Aug 11 04:53:01 PM PDT 24 Aug 11 05:00:02 PM PDT 24 4863864819 ps
T165 /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.3465238946 Aug 11 04:52:39 PM PDT 24 Aug 11 04:59:50 PM PDT 24 5366817938 ps
T777 /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.2845453269 Aug 11 04:52:49 PM PDT 24 Aug 11 04:52:58 PM PDT 24 206383026 ps
T778 /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.2500910758 Aug 11 04:53:02 PM PDT 24 Aug 11 04:53:04 PM PDT 24 6763532 ps
T779 /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.678042629 Aug 11 04:52:56 PM PDT 24 Aug 11 04:53:05 PM PDT 24 110569276 ps
T169 /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.1467594371 Aug 11 04:52:59 PM PDT 24 Aug 11 04:55:21 PM PDT 24 3137238819 ps
T780 /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.2171043958 Aug 11 04:53:01 PM PDT 24 Aug 11 04:53:09 PM PDT 24 38122202 ps
T162 /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.3869026918 Aug 11 04:52:50 PM PDT 24 Aug 11 05:01:02 PM PDT 24 6270786199 ps
T166 /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.4056996214 Aug 11 04:52:59 PM PDT 24 Aug 11 05:05:19 PM PDT 24 9304876363 ps
T781 /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.3117326625 Aug 11 04:52:58 PM PDT 24 Aug 11 04:53:17 PM PDT 24 1589562864 ps
T782 /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.3517515860 Aug 11 04:53:07 PM PDT 24 Aug 11 04:53:09 PM PDT 24 9011172 ps
T167 /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.2011060319 Aug 11 04:52:51 PM PDT 24 Aug 11 04:55:32 PM PDT 24 2634808832 ps
T783 /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.4061359511 Aug 11 04:52:56 PM PDT 24 Aug 11 04:52:58 PM PDT 24 12568356 ps
T784 /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.1676272432 Aug 11 04:52:50 PM PDT 24 Aug 11 04:53:00 PM PDT 24 250023745 ps
T785 /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.659368455 Aug 11 04:52:42 PM PDT 24 Aug 11 04:52:48 PM PDT 24 304428752 ps
T786 /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.85007004 Aug 11 04:52:54 PM PDT 24 Aug 11 04:52:59 PM PDT 24 158548810 ps
T787 /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.2673442284 Aug 11 04:52:47 PM PDT 24 Aug 11 04:52:55 PM PDT 24 667757674 ps
T788 /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.2220229899 Aug 11 04:53:00 PM PDT 24 Aug 11 04:53:03 PM PDT 24 110321143 ps
T158 /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.174760206 Aug 11 04:52:39 PM PDT 24 Aug 11 05:03:48 PM PDT 24 8107696902 ps
T168 /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.3767785191 Aug 11 04:52:54 PM PDT 24 Aug 11 04:59:18 PM PDT 24 4535307118 ps
T789 /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.2960781496 Aug 11 04:52:51 PM PDT 24 Aug 11 04:52:57 PM PDT 24 246529830 ps
T790 /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.3334031665 Aug 11 04:52:40 PM PDT 24 Aug 11 04:54:46 PM PDT 24 3268173647 ps
T791 /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.2218100313 Aug 11 04:52:53 PM PDT 24 Aug 11 04:52:55 PM PDT 24 11077792 ps
T792 /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.55589408 Aug 11 04:53:07 PM PDT 24 Aug 11 04:53:09 PM PDT 24 20664815 ps
T180 /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.1279566112 Aug 11 04:52:54 PM PDT 24 Aug 11 04:52:57 PM PDT 24 147864249 ps
T793 /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.1670716088 Aug 11 04:52:50 PM PDT 24 Aug 11 04:52:59 PM PDT 24 186154519 ps
T794 /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.3160530442 Aug 11 04:52:54 PM PDT 24 Aug 11 04:52:58 PM PDT 24 26633623 ps
T795 /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.177600414 Aug 11 04:52:48 PM PDT 24 Aug 11 04:53:29 PM PDT 24 546579123 ps
T796 /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.1052285221 Aug 11 04:52:59 PM PDT 24 Aug 11 04:53:08 PM PDT 24 68008034 ps
T797 /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.3153189487 Aug 11 04:53:07 PM PDT 24 Aug 11 04:53:09 PM PDT 24 11772167 ps
T181 /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.4249297094 Aug 11 04:52:50 PM PDT 24 Aug 11 04:54:01 PM PDT 24 987116377 ps
T798 /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.857740221 Aug 11 04:52:42 PM PDT 24 Aug 11 04:52:46 PM PDT 24 50166226 ps
T160 /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.1673078953 Aug 11 04:52:57 PM PDT 24 Aug 11 04:54:29 PM PDT 24 1597706391 ps
T163 /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.3153336571 Aug 11 04:52:54 PM PDT 24 Aug 11 05:01:06 PM PDT 24 7746548209 ps
T164 /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.954654785 Aug 11 04:52:52 PM PDT 24 Aug 11 05:00:43 PM PDT 24 56195266593 ps
T799 /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.2875711899 Aug 11 04:53:04 PM PDT 24 Aug 11 04:53:06 PM PDT 24 9370977 ps
T800 /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.3662757530 Aug 11 04:52:59 PM PDT 24 Aug 11 04:53:04 PM PDT 24 263398098 ps
T801 /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.2207800055 Aug 11 04:52:54 PM PDT 24 Aug 11 04:58:58 PM PDT 24 9293533348 ps
T802 /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.270486325 Aug 11 04:52:59 PM PDT 24 Aug 11 04:53:04 PM PDT 24 69481070 ps
T803 /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.2092274451 Aug 11 04:52:45 PM PDT 24 Aug 11 04:52:54 PM PDT 24 62171009 ps
T804 /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.2262223913 Aug 11 04:53:05 PM PDT 24 Aug 11 04:53:07 PM PDT 24 98179270 ps
T805 /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.664859133 Aug 11 04:53:07 PM PDT 24 Aug 11 04:53:15 PM PDT 24 366230872 ps
T806 /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.3625967981 Aug 11 04:52:59 PM PDT 24 Aug 11 04:53:22 PM PDT 24 508545429 ps
T807 /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.1690966098 Aug 11 04:52:52 PM PDT 24 Aug 11 04:54:31 PM PDT 24 935595813 ps
T808 /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.2405173393 Aug 11 04:52:55 PM PDT 24 Aug 11 04:52:56 PM PDT 24 6472741 ps
T809 /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.2389806747 Aug 11 04:53:05 PM PDT 24 Aug 11 04:53:07 PM PDT 24 13954689 ps
T810 /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.1040715380 Aug 11 04:52:45 PM PDT 24 Aug 11 04:53:10 PM PDT 24 1165537950 ps
T811 /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.690220584 Aug 11 04:52:56 PM PDT 24 Aug 11 04:55:34 PM PDT 24 2299212711 ps
T812 /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.3017539992 Aug 11 04:52:45 PM PDT 24 Aug 11 04:53:01 PM PDT 24 817005253 ps
T813 /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.2253254659 Aug 11 04:52:50 PM PDT 24 Aug 11 04:53:11 PM PDT 24 2695412324 ps
T814 /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.2076004527 Aug 11 04:52:45 PM PDT 24 Aug 11 04:52:47 PM PDT 24 9271289 ps
T815 /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.924533849 Aug 11 04:52:57 PM PDT 24 Aug 11 04:53:03 PM PDT 24 137600574 ps
T816 /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.1946327060 Aug 11 04:52:57 PM PDT 24 Aug 11 04:53:07 PM PDT 24 136077356 ps
T817 /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.2525276962 Aug 11 04:52:50 PM PDT 24 Aug 11 04:53:04 PM PDT 24 155164955 ps
T818 /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.3682591193 Aug 11 04:52:58 PM PDT 24 Aug 11 04:53:03 PM PDT 24 36650297 ps
T819 /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.299549174 Aug 11 04:52:54 PM PDT 24 Aug 11 04:53:15 PM PDT 24 4324823200 ps
T820 /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.377784150 Aug 11 04:52:47 PM PDT 24 Aug 11 04:52:48 PM PDT 24 8939668 ps
T821 /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.2169586441 Aug 11 04:52:49 PM PDT 24 Aug 11 04:52:55 PM PDT 24 160520014 ps
T822 /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.1838165874 Aug 11 04:52:58 PM PDT 24 Aug 11 04:53:10 PM PDT 24 126216019 ps
T823 /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.3127776473 Aug 11 04:52:59 PM PDT 24 Aug 11 04:53:00 PM PDT 24 7793169 ps
T824 /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.675134047 Aug 11 04:53:01 PM PDT 24 Aug 11 04:53:03 PM PDT 24 9744757 ps
T178 /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.4067077781 Aug 11 04:52:50 PM PDT 24 Aug 11 04:52:53 PM PDT 24 56947634 ps
T825 /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.2919498617 Aug 11 04:53:05 PM PDT 24 Aug 11 04:53:07 PM PDT 24 7783406 ps
T826 /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.2997946522 Aug 11 04:52:44 PM PDT 24 Aug 11 04:52:47 PM PDT 24 43773164 ps
T827 /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.2313424526 Aug 11 04:52:55 PM PDT 24 Aug 11 04:56:40 PM PDT 24 3684799926 ps
T828 /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.3552850714 Aug 11 04:52:42 PM PDT 24 Aug 11 04:53:03 PM PDT 24 523157861 ps
T829 /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.1218688208 Aug 11 04:52:51 PM PDT 24 Aug 11 04:53:04 PM PDT 24 740550130 ps
T830 /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.4081699972 Aug 11 04:52:47 PM PDT 24 Aug 11 04:52:49 PM PDT 24 19623193 ps
T831 /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.1745421878 Aug 11 04:52:48 PM PDT 24 Aug 11 04:53:33 PM PDT 24 656458558 ps
T832 /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.3017860713 Aug 11 04:52:59 PM PDT 24 Aug 11 04:53:01 PM PDT 24 11148355 ps
T833 /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.1465115612 Aug 11 04:52:39 PM PDT 24 Aug 11 04:56:45 PM PDT 24 7735001447 ps
T834 /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.1355641092 Aug 11 04:52:58 PM PDT 24 Aug 11 04:53:00 PM PDT 24 15882714 ps
T835 /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.925147925 Aug 11 04:52:51 PM PDT 24 Aug 11 04:56:44 PM PDT 24 2913202530 ps
T836 /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.1195765683 Aug 11 04:52:54 PM PDT 24 Aug 11 04:53:03 PM PDT 24 197747425 ps

Test location /workspace/coverage/default/23.alert_handler_stress_all_with_rand_reset.3642074443
Short name T4
Test name
Test status
Simulation time 118589411923 ps
CPU time 9567.65 seconds
Started Aug 11 04:54:03 PM PDT 24
Finished Aug 11 07:33:31 PM PDT 24
Peak memory 370708 kb
Host smart-1b2458e1-d7be-4f08-8bae-4737fa7b01d1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3642074443 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.alert_handler_stress_all_with_rand_reset.3642074443
Directory /workspace/23.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all_with_rand_reset.2450779530
Short name T6
Test name
Test status
Simulation time 133129089521 ps
CPU time 6339.67 seconds
Started Aug 11 04:55:28 PM PDT 24
Finished Aug 11 06:41:09 PM PDT 24
Peak memory 289620 kb
Host smart-6c17cdc0-3663-44ce-96ab-2c424751a173
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2450779530 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.alert_handler_stress_all_with_rand_reset.2450779530
Directory /workspace/45.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.3527863638
Short name T9
Test name
Test status
Simulation time 1247189719 ps
CPU time 19.82 seconds
Started Aug 11 04:53:17 PM PDT 24
Finished Aug 11 04:53:37 PM PDT 24
Peak memory 269528 kb
Host smart-aed819a7-51aa-45a9-b4c3-4f10d90bd350
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3527863638 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.3527863638
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all_with_rand_reset.1234818869
Short name T30
Test name
Test status
Simulation time 178805253755 ps
CPU time 3501.21 seconds
Started Aug 11 04:53:09 PM PDT 24
Finished Aug 11 05:51:31 PM PDT 24
Peak memory 305616 kb
Host smart-d28a8e67-be65-4de5-96af-00100b1567d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1234818869 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.alert_handler_stress_all_with_rand_reset.1234818869
Directory /workspace/2.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.2219554518
Short name T170
Test name
Test status
Simulation time 2000476991 ps
CPU time 41.17 seconds
Started Aug 11 04:52:54 PM PDT 24
Finished Aug 11 04:53:35 PM PDT 24
Peak memory 237900 kb
Host smart-40950f0c-b3e5-4943-bb20-227d32f787a0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2219554518 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.2219554518
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.459986946
Short name T19
Test name
Test status
Simulation time 22572717801 ps
CPU time 1124.98 seconds
Started Aug 11 04:53:14 PM PDT 24
Finished Aug 11 05:11:59 PM PDT 24
Peak memory 270764 kb
Host smart-5563a4d9-ea29-422b-8e03-31931d85240c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459986946 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.459986946
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.3243785150
Short name T115
Test name
Test status
Simulation time 29717128177 ps
CPU time 1901.05 seconds
Started Aug 11 04:55:47 PM PDT 24
Finished Aug 11 05:27:28 PM PDT 24
Peak memory 272804 kb
Host smart-35462b4f-2d19-464e-a4fb-04cf99920575
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3243785150 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_ha
ndler_stress_all.3243785150
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.3595031414
Short name T229
Test name
Test status
Simulation time 273953487 ps
CPU time 14.07 seconds
Started Aug 11 04:53:14 PM PDT 24
Finished Aug 11 04:53:28 PM PDT 24
Peak memory 248124 kb
Host smart-c4c134cb-9497-4727-962f-2c7e669ebb03
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3595031414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.3595031414
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.2565906842
Short name T96
Test name
Test status
Simulation time 24268213588 ps
CPU time 1523.97 seconds
Started Aug 11 04:55:02 PM PDT 24
Finished Aug 11 05:20:26 PM PDT 24
Peak memory 272260 kb
Host smart-cebc9c71-2f33-4fc3-a03e-fada3f06800a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2565906842 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.2565906842
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.849856897
Short name T138
Test name
Test status
Simulation time 1732016830 ps
CPU time 194.55 seconds
Started Aug 11 04:52:52 PM PDT 24
Finished Aug 11 04:56:06 PM PDT 24
Peak memory 265472 kb
Host smart-b2dbddce-2c4f-4237-af1e-ac295a3c86b4
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=849856897 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_erro
rs.849856897
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.662598641
Short name T300
Test name
Test status
Simulation time 43476153256 ps
CPU time 641.95 seconds
Started Aug 11 04:53:47 PM PDT 24
Finished Aug 11 05:04:29 PM PDT 24
Peak memory 256472 kb
Host smart-2840c2ac-1bfa-4d1f-923e-81f76e8a89b7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=662598641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_han
dler_stress_all.662598641
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.2917184639
Short name T134
Test name
Test status
Simulation time 33944413338 ps
CPU time 1128.49 seconds
Started Aug 11 04:52:55 PM PDT 24
Finished Aug 11 05:11:44 PM PDT 24
Peak memory 273460 kb
Host smart-6b56a974-bf31-4def-af73-1794fed059ac
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2917184639 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.2917184639
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.1528940745
Short name T156
Test name
Test status
Simulation time 4352610738 ps
CPU time 780.27 seconds
Started Aug 11 04:52:50 PM PDT 24
Finished Aug 11 05:05:50 PM PDT 24
Peak memory 265844 kb
Host smart-bdf32fe4-a72f-4831-885b-a09d220f75a0
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1528940745 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.1528940745
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.891713143
Short name T7
Test name
Test status
Simulation time 185764032663 ps
CPU time 2787.96 seconds
Started Aug 11 04:54:02 PM PDT 24
Finished Aug 11 05:40:30 PM PDT 24
Peak memory 288804 kb
Host smart-b4c8fb96-92aa-4b7d-b79f-6368587c0563
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=891713143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.891713143
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.4032817903
Short name T150
Test name
Test status
Simulation time 6160571366 ps
CPU time 201.23 seconds
Started Aug 11 04:52:59 PM PDT 24
Finished Aug 11 04:56:20 PM PDT 24
Peak memory 273028 kb
Host smart-bf468a63-e0c6-4baf-a3c9-9ab1a669eda6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4032817903 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_err
ors.4032817903
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all_with_rand_reset.1310505314
Short name T5
Test name
Test status
Simulation time 20522110773 ps
CPU time 2490.41 seconds
Started Aug 11 04:53:16 PM PDT 24
Finished Aug 11 05:34:46 PM PDT 24
Peak memory 305136 kb
Host smart-8e74fe95-d296-4b0e-9867-86005240082c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1310505314 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.alert_handler_stress_all_with_rand_reset.1310505314
Directory /workspace/4.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.3959344652
Short name T324
Test name
Test status
Simulation time 12336177057 ps
CPU time 517.3 seconds
Started Aug 11 04:53:46 PM PDT 24
Finished Aug 11 05:02:24 PM PDT 24
Peak memory 248216 kb
Host smart-6dd67720-77e1-4ce0-a3f2-5108487c7c05
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3959344652 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.3959344652
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.869650633
Short name T359
Test name
Test status
Simulation time 16027545 ps
CPU time 1.5 seconds
Started Aug 11 04:53:01 PM PDT 24
Finished Aug 11 04:53:03 PM PDT 24
Peak memory 237588 kb
Host smart-ca003f4b-145c-4ab7-a8f4-e0e4262d5ee8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=869650633 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.869650633
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.3465238946
Short name T165
Test name
Test status
Simulation time 5366817938 ps
CPU time 430.36 seconds
Started Aug 11 04:52:39 PM PDT 24
Finished Aug 11 04:59:50 PM PDT 24
Peak memory 265632 kb
Host smart-d9150f69-c678-494b-8a08-cbae85781b8d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3465238946 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_erro
rs.3465238946
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.1817726079
Short name T277
Test name
Test status
Simulation time 77997187892 ps
CPU time 2308.62 seconds
Started Aug 11 04:55:08 PM PDT 24
Finished Aug 11 05:33:38 PM PDT 24
Peak memory 281008 kb
Host smart-b0184f53-dec4-4a1f-91d7-2e600e6feaad
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1817726079 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.1817726079
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.1705619774
Short name T145
Test name
Test status
Simulation time 17895122813 ps
CPU time 636.18 seconds
Started Aug 11 04:52:58 PM PDT 24
Finished Aug 11 05:03:35 PM PDT 24
Peak memory 265672 kb
Host smart-c505b3b9-d9ee-4ee8-a57a-e30bee9cdf36
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705619774 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.1705619774
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.960035165
Short name T16
Test name
Test status
Simulation time 21219369374 ps
CPU time 1587.53 seconds
Started Aug 11 04:54:43 PM PDT 24
Finished Aug 11 05:21:11 PM PDT 24
Peak memory 272668 kb
Host smart-c055ed63-c303-4665-9630-cbe69ced8e75
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=960035165 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.960035165
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.3575769468
Short name T24
Test name
Test status
Simulation time 63973965534 ps
CPU time 3590.59 seconds
Started Aug 11 04:54:50 PM PDT 24
Finished Aug 11 05:54:42 PM PDT 24
Peak memory 288968 kb
Host smart-b2e6e5dc-ea4a-491d-b7db-b7ec0a31bee9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3575769468 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.3575769468
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.2831248063
Short name T148
Test name
Test status
Simulation time 39889139232 ps
CPU time 321.76 seconds
Started Aug 11 04:52:42 PM PDT 24
Finished Aug 11 04:58:04 PM PDT 24
Peak memory 273644 kb
Host smart-6df145e6-71fd-448c-8466-47222ab03663
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2831248063 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_erro
rs.2831248063
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.1879201882
Short name T332
Test name
Test status
Simulation time 77927432654 ps
CPU time 441 seconds
Started Aug 11 04:54:06 PM PDT 24
Finished Aug 11 05:01:27 PM PDT 24
Peak memory 254816 kb
Host smart-9914041f-403a-413b-b713-e7efb1fe3810
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1879201882 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.1879201882
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.2938571234
Short name T142
Test name
Test status
Simulation time 72568662092 ps
CPU time 1069.12 seconds
Started Aug 11 04:52:50 PM PDT 24
Finished Aug 11 05:10:39 PM PDT 24
Peak memory 265664 kb
Host smart-a52ccfc9-b12a-4646-a281-b55f310457f9
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2938571234 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.2938571234
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.2146453944
Short name T114
Test name
Test status
Simulation time 56625963502 ps
CPU time 3320.36 seconds
Started Aug 11 04:55:27 PM PDT 24
Finished Aug 11 05:50:48 PM PDT 24
Peak memory 304840 kb
Host smart-76b893f7-1540-4322-b250-fe370c94e6b5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2146453944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_ha
ndler_stress_all.2146453944
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.510044980
Short name T329
Test name
Test status
Simulation time 34614216765 ps
CPU time 486.59 seconds
Started Aug 11 04:55:27 PM PDT 24
Finished Aug 11 05:03:34 PM PDT 24
Peak memory 248100 kb
Host smart-85d204ed-6f09-4646-a68e-f3bbf4803f33
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=510044980 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.510044980
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all_with_rand_reset.2366200903
Short name T49
Test name
Test status
Simulation time 158362820583 ps
CPU time 4981.2 seconds
Started Aug 11 04:54:07 PM PDT 24
Finished Aug 11 06:17:09 PM PDT 24
Peak memory 322168 kb
Host smart-b1313470-71f2-43bd-80c4-5476959bf26a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366200903 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.alert_handler_stress_all_with_rand_reset.2366200903
Directory /workspace/24.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.4252441414
Short name T139
Test name
Test status
Simulation time 67168745124 ps
CPU time 1332.85 seconds
Started Aug 11 04:52:47 PM PDT 24
Finished Aug 11 05:15:00 PM PDT 24
Peak memory 272792 kb
Host smart-b13bb5a3-3f88-42e6-9ceb-5bb0d2542964
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252441414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.4252441414
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.346100226
Short name T331
Test name
Test status
Simulation time 14733348220 ps
CPU time 575.96 seconds
Started Aug 11 04:53:45 PM PDT 24
Finished Aug 11 05:03:21 PM PDT 24
Peak memory 248244 kb
Host smart-e4b6156c-def1-4751-bfd9-e51e749595ef
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=346100226 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.346100226
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.2019019764
Short name T274
Test name
Test status
Simulation time 110095447566 ps
CPU time 3300.45 seconds
Started Aug 11 04:54:30 PM PDT 24
Finished Aug 11 05:49:31 PM PDT 24
Peak memory 289212 kb
Host smart-f3377b1c-9156-4da4-85e4-8774b91a1212
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2019019764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.2019019764
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.3402371929
Short name T348
Test name
Test status
Simulation time 36927676130 ps
CPU time 2407.96 seconds
Started Aug 11 04:54:56 PM PDT 24
Finished Aug 11 05:35:04 PM PDT 24
Peak memory 284400 kb
Host smart-84a1faed-312f-4252-8021-799fd359d80a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3402371929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.3402371929
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.3092106492
Short name T340
Test name
Test status
Simulation time 13734524507 ps
CPU time 582.71 seconds
Started Aug 11 04:55:46 PM PDT 24
Finished Aug 11 05:05:29 PM PDT 24
Peak memory 247284 kb
Host smart-674566ba-4189-4e06-9bc0-a310f547dd3f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3092106492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.3092106492
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all_with_rand_reset.1217830069
Short name T113
Test name
Test status
Simulation time 220403612495 ps
CPU time 3583.17 seconds
Started Aug 11 04:55:47 PM PDT 24
Finished Aug 11 05:55:30 PM PDT 24
Peak memory 305116 kb
Host smart-c0d81439-d05e-4075-9a69-03d6163d17dc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1217830069 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.alert_handler_stress_all_with_rand_reset.1217830069
Directory /workspace/47.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.3384361867
Short name T140
Test name
Test status
Simulation time 18810619728 ps
CPU time 344.29 seconds
Started Aug 11 04:53:05 PM PDT 24
Finished Aug 11 04:58:49 PM PDT 24
Peak memory 272228 kb
Host smart-41576a6e-c837-491c-8085-4caf04c6f0bf
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3384361867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_err
ors.3384361867
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.2853359962
Short name T360
Test name
Test status
Simulation time 18190165 ps
CPU time 1.47 seconds
Started Aug 11 04:53:00 PM PDT 24
Finished Aug 11 04:53:02 PM PDT 24
Peak memory 236508 kb
Host smart-797fb1dd-a227-4802-9ef0-4e9a98184119
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2853359962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.2853359962
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all_with_rand_reset.2198948411
Short name T121
Test name
Test status
Simulation time 103233512654 ps
CPU time 9008.74 seconds
Started Aug 11 04:55:04 PM PDT 24
Finished Aug 11 07:25:13 PM PDT 24
Peak memory 394592 kb
Host smart-55d57c05-6dfa-4fc2-8f92-57a88fbb694a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2198948411 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.alert_handler_stress_all_with_rand_reset.2198948411
Directory /workspace/40.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.4252729508
Short name T155
Test name
Test status
Simulation time 25166917338 ps
CPU time 1007.79 seconds
Started Aug 11 04:53:03 PM PDT 24
Finished Aug 11 05:09:51 PM PDT 24
Peak memory 265588 kb
Host smart-56cbff1c-69b0-432d-ab0c-5e00cfa34ee3
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252729508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.4252729508
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.2321249699
Short name T189
Test name
Test status
Simulation time 372917406 ps
CPU time 3.96 seconds
Started Aug 11 04:52:53 PM PDT 24
Finished Aug 11 04:52:57 PM PDT 24
Peak memory 236700 kb
Host smart-fdfa8996-b9e4-4e15-88af-4e3c2ef0253b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2321249699 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.2321249699
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.955267303
Short name T363
Test name
Test status
Simulation time 2070964510 ps
CPU time 282.99 seconds
Started Aug 11 04:52:54 PM PDT 24
Finished Aug 11 04:57:37 PM PDT 24
Peak memory 237556 kb
Host smart-82d08d90-c6fc-4b35-a277-3d15a8c76d6f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=955267303 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.955267303
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.1068168077
Short name T691
Test name
Test status
Simulation time 8265774036 ps
CPU time 319.72 seconds
Started Aug 11 04:53:16 PM PDT 24
Finished Aug 11 04:58:36 PM PDT 24
Peak memory 248208 kb
Host smart-4d377371-f3ec-4ee4-8dbe-fd21b117ab06
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1068168077 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.1068168077
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.1570241582
Short name T337
Test name
Test status
Simulation time 171013948522 ps
CPU time 2415.01 seconds
Started Aug 11 04:55:46 PM PDT 24
Finished Aug 11 05:36:01 PM PDT 24
Peak memory 286960 kb
Host smart-89e2bbfc-364a-405b-8473-c2d9961d4c77
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570241582 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.1570241582
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all_with_rand_reset.590975415
Short name T116
Test name
Test status
Simulation time 93237189474 ps
CPU time 1595.89 seconds
Started Aug 11 04:55:48 PM PDT 24
Finished Aug 11 05:22:25 PM PDT 24
Peak memory 281088 kb
Host smart-eaf22f62-01ac-4dd9-b61a-6e30030c453c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=590975415 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 49.alert_handler_stress_all_with_rand_reset.590975415
Directory /workspace/49.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.3099895449
Short name T82
Test name
Test status
Simulation time 341882038104 ps
CPU time 2843.35 seconds
Started Aug 11 04:53:37 PM PDT 24
Finished Aug 11 05:41:01 PM PDT 24
Peak memory 289160 kb
Host smart-b633741f-0a7a-43a9-99f2-25667aabfca4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099895449 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_ha
ndler_stress_all.3099895449
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.3408454772
Short name T159
Test name
Test status
Simulation time 5039388813 ps
CPU time 355.01 seconds
Started Aug 11 04:52:57 PM PDT 24
Finished Aug 11 04:58:52 PM PDT 24
Peak memory 272716 kb
Host smart-78267058-3a3a-4729-b415-15e23b9a9811
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3408454772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_erro
rs.3408454772
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.4098998274
Short name T293
Test name
Test status
Simulation time 7312882570 ps
CPU time 51.66 seconds
Started Aug 11 04:55:26 PM PDT 24
Finished Aug 11 04:56:18 PM PDT 24
Peak memory 248860 kb
Host smart-89328383-d972-4236-b4fb-6a29b100f0ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40989
98274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.4098998274
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.17216295
Short name T215
Test name
Test status
Simulation time 132937740 ps
CPU time 3.05 seconds
Started Aug 11 04:53:08 PM PDT 24
Finished Aug 11 04:53:11 PM PDT 24
Peak memory 248224 kb
Host smart-a2d50198-b964-4c1e-a38f-a7251a2d6825
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=17216295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.17216295
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.1412423255
Short name T221
Test name
Test status
Simulation time 15906015 ps
CPU time 2.51 seconds
Started Aug 11 04:53:06 PM PDT 24
Finished Aug 11 04:53:08 PM PDT 24
Peak memory 248476 kb
Host smart-3429cca6-a086-433b-8a24-6d57324d5cf6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1412423255 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.1412423255
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.558103590
Short name T220
Test name
Test status
Simulation time 73673956 ps
CPU time 3.62 seconds
Started Aug 11 04:53:42 PM PDT 24
Finished Aug 11 04:53:45 PM PDT 24
Peak memory 248324 kb
Host smart-3468928c-7ad7-45fc-88b7-465ffe9fb924
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=558103590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.558103590
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.3301396170
Short name T223
Test name
Test status
Simulation time 17231927 ps
CPU time 2.9 seconds
Started Aug 11 04:53:38 PM PDT 24
Finished Aug 11 04:53:41 PM PDT 24
Peak memory 248512 kb
Host smart-6ce4fbb9-2e94-4f19-9ed4-ed2c00a3a69a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3301396170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.3301396170
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.1569869643
Short name T237
Test name
Test status
Simulation time 95590572148 ps
CPU time 1620.09 seconds
Started Aug 11 04:53:35 PM PDT 24
Finished Aug 11 05:20:36 PM PDT 24
Peak memory 272608 kb
Host smart-63ddd40b-8350-47f7-8690-ceff624175f4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1569869643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.1569869643
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.3180701673
Short name T325
Test name
Test status
Simulation time 23980538904 ps
CPU time 508.55 seconds
Started Aug 11 04:53:49 PM PDT 24
Finished Aug 11 05:02:18 PM PDT 24
Peak memory 248060 kb
Host smart-ed3690ac-3764-4c94-b05f-3042d19eaf84
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180701673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.3180701673
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all_with_rand_reset.4206531376
Short name T258
Test name
Test status
Simulation time 205441532903 ps
CPU time 3220.53 seconds
Started Aug 11 04:54:17 PM PDT 24
Finished Aug 11 05:47:58 PM PDT 24
Peak memory 305160 kb
Host smart-9da13aa8-f0c6-4531-ba82-7a31f457fd47
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4206531376 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.alert_handler_stress_all_with_rand_reset.4206531376
Directory /workspace/25.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all_with_rand_reset.4004243827
Short name T27
Test name
Test status
Simulation time 21038734272 ps
CPU time 1349.1 seconds
Started Aug 11 04:53:13 PM PDT 24
Finished Aug 11 05:15:43 PM PDT 24
Peak memory 270444 kb
Host smart-4640b6e3-0c72-4b00-bd8a-3be29ad876b2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4004243827 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.alert_handler_stress_all_with_rand_reset.4004243827
Directory /workspace/3.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all_with_rand_reset.3313996583
Short name T94
Test name
Test status
Simulation time 171391096761 ps
CPU time 2675.84 seconds
Started Aug 11 04:54:44 PM PDT 24
Finished Aug 11 05:39:20 PM PDT 24
Peak memory 297524 kb
Host smart-ad58b52e-d097-47d9-b494-91cfd8060d64
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3313996583 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.alert_handler_stress_all_with_rand_reset.3313996583
Directory /workspace/34.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.3403761247
Short name T297
Test name
Test status
Simulation time 2256526586 ps
CPU time 43.33 seconds
Started Aug 11 04:55:04 PM PDT 24
Finished Aug 11 04:55:47 PM PDT 24
Peak memory 248292 kb
Host smart-c6f0a55c-8357-45aa-93af-ed5c5fb2633d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34037
61247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.3403761247
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.2379009153
Short name T294
Test name
Test status
Simulation time 1106186398 ps
CPU time 68.78 seconds
Started Aug 11 04:55:15 PM PDT 24
Finished Aug 11 04:56:24 PM PDT 24
Peak memory 255644 kb
Host smart-4402a715-c4e4-40f1-8b3d-96233f5c2adb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23790
09153 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.2379009153
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all_with_rand_reset.3675666139
Short name T103
Test name
Test status
Simulation time 44292118899 ps
CPU time 4918.95 seconds
Started Aug 11 04:53:32 PM PDT 24
Finished Aug 11 06:15:32 PM PDT 24
Peak memory 354852 kb
Host smart-8e2c06b0-aa89-4056-9881-f0354d40acf1
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3675666139 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.alert_handler_stress_all_with_rand_reset.3675666139
Directory /workspace/7.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.117892345
Short name T153
Test name
Test status
Simulation time 8556367360 ps
CPU time 347.85 seconds
Started Aug 11 04:52:51 PM PDT 24
Finished Aug 11 04:58:39 PM PDT 24
Peak memory 265492 kb
Host smart-a836f03a-8e2c-4469-b047-63c45e327f1a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117892345 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.117892345
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.2011060319
Short name T167
Test name
Test status
Simulation time 2634808832 ps
CPU time 160.53 seconds
Started Aug 11 04:52:51 PM PDT 24
Finished Aug 11 04:55:32 PM PDT 24
Peak memory 265436 kb
Host smart-377f87b9-2f58-40ae-8339-622e263a0751
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2011060319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_erro
rs.2011060319
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.1016198235
Short name T228
Test name
Test status
Simulation time 154098784632 ps
CPU time 2056.31 seconds
Started Aug 11 04:53:02 PM PDT 24
Finished Aug 11 05:27:19 PM PDT 24
Peak memory 272168 kb
Host smart-e4d72857-02ad-4090-9dc7-d10c27e21ec2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1016198235 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.1016198235
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.1084143492
Short name T334
Test name
Test status
Simulation time 11868222299 ps
CPU time 503.71 seconds
Started Aug 11 04:53:30 PM PDT 24
Finished Aug 11 05:01:54 PM PDT 24
Peak memory 248048 kb
Host smart-a51dd372-6389-4af2-8954-090de09de3e7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1084143492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.1084143492
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.822016443
Short name T271
Test name
Test status
Simulation time 1911054683 ps
CPU time 33.58 seconds
Started Aug 11 04:53:36 PM PDT 24
Finished Aug 11 04:54:10 PM PDT 24
Peak memory 255632 kb
Host smart-bd4b433c-887a-4b43-a5f8-a98e76d33709
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82201
6443 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.822016443
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all_with_rand_reset.826940181
Short name T52
Test name
Test status
Simulation time 54304015790 ps
CPU time 2701.08 seconds
Started Aug 11 04:53:40 PM PDT 24
Finished Aug 11 05:38:41 PM PDT 24
Peak memory 289312 kb
Host smart-f6028dcd-1d26-4549-ae2c-75aaede0761a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=826940181 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 10.alert_handler_stress_all_with_rand_reset.826940181
Directory /workspace/10.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.2606709395
Short name T299
Test name
Test status
Simulation time 2755497579 ps
CPU time 31.07 seconds
Started Aug 11 04:53:41 PM PDT 24
Finished Aug 11 04:54:12 PM PDT 24
Peak memory 248108 kb
Host smart-773404c4-c0ae-4ebb-ae5a-d85cb5fb4d9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26067
09395 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.2606709395
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.3591596071
Short name T104
Test name
Test status
Simulation time 11505042596 ps
CPU time 1442.08 seconds
Started Aug 11 04:53:39 PM PDT 24
Finished Aug 11 05:17:41 PM PDT 24
Peak memory 286184 kb
Host smart-bc4014b2-826c-4277-bc64-e0282c15f96e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3591596071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_ha
ndler_stress_all.3591596071
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.2505775404
Short name T268
Test name
Test status
Simulation time 1028188319 ps
CPU time 46.48 seconds
Started Aug 11 04:53:47 PM PDT 24
Finished Aug 11 04:54:33 PM PDT 24
Peak memory 247996 kb
Host smart-6b07d2ba-b6ae-451f-b693-90e47e6a2f33
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25057
75404 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.2505775404
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.698637202
Short name T304
Test name
Test status
Simulation time 19476369025 ps
CPU time 1996.85 seconds
Started Aug 11 04:54:28 PM PDT 24
Finished Aug 11 05:27:46 PM PDT 24
Peak memory 289024 kb
Host smart-4a82b6f3-7121-454a-8c33-b6229bd8f84b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=698637202 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_han
dler_stress_all.698637202
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.4294233267
Short name T201
Test name
Test status
Simulation time 8827618577 ps
CPU time 360 seconds
Started Aug 11 04:54:36 PM PDT 24
Finished Aug 11 05:00:36 PM PDT 24
Peak memory 248228 kb
Host smart-cba4e15b-6378-40aa-861e-92ab469155dd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4294233267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.4294233267
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all_with_rand_reset.2133679974
Short name T283
Test name
Test status
Simulation time 59236774400 ps
CPU time 5856.74 seconds
Started Aug 11 04:55:16 PM PDT 24
Finished Aug 11 06:32:54 PM PDT 24
Peak memory 338508 kb
Host smart-bd9658ad-8ceb-463f-a10b-5752c4a99b91
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2133679974 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.alert_handler_stress_all_with_rand_reset.2133679974
Directory /workspace/43.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.954654785
Short name T164
Test name
Test status
Simulation time 56195266593 ps
CPU time 470.44 seconds
Started Aug 11 04:52:52 PM PDT 24
Finished Aug 11 05:00:43 PM PDT 24
Peak memory 273496 kb
Host smart-9ca0e0e2-3a5f-47ff-a7be-93a990abb811
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=954654785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.954654785
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.786433247
Short name T179
Test name
Test status
Simulation time 66377719 ps
CPU time 3.55 seconds
Started Aug 11 04:52:52 PM PDT 24
Finished Aug 11 04:52:56 PM PDT 24
Peak memory 236656 kb
Host smart-3c600c51-72f0-46f6-8129-ec392b564199
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=786433247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.786433247
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.4249297094
Short name T181
Test name
Test status
Simulation time 987116377 ps
CPU time 71.35 seconds
Started Aug 11 04:52:50 PM PDT 24
Finished Aug 11 04:54:01 PM PDT 24
Peak memory 240492 kb
Host smart-d4208eec-57e0-4d47-8d95-f51460301717
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4249297094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.4249297094
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all_with_rand_reset.3991051451
Short name T76
Test name
Test status
Simulation time 14307120479 ps
CPU time 1489.6 seconds
Started Aug 11 04:55:22 PM PDT 24
Finished Aug 11 05:20:12 PM PDT 24
Peak memory 305708 kb
Host smart-ecbac22f-7f99-4f75-a3b9-08f40093d2e3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3991051451 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.alert_handler_stress_all_with_rand_reset.3991051451
Directory /workspace/44.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.1017766328
Short name T182
Test name
Test status
Simulation time 1259195064 ps
CPU time 49.65 seconds
Started Aug 11 04:52:59 PM PDT 24
Finished Aug 11 04:53:49 PM PDT 24
Peak memory 240512 kb
Host smart-b894e223-c32e-4fb5-851c-4f7f9495a94f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1017766328 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.1017766328
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.1279566112
Short name T180
Test name
Test status
Simulation time 147864249 ps
CPU time 3.16 seconds
Started Aug 11 04:52:54 PM PDT 24
Finished Aug 11 04:52:57 PM PDT 24
Peak memory 237568 kb
Host smart-62ba5bb5-18df-4130-ba0c-a20172f437e2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1279566112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.1279566112
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.1478291474
Short name T186
Test name
Test status
Simulation time 1846574616 ps
CPU time 65.3 seconds
Started Aug 11 04:52:44 PM PDT 24
Finished Aug 11 04:53:50 PM PDT 24
Peak memory 240576 kb
Host smart-f5437571-7542-46e8-be1b-8341caf08a22
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1478291474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.1478291474
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.1467594371
Short name T169
Test name
Test status
Simulation time 3137238819 ps
CPU time 142.66 seconds
Started Aug 11 04:52:59 PM PDT 24
Finished Aug 11 04:55:21 PM PDT 24
Peak memory 265984 kb
Host smart-e43ae25d-7edf-452f-ab4a-847a6120e0d0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1467594371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_err
ors.1467594371
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.3763416722
Short name T183
Test name
Test status
Simulation time 289381819 ps
CPU time 4.5 seconds
Started Aug 11 04:52:55 PM PDT 24
Finished Aug 11 04:52:59 PM PDT 24
Peak memory 237804 kb
Host smart-62f67ec4-1e40-451c-9e06-12382af14b3a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3763416722 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.3763416722
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.4262333640
Short name T137
Test name
Test status
Simulation time 1769904199 ps
CPU time 107.25 seconds
Started Aug 11 04:53:01 PM PDT 24
Finished Aug 11 04:54:49 PM PDT 24
Peak memory 267404 kb
Host smart-bc8b7eac-00ce-4ed0-8378-4a02ce33f8fe
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4262333640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_err
ors.4262333640
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.3528228049
Short name T185
Test name
Test status
Simulation time 5187472325 ps
CPU time 64.03 seconds
Started Aug 11 04:52:54 PM PDT 24
Finished Aug 11 04:53:59 PM PDT 24
Peak memory 248784 kb
Host smart-88075d88-6fc5-46b2-bfa3-427d1ff03486
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3528228049 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.3528228049
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.203918678
Short name T188
Test name
Test status
Simulation time 466286652 ps
CPU time 36.69 seconds
Started Aug 11 04:52:39 PM PDT 24
Finished Aug 11 04:53:16 PM PDT 24
Peak memory 237640 kb
Host smart-a32a0cfc-bf86-4fe4-a603-c46ee67a598d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=203918678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.203918678
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.1746333599
Short name T184
Test name
Test status
Simulation time 70365507 ps
CPU time 4.22 seconds
Started Aug 11 04:52:42 PM PDT 24
Finished Aug 11 04:52:46 PM PDT 24
Peak memory 237912 kb
Host smart-fdc7ec5c-2ff1-4759-a95d-ac619f9b970c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1746333599 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.1746333599
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.4067077781
Short name T178
Test name
Test status
Simulation time 56947634 ps
CPU time 2.24 seconds
Started Aug 11 04:52:50 PM PDT 24
Finished Aug 11 04:52:53 PM PDT 24
Peak memory 237780 kb
Host smart-b3acd8a8-8684-437b-ae8c-138f45a96fc3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4067077781 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.4067077781
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.1305279636
Short name T172
Test name
Test status
Simulation time 2537082506 ps
CPU time 79.01 seconds
Started Aug 11 04:52:57 PM PDT 24
Finished Aug 11 04:54:17 PM PDT 24
Peak memory 240512 kb
Host smart-0ad68a99-72af-42be-bb3b-f64313614839
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1305279636 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.1305279636
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.1359179404
Short name T176
Test name
Test status
Simulation time 196349807 ps
CPU time 3.84 seconds
Started Aug 11 04:52:50 PM PDT 24
Finished Aug 11 04:52:55 PM PDT 24
Peak memory 237812 kb
Host smart-d2570448-9425-4eda-ae22-7636f9439bba
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1359179404 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.1359179404
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.4000106048
Short name T171
Test name
Test status
Simulation time 242937718 ps
CPU time 3.74 seconds
Started Aug 11 04:52:47 PM PDT 24
Finished Aug 11 04:52:51 PM PDT 24
Peak memory 237500 kb
Host smart-ff711315-ef33-4c08-b2de-e437c5f007db
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4000106048 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.4000106048
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.1864394221
Short name T23
Test name
Test status
Simulation time 13956813455 ps
CPU time 1309.74 seconds
Started Aug 11 04:54:15 PM PDT 24
Finished Aug 11 05:16:05 PM PDT 24
Peak memory 288680 kb
Host smart-4c8e172c-b7c1-43f6-8606-183cca68c61b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1864394221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_ha
ndler_stress_all.1864394221
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.3334031665
Short name T790
Test name
Test status
Simulation time 3268173647 ps
CPU time 126.11 seconds
Started Aug 11 04:52:40 PM PDT 24
Finished Aug 11 04:54:46 PM PDT 24
Peak memory 237632 kb
Host smart-0a290190-f6c9-4016-a233-8d8630c9b650
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3334031665 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.3334031665
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.1465115612
Short name T833
Test name
Test status
Simulation time 7735001447 ps
CPU time 245.61 seconds
Started Aug 11 04:52:39 PM PDT 24
Finished Aug 11 04:56:45 PM PDT 24
Peak memory 236748 kb
Host smart-c3f21095-dc5b-4078-8a1c-9483359cc946
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1465115612 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.1465115612
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.2418572339
Short name T739
Test name
Test status
Simulation time 60445659 ps
CPU time 5.5 seconds
Started Aug 11 04:52:40 PM PDT 24
Finished Aug 11 04:52:45 PM PDT 24
Peak memory 240536 kb
Host smart-78132b84-f156-464e-9165-fdbd41cd56a2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2418572339 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.2418572339
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.2673442284
Short name T787
Test name
Test status
Simulation time 667757674 ps
CPU time 8.35 seconds
Started Aug 11 04:52:47 PM PDT 24
Finished Aug 11 04:52:55 PM PDT 24
Peak memory 240452 kb
Host smart-71a8f4fc-e098-485e-91f8-335fe5878f02
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2673442284 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 0.alert_handler_csr_mem_rw_with_rand_reset.2673442284
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.601726702
Short name T192
Test name
Test status
Simulation time 136329392 ps
CPU time 10.69 seconds
Started Aug 11 04:52:37 PM PDT 24
Finished Aug 11 04:52:48 PM PDT 24
Peak memory 237492 kb
Host smart-3b58b62a-bbb4-4ebf-a9a1-5217b38d7c28
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=601726702 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.601726702
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.3889310492
Short name T763
Test name
Test status
Simulation time 11060426 ps
CPU time 1.31 seconds
Started Aug 11 04:52:42 PM PDT 24
Finished Aug 11 04:52:43 PM PDT 24
Peak memory 235628 kb
Host smart-3fba313f-e614-46e1-b501-829f7276c4d1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3889310492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.3889310492
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.2304172416
Short name T754
Test name
Test status
Simulation time 2018474881 ps
CPU time 39.84 seconds
Started Aug 11 04:52:45 PM PDT 24
Finished Aug 11 04:53:25 PM PDT 24
Peak memory 245644 kb
Host smart-42792304-e4f5-4978-9feb-f64edee69609
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2304172416 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_out
standing.2304172416
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.678271408
Short name T151
Test name
Test status
Simulation time 25484686582 ps
CPU time 509.93 seconds
Started Aug 11 04:52:41 PM PDT 24
Finished Aug 11 05:01:12 PM PDT 24
Peak memory 265540 kb
Host smart-2ec582e6-5b2b-4269-9d47-44c1e2d2b4cf
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=678271408 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.678271408
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.3821533260
Short name T737
Test name
Test status
Simulation time 280605386 ps
CPU time 11.18 seconds
Started Aug 11 04:52:42 PM PDT 24
Finished Aug 11 04:52:53 PM PDT 24
Peak memory 248676 kb
Host smart-24b13a8d-905a-42ca-a872-02733e9db151
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3821533260 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.3821533260
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.3318047004
Short name T744
Test name
Test status
Simulation time 18005844741 ps
CPU time 312.01 seconds
Started Aug 11 04:52:47 PM PDT 24
Finished Aug 11 04:57:59 PM PDT 24
Peak memory 241468 kb
Host smart-7b7cc408-61a4-4ba4-9015-cc50a5cdde67
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3318047004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.3318047004
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.1222584667
Short name T762
Test name
Test status
Simulation time 53728000 ps
CPU time 6.54 seconds
Started Aug 11 04:52:41 PM PDT 24
Finished Aug 11 04:52:48 PM PDT 24
Peak memory 240512 kb
Host smart-19a9b1c4-0391-4257-bf00-1154f0507bc2
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1222584667 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.1222584667
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.2316158961
Short name T734
Test name
Test status
Simulation time 147092923 ps
CPU time 7.72 seconds
Started Aug 11 04:52:54 PM PDT 24
Finished Aug 11 04:53:01 PM PDT 24
Peak memory 239608 kb
Host smart-cdc88025-6217-4f6e-9e40-c913d87016f0
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2316158961 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 1.alert_handler_csr_mem_rw_with_rand_reset.2316158961
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.2824353763
Short name T724
Test name
Test status
Simulation time 36513403 ps
CPU time 3.27 seconds
Started Aug 11 04:52:53 PM PDT 24
Finished Aug 11 04:52:57 PM PDT 24
Peak memory 236648 kb
Host smart-12ad8978-6c08-4493-b527-6e01aa12661e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2824353763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.2824353763
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.2076004527
Short name T814
Test name
Test status
Simulation time 9271289 ps
CPU time 1.49 seconds
Started Aug 11 04:52:45 PM PDT 24
Finished Aug 11 04:52:47 PM PDT 24
Peak memory 235616 kb
Host smart-00e58314-58cb-4b9b-a09c-f33f89845d5b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2076004527 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.2076004527
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.3117326625
Short name T781
Test name
Test status
Simulation time 1589562864 ps
CPU time 18.13 seconds
Started Aug 11 04:52:58 PM PDT 24
Finished Aug 11 04:53:17 PM PDT 24
Peak memory 248692 kb
Host smart-de09d9e0-9bda-4284-b286-ba0e73673fbf
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3117326625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_out
standing.3117326625
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.174760206
Short name T158
Test name
Test status
Simulation time 8107696902 ps
CPU time 669 seconds
Started Aug 11 04:52:39 PM PDT 24
Finished Aug 11 05:03:48 PM PDT 24
Peak memory 268900 kb
Host smart-79ecbf7c-e92c-4f53-97c2-195d71eb09ca
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=174760206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.174760206
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.889451806
Short name T729
Test name
Test status
Simulation time 1088574400 ps
CPU time 19.71 seconds
Started Aug 11 04:52:39 PM PDT 24
Finished Aug 11 04:52:59 PM PDT 24
Peak memory 248184 kb
Host smart-16eef6b2-0b82-4584-b644-35dee0a0b5cc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=889451806 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.889451806
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.366904783
Short name T773
Test name
Test status
Simulation time 234105756 ps
CPU time 8.19 seconds
Started Aug 11 04:52:54 PM PDT 24
Finished Aug 11 04:53:03 PM PDT 24
Peak memory 239832 kb
Host smart-d34b015d-713d-4d75-afe3-48dfaa2148b2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366904783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 10.alert_handler_csr_mem_rw_with_rand_reset.366904783
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.658623709
Short name T775
Test name
Test status
Simulation time 117749634 ps
CPU time 5.34 seconds
Started Aug 11 04:52:53 PM PDT 24
Finished Aug 11 04:52:58 PM PDT 24
Peak memory 240880 kb
Host smart-c8ec2912-e2c0-4b16-ad09-90fb276da110
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=658623709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.658623709
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.377784150
Short name T820
Test name
Test status
Simulation time 8939668 ps
CPU time 1.37 seconds
Started Aug 11 04:52:47 PM PDT 24
Finished Aug 11 04:52:48 PM PDT 24
Peak memory 236668 kb
Host smart-b5a34239-8e92-4d75-b6b7-c01a7021e89e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=377784150 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.377784150
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.826135490
Short name T752
Test name
Test status
Simulation time 175880442 ps
CPU time 28.7 seconds
Started Aug 11 04:52:54 PM PDT 24
Finished Aug 11 04:53:23 PM PDT 24
Peak memory 245828 kb
Host smart-eed990de-0702-43ab-aa25-fe08ce4472d2
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=826135490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_out
standing.826135490
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.3869026918
Short name T162
Test name
Test status
Simulation time 6270786199 ps
CPU time 492.48 seconds
Started Aug 11 04:52:50 PM PDT 24
Finished Aug 11 05:01:02 PM PDT 24
Peak memory 269028 kb
Host smart-4f9f235a-8785-40c7-b88d-01a6a3735874
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3869026918 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.3869026918
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.1218688208
Short name T829
Test name
Test status
Simulation time 740550130 ps
CPU time 13.07 seconds
Started Aug 11 04:52:51 PM PDT 24
Finished Aug 11 04:53:04 PM PDT 24
Peak memory 248428 kb
Host smart-d8d2764d-ca45-465f-bf05-3e0a24ea56e4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1218688208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.1218688208
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.3682591193
Short name T818
Test name
Test status
Simulation time 36650297 ps
CPU time 5.31 seconds
Started Aug 11 04:52:58 PM PDT 24
Finished Aug 11 04:53:03 PM PDT 24
Peak memory 256880 kb
Host smart-ed6f2488-735d-467c-8373-b56688c9b31a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3682591193 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.alert_handler_csr_mem_rw_with_rand_reset.3682591193
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.3179525481
Short name T719
Test name
Test status
Simulation time 2046891977 ps
CPU time 9.77 seconds
Started Aug 11 04:52:49 PM PDT 24
Finished Aug 11 04:52:59 PM PDT 24
Peak memory 237376 kb
Host smart-f5f81fb4-d268-4862-840b-3063551e9fc9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3179525481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.3179525481
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.2405173393
Short name T808
Test name
Test status
Simulation time 6472741 ps
CPU time 1.47 seconds
Started Aug 11 04:52:55 PM PDT 24
Finished Aug 11 04:52:56 PM PDT 24
Peak memory 237588 kb
Host smart-ac46b215-6f39-4c55-85bb-f0a185cd9aca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2405173393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.2405173393
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.2495597565
Short name T717
Test name
Test status
Simulation time 86128927 ps
CPU time 12.86 seconds
Started Aug 11 04:52:54 PM PDT 24
Finished Aug 11 04:53:08 PM PDT 24
Peak memory 240424 kb
Host smart-3899384f-6e19-4f01-96b8-a2f88e56a8a0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2495597565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_ou
tstanding.2495597565
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.1330404348
Short name T135
Test name
Test status
Simulation time 34243246717 ps
CPU time 389.33 seconds
Started Aug 11 04:52:47 PM PDT 24
Finished Aug 11 04:59:17 PM PDT 24
Peak memory 265536 kb
Host smart-14b003bf-b10c-4812-9bba-25fcf8b5cf4c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1330404348 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_err
ors.1330404348
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.3153336571
Short name T163
Test name
Test status
Simulation time 7746548209 ps
CPU time 492.63 seconds
Started Aug 11 04:52:54 PM PDT 24
Finished Aug 11 05:01:06 PM PDT 24
Peak memory 265592 kb
Host smart-5cd4e043-7fb4-4719-b60f-2b596b8e1e26
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3153336571 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.3153336571
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.671227655
Short name T711
Test name
Test status
Simulation time 416233178 ps
CPU time 8.29 seconds
Started Aug 11 04:52:52 PM PDT 24
Finished Aug 11 04:53:01 PM PDT 24
Peak memory 251040 kb
Host smart-26a2e306-2aa6-4607-9bbc-e9b1019e5e36
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=671227655 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.671227655
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.612848453
Short name T721
Test name
Test status
Simulation time 87793848 ps
CPU time 6.62 seconds
Started Aug 11 04:52:50 PM PDT 24
Finished Aug 11 04:52:56 PM PDT 24
Peak memory 240308 kb
Host smart-ecdb52d9-f371-4c12-9f69-91f052c8fb20
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=612848453 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 12.alert_handler_csr_mem_rw_with_rand_reset.612848453
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.2920126220
Short name T190
Test name
Test status
Simulation time 231238233 ps
CPU time 7.48 seconds
Started Aug 11 04:52:48 PM PDT 24
Finished Aug 11 04:52:56 PM PDT 24
Peak memory 237544 kb
Host smart-b14fbf58-f2cb-4877-b86b-1ff37d0f9f5f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2920126220 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.2920126220
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.2349438803
Short name T748
Test name
Test status
Simulation time 25386704 ps
CPU time 1.26 seconds
Started Aug 11 04:52:55 PM PDT 24
Finished Aug 11 04:52:57 PM PDT 24
Peak memory 235612 kb
Host smart-03622c4e-f583-4db4-b260-b12b94ea00af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2349438803 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.2349438803
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.2794677688
Short name T204
Test name
Test status
Simulation time 1790004580 ps
CPU time 38.71 seconds
Started Aug 11 04:52:53 PM PDT 24
Finished Aug 11 04:53:32 PM PDT 24
Peak memory 244876 kb
Host smart-df0b76b0-2324-461d-a3ae-5bc29d674eda
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2794677688 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_ou
tstanding.2794677688
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.2967154415
Short name T161
Test name
Test status
Simulation time 8297166998 ps
CPU time 653.01 seconds
Started Aug 11 04:52:51 PM PDT 24
Finished Aug 11 05:03:45 PM PDT 24
Peak memory 270552 kb
Host smart-db2936dc-658e-4f1f-8e52-c0cd24b6a8a8
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967154415 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.2967154415
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.299549174
Short name T819
Test name
Test status
Simulation time 4324823200 ps
CPU time 20.48 seconds
Started Aug 11 04:52:54 PM PDT 24
Finished Aug 11 04:53:15 PM PDT 24
Peak memory 254216 kb
Host smart-5cc1d76e-bddf-45cb-a5f1-568493edb8d7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=299549174 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.299549174
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.4266194857
Short name T207
Test name
Test status
Simulation time 201294458 ps
CPU time 3.2 seconds
Started Aug 11 04:52:52 PM PDT 24
Finished Aug 11 04:52:56 PM PDT 24
Peak memory 237448 kb
Host smart-b88e8e6f-ea00-4a23-aace-7e677a51ff84
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4266194857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.4266194857
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.3051942747
Short name T362
Test name
Test status
Simulation time 221275824 ps
CPU time 4.84 seconds
Started Aug 11 04:52:59 PM PDT 24
Finished Aug 11 04:53:04 PM PDT 24
Peak memory 240192 kb
Host smart-72d267a4-bf4a-44ea-80cd-f4273a44f328
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3051942747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 13.alert_handler_csr_mem_rw_with_rand_reset.3051942747
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.1838165874
Short name T822
Test name
Test status
Simulation time 126216019 ps
CPU time 11.45 seconds
Started Aug 11 04:52:58 PM PDT 24
Finished Aug 11 04:53:10 PM PDT 24
Peak memory 240524 kb
Host smart-ace3b6c1-4dbf-443a-a62d-d95010b239fc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1838165874 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.1838165874
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.110484153
Short name T765
Test name
Test status
Simulation time 12253766 ps
CPU time 1.48 seconds
Started Aug 11 04:52:54 PM PDT 24
Finished Aug 11 04:52:56 PM PDT 24
Peak memory 236432 kb
Host smart-7d76ec7f-3ad1-44cc-b40c-c5d8ee122025
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=110484153 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.110484153
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.4026887672
Short name T743
Test name
Test status
Simulation time 95369135 ps
CPU time 16.88 seconds
Started Aug 11 04:52:48 PM PDT 24
Finished Aug 11 04:53:05 PM PDT 24
Peak memory 240428 kb
Host smart-218fc1c1-abe4-4fee-94b1-0c786d4e3b1f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4026887672 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_ou
tstanding.4026887672
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.690220584
Short name T811
Test name
Test status
Simulation time 2299212711 ps
CPU time 157.88 seconds
Started Aug 11 04:52:56 PM PDT 24
Finished Aug 11 04:55:34 PM PDT 24
Peak memory 265416 kb
Host smart-7a4a88a5-44cc-43c5-8533-99aa32934dea
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=690220584 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_erro
rs.690220584
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.2285324382
Short name T157
Test name
Test status
Simulation time 51688789939 ps
CPU time 1098.02 seconds
Started Aug 11 04:52:49 PM PDT 24
Finished Aug 11 05:11:07 PM PDT 24
Peak memory 265500 kb
Host smart-5e1a6692-a15a-40aa-aa43-050cac6c394f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2285324382 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.2285324382
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.2169586441
Short name T821
Test name
Test status
Simulation time 160520014 ps
CPU time 6.05 seconds
Started Aug 11 04:52:49 PM PDT 24
Finished Aug 11 04:52:55 PM PDT 24
Peak memory 253476 kb
Host smart-d48ac0b3-0d55-4a42-98cb-142c3143b45e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2169586441 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.2169586441
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.1160214878
Short name T712
Test name
Test status
Simulation time 224935752 ps
CPU time 6.14 seconds
Started Aug 11 04:52:56 PM PDT 24
Finished Aug 11 04:53:03 PM PDT 24
Peak memory 240592 kb
Host smart-db5a9f54-4b0c-4938-8641-7ede8690e52b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1160214878 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 14.alert_handler_csr_mem_rw_with_rand_reset.1160214878
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.924533849
Short name T815
Test name
Test status
Simulation time 137600574 ps
CPU time 6.61 seconds
Started Aug 11 04:52:57 PM PDT 24
Finished Aug 11 04:53:03 PM PDT 24
Peak memory 240380 kb
Host smart-a88f8c62-76fc-4981-b371-94c39b27c48d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=924533849 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.924533849
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.2633341469
Short name T355
Test name
Test status
Simulation time 14094119 ps
CPU time 1.3 seconds
Started Aug 11 04:52:58 PM PDT 24
Finished Aug 11 04:53:00 PM PDT 24
Peak memory 236624 kb
Host smart-21bd174b-2eb0-4c16-af44-1f7c912f8a6e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2633341469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.2633341469
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.2121421351
Short name T191
Test name
Test status
Simulation time 1021706767 ps
CPU time 20.19 seconds
Started Aug 11 04:52:54 PM PDT 24
Finished Aug 11 04:53:14 PM PDT 24
Peak memory 245820 kb
Host smart-acaa5185-afa4-4452-8325-429ea8bf3fba
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2121421351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_ou
tstanding.2121421351
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.3692573726
Short name T147
Test name
Test status
Simulation time 2898507182 ps
CPU time 231.7 seconds
Started Aug 11 04:52:53 PM PDT 24
Finished Aug 11 04:56:45 PM PDT 24
Peak memory 265592 kb
Host smart-cf6ace54-331d-422f-b2f2-4e1049492f1a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3692573726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_err
ors.3692573726
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.4056996214
Short name T166
Test name
Test status
Simulation time 9304876363 ps
CPU time 739.39 seconds
Started Aug 11 04:52:59 PM PDT 24
Finished Aug 11 05:05:19 PM PDT 24
Peak memory 265424 kb
Host smart-6ca1e46f-56d0-41a7-aa44-ea273018787e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4056996214 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.4056996214
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.678042629
Short name T779
Test name
Test status
Simulation time 110569276 ps
CPU time 8.91 seconds
Started Aug 11 04:52:56 PM PDT 24
Finished Aug 11 04:53:05 PM PDT 24
Peak memory 248432 kb
Host smart-9e9d84c6-7ede-435e-b64c-65520baeaa75
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=678042629 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.678042629
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.3644013808
Short name T177
Test name
Test status
Simulation time 140802289 ps
CPU time 2.74 seconds
Started Aug 11 04:53:03 PM PDT 24
Finished Aug 11 04:53:06 PM PDT 24
Peak memory 236696 kb
Host smart-1c0db802-aa15-4dd7-8dd7-743ee6665362
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3644013808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.3644013808
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.85007004
Short name T786
Test name
Test status
Simulation time 158548810 ps
CPU time 4.67 seconds
Started Aug 11 04:52:54 PM PDT 24
Finished Aug 11 04:52:59 PM PDT 24
Peak memory 241068 kb
Host smart-9c1e19fd-9bf1-4c38-985b-1c9d62cce0f6
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85007004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 15.alert_handler_csr_mem_rw_with_rand_reset.85007004
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.4139550247
Short name T726
Test name
Test status
Simulation time 123991762 ps
CPU time 5.19 seconds
Started Aug 11 04:52:59 PM PDT 24
Finished Aug 11 04:53:05 PM PDT 24
Peak memory 236676 kb
Host smart-322d319a-3ecd-476d-8adc-ce44c17ec455
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4139550247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.4139550247
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.3625967981
Short name T806
Test name
Test status
Simulation time 508545429 ps
CPU time 22.01 seconds
Started Aug 11 04:52:59 PM PDT 24
Finished Aug 11 04:53:22 PM PDT 24
Peak memory 245688 kb
Host smart-34398609-be9d-4da5-adb0-115b0beb9641
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3625967981 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_ou
tstanding.3625967981
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.53317224
Short name T154
Test name
Test status
Simulation time 4863864819 ps
CPU time 420.61 seconds
Started Aug 11 04:53:01 PM PDT 24
Finished Aug 11 05:00:02 PM PDT 24
Peak memory 265884 kb
Host smart-6f510540-296f-45d8-981f-df7aef48787a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53317224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -
cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.53317224
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.3126665624
Short name T709
Test name
Test status
Simulation time 49590829 ps
CPU time 6.06 seconds
Started Aug 11 04:52:57 PM PDT 24
Finished Aug 11 04:53:03 PM PDT 24
Peak memory 254360 kb
Host smart-ffdd5c62-8140-4867-96c9-aeb240f8d17d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3126665624 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.3126665624
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.3662757530
Short name T800
Test name
Test status
Simulation time 263398098 ps
CPU time 5.28 seconds
Started Aug 11 04:52:59 PM PDT 24
Finished Aug 11 04:53:04 PM PDT 24
Peak memory 240188 kb
Host smart-bc6bc308-67d5-4b91-9d62-06398c67cc9f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3662757530 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 16.alert_handler_csr_mem_rw_with_rand_reset.3662757530
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.1069894204
Short name T768
Test name
Test status
Simulation time 71553435 ps
CPU time 5.31 seconds
Started Aug 11 04:52:59 PM PDT 24
Finished Aug 11 04:53:05 PM PDT 24
Peak memory 236684 kb
Host smart-135bf056-8c0b-40fd-b4f8-ae7dd2033d1b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1069894204 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.1069894204
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.1256151954
Short name T358
Test name
Test status
Simulation time 10265671 ps
CPU time 1.63 seconds
Started Aug 11 04:52:58 PM PDT 24
Finished Aug 11 04:52:59 PM PDT 24
Peak memory 237616 kb
Host smart-56ae5999-e024-4d4e-be51-706d0a96e006
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1256151954 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.1256151954
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.1454596325
Short name T723
Test name
Test status
Simulation time 688048616 ps
CPU time 26.43 seconds
Started Aug 11 04:52:59 PM PDT 24
Finished Aug 11 04:53:25 PM PDT 24
Peak memory 245788 kb
Host smart-0c0aa389-d01b-4903-a737-a8a768ce785d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1454596325 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_ou
tstanding.1454596325
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.3746203771
Short name T708
Test name
Test status
Simulation time 122688657 ps
CPU time 9.25 seconds
Started Aug 11 04:52:53 PM PDT 24
Finished Aug 11 04:53:03 PM PDT 24
Peak memory 254040 kb
Host smart-ed72b7fa-b6c3-498b-b1fd-4d48d57e0b95
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3746203771 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.3746203771
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.3334387167
Short name T264
Test name
Test status
Simulation time 92863724 ps
CPU time 2.68 seconds
Started Aug 11 04:52:56 PM PDT 24
Finished Aug 11 04:52:59 PM PDT 24
Peak memory 237872 kb
Host smart-9a47369a-6c8d-4fae-bba7-9e00c3386bce
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3334387167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.3334387167
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.1052285221
Short name T796
Test name
Test status
Simulation time 68008034 ps
CPU time 9.23 seconds
Started Aug 11 04:52:59 PM PDT 24
Finished Aug 11 04:53:08 PM PDT 24
Peak memory 256640 kb
Host smart-62f4a54f-d844-47b1-aa39-4b49fa611ddc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1052285221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 17.alert_handler_csr_mem_rw_with_rand_reset.1052285221
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.270486325
Short name T802
Test name
Test status
Simulation time 69481070 ps
CPU time 5.45 seconds
Started Aug 11 04:52:59 PM PDT 24
Finished Aug 11 04:53:04 PM PDT 24
Peak memory 237580 kb
Host smart-dcf08446-6678-4355-99fa-e7fc297af9d8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=270486325 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.270486325
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.4061359511
Short name T783
Test name
Test status
Simulation time 12568356 ps
CPU time 1.35 seconds
Started Aug 11 04:52:56 PM PDT 24
Finished Aug 11 04:52:58 PM PDT 24
Peak memory 236660 kb
Host smart-f7f39745-032d-4570-b16a-88c4abaf20d7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4061359511 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.4061359511
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.2347542842
Short name T741
Test name
Test status
Simulation time 173596065 ps
CPU time 24.16 seconds
Started Aug 11 04:52:57 PM PDT 24
Finished Aug 11 04:53:21 PM PDT 24
Peak memory 245796 kb
Host smart-3ac8ca6f-a4c9-45aa-8795-147e24833b3d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2347542842 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_ou
tstanding.2347542842
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.2313424526
Short name T827
Test name
Test status
Simulation time 3684799926 ps
CPU time 225.05 seconds
Started Aug 11 04:52:55 PM PDT 24
Finished Aug 11 04:56:40 PM PDT 24
Peak memory 265464 kb
Host smart-dc547753-338d-47f3-92a4-f18e53a0329f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2313424526 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_err
ors.2313424526
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.3160530442
Short name T794
Test name
Test status
Simulation time 26633623 ps
CPU time 3.86 seconds
Started Aug 11 04:52:54 PM PDT 24
Finished Aug 11 04:52:58 PM PDT 24
Peak memory 248404 kb
Host smart-37d80928-76c7-45d3-81dd-7601b71735a1
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3160530442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.3160530442
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.2171043958
Short name T780
Test name
Test status
Simulation time 38122202 ps
CPU time 7.34 seconds
Started Aug 11 04:53:01 PM PDT 24
Finished Aug 11 04:53:09 PM PDT 24
Peak memory 252920 kb
Host smart-574a5300-db4b-428e-9b81-213228001a9c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2171043958 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 18.alert_handler_csr_mem_rw_with_rand_reset.2171043958
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.3597056210
Short name T759
Test name
Test status
Simulation time 35571781 ps
CPU time 3.92 seconds
Started Aug 11 04:52:57 PM PDT 24
Finished Aug 11 04:53:01 PM PDT 24
Peak memory 240444 kb
Host smart-63fa9656-018a-4904-a9ac-864a73479b3c
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3597056210 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.3597056210
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.2251115448
Short name T756
Test name
Test status
Simulation time 10492149 ps
CPU time 1.61 seconds
Started Aug 11 04:52:56 PM PDT 24
Finished Aug 11 04:52:58 PM PDT 24
Peak memory 237544 kb
Host smart-ad290876-9cdb-4bab-a0b4-ea6ba04acd14
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2251115448 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.2251115448
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.2447651542
Short name T193
Test name
Test status
Simulation time 352132277 ps
CPU time 13.82 seconds
Started Aug 11 04:52:57 PM PDT 24
Finished Aug 11 04:53:11 PM PDT 24
Peak memory 244888 kb
Host smart-1214ac38-ba9b-4d93-820d-fb9aa2cd47dd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2447651542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_ou
tstanding.2447651542
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.4291675102
Short name T143
Test name
Test status
Simulation time 7099509722 ps
CPU time 227.23 seconds
Started Aug 11 04:52:56 PM PDT 24
Finished Aug 11 04:56:43 PM PDT 24
Peak memory 265592 kb
Host smart-fec58aa8-de08-4f89-bb42-4adb8bfffdba
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4291675102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_err
ors.4291675102
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.3525262993
Short name T707
Test name
Test status
Simulation time 337901977 ps
CPU time 10.2 seconds
Started Aug 11 04:53:00 PM PDT 24
Finished Aug 11 04:53:10 PM PDT 24
Peak memory 254312 kb
Host smart-3e5343fb-b7b2-41f0-b152-e08ed1327e7b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3525262993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.3525262993
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.2018600508
Short name T716
Test name
Test status
Simulation time 79928185 ps
CPU time 7.02 seconds
Started Aug 11 04:53:04 PM PDT 24
Finished Aug 11 04:53:11 PM PDT 24
Peak memory 240600 kb
Host smart-eaa4c0b8-6032-4155-a358-46ef603119f9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2018600508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 19.alert_handler_csr_mem_rw_with_rand_reset.2018600508
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.664859133
Short name T805
Test name
Test status
Simulation time 366230872 ps
CPU time 7.01 seconds
Started Aug 11 04:53:07 PM PDT 24
Finished Aug 11 04:53:15 PM PDT 24
Peak memory 235720 kb
Host smart-39a38fe4-27c3-4c7d-b8ce-7c210a97903e
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=664859133 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.664859133
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.3696716784
Short name T740
Test name
Test status
Simulation time 7865516 ps
CPU time 1.48 seconds
Started Aug 11 04:53:07 PM PDT 24
Finished Aug 11 04:53:09 PM PDT 24
Peak memory 234592 kb
Host smart-038ec902-2444-43f4-8841-492cb2cd54b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3696716784 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.3696716784
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.1745795342
Short name T722
Test name
Test status
Simulation time 167251478 ps
CPU time 22.21 seconds
Started Aug 11 04:53:06 PM PDT 24
Finished Aug 11 04:53:29 PM PDT 24
Peak memory 245776 kb
Host smart-c08ca9c2-d9bb-4b39-ad63-03c8eeb7dce1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1745795342 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_ou
tstanding.1745795342
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.725627267
Short name T144
Test name
Test status
Simulation time 28752868754 ps
CPU time 559.48 seconds
Started Aug 11 04:52:57 PM PDT 24
Finished Aug 11 05:02:17 PM PDT 24
Peak memory 271356 kb
Host smart-1e5e639d-9515-4075-bf02-b51bcdfad1c4
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725627267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.725627267
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.1185349477
Short name T736
Test name
Test status
Simulation time 1067985594 ps
CPU time 22 seconds
Started Aug 11 04:52:59 PM PDT 24
Finished Aug 11 04:53:21 PM PDT 24
Peak memory 248868 kb
Host smart-0a97ee20-8b99-4936-b03e-de606f79405e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1185349477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.1185349477
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.2220229899
Short name T788
Test name
Test status
Simulation time 110321143 ps
CPU time 2.88 seconds
Started Aug 11 04:53:00 PM PDT 24
Finished Aug 11 04:53:03 PM PDT 24
Peak memory 237556 kb
Host smart-8f8b58c1-9889-4ec2-8f7c-50e50c127fdd
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2220229899 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.2220229899
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.2161025922
Short name T728
Test name
Test status
Simulation time 2226938044 ps
CPU time 166.27 seconds
Started Aug 11 04:52:52 PM PDT 24
Finished Aug 11 04:55:39 PM PDT 24
Peak memory 240492 kb
Host smart-ae381f6f-142f-4305-ad51-2478ae042954
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2161025922 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.2161025922
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.925147925
Short name T835
Test name
Test status
Simulation time 2913202530 ps
CPU time 232.82 seconds
Started Aug 11 04:52:51 PM PDT 24
Finished Aug 11 04:56:44 PM PDT 24
Peak memory 237636 kb
Host smart-26614bde-1e43-4ce6-a47b-eaeb3555da6c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=925147925 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.925147925
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.735781628
Short name T731
Test name
Test status
Simulation time 356540990 ps
CPU time 8.26 seconds
Started Aug 11 04:52:44 PM PDT 24
Finished Aug 11 04:52:53 PM PDT 24
Peak memory 249068 kb
Host smart-fac2f129-39af-4606-b051-c6c5d1c2fb03
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=735781628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.735781628
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.2997946522
Short name T826
Test name
Test status
Simulation time 43773164 ps
CPU time 3.69 seconds
Started Aug 11 04:52:44 PM PDT 24
Finished Aug 11 04:52:47 PM PDT 24
Peak memory 240408 kb
Host smart-2fe0db75-c77f-473e-99f4-f777e32e3331
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2997946522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.alert_handler_csr_mem_rw_with_rand_reset.2997946522
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.1692574636
Short name T713
Test name
Test status
Simulation time 22438093 ps
CPU time 4.56 seconds
Started Aug 11 04:52:50 PM PDT 24
Finished Aug 11 04:52:55 PM PDT 24
Peak memory 237580 kb
Host smart-67b5f86f-d744-4582-8977-5c6ced19d636
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1692574636 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.1692574636
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.4081699972
Short name T830
Test name
Test status
Simulation time 19623193 ps
CPU time 1.44 seconds
Started Aug 11 04:52:47 PM PDT 24
Finished Aug 11 04:52:49 PM PDT 24
Peak memory 236604 kb
Host smart-5f77e836-5f58-4de1-9fda-4ef9d7c1d40a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4081699972 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.4081699972
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.3877893223
Short name T750
Test name
Test status
Simulation time 692095727 ps
CPU time 53.46 seconds
Started Aug 11 04:52:44 PM PDT 24
Finished Aug 11 04:53:37 PM PDT 24
Peak memory 245844 kb
Host smart-b0e1f436-2b53-4de7-a651-d0107543aff3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3877893223 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_out
standing.3877893223
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.2564547645
Short name T141
Test name
Test status
Simulation time 4463169723 ps
CPU time 336.36 seconds
Started Aug 11 04:52:48 PM PDT 24
Finished Aug 11 04:58:24 PM PDT 24
Peak memory 265660 kb
Host smart-0aa1ef60-7e1c-4ef8-b1d2-eb68ee217e54
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2564547645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_erro
rs.2564547645
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.3552850714
Short name T828
Test name
Test status
Simulation time 523157861 ps
CPU time 20.81 seconds
Started Aug 11 04:52:42 PM PDT 24
Finished Aug 11 04:53:03 PM PDT 24
Peak memory 248220 kb
Host smart-5fdb562c-f621-418e-9610-98cb951e0a36
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3552850714 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.3552850714
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.675134047
Short name T824
Test name
Test status
Simulation time 9744757 ps
CPU time 1.57 seconds
Started Aug 11 04:53:01 PM PDT 24
Finished Aug 11 04:53:03 PM PDT 24
Peak memory 236708 kb
Host smart-ef43ef27-027d-4a6c-8460-cf4c1ce5643f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=675134047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.675134047
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.1152754108
Short name T746
Test name
Test status
Simulation time 19068012 ps
CPU time 1.44 seconds
Started Aug 11 04:53:03 PM PDT 24
Finished Aug 11 04:53:04 PM PDT 24
Peak memory 236636 kb
Host smart-f97af55d-55a7-4baa-9fa8-a5c334276e06
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1152754108 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.1152754108
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.1637109155
Short name T733
Test name
Test status
Simulation time 13351119 ps
CPU time 1.82 seconds
Started Aug 11 04:53:38 PM PDT 24
Finished Aug 11 04:53:39 PM PDT 24
Peak memory 236644 kb
Host smart-4a3a85a5-1299-4dc1-9c23-e3b88f182bb9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1637109155 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.1637109155
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.2919498617
Short name T825
Test name
Test status
Simulation time 7783406 ps
CPU time 1.62 seconds
Started Aug 11 04:53:05 PM PDT 24
Finished Aug 11 04:53:07 PM PDT 24
Peak memory 237916 kb
Host smart-8b9cc814-78c1-4416-b8a5-d6324796e841
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2919498617 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.2919498617
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.3017860713
Short name T832
Test name
Test status
Simulation time 11148355 ps
CPU time 1.56 seconds
Started Aug 11 04:52:59 PM PDT 24
Finished Aug 11 04:53:01 PM PDT 24
Peak memory 237588 kb
Host smart-5d8eee65-b39a-4c35-a257-ee287f98c34b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3017860713 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.3017860713
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.4038351342
Short name T767
Test name
Test status
Simulation time 15270266 ps
CPU time 1.64 seconds
Started Aug 11 04:52:59 PM PDT 24
Finished Aug 11 04:53:01 PM PDT 24
Peak memory 237608 kb
Host smart-119b19e7-42bb-40d8-b7cb-717a7848798b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4038351342 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.4038351342
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.4276695791
Short name T749
Test name
Test status
Simulation time 17664918 ps
CPU time 1.45 seconds
Started Aug 11 04:53:05 PM PDT 24
Finished Aug 11 04:53:07 PM PDT 24
Peak memory 237528 kb
Host smart-ce0f9a90-f7a4-4651-89aa-beab57161ea3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4276695791 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.4276695791
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.3153189487
Short name T797
Test name
Test status
Simulation time 11772167 ps
CPU time 1.45 seconds
Started Aug 11 04:53:07 PM PDT 24
Finished Aug 11 04:53:09 PM PDT 24
Peak memory 235816 kb
Host smart-77bc045d-fe41-4857-b8d0-bad7ef5b688c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3153189487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.3153189487
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.2190920154
Short name T745
Test name
Test status
Simulation time 10727927 ps
CPU time 1.33 seconds
Started Aug 11 04:53:03 PM PDT 24
Finished Aug 11 04:53:04 PM PDT 24
Peak memory 236704 kb
Host smart-fd4420ab-b2e5-48a2-be1e-37e2346848de
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2190920154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.2190920154
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.3361733824
Short name T361
Test name
Test status
Simulation time 6801821 ps
CPU time 1.45 seconds
Started Aug 11 04:52:58 PM PDT 24
Finished Aug 11 04:53:00 PM PDT 24
Peak memory 237520 kb
Host smart-04ed686d-85c4-4c8b-a751-ebcb12d3dbda
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3361733824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.3361733824
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.492781403
Short name T761
Test name
Test status
Simulation time 3309635653 ps
CPU time 230.13 seconds
Started Aug 11 04:52:43 PM PDT 24
Finished Aug 11 04:56:33 PM PDT 24
Peak memory 240684 kb
Host smart-5719b4e8-5883-4ccb-a625-0510512e6b1c
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=492781403 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.492781403
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.1488501326
Short name T764
Test name
Test status
Simulation time 840325985 ps
CPU time 124.01 seconds
Started Aug 11 04:52:54 PM PDT 24
Finished Aug 11 04:54:58 PM PDT 24
Peak memory 237904 kb
Host smart-cae428e2-d10d-4659-94ea-fe465230e42c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1488501326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.1488501326
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.3902848680
Short name T738
Test name
Test status
Simulation time 494751096 ps
CPU time 10.06 seconds
Started Aug 11 04:52:42 PM PDT 24
Finished Aug 11 04:52:52 PM PDT 24
Peak memory 249116 kb
Host smart-1d0d1046-1f33-4e5a-ab5d-8d3bab52697c
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3902848680 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.3902848680
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.3017539992
Short name T812
Test name
Test status
Simulation time 817005253 ps
CPU time 15.91 seconds
Started Aug 11 04:52:45 PM PDT 24
Finished Aug 11 04:53:01 PM PDT 24
Peak memory 251780 kb
Host smart-3dbbad10-5128-4a94-bbac-f98a008899f2
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3017539992 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.alert_handler_csr_mem_rw_with_rand_reset.3017539992
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.1676272432
Short name T784
Test name
Test status
Simulation time 250023745 ps
CPU time 10.27 seconds
Started Aug 11 04:52:50 PM PDT 24
Finished Aug 11 04:53:00 PM PDT 24
Peak memory 237540 kb
Host smart-5cf475ad-5956-4249-b43a-c145b3c4a7ed
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1676272432 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.1676272432
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.1773070749
Short name T757
Test name
Test status
Simulation time 11439363 ps
CPU time 1.3 seconds
Started Aug 11 04:52:43 PM PDT 24
Finished Aug 11 04:52:45 PM PDT 24
Peak memory 235704 kb
Host smart-f2ea5104-79c7-492e-a103-ce7a0fb0cac8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1773070749 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.1773070749
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.2253254659
Short name T813
Test name
Test status
Simulation time 2695412324 ps
CPU time 19.77 seconds
Started Aug 11 04:52:50 PM PDT 24
Finished Aug 11 04:53:11 PM PDT 24
Peak memory 244788 kb
Host smart-b2418d56-fd8d-4e33-8ae8-e61d5ab305fc
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2253254659 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_out
standing.2253254659
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.3810215823
Short name T714
Test name
Test status
Simulation time 1266981741 ps
CPU time 21.7 seconds
Started Aug 11 04:52:47 PM PDT 24
Finished Aug 11 04:53:09 PM PDT 24
Peak memory 254544 kb
Host smart-a8edc92f-364b-493b-b737-5d41061878f8
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3810215823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.3810215823
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.4289950781
Short name T766
Test name
Test status
Simulation time 17650151 ps
CPU time 1.42 seconds
Started Aug 11 04:53:01 PM PDT 24
Finished Aug 11 04:53:02 PM PDT 24
Peak memory 237600 kb
Host smart-68c35990-7659-4b3f-99e0-4ad4f089a4cf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4289950781 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.4289950781
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.1814854998
Short name T769
Test name
Test status
Simulation time 19272917 ps
CPU time 1.58 seconds
Started Aug 11 04:53:00 PM PDT 24
Finished Aug 11 04:53:02 PM PDT 24
Peak memory 236600 kb
Host smart-9b302cf9-1bac-4eeb-86c3-0b778282b609
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1814854998 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.1814854998
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.379084158
Short name T760
Test name
Test status
Simulation time 8392091 ps
CPU time 1.69 seconds
Started Aug 11 04:53:00 PM PDT 24
Finished Aug 11 04:53:01 PM PDT 24
Peak memory 237528 kb
Host smart-fe120cd8-16e0-4c37-8a15-2394d1f9123a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=379084158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.379084158
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.3489004530
Short name T758
Test name
Test status
Simulation time 15279485 ps
CPU time 1.39 seconds
Started Aug 11 04:53:02 PM PDT 24
Finished Aug 11 04:53:03 PM PDT 24
Peak memory 237564 kb
Host smart-5ca64259-707f-475e-bdd1-2811386aaf96
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3489004530 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.3489004530
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.1580327840
Short name T776
Test name
Test status
Simulation time 9693658 ps
CPU time 1.71 seconds
Started Aug 11 04:53:00 PM PDT 24
Finished Aug 11 04:53:02 PM PDT 24
Peak memory 237592 kb
Host smart-92d978f7-c2d0-4798-a18f-361a50e5e067
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1580327840 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.1580327840
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.3517515860
Short name T782
Test name
Test status
Simulation time 9011172 ps
CPU time 1.56 seconds
Started Aug 11 04:53:07 PM PDT 24
Finished Aug 11 04:53:09 PM PDT 24
Peak memory 237048 kb
Host smart-c2daecea-11a5-47c1-9404-9c7e4e889261
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3517515860 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.3517515860
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.55589408
Short name T792
Test name
Test status
Simulation time 20664815 ps
CPU time 1.32 seconds
Started Aug 11 04:53:07 PM PDT 24
Finished Aug 11 04:53:09 PM PDT 24
Peak memory 237100 kb
Host smart-7c0c8863-83f2-4aa1-93c8-919514110808
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=55589408 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.55589408
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.2262223913
Short name T804
Test name
Test status
Simulation time 98179270 ps
CPU time 1.47 seconds
Started Aug 11 04:53:05 PM PDT 24
Finished Aug 11 04:53:07 PM PDT 24
Peak memory 236488 kb
Host smart-56a8d291-0b7d-4df7-8286-2b4766809c94
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2262223913 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.2262223913
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.99862473
Short name T357
Test name
Test status
Simulation time 9674197 ps
CPU time 1.7 seconds
Started Aug 11 04:52:57 PM PDT 24
Finished Aug 11 04:52:59 PM PDT 24
Peak memory 237532 kb
Host smart-147b6142-43b3-480a-87a3-7e966896783b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=99862473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.99862473
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.2494933206
Short name T755
Test name
Test status
Simulation time 6285110037 ps
CPU time 341.41 seconds
Started Aug 11 04:52:44 PM PDT 24
Finished Aug 11 04:58:26 PM PDT 24
Peak memory 240672 kb
Host smart-dc888071-155e-4e81-b0b6-a0a51ba50759
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2494933206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.2494933206
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.3557109606
Short name T770
Test name
Test status
Simulation time 16795547339 ps
CPU time 198.64 seconds
Started Aug 11 04:52:55 PM PDT 24
Finished Aug 11 04:56:13 PM PDT 24
Peak memory 236796 kb
Host smart-24e981e4-ceda-4c87-964e-e4d7f133e24c
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3557109606 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.3557109606
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.245650014
Short name T249
Test name
Test status
Simulation time 432157305 ps
CPU time 9.2 seconds
Started Aug 11 04:52:43 PM PDT 24
Finished Aug 11 04:52:52 PM PDT 24
Peak memory 248660 kb
Host smart-84ab22f2-981d-4e55-b5b2-6c4975259f55
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=245650014 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.245650014
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.659368455
Short name T785
Test name
Test status
Simulation time 304428752 ps
CPU time 6.17 seconds
Started Aug 11 04:52:42 PM PDT 24
Finished Aug 11 04:52:48 PM PDT 24
Peak memory 240264 kb
Host smart-4ec81e66-e749-48a0-8f74-45e8fbaf86fb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=659368455 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 4.alert_handler_csr_mem_rw_with_rand_reset.659368455
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.1670716088
Short name T793
Test name
Test status
Simulation time 186154519 ps
CPU time 8.19 seconds
Started Aug 11 04:52:50 PM PDT 24
Finished Aug 11 04:52:59 PM PDT 24
Peak memory 236648 kb
Host smart-f0a3faa2-b6a2-4e88-86d3-a603298d2ea1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1670716088 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.1670716088
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.4186542493
Short name T742
Test name
Test status
Simulation time 14653463 ps
CPU time 1.5 seconds
Started Aug 11 04:52:53 PM PDT 24
Finished Aug 11 04:52:55 PM PDT 24
Peak memory 236748 kb
Host smart-ddadcb19-d0de-44be-aa75-2c87de9ddc91
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4186542493 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.4186542493
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.1040715380
Short name T810
Test name
Test status
Simulation time 1165537950 ps
CPU time 25.61 seconds
Started Aug 11 04:52:45 PM PDT 24
Finished Aug 11 04:53:10 PM PDT 24
Peak memory 240468 kb
Host smart-2b1a2781-48b1-4b67-a4f0-e4f49b908cb1
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1040715380 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_out
standing.1040715380
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.2434194138
Short name T146
Test name
Test status
Simulation time 6122691964 ps
CPU time 222.21 seconds
Started Aug 11 04:52:43 PM PDT 24
Finished Aug 11 04:56:25 PM PDT 24
Peak memory 265532 kb
Host smart-d3279a72-ac19-450f-ae2c-232eeccc44ad
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2434194138 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_erro
rs.2434194138
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.4248046742
Short name T149
Test name
Test status
Simulation time 14046564904 ps
CPU time 1129.52 seconds
Started Aug 11 04:52:49 PM PDT 24
Finished Aug 11 05:11:39 PM PDT 24
Peak memory 265484 kb
Host smart-0b8a52a4-0b84-47b4-93b6-cfd7046706b7
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4248046742 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.4248046742
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.141141244
Short name T727
Test name
Test status
Simulation time 362794722 ps
CPU time 7.88 seconds
Started Aug 11 04:52:43 PM PDT 24
Finished Aug 11 04:52:51 PM PDT 24
Peak memory 249888 kb
Host smart-5fc95f44-98db-48ab-a04a-22dbb00bd684
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=141141244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.141141244
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.3127776473
Short name T823
Test name
Test status
Simulation time 7793169 ps
CPU time 1.53 seconds
Started Aug 11 04:52:59 PM PDT 24
Finished Aug 11 04:53:00 PM PDT 24
Peak memory 236624 kb
Host smart-b84676a0-5243-40aa-b8dd-f75bacc8df4c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3127776473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.3127776473
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.3503944247
Short name T356
Test name
Test status
Simulation time 21111754 ps
CPU time 1.43 seconds
Started Aug 11 04:52:59 PM PDT 24
Finished Aug 11 04:53:01 PM PDT 24
Peak memory 236720 kb
Host smart-1f0e1790-b210-4849-a0d9-c14aa5a3334d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3503944247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.3503944247
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.3632940580
Short name T771
Test name
Test status
Simulation time 6435054 ps
CPU time 1.35 seconds
Started Aug 11 04:53:07 PM PDT 24
Finished Aug 11 04:53:09 PM PDT 24
Peak memory 236160 kb
Host smart-5115e7d7-6661-4829-8d89-3dd44598bb2e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3632940580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.3632940580
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.2389806747
Short name T809
Test name
Test status
Simulation time 13954689 ps
CPU time 1.36 seconds
Started Aug 11 04:53:05 PM PDT 24
Finished Aug 11 04:53:07 PM PDT 24
Peak memory 237552 kb
Host smart-67f9524a-9059-4c5f-a5fa-a186bcb9c653
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2389806747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.2389806747
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.2875711899
Short name T799
Test name
Test status
Simulation time 9370977 ps
CPU time 1.33 seconds
Started Aug 11 04:53:04 PM PDT 24
Finished Aug 11 04:53:06 PM PDT 24
Peak memory 236704 kb
Host smart-a4304b7f-919c-44f0-b563-9161e2488c95
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2875711899 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.2875711899
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.2534686314
Short name T173
Test name
Test status
Simulation time 7262272 ps
CPU time 1.52 seconds
Started Aug 11 04:53:05 PM PDT 24
Finished Aug 11 04:53:07 PM PDT 24
Peak memory 235560 kb
Host smart-289b2b2b-bd1e-4bea-9af4-ed23adf7ba9d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2534686314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.2534686314
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.3348998511
Short name T774
Test name
Test status
Simulation time 10849159 ps
CPU time 1.48 seconds
Started Aug 11 04:53:00 PM PDT 24
Finished Aug 11 04:53:02 PM PDT 24
Peak memory 235688 kb
Host smart-f030429f-9f3f-4de4-81f8-0f989d9ba5c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3348998511 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.3348998511
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.3217003066
Short name T174
Test name
Test status
Simulation time 13751868 ps
CPU time 1.32 seconds
Started Aug 11 04:53:01 PM PDT 24
Finished Aug 11 04:53:03 PM PDT 24
Peak memory 236672 kb
Host smart-a6adeb69-5e2e-496f-885b-5a8d598d2c23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3217003066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.3217003066
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.1355641092
Short name T834
Test name
Test status
Simulation time 15882714 ps
CPU time 1.68 seconds
Started Aug 11 04:52:58 PM PDT 24
Finished Aug 11 04:53:00 PM PDT 24
Peak memory 237528 kb
Host smart-bf8736dc-9177-4647-981c-e50a5a49aa7e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1355641092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.1355641092
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.2500910758
Short name T778
Test name
Test status
Simulation time 6763532 ps
CPU time 1.54 seconds
Started Aug 11 04:53:02 PM PDT 24
Finished Aug 11 04:53:04 PM PDT 24
Peak memory 237568 kb
Host smart-9bf2cd9b-dec2-44a2-bf55-abcbea25ca80
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2500910758 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.2500910758
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.857740221
Short name T798
Test name
Test status
Simulation time 50166226 ps
CPU time 4.47 seconds
Started Aug 11 04:52:42 PM PDT 24
Finished Aug 11 04:52:46 PM PDT 24
Peak memory 251348 kb
Host smart-c2902ba2-5435-4810-bbc6-eae0b5e7e049
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=857740221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 5.alert_handler_csr_mem_rw_with_rand_reset.857740221
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.2960781496
Short name T789
Test name
Test status
Simulation time 246529830 ps
CPU time 6.05 seconds
Started Aug 11 04:52:51 PM PDT 24
Finished Aug 11 04:52:57 PM PDT 24
Peak memory 237508 kb
Host smart-2a1d27cc-3db6-4a52-b02f-6ccf20e77e17
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2960781496 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.2960781496
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.2370294483
Short name T175
Test name
Test status
Simulation time 11382504 ps
CPU time 1.33 seconds
Started Aug 11 04:52:55 PM PDT 24
Finished Aug 11 04:52:56 PM PDT 24
Peak memory 236704 kb
Host smart-b38768c7-d003-4b77-bc27-701ef8e99d61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2370294483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.2370294483
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.134701438
Short name T205
Test name
Test status
Simulation time 1047268693 ps
CPU time 36.21 seconds
Started Aug 11 04:52:48 PM PDT 24
Finished Aug 11 04:53:25 PM PDT 24
Peak memory 244884 kb
Host smart-064e144a-f4cd-49d8-b2b5-79acba466f53
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=134701438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_outs
tanding.134701438
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.2279279810
Short name T136
Test name
Test status
Simulation time 8158129061 ps
CPU time 152.82 seconds
Started Aug 11 04:52:51 PM PDT 24
Finished Aug 11 04:55:24 PM PDT 24
Peak memory 268372 kb
Host smart-5c7d73d7-d22d-4b52-bf63-4d039c97db87
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2279279810 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_erro
rs.2279279810
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.2092274451
Short name T803
Test name
Test status
Simulation time 62171009 ps
CPU time 9.12 seconds
Started Aug 11 04:52:45 PM PDT 24
Finished Aug 11 04:52:54 PM PDT 24
Peak memory 248732 kb
Host smart-ef85da05-c52b-4be8-a0d4-12e568d1902f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2092274451 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.2092274451
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.2525276962
Short name T817
Test name
Test status
Simulation time 155164955 ps
CPU time 13.41 seconds
Started Aug 11 04:52:50 PM PDT 24
Finished Aug 11 04:53:04 PM PDT 24
Peak memory 252100 kb
Host smart-8829ce76-a25f-4da8-ac60-c9c71a764356
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2525276962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.alert_handler_csr_mem_rw_with_rand_reset.2525276962
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.3387630635
Short name T710
Test name
Test status
Simulation time 266049202 ps
CPU time 6.11 seconds
Started Aug 11 04:52:48 PM PDT 24
Finished Aug 11 04:52:54 PM PDT 24
Peak memory 237576 kb
Host smart-5345edf5-edec-41fd-8e1f-c2a3c3d10186
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3387630635 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.3387630635
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.2218100313
Short name T791
Test name
Test status
Simulation time 11077792 ps
CPU time 1.41 seconds
Started Aug 11 04:52:53 PM PDT 24
Finished Aug 11 04:52:55 PM PDT 24
Peak memory 236700 kb
Host smart-4174b5e6-7cd6-4ffa-9baa-3cc67d909c97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2218100313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.2218100313
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.1661536396
Short name T751
Test name
Test status
Simulation time 343029341 ps
CPU time 28.64 seconds
Started Aug 11 04:52:48 PM PDT 24
Finished Aug 11 04:53:16 PM PDT 24
Peak memory 244832 kb
Host smart-559b3ef2-ed15-45dd-9741-5c6de309514c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1661536396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_out
standing.1661536396
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.1690966098
Short name T807
Test name
Test status
Simulation time 935595813 ps
CPU time 98.05 seconds
Started Aug 11 04:52:52 PM PDT 24
Finished Aug 11 04:54:31 PM PDT 24
Peak memory 257024 kb
Host smart-ff0fbf35-edbb-4c76-9c6f-c6d481774dd7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1690966098 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_erro
rs.1690966098
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.2899780192
Short name T715
Test name
Test status
Simulation time 205309981 ps
CPU time 12.55 seconds
Started Aug 11 04:52:44 PM PDT 24
Finished Aug 11 04:52:56 PM PDT 24
Peak memory 248656 kb
Host smart-ec207db8-1b68-4f79-97ec-7a6555d16c03
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2899780192 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.2899780192
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.3592042810
Short name T187
Test name
Test status
Simulation time 181206876 ps
CPU time 4.35 seconds
Started Aug 11 04:52:56 PM PDT 24
Finished Aug 11 04:53:01 PM PDT 24
Peak memory 238600 kb
Host smart-d8b9d8a4-2972-4f34-a664-70e7645b67a6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3592042810 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.3592042810
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.3404057176
Short name T735
Test name
Test status
Simulation time 64472554 ps
CPU time 10.66 seconds
Started Aug 11 04:52:51 PM PDT 24
Finished Aug 11 04:53:02 PM PDT 24
Peak memory 250864 kb
Host smart-aa63d480-556a-4d09-bd36-7d86fd5cba31
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3404057176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 7.alert_handler_csr_mem_rw_with_rand_reset.3404057176
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.1015656156
Short name T732
Test name
Test status
Simulation time 70079480 ps
CPU time 5.76 seconds
Started Aug 11 04:52:51 PM PDT 24
Finished Aug 11 04:52:57 PM PDT 24
Peak memory 237568 kb
Host smart-9ff5d129-fc03-4bf3-a67e-d74c7b873cc9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1015656156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.1015656156
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.2713355750
Short name T772
Test name
Test status
Simulation time 9456091 ps
CPU time 1.31 seconds
Started Aug 11 04:52:56 PM PDT 24
Finished Aug 11 04:52:58 PM PDT 24
Peak memory 235936 kb
Host smart-61f113d7-71fc-45de-9d85-c231ce9f4011
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2713355750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.2713355750
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.1745421878
Short name T831
Test name
Test status
Simulation time 656458558 ps
CPU time 44.81 seconds
Started Aug 11 04:52:48 PM PDT 24
Finished Aug 11 04:53:33 PM PDT 24
Peak memory 248784 kb
Host smart-c89d3bf7-5164-42ff-ad82-981b9cb68482
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1745421878 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_out
standing.1745421878
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.1660871862
Short name T725
Test name
Test status
Simulation time 72299459 ps
CPU time 8.21 seconds
Started Aug 11 04:52:53 PM PDT 24
Finished Aug 11 04:53:01 PM PDT 24
Peak memory 247656 kb
Host smart-4fcde929-f6d2-4f16-ac0d-ccb94420f485
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1660871862 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.1660871862
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.3134688417
Short name T720
Test name
Test status
Simulation time 52330022 ps
CPU time 9.38 seconds
Started Aug 11 04:53:01 PM PDT 24
Finished Aug 11 04:53:10 PM PDT 24
Peak memory 254736 kb
Host smart-2a68eeb9-496b-4e96-8fa4-a0bd42b0468e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3134688417 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.alert_handler_csr_mem_rw_with_rand_reset.3134688417
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.2845453269
Short name T777
Test name
Test status
Simulation time 206383026 ps
CPU time 8.19 seconds
Started Aug 11 04:52:49 PM PDT 24
Finished Aug 11 04:52:58 PM PDT 24
Peak memory 237580 kb
Host smart-c6e70217-8f41-49a9-b42e-ea924cfdf9e0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2845453269 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.2845453269
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.361410876
Short name T747
Test name
Test status
Simulation time 12252364 ps
CPU time 1.34 seconds
Started Aug 11 04:52:54 PM PDT 24
Finished Aug 11 04:52:55 PM PDT 24
Peak memory 236696 kb
Host smart-04999055-5a26-430d-aafb-594a7558cf29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=361410876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.361410876
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.177600414
Short name T795
Test name
Test status
Simulation time 546579123 ps
CPU time 40.6 seconds
Started Aug 11 04:52:48 PM PDT 24
Finished Aug 11 04:53:29 PM PDT 24
Peak memory 244908 kb
Host smart-1050a8b1-e819-4d9b-a277-bd745ea00962
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=177600414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_outs
tanding.177600414
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.3600409810
Short name T152
Test name
Test status
Simulation time 6210677979 ps
CPU time 213.22 seconds
Started Aug 11 04:52:54 PM PDT 24
Finished Aug 11 04:56:28 PM PDT 24
Peak memory 265428 kb
Host smart-ba3a1714-fe52-4155-bcf4-f33723d4d780
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3600409810 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_erro
rs.3600409810
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.2207800055
Short name T801
Test name
Test status
Simulation time 9293533348 ps
CPU time 363.62 seconds
Started Aug 11 04:52:54 PM PDT 24
Finished Aug 11 04:58:58 PM PDT 24
Peak memory 265488 kb
Host smart-3646225a-73c9-4dbd-9a58-cca045a79979
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2207800055 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.2207800055
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.1503261879
Short name T753
Test name
Test status
Simulation time 226635374 ps
CPU time 11.22 seconds
Started Aug 11 04:52:56 PM PDT 24
Finished Aug 11 04:53:08 PM PDT 24
Peak memory 247408 kb
Host smart-955f10db-813b-4c5e-8bfa-e67074db8033
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1503261879 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.1503261879
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.1195765683
Short name T836
Test name
Test status
Simulation time 197747425 ps
CPU time 8.3 seconds
Started Aug 11 04:52:54 PM PDT 24
Finished Aug 11 04:53:03 PM PDT 24
Peak memory 240476 kb
Host smart-43b5401f-aa71-47d1-a2f5-35ae7e6dda0b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1195765683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.alert_handler_csr_mem_rw_with_rand_reset.1195765683
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.1946327060
Short name T816
Test name
Test status
Simulation time 136077356 ps
CPU time 9.67 seconds
Started Aug 11 04:52:57 PM PDT 24
Finished Aug 11 04:53:07 PM PDT 24
Peak memory 240512 kb
Host smart-ab82d92e-3b32-44b3-96f7-3ce52f32fee6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1946327060 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.1946327060
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.2934736634
Short name T730
Test name
Test status
Simulation time 23432533 ps
CPU time 1.34 seconds
Started Aug 11 04:52:54 PM PDT 24
Finished Aug 11 04:52:55 PM PDT 24
Peak memory 236688 kb
Host smart-ac7617df-9aea-4dac-af0b-dc49120399c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2934736634 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.2934736634
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.1835554242
Short name T203
Test name
Test status
Simulation time 134410996 ps
CPU time 16.18 seconds
Started Aug 11 04:52:57 PM PDT 24
Finished Aug 11 04:53:14 PM PDT 24
Peak memory 244896 kb
Host smart-ece8f4e5-6b24-4019-b53c-5fbed134adcb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1835554242 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_out
standing.1835554242
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.1673078953
Short name T160
Test name
Test status
Simulation time 1597706391 ps
CPU time 92.26 seconds
Started Aug 11 04:52:57 PM PDT 24
Finished Aug 11 04:54:29 PM PDT 24
Peak memory 257192 kb
Host smart-fa7c9fa8-392c-4a25-87c4-c0113e9ffb5a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1673078953 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_erro
rs.1673078953
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.3767785191
Short name T168
Test name
Test status
Simulation time 4535307118 ps
CPU time 384.31 seconds
Started Aug 11 04:52:54 PM PDT 24
Finished Aug 11 04:59:18 PM PDT 24
Peak memory 265336 kb
Host smart-9dbee0a0-ac8e-4495-88d7-5fd23df6a247
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767785191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.3767785191
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.2640379747
Short name T718
Test name
Test status
Simulation time 106672811 ps
CPU time 4.3 seconds
Started Aug 11 04:52:53 PM PDT 24
Finished Aug 11 04:52:57 PM PDT 24
Peak memory 248860 kb
Host smart-c4388322-bbf4-4d5a-96c2-4166cbefc60f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2640379747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.2640379747
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.763520779
Short name T705
Test name
Test status
Simulation time 20851785582 ps
CPU time 1624.53 seconds
Started Aug 11 04:53:08 PM PDT 24
Finished Aug 11 05:20:13 PM PDT 24
Peak memory 288880 kb
Host smart-fb4f28d1-9561-4a48-96b2-e0cffdf850f9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=763520779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.763520779
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.3872711426
Short name T474
Test name
Test status
Simulation time 928298180 ps
CPU time 42.55 seconds
Started Aug 11 04:53:07 PM PDT 24
Finished Aug 11 04:53:50 PM PDT 24
Peak memory 246744 kb
Host smart-51dc4d68-a18f-43a3-bfbc-3dd1a974ef64
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3872711426 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.3872711426
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.1505557824
Short name T596
Test name
Test status
Simulation time 137757690 ps
CPU time 14.74 seconds
Started Aug 11 04:53:01 PM PDT 24
Finished Aug 11 04:53:16 PM PDT 24
Peak memory 255720 kb
Host smart-f3bbc0f7-5497-4e37-9d4a-05b9139ce10d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15055
57824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.1505557824
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.2684606931
Short name T562
Test name
Test status
Simulation time 535059608 ps
CPU time 20.43 seconds
Started Aug 11 04:53:08 PM PDT 24
Finished Aug 11 04:53:29 PM PDT 24
Peak memory 256064 kb
Host smart-e17389a8-0812-45cf-ba0c-8f2d273e12f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26846
06931 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.2684606931
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.3426278923
Short name T669
Test name
Test status
Simulation time 90784400514 ps
CPU time 2595.58 seconds
Started Aug 11 04:53:08 PM PDT 24
Finished Aug 11 05:36:24 PM PDT 24
Peak memory 284248 kb
Host smart-5fa1ed21-59cd-4196-8e66-e09df7d33d6b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3426278923 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.3426278923
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.719884994
Short name T247
Test name
Test status
Simulation time 12710046984 ps
CPU time 503.23 seconds
Started Aug 11 04:53:00 PM PDT 24
Finished Aug 11 05:01:24 PM PDT 24
Peak memory 248348 kb
Host smart-354643ee-7169-4592-adac-e27a38be6229
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=719884994 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.719884994
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.1829511748
Short name T480
Test name
Test status
Simulation time 246767912 ps
CPU time 14.98 seconds
Started Aug 11 04:53:00 PM PDT 24
Finished Aug 11 04:53:15 PM PDT 24
Peak memory 248232 kb
Host smart-78679418-7634-4b51-868d-26ab286b1c89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18295
11748 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.1829511748
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.3086235309
Short name T697
Test name
Test status
Simulation time 2454110643 ps
CPU time 62.14 seconds
Started Aug 11 04:53:01 PM PDT 24
Finished Aug 11 04:54:04 PM PDT 24
Peak memory 248220 kb
Host smart-1ca08e92-76dc-4c0e-817a-c7a49b06fc6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30862
35309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.3086235309
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.3345073656
Short name T32
Test name
Test status
Simulation time 643960541 ps
CPU time 30.7 seconds
Started Aug 11 04:53:07 PM PDT 24
Finished Aug 11 04:53:38 PM PDT 24
Peak memory 269104 kb
Host smart-7ca00aed-eb84-4265-bee8-ace15c61474d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3345073656 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.3345073656
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.2884051458
Short name T465
Test name
Test status
Simulation time 57424675 ps
CPU time 8.71 seconds
Started Aug 11 04:53:00 PM PDT 24
Finished Aug 11 04:53:08 PM PDT 24
Peak memory 248240 kb
Host smart-f8927708-92a4-49ed-aad6-005360f410c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28840
51458 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.2884051458
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.505118960
Short name T487
Test name
Test status
Simulation time 357344138 ps
CPU time 29.72 seconds
Started Aug 11 04:52:59 PM PDT 24
Finished Aug 11 04:53:29 PM PDT 24
Peak memory 256236 kb
Host smart-eac8e75d-9fb9-4426-84fb-9f5c1c76aa9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50511
8960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.505118960
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.909571212
Short name T423
Test name
Test status
Simulation time 795075742 ps
CPU time 75.82 seconds
Started Aug 11 04:53:07 PM PDT 24
Finished Aug 11 04:54:23 PM PDT 24
Peak memory 249168 kb
Host smart-ac744455-6025-4d22-9dd1-d1dbb5d063ab
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909571212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_hand
ler_stress_all.909571212
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all_with_rand_reset.3348636138
Short name T132
Test name
Test status
Simulation time 63762908245 ps
CPU time 2380.12 seconds
Started Aug 11 04:53:02 PM PDT 24
Finished Aug 11 05:32:43 PM PDT 24
Peak memory 289256 kb
Host smart-116f87ee-12c1-44e3-9824-8e8ba5cf6af6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3348636138 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 0.alert_handler_stress_all_with_rand_reset.3348636138
Directory /workspace/0.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.2996987620
Short name T479
Test name
Test status
Simulation time 94510642194 ps
CPU time 1489.81 seconds
Started Aug 11 04:53:09 PM PDT 24
Finished Aug 11 05:17:59 PM PDT 24
Peak memory 272888 kb
Host smart-f56661bd-7bf7-4af7-93d3-053915deb7a0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2996987620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.2996987620
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.2426535926
Short name T445
Test name
Test status
Simulation time 155142394 ps
CPU time 6.49 seconds
Started Aug 11 04:53:09 PM PDT 24
Finished Aug 11 04:53:15 PM PDT 24
Peak memory 248252 kb
Host smart-645c59de-989b-40c4-b355-92c0a5480c3d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2426535926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.2426535926
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.1644602135
Short name T640
Test name
Test status
Simulation time 3020172977 ps
CPU time 147.3 seconds
Started Aug 11 04:53:08 PM PDT 24
Finished Aug 11 04:55:35 PM PDT 24
Peak memory 250316 kb
Host smart-ec6eca05-b39a-4a14-8b7b-5b789974a63a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16446
02135 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.1644602135
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.1060188759
Short name T618
Test name
Test status
Simulation time 18651559 ps
CPU time 3.88 seconds
Started Aug 11 04:53:06 PM PDT 24
Finished Aug 11 04:53:10 PM PDT 24
Peak memory 239948 kb
Host smart-a0c4114f-42a4-4abf-9aae-cc6e83075be2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10601
88759 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.1060188759
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.3498420481
Short name T646
Test name
Test status
Simulation time 106559208749 ps
CPU time 1732.59 seconds
Started Aug 11 04:53:06 PM PDT 24
Finished Aug 11 05:21:59 PM PDT 24
Peak memory 272764 kb
Host smart-45c5d2b0-2093-49f0-b19b-0299395bb1a1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498420481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.3498420481
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.2174106678
Short name T624
Test name
Test status
Simulation time 49369488469 ps
CPU time 1132.34 seconds
Started Aug 11 04:53:05 PM PDT 24
Finished Aug 11 05:11:58 PM PDT 24
Peak memory 280452 kb
Host smart-8a22bae7-a5f2-4d59-9206-94fd238a5a85
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2174106678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.2174106678
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.2715853188
Short name T322
Test name
Test status
Simulation time 26717613170 ps
CPU time 286.66 seconds
Started Aug 11 04:53:09 PM PDT 24
Finished Aug 11 04:57:56 PM PDT 24
Peak memory 247204 kb
Host smart-299bd950-cfd3-449e-b459-16ae0e9a6b02
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715853188 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.2715853188
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.1663967911
Short name T200
Test name
Test status
Simulation time 2041456413 ps
CPU time 37.59 seconds
Started Aug 11 04:53:08 PM PDT 24
Finished Aug 11 04:53:46 PM PDT 24
Peak memory 255672 kb
Host smart-d7781ba8-ee5c-419f-95b8-fd268665b9dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16639
67911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.1663967911
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.1319262100
Short name T422
Test name
Test status
Simulation time 255364405 ps
CPU time 8.69 seconds
Started Aug 11 04:53:07 PM PDT 24
Finished Aug 11 04:53:16 PM PDT 24
Peak memory 252612 kb
Host smart-30fd2815-b4d8-473f-9e6b-2b8824066b3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13192
62100 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.1319262100
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.4098441771
Short name T31
Test name
Test status
Simulation time 1023119547 ps
CPU time 24.4 seconds
Started Aug 11 04:53:06 PM PDT 24
Finished Aug 11 04:53:31 PM PDT 24
Peak memory 275500 kb
Host smart-db446aee-885f-4128-81bd-d358b0808a5e
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4098441771 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.4098441771
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.3536314907
Short name T292
Test name
Test status
Simulation time 3288040504 ps
CPU time 51.93 seconds
Started Aug 11 04:53:07 PM PDT 24
Finished Aug 11 04:53:59 PM PDT 24
Peak memory 248308 kb
Host smart-5d1d3abb-3724-4a19-9964-2fc1d740d4b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35363
14907 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.3536314907
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.2365636207
Short name T699
Test name
Test status
Simulation time 1593087333 ps
CPU time 23.48 seconds
Started Aug 11 04:53:00 PM PDT 24
Finished Aug 11 04:53:23 PM PDT 24
Peak memory 248728 kb
Host smart-b38f5cae-b7e9-48ea-98a9-01575bcf2ae1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23656
36207 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.2365636207
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.67138917
Short name T555
Test name
Test status
Simulation time 1635962637 ps
CPU time 194.96 seconds
Started Aug 11 04:53:09 PM PDT 24
Finished Aug 11 04:56:24 PM PDT 24
Peak memory 252188 kb
Host smart-4c36c462-30c3-4f9e-9f5a-58882073551e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67138917 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handl
er_stress_all.67138917
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.3453795066
Short name T226
Test name
Test status
Simulation time 72475935 ps
CPU time 3.8 seconds
Started Aug 11 04:53:31 PM PDT 24
Finished Aug 11 04:53:35 PM PDT 24
Peak memory 248388 kb
Host smart-91c28f7e-a5d1-491c-8dd3-eb2045667f50
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3453795066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.3453795066
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.1983652887
Short name T612
Test name
Test status
Simulation time 6615439765 ps
CPU time 19.65 seconds
Started Aug 11 04:53:37 PM PDT 24
Finished Aug 11 04:53:57 PM PDT 24
Peak memory 248240 kb
Host smart-6307d084-ecf6-453d-99f3-c4711873efbe
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1983652887 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.1983652887
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.1185100950
Short name T112
Test name
Test status
Simulation time 15708482421 ps
CPU time 200.74 seconds
Started Aug 11 04:53:37 PM PDT 24
Finished Aug 11 04:56:58 PM PDT 24
Peak memory 256248 kb
Host smart-3e496583-1757-4b2c-9179-5e24deb0a9cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11851
00950 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.1185100950
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.652036514
Short name T386
Test name
Test status
Simulation time 1397379253 ps
CPU time 47.52 seconds
Started Aug 11 04:53:32 PM PDT 24
Finished Aug 11 04:54:20 PM PDT 24
Peak memory 255832 kb
Host smart-1ab49e4c-19cd-4f07-9534-222ebb0b9d0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65203
6514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.652036514
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.3819696859
Short name T702
Test name
Test status
Simulation time 177540715863 ps
CPU time 2630.45 seconds
Started Aug 11 04:53:31 PM PDT 24
Finished Aug 11 05:37:21 PM PDT 24
Peak memory 289224 kb
Host smart-aef304ee-35bb-45bc-ab13-c976355876b0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3819696859 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.3819696859
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.1209378461
Short name T592
Test name
Test status
Simulation time 143753002192 ps
CPU time 2466.7 seconds
Started Aug 11 04:53:37 PM PDT 24
Finished Aug 11 05:34:44 PM PDT 24
Peak memory 281048 kb
Host smart-ba0112f4-d571-4928-9f1b-060ccfe69943
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1209378461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.1209378461
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.3047762888
Short name T670
Test name
Test status
Simulation time 1065930736 ps
CPU time 46.33 seconds
Started Aug 11 04:53:31 PM PDT 24
Finished Aug 11 04:54:17 PM PDT 24
Peak memory 248168 kb
Host smart-5f78bcea-8bcf-4ca5-b7c0-6391f1af5365
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30477
62888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.3047762888
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.244941230
Short name T536
Test name
Test status
Simulation time 659333795 ps
CPU time 41.61 seconds
Started Aug 11 04:53:34 PM PDT 24
Finished Aug 11 04:54:16 PM PDT 24
Peak memory 248480 kb
Host smart-27666fd9-8202-468b-bc70-1608cdd0b566
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24494
1230 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.244941230
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.4111031758
Short name T110
Test name
Test status
Simulation time 866346997 ps
CPU time 53.85 seconds
Started Aug 11 04:53:29 PM PDT 24
Finished Aug 11 04:54:23 PM PDT 24
Peak memory 248288 kb
Host smart-5d899ce2-f577-48d7-9f78-d05ca7ae30e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41110
31758 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.4111031758
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.637451214
Short name T209
Test name
Test status
Simulation time 41798816 ps
CPU time 3.11 seconds
Started Aug 11 04:53:37 PM PDT 24
Finished Aug 11 04:53:41 PM PDT 24
Peak memory 248552 kb
Host smart-d8b1dbb6-ddf0-462b-a3fa-89aefbc5114f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=637451214 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.637451214
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.3208145898
Short name T586
Test name
Test status
Simulation time 46385481506 ps
CPU time 2496.84 seconds
Started Aug 11 04:53:32 PM PDT 24
Finished Aug 11 05:35:10 PM PDT 24
Peak memory 283196 kb
Host smart-3604e0b7-2a13-4d99-b264-bbfbcfb3326a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3208145898 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.3208145898
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.3564767222
Short name T253
Test name
Test status
Simulation time 634149853 ps
CPU time 12.42 seconds
Started Aug 11 04:53:31 PM PDT 24
Finished Aug 11 04:53:44 PM PDT 24
Peak memory 248184 kb
Host smart-5e157452-04eb-4ecd-9750-f313d8169157
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3564767222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.3564767222
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.381270518
Short name T615
Test name
Test status
Simulation time 10146872017 ps
CPU time 142.53 seconds
Started Aug 11 04:53:37 PM PDT 24
Finished Aug 11 04:56:00 PM PDT 24
Peak memory 256132 kb
Host smart-1822ec6b-9dd6-414b-bf2d-46db20e6622e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38127
0518 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.381270518
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.2353901477
Short name T515
Test name
Test status
Simulation time 115534909 ps
CPU time 14.13 seconds
Started Aug 11 04:53:35 PM PDT 24
Finished Aug 11 04:53:50 PM PDT 24
Peak memory 247648 kb
Host smart-a196efe0-158d-45f2-8e29-737282b42602
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23539
01477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.2353901477
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.1755415379
Short name T316
Test name
Test status
Simulation time 331689212438 ps
CPU time 1485.86 seconds
Started Aug 11 04:53:43 PM PDT 24
Finished Aug 11 05:18:29 PM PDT 24
Peak memory 272468 kb
Host smart-a4aceb79-232e-47cb-9b14-3b68a87c093e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1755415379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.1755415379
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.3557070326
Short name T452
Test name
Test status
Simulation time 30916740180 ps
CPU time 2053.57 seconds
Started Aug 11 04:53:33 PM PDT 24
Finished Aug 11 05:27:47 PM PDT 24
Peak memory 283112 kb
Host smart-b97e6f96-494b-4010-b4c8-fccbb5cc84c6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3557070326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.3557070326
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.480837945
Short name T333
Test name
Test status
Simulation time 6535992491 ps
CPU time 273.92 seconds
Started Aug 11 04:53:37 PM PDT 24
Finished Aug 11 04:58:11 PM PDT 24
Peak memory 248228 kb
Host smart-9d388a93-4385-442a-949a-621ec457c339
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=480837945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.480837945
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.723026183
Short name T684
Test name
Test status
Simulation time 170761892 ps
CPU time 16.97 seconds
Started Aug 11 04:53:39 PM PDT 24
Finished Aug 11 04:53:57 PM PDT 24
Peak memory 255648 kb
Host smart-117edb53-9b5b-4bcb-a5c4-8690698e8d83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72302
6183 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.723026183
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.665111527
Short name T589
Test name
Test status
Simulation time 5570247012 ps
CPU time 23.02 seconds
Started Aug 11 04:53:36 PM PDT 24
Finished Aug 11 04:53:59 PM PDT 24
Peak memory 255788 kb
Host smart-383f041c-019f-4bc2-a2bf-9045e6a693a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66511
1527 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.665111527
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.3750059144
Short name T255
Test name
Test status
Simulation time 544669311 ps
CPU time 42.64 seconds
Started Aug 11 04:53:32 PM PDT 24
Finished Aug 11 04:54:15 PM PDT 24
Peak memory 248180 kb
Host smart-33ed1fef-7629-4dde-8cd0-9f73e6326781
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37500
59144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.3750059144
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.2803582141
Short name T591
Test name
Test status
Simulation time 1528627140 ps
CPU time 33.52 seconds
Started Aug 11 04:53:43 PM PDT 24
Finished Aug 11 04:54:17 PM PDT 24
Peak memory 256452 kb
Host smart-f479f98c-1927-4f41-b4a4-f319efa91c41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28035
82141 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.2803582141
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.1822962423
Short name T481
Test name
Test status
Simulation time 10542175793 ps
CPU time 1207.8 seconds
Started Aug 11 04:53:34 PM PDT 24
Finished Aug 11 05:13:42 PM PDT 24
Peak memory 288900 kb
Host smart-5f9e9152-df18-4162-b5bc-a4778bc9d1de
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1822962423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_ha
ndler_stress_all.1822962423
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all_with_rand_reset.600606343
Short name T100
Test name
Test status
Simulation time 58559160783 ps
CPU time 3293.37 seconds
Started Aug 11 04:53:35 PM PDT 24
Finished Aug 11 05:48:28 PM PDT 24
Peak memory 321628 kb
Host smart-5c345daf-58ef-4309-b4a2-cfd7df433943
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=600606343 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 11.alert_handler_stress_all_with_rand_reset.600606343
Directory /workspace/11.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.143922104
Short name T238
Test name
Test status
Simulation time 47268875603 ps
CPU time 1224.94 seconds
Started Aug 11 04:53:35 PM PDT 24
Finished Aug 11 05:14:00 PM PDT 24
Peak memory 272832 kb
Host smart-da1a7a35-c45a-47b2-bae2-8d4454d55cee
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=143922104 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.143922104
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.3112911234
Short name T400
Test name
Test status
Simulation time 942571828 ps
CPU time 42.04 seconds
Started Aug 11 04:53:39 PM PDT 24
Finished Aug 11 04:54:21 PM PDT 24
Peak memory 248176 kb
Host smart-74bf8996-e438-4ff2-a06f-46ff81f2066d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3112911234 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.3112911234
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.2395988060
Short name T482
Test name
Test status
Simulation time 3152962289 ps
CPU time 193.72 seconds
Started Aug 11 04:53:32 PM PDT 24
Finished Aug 11 04:56:45 PM PDT 24
Peak memory 255796 kb
Host smart-35cf1588-6448-4b35-aa65-5cf74d1f94b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23959
88060 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.2395988060
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.3835572895
Short name T78
Test name
Test status
Simulation time 7976024120 ps
CPU time 79.28 seconds
Started Aug 11 04:53:40 PM PDT 24
Finished Aug 11 04:54:59 PM PDT 24
Peak memory 256380 kb
Host smart-77c1ee15-2e8e-4990-b128-bb19274e7f5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38355
72895 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.3835572895
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.1116542453
Short name T511
Test name
Test status
Simulation time 43672738568 ps
CPU time 1048.29 seconds
Started Aug 11 04:53:43 PM PDT 24
Finished Aug 11 05:11:11 PM PDT 24
Peak memory 272776 kb
Host smart-9f4fac92-78d5-4aa1-914f-c20d19efb722
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1116542453 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.1116542453
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.1176045096
Short name T93
Test name
Test status
Simulation time 181891714736 ps
CPU time 3031.22 seconds
Started Aug 11 04:53:45 PM PDT 24
Finished Aug 11 05:44:16 PM PDT 24
Peak memory 288624 kb
Host smart-344adbde-2790-45c6-b321-2dcf2d6b2ce5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1176045096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.1176045096
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.3136793045
Short name T317
Test name
Test status
Simulation time 53323276300 ps
CPU time 383.51 seconds
Started Aug 11 04:53:31 PM PDT 24
Finished Aug 11 04:59:55 PM PDT 24
Peak memory 248164 kb
Host smart-f1c3b4d3-b758-481e-868c-8a9384ccee03
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136793045 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.3136793045
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.4226256912
Short name T194
Test name
Test status
Simulation time 87507238 ps
CPU time 13.45 seconds
Started Aug 11 04:53:32 PM PDT 24
Finished Aug 11 04:53:45 PM PDT 24
Peak memory 254412 kb
Host smart-a58f8b95-005e-4465-94fb-31e5b356268e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42262
56912 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.4226256912
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.945026342
Short name T387
Test name
Test status
Simulation time 282581316 ps
CPU time 21.43 seconds
Started Aug 11 04:53:32 PM PDT 24
Finished Aug 11 04:53:54 PM PDT 24
Peak memory 247896 kb
Host smart-c533e155-0815-4171-8f7f-c6adc8c7fd80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94502
6342 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.945026342
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.2223075431
Short name T105
Test name
Test status
Simulation time 3152029802 ps
CPU time 51.08 seconds
Started Aug 11 04:53:35 PM PDT 24
Finished Aug 11 04:54:26 PM PDT 24
Peak memory 248632 kb
Host smart-4bd5c0bf-0ae0-4081-8121-19b0f1ff0176
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22230
75431 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.2223075431
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.863652204
Short name T416
Test name
Test status
Simulation time 1114308796 ps
CPU time 67.14 seconds
Started Aug 11 04:53:35 PM PDT 24
Finished Aug 11 04:54:42 PM PDT 24
Peak memory 256396 kb
Host smart-ce242028-c169-428c-aaaa-d390d4fce2da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86365
2204 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.863652204
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.1741763419
Short name T124
Test name
Test status
Simulation time 79783568025 ps
CPU time 3056.12 seconds
Started Aug 11 04:53:44 PM PDT 24
Finished Aug 11 05:44:40 PM PDT 24
Peak memory 289204 kb
Host smart-0e1da52c-b412-4aef-b305-dd147cc919be
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1741763419 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_ha
ndler_stress_all.1741763419
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all_with_rand_reset.3781494090
Short name T295
Test name
Test status
Simulation time 343884575128 ps
CPU time 1360.52 seconds
Started Aug 11 04:53:41 PM PDT 24
Finished Aug 11 05:16:22 PM PDT 24
Peak memory 286236 kb
Host smart-cc2fe331-c12e-4900-a8ed-d793bcebad42
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3781494090 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.alert_handler_stress_all_with_rand_reset.3781494090
Directory /workspace/12.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.1146925714
Short name T429
Test name
Test status
Simulation time 134448913353 ps
CPU time 1478.94 seconds
Started Aug 11 04:53:42 PM PDT 24
Finished Aug 11 05:18:22 PM PDT 24
Peak memory 287732 kb
Host smart-1c44e87b-88c0-4214-a518-cf83a254241a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1146925714 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.1146925714
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.4030600740
Short name T502
Test name
Test status
Simulation time 4714776193 ps
CPU time 48.85 seconds
Started Aug 11 04:53:43 PM PDT 24
Finished Aug 11 04:54:32 PM PDT 24
Peak memory 248240 kb
Host smart-ee2a597c-f9fe-4e29-ad2a-63b2a089b4a8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4030600740 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.4030600740
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.3430855302
Short name T679
Test name
Test status
Simulation time 1149091011 ps
CPU time 51.71 seconds
Started Aug 11 04:53:38 PM PDT 24
Finished Aug 11 04:54:30 PM PDT 24
Peak memory 255540 kb
Host smart-171ba200-cfd3-4126-bc96-387bfb85fba9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34308
55302 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.3430855302
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.1749101384
Short name T439
Test name
Test status
Simulation time 1097354101 ps
CPU time 28.08 seconds
Started Aug 11 04:53:49 PM PDT 24
Finished Aug 11 04:54:17 PM PDT 24
Peak memory 248472 kb
Host smart-90940b8d-dbb9-4661-bde7-c442a5dfb6f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17491
01384 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.1749101384
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.1192461281
Short name T509
Test name
Test status
Simulation time 35228184529 ps
CPU time 1208.49 seconds
Started Aug 11 04:53:40 PM PDT 24
Finished Aug 11 05:13:49 PM PDT 24
Peak memory 271248 kb
Host smart-c95adc33-b8f7-4e66-a058-0ae6ecfd15f2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1192461281 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.1192461281
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.2251315895
Short name T17
Test name
Test status
Simulation time 8784051595 ps
CPU time 736.03 seconds
Started Aug 11 04:53:41 PM PDT 24
Finished Aug 11 05:05:57 PM PDT 24
Peak memory 272216 kb
Host smart-12ce850d-ef8d-4615-b30a-4ff71bbd358d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2251315895 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.2251315895
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.2842965370
Short name T343
Test name
Test status
Simulation time 4651045823 ps
CPU time 200.1 seconds
Started Aug 11 04:53:40 PM PDT 24
Finished Aug 11 04:57:01 PM PDT 24
Peak memory 248084 kb
Host smart-fb916b26-5323-4fb6-8e5a-987ac9aaef49
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2842965370 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.2842965370
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.3108236821
Short name T686
Test name
Test status
Simulation time 866811727 ps
CPU time 51.83 seconds
Started Aug 11 04:53:41 PM PDT 24
Finished Aug 11 04:54:33 PM PDT 24
Peak memory 256280 kb
Host smart-52abf607-894a-45d9-bc69-51a747d1c41d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31082
36821 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.3108236821
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.3512337235
Short name T492
Test name
Test status
Simulation time 364343856 ps
CPU time 13.47 seconds
Started Aug 11 04:53:38 PM PDT 24
Finished Aug 11 04:53:52 PM PDT 24
Peak memory 247588 kb
Host smart-ba4b0ffe-0a90-4915-bfb9-9339290c3e5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35123
37235 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.3512337235
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.2243798583
Short name T608
Test name
Test status
Simulation time 3567169605 ps
CPU time 51.38 seconds
Started Aug 11 04:53:39 PM PDT 24
Finished Aug 11 04:54:31 PM PDT 24
Peak memory 255540 kb
Host smart-2d519a91-69e0-48bf-81f7-724f61e199d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22437
98583 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.2243798583
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.1938848956
Short name T613
Test name
Test status
Simulation time 1413494812 ps
CPU time 9.16 seconds
Started Aug 11 04:53:49 PM PDT 24
Finished Aug 11 04:53:58 PM PDT 24
Peak memory 252020 kb
Host smart-76fdd564-f65d-4510-90ca-2dc981006c8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19388
48956 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.1938848956
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.1111552445
Short name T307
Test name
Test status
Simulation time 38771920215 ps
CPU time 1668.4 seconds
Started Aug 11 04:53:42 PM PDT 24
Finished Aug 11 05:21:31 PM PDT 24
Peak memory 289224 kb
Host smart-d534a935-8305-48dc-974e-2ac074c6e2ac
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1111552445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_ha
ndler_stress_all.1111552445
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all_with_rand_reset.3173208379
Short name T133
Test name
Test status
Simulation time 431970353092 ps
CPU time 5389.82 seconds
Started Aug 11 04:53:39 PM PDT 24
Finished Aug 11 06:23:30 PM PDT 24
Peak memory 314956 kb
Host smart-5f6a3380-bd0b-41da-8a14-a00c9a3a9bcf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3173208379 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.alert_handler_stress_all_with_rand_reset.3173208379
Directory /workspace/13.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.2067380319
Short name T218
Test name
Test status
Simulation time 218462384 ps
CPU time 5.37 seconds
Started Aug 11 04:53:47 PM PDT 24
Finished Aug 11 04:53:52 PM PDT 24
Peak memory 248820 kb
Host smart-b35cee77-d029-4181-813e-9ea149f8b7ed
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2067380319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.2067380319
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.3025624562
Short name T385
Test name
Test status
Simulation time 24494422238 ps
CPU time 1458 seconds
Started Aug 11 04:53:48 PM PDT 24
Finished Aug 11 05:18:06 PM PDT 24
Peak memory 272348 kb
Host smart-7af697f5-d03b-4a40-8e52-e2885829e99b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3025624562 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.3025624562
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.1207402830
Short name T663
Test name
Test status
Simulation time 234631536 ps
CPU time 12.8 seconds
Started Aug 11 04:53:39 PM PDT 24
Finished Aug 11 04:53:52 PM PDT 24
Peak memory 248212 kb
Host smart-110da72b-323d-4086-b136-ee0795cc06ad
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1207402830 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.1207402830
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.987614353
Short name T704
Test name
Test status
Simulation time 2634442863 ps
CPU time 146.58 seconds
Started Aug 11 04:53:49 PM PDT 24
Finished Aug 11 04:56:15 PM PDT 24
Peak memory 256428 kb
Host smart-ebdc2a40-e955-4564-bf32-3e16aa9ed604
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=98761
4353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.987614353
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.3184117963
Short name T595
Test name
Test status
Simulation time 1042674040 ps
CPU time 42.2 seconds
Started Aug 11 04:53:43 PM PDT 24
Finished Aug 11 04:54:26 PM PDT 24
Peak memory 248136 kb
Host smart-8086a96f-df25-4214-9896-dee71a95471a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31841
17963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.3184117963
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.3352504557
Short name T349
Test name
Test status
Simulation time 10206750942 ps
CPU time 889.23 seconds
Started Aug 11 04:53:38 PM PDT 24
Finished Aug 11 05:08:28 PM PDT 24
Peak memory 272004 kb
Host smart-2b1fcf56-6d57-4874-ada0-6547c3d58257
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3352504557 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.3352504557
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.291626164
Short name T605
Test name
Test status
Simulation time 34402782501 ps
CPU time 2234.92 seconds
Started Aug 11 04:53:42 PM PDT 24
Finished Aug 11 05:30:58 PM PDT 24
Peak memory 288656 kb
Host smart-0ee89e23-c51d-4b02-accc-de57ddadc74a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291626164 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.291626164
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.1526518075
Short name T199
Test name
Test status
Simulation time 353542363 ps
CPU time 24.5 seconds
Started Aug 11 04:53:44 PM PDT 24
Finished Aug 11 04:54:08 PM PDT 24
Peak memory 248220 kb
Host smart-d3175183-f3ec-4cc7-8442-91892f4edb4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15265
18075 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.1526518075
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.2035981065
Short name T245
Test name
Test status
Simulation time 1309331232 ps
CPU time 37.66 seconds
Started Aug 11 04:53:43 PM PDT 24
Finished Aug 11 04:54:21 PM PDT 24
Peak memory 256336 kb
Host smart-94da91ea-885d-4fb1-b497-f8b793af10a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20359
81065 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.2035981065
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.4144588561
Short name T703
Test name
Test status
Simulation time 579162649 ps
CPU time 40.88 seconds
Started Aug 11 04:53:36 PM PDT 24
Finished Aug 11 04:54:17 PM PDT 24
Peak memory 255520 kb
Host smart-e8dbba67-173c-4b12-8eeb-9166a1a3e314
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41445
88561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.4144588561
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all_with_rand_reset.4252244796
Short name T257
Test name
Test status
Simulation time 25864044269 ps
CPU time 488.62 seconds
Started Aug 11 04:53:46 PM PDT 24
Finished Aug 11 05:01:55 PM PDT 24
Peak memory 268492 kb
Host smart-ae3ec86c-0d63-4ec7-8316-e3a8bc7c3204
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4252244796 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.alert_handler_stress_all_with_rand_reset.4252244796
Directory /workspace/14.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.2026011632
Short name T222
Test name
Test status
Simulation time 109068713 ps
CPU time 3.19 seconds
Started Aug 11 04:53:39 PM PDT 24
Finished Aug 11 04:53:42 PM PDT 24
Peak memory 248464 kb
Host smart-cae4ec02-be7a-4837-89ce-0b7feea6c168
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2026011632 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.2026011632
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.4025782037
Short name T488
Test name
Test status
Simulation time 69467856082 ps
CPU time 1147.14 seconds
Started Aug 11 04:53:42 PM PDT 24
Finished Aug 11 05:12:50 PM PDT 24
Peak memory 272712 kb
Host smart-5a372b5d-6889-4978-b823-fb7ff911f71c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4025782037 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.4025782037
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.1623302480
Short name T33
Test name
Test status
Simulation time 969716797 ps
CPU time 19.31 seconds
Started Aug 11 04:53:39 PM PDT 24
Finished Aug 11 04:53:59 PM PDT 24
Peak memory 248188 kb
Host smart-9f297cb9-fc9f-449a-b622-087660031428
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1623302480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.1623302480
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.2722427911
Short name T471
Test name
Test status
Simulation time 3271592138 ps
CPU time 164.79 seconds
Started Aug 11 04:53:43 PM PDT 24
Finished Aug 11 04:56:27 PM PDT 24
Peak memory 256440 kb
Host smart-31a684b4-9360-4e96-8965-242499f84dd4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27224
27911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.2722427911
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.1668400969
Short name T641
Test name
Test status
Simulation time 832592587 ps
CPU time 16.55 seconds
Started Aug 11 04:53:39 PM PDT 24
Finished Aug 11 04:53:56 PM PDT 24
Peak memory 255512 kb
Host smart-bde22f69-468b-486a-8705-96d6d868e5e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16684
00969 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.1668400969
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.59832391
Short name T236
Test name
Test status
Simulation time 156654257767 ps
CPU time 1423.66 seconds
Started Aug 11 04:53:44 PM PDT 24
Finished Aug 11 05:17:28 PM PDT 24
Peak memory 272120 kb
Host smart-27ac97fe-dc16-4121-b273-030f03611fe8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=59832391 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.59832391
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.2982020183
Short name T496
Test name
Test status
Simulation time 41652915915 ps
CPU time 741.32 seconds
Started Aug 11 04:53:39 PM PDT 24
Finished Aug 11 05:06:01 PM PDT 24
Peak memory 272728 kb
Host smart-e6edf891-2f16-4fc5-9b74-a75cd173007d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2982020183 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.2982020183
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.4139981624
Short name T336
Test name
Test status
Simulation time 10114761288 ps
CPU time 416.17 seconds
Started Aug 11 04:53:39 PM PDT 24
Finished Aug 11 05:00:36 PM PDT 24
Peak memory 248224 kb
Host smart-dd356e1b-6afd-4773-b3a4-38d290feeb19
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4139981624 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.4139981624
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.1961592641
Short name T620
Test name
Test status
Simulation time 541119076 ps
CPU time 19.39 seconds
Started Aug 11 04:53:46 PM PDT 24
Finished Aug 11 04:54:06 PM PDT 24
Peak memory 254904 kb
Host smart-045f5291-3eeb-4971-be0e-8667c6cd3845
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19615
92641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.1961592641
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.2819709263
Short name T614
Test name
Test status
Simulation time 1064679882 ps
CPU time 59.39 seconds
Started Aug 11 04:53:38 PM PDT 24
Finished Aug 11 04:54:37 PM PDT 24
Peak memory 248128 kb
Host smart-1c02b8b1-2d92-425e-b406-f32258654859
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28197
09263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.2819709263
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.2378781660
Short name T310
Test name
Test status
Simulation time 635161469 ps
CPU time 44.07 seconds
Started Aug 11 04:53:42 PM PDT 24
Finished Aug 11 04:54:26 PM PDT 24
Peak memory 247668 kb
Host smart-1a1cdf83-9fa0-44db-abe8-51d805c09f2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23787
81660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.2378781660
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.2883874322
Short name T427
Test name
Test status
Simulation time 733079010 ps
CPU time 32.73 seconds
Started Aug 11 04:53:43 PM PDT 24
Finished Aug 11 04:54:16 PM PDT 24
Peak memory 256236 kb
Host smart-b41a348e-d8b7-4f69-a1dd-8380a0adf0ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28838
74322 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.2883874322
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.804898911
Short name T656
Test name
Test status
Simulation time 328782609361 ps
CPU time 2571.18 seconds
Started Aug 11 04:53:40 PM PDT 24
Finished Aug 11 05:36:31 PM PDT 24
Peak memory 288508 kb
Host smart-37f44a5a-c3ab-493e-afc7-cf95a5339a8b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=804898911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_han
dler_stress_all.804898911
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.3430265419
Short name T211
Test name
Test status
Simulation time 45150256 ps
CPU time 3.79 seconds
Started Aug 11 04:53:46 PM PDT 24
Finished Aug 11 04:53:50 PM PDT 24
Peak memory 248432 kb
Host smart-8dd553a7-da95-47de-a1f4-68d86acfad0b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3430265419 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.3430265419
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.316902648
Short name T455
Test name
Test status
Simulation time 52739213450 ps
CPU time 674.33 seconds
Started Aug 11 04:53:41 PM PDT 24
Finished Aug 11 05:04:56 PM PDT 24
Peak memory 265544 kb
Host smart-f7082935-d9e1-44ed-82c5-335275b93c35
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=316902648 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.316902648
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.1800162625
Short name T470
Test name
Test status
Simulation time 658340547 ps
CPU time 11.55 seconds
Started Aug 11 04:53:47 PM PDT 24
Finished Aug 11 04:53:58 PM PDT 24
Peak memory 248128 kb
Host smart-7b241813-9a77-4d05-a750-ade490cbfa4c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1800162625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.1800162625
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.80263272
Short name T461
Test name
Test status
Simulation time 3442541247 ps
CPU time 117.77 seconds
Started Aug 11 04:53:43 PM PDT 24
Finished Aug 11 04:55:41 PM PDT 24
Peak memory 256016 kb
Host smart-87e33c78-ca85-4bd9-83d7-200cf0c4e604
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80263
272 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.80263272
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.645198857
Short name T706
Test name
Test status
Simulation time 1261942068 ps
CPU time 15.34 seconds
Started Aug 11 04:53:39 PM PDT 24
Finished Aug 11 04:53:55 PM PDT 24
Peak memory 255500 kb
Host smart-ecc1fc78-5c8f-4e12-9922-b69831d8968f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64519
8857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.645198857
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.729116253
Short name T478
Test name
Test status
Simulation time 34626275663 ps
CPU time 734.41 seconds
Started Aug 11 04:53:44 PM PDT 24
Finished Aug 11 05:05:59 PM PDT 24
Peak memory 272092 kb
Host smart-95c2d016-04d4-4fbc-a6dd-dad50190e9dc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=729116253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.729116253
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.1315754362
Short name T622
Test name
Test status
Simulation time 8643174838 ps
CPU time 1171.5 seconds
Started Aug 11 04:53:49 PM PDT 24
Finished Aug 11 05:13:21 PM PDT 24
Peak memory 281908 kb
Host smart-fca0aafc-3bcf-44d5-aed0-f5d84dd0de05
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1315754362 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.1315754362
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.2275528145
Short name T321
Test name
Test status
Simulation time 36674646387 ps
CPU time 186.04 seconds
Started Aug 11 04:53:48 PM PDT 24
Finished Aug 11 04:56:54 PM PDT 24
Peak memory 254784 kb
Host smart-663d67db-ef52-47c1-8433-a57c0e213bcd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2275528145 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.2275528145
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.3352424221
Short name T658
Test name
Test status
Simulation time 6036643142 ps
CPU time 33.39 seconds
Started Aug 11 04:53:46 PM PDT 24
Finished Aug 11 04:54:19 PM PDT 24
Peak memory 255000 kb
Host smart-90afbff1-b36a-4752-bac3-924f704246bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33524
24221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.3352424221
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.1854154462
Short name T578
Test name
Test status
Simulation time 459604917 ps
CPU time 17.87 seconds
Started Aug 11 04:53:40 PM PDT 24
Finished Aug 11 04:53:58 PM PDT 24
Peak memory 255692 kb
Host smart-b50d9d1a-e368-41d5-8a50-970cac7743ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18541
54462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.1854154462
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.1585394737
Short name T490
Test name
Test status
Simulation time 4348569043 ps
CPU time 75.42 seconds
Started Aug 11 04:53:44 PM PDT 24
Finished Aug 11 04:54:59 PM PDT 24
Peak memory 256416 kb
Host smart-ef2ae9bd-f588-45d6-85de-e5a25b50891a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15853
94737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.1585394737
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.3572916644
Short name T365
Test name
Test status
Simulation time 1387897309 ps
CPU time 41.74 seconds
Started Aug 11 04:53:45 PM PDT 24
Finished Aug 11 04:54:27 PM PDT 24
Peak memory 255600 kb
Host smart-f68b8601-3164-4e55-abce-384a3fd83d53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35729
16644 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.3572916644
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.1916872237
Short name T262
Test name
Test status
Simulation time 3078132506 ps
CPU time 330.13 seconds
Started Aug 11 04:53:43 PM PDT 24
Finished Aug 11 04:59:13 PM PDT 24
Peak memory 256464 kb
Host smart-a97c189b-91b1-4eb6-9343-15c7358ecefd
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1916872237 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_ha
ndler_stress_all.1916872237
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all_with_rand_reset.896636975
Short name T425
Test name
Test status
Simulation time 10426577735 ps
CPU time 737.13 seconds
Started Aug 11 04:53:45 PM PDT 24
Finished Aug 11 05:06:02 PM PDT 24
Peak memory 272996 kb
Host smart-ed383b83-b4f1-4936-a5e5-4a75db82f520
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=896636975 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 16.alert_handler_stress_all_with_rand_reset.896636975
Directory /workspace/16.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.2706170547
Short name T227
Test name
Test status
Simulation time 30455001 ps
CPU time 3.52 seconds
Started Aug 11 04:53:44 PM PDT 24
Finished Aug 11 04:53:48 PM PDT 24
Peak memory 248492 kb
Host smart-ce2b0a32-9a39-41e5-ac38-d9f1b2588ef8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2706170547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.2706170547
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.1296668224
Short name T695
Test name
Test status
Simulation time 407596819107 ps
CPU time 2828.85 seconds
Started Aug 11 04:53:44 PM PDT 24
Finished Aug 11 05:40:54 PM PDT 24
Peak memory 288748 kb
Host smart-3a2fe851-69dc-4aea-86d9-a032d21b5cc9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1296668224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.1296668224
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.2561043697
Short name T649
Test name
Test status
Simulation time 255639119 ps
CPU time 12.94 seconds
Started Aug 11 04:53:46 PM PDT 24
Finished Aug 11 04:53:59 PM PDT 24
Peak memory 248168 kb
Host smart-d206faaf-abdf-4275-8223-bec695a687a2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2561043697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.2561043697
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.3588853608
Short name T535
Test name
Test status
Simulation time 437223832 ps
CPU time 28.87 seconds
Started Aug 11 04:53:45 PM PDT 24
Finished Aug 11 04:54:14 PM PDT 24
Peak memory 256424 kb
Host smart-04e6824f-14db-4379-b71f-420db317490c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35888
53608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.3588853608
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.1849855163
Short name T379
Test name
Test status
Simulation time 600147636 ps
CPU time 33.21 seconds
Started Aug 11 04:53:50 PM PDT 24
Finished Aug 11 04:54:24 PM PDT 24
Peak memory 248228 kb
Host smart-86031568-edba-4235-9d86-604045c6aa86
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18498
55163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.1849855163
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.2610188169
Short name T346
Test name
Test status
Simulation time 12707373544 ps
CPU time 1183.32 seconds
Started Aug 11 04:53:47 PM PDT 24
Finished Aug 11 05:13:30 PM PDT 24
Peak memory 283976 kb
Host smart-d1a9b03e-c57d-4e75-9709-afe7513b4ad1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2610188169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.2610188169
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.1425957492
Short name T126
Test name
Test status
Simulation time 25511691201 ps
CPU time 1372.27 seconds
Started Aug 11 04:53:43 PM PDT 24
Finished Aug 11 05:16:35 PM PDT 24
Peak memory 280960 kb
Host smart-02c9695c-1b99-4da4-9e39-cf0e5d351bcc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1425957492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.1425957492
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.3915516528
Short name T530
Test name
Test status
Simulation time 264947458 ps
CPU time 16.72 seconds
Started Aug 11 04:53:43 PM PDT 24
Finished Aug 11 04:54:00 PM PDT 24
Peak memory 248204 kb
Host smart-2c4ff31e-1cf9-4912-945b-9375afc032be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39155
16528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.3915516528
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.3412634624
Short name T47
Test name
Test status
Simulation time 177984219 ps
CPU time 13.84 seconds
Started Aug 11 04:53:48 PM PDT 24
Finished Aug 11 04:54:02 PM PDT 24
Peak memory 253616 kb
Host smart-1566836f-f88a-4afa-8d2b-a587c7f49917
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34126
34624 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.3412634624
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.2685053912
Short name T407
Test name
Test status
Simulation time 4253250252 ps
CPU time 56.74 seconds
Started Aug 11 04:53:45 PM PDT 24
Finished Aug 11 04:54:42 PM PDT 24
Peak memory 256120 kb
Host smart-875624a1-8882-45f2-9978-761c146f2770
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26850
53912 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.2685053912
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.1319608039
Short name T443
Test name
Test status
Simulation time 9651691908 ps
CPU time 324.27 seconds
Started Aug 11 04:53:42 PM PDT 24
Finished Aug 11 04:59:07 PM PDT 24
Peak memory 256676 kb
Host smart-150894b1-361c-4dee-aa38-a7463e2f293f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1319608039 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_ha
ndler_stress_all.1319608039
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.805946328
Short name T219
Test name
Test status
Simulation time 81287042 ps
CPU time 3.63 seconds
Started Aug 11 04:53:44 PM PDT 24
Finished Aug 11 04:53:48 PM PDT 24
Peak memory 248304 kb
Host smart-ae45a8ce-9725-4b6b-ae2d-351d439b35f7
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=805946328 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.805946328
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.4276078478
Short name T477
Test name
Test status
Simulation time 74618217026 ps
CPU time 1527.84 seconds
Started Aug 11 04:53:47 PM PDT 24
Finished Aug 11 05:19:15 PM PDT 24
Peak memory 288352 kb
Host smart-c2c461c1-778a-4054-9d4d-9739d693d86f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276078478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.4276078478
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.2993166935
Short name T438
Test name
Test status
Simulation time 547934576 ps
CPU time 24.19 seconds
Started Aug 11 04:53:49 PM PDT 24
Finished Aug 11 04:54:13 PM PDT 24
Peak memory 248176 kb
Host smart-32fbaf53-ccec-463a-9678-0ce89d2b7884
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2993166935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.2993166935
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.2610368442
Short name T603
Test name
Test status
Simulation time 4279859750 ps
CPU time 83.64 seconds
Started Aug 11 04:53:49 PM PDT 24
Finished Aug 11 04:55:13 PM PDT 24
Peak memory 255656 kb
Host smart-4679395f-86b7-405a-a93a-57db37026bb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26103
68442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.2610368442
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.906684609
Short name T301
Test name
Test status
Simulation time 3343441721 ps
CPU time 43.5 seconds
Started Aug 11 04:53:43 PM PDT 24
Finished Aug 11 04:54:26 PM PDT 24
Peak memory 248044 kb
Host smart-ce9e3a17-1930-43d7-b52e-b76e9669fceb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90668
4609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.906684609
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.2479909140
Short name T123
Test name
Test status
Simulation time 24720240747 ps
CPU time 1588.54 seconds
Started Aug 11 04:53:45 PM PDT 24
Finished Aug 11 05:20:14 PM PDT 24
Peak memory 272052 kb
Host smart-7fc745bd-3b05-45df-bea8-61a66180093c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479909140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.2479909140
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.292179215
Short name T122
Test name
Test status
Simulation time 19558646272 ps
CPU time 1120.12 seconds
Started Aug 11 04:53:43 PM PDT 24
Finished Aug 11 05:12:23 PM PDT 24
Peak memory 265604 kb
Host smart-59768580-d06a-4520-a69d-3a5b5f177fcb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=292179215 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.292179215
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.2386924514
Short name T611
Test name
Test status
Simulation time 172304638 ps
CPU time 4.4 seconds
Started Aug 11 04:53:48 PM PDT 24
Finished Aug 11 04:53:53 PM PDT 24
Peak memory 239924 kb
Host smart-7986e2ec-d9e5-4a12-95f8-28071dae8390
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23869
24514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.2386924514
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.1706776313
Short name T61
Test name
Test status
Simulation time 374566105 ps
CPU time 7.92 seconds
Started Aug 11 04:53:42 PM PDT 24
Finished Aug 11 04:53:50 PM PDT 24
Peak memory 251648 kb
Host smart-e137c02c-427d-493d-a0b3-31f1a627e54f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17067
76313 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.1706776313
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.1440837421
Short name T405
Test name
Test status
Simulation time 103563956 ps
CPU time 12.93 seconds
Started Aug 11 04:53:47 PM PDT 24
Finished Aug 11 04:54:00 PM PDT 24
Peak memory 247632 kb
Host smart-a2789b02-f89b-4590-82ad-b8984250fe9a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14408
37421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.1440837421
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.544743857
Short name T60
Test name
Test status
Simulation time 205778115 ps
CPU time 10.43 seconds
Started Aug 11 04:53:45 PM PDT 24
Finished Aug 11 04:53:56 PM PDT 24
Peak memory 255316 kb
Host smart-c1e08802-b9df-4863-bb9e-0ea88f29ac7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54474
3857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.544743857
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all_with_rand_reset.1497974875
Short name T54
Test name
Test status
Simulation time 195335725317 ps
CPU time 2928.48 seconds
Started Aug 11 04:53:44 PM PDT 24
Finished Aug 11 05:42:33 PM PDT 24
Peak memory 297488 kb
Host smart-2821484d-90c2-4e78-b2d3-55890a00d21b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1497974875 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.alert_handler_stress_all_with_rand_reset.1497974875
Directory /workspace/18.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.3008517349
Short name T210
Test name
Test status
Simulation time 35660191 ps
CPU time 2.59 seconds
Started Aug 11 04:53:50 PM PDT 24
Finished Aug 11 04:53:52 PM PDT 24
Peak memory 248552 kb
Host smart-51438380-50dc-4eb2-a4e3-bcd0da586eb9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3008517349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.3008517349
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.3235819266
Short name T553
Test name
Test status
Simulation time 36928830202 ps
CPU time 2018.1 seconds
Started Aug 11 04:53:49 PM PDT 24
Finished Aug 11 05:27:28 PM PDT 24
Peak memory 272740 kb
Host smart-d1251edc-22a3-4ab6-8175-091f1b76eda1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3235819266 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.3235819266
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.967668358
Short name T370
Test name
Test status
Simulation time 2284985642 ps
CPU time 28.64 seconds
Started Aug 11 04:53:52 PM PDT 24
Finished Aug 11 04:54:20 PM PDT 24
Peak memory 248344 kb
Host smart-1abe0984-81d1-4b2a-9489-5c0e5613af7e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=967668358 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.967668358
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.1701985067
Short name T366
Test name
Test status
Simulation time 5075298750 ps
CPU time 153.07 seconds
Started Aug 11 04:53:47 PM PDT 24
Finished Aug 11 04:56:20 PM PDT 24
Peak memory 251440 kb
Host smart-d8f39919-5ea6-4819-8bfa-ed2293e9e861
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17019
85067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.1701985067
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.26088843
Short name T368
Test name
Test status
Simulation time 36554267 ps
CPU time 4.27 seconds
Started Aug 11 04:53:41 PM PDT 24
Finished Aug 11 04:53:45 PM PDT 24
Peak memory 248228 kb
Host smart-a61dee3e-425c-4014-a8ae-a8c402566a03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26088
843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.26088843
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.53672602
Short name T534
Test name
Test status
Simulation time 54546127476 ps
CPU time 1321.59 seconds
Started Aug 11 04:53:49 PM PDT 24
Finished Aug 11 05:15:51 PM PDT 24
Peak memory 283424 kb
Host smart-69f31d85-9d99-47e7-87f3-4c6f932b3985
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=53672602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.53672602
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.3622604856
Short name T537
Test name
Test status
Simulation time 25704811363 ps
CPU time 1402.22 seconds
Started Aug 11 04:53:51 PM PDT 24
Finished Aug 11 05:17:14 PM PDT 24
Peak memory 288292 kb
Host smart-2d2d865b-0d3e-4665-86bf-564897522853
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622604856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.3622604856
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.3142775215
Short name T676
Test name
Test status
Simulation time 16929439209 ps
CPU time 384.49 seconds
Started Aug 11 04:53:48 PM PDT 24
Finished Aug 11 05:00:13 PM PDT 24
Peak memory 255020 kb
Host smart-9a70cb1e-cd54-413d-8f3f-6cd766c3ebca
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3142775215 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.3142775215
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.2946115845
Short name T272
Test name
Test status
Simulation time 3986282457 ps
CPU time 52.99 seconds
Started Aug 11 04:53:46 PM PDT 24
Finished Aug 11 04:54:39 PM PDT 24
Peak memory 255688 kb
Host smart-d40f02d5-053b-4fd8-a6d2-e9945204d99f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29461
15845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.2946115845
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.2394953736
Short name T459
Test name
Test status
Simulation time 48605080 ps
CPU time 7.33 seconds
Started Aug 11 04:53:49 PM PDT 24
Finished Aug 11 04:53:56 PM PDT 24
Peak memory 247512 kb
Host smart-e7f8dd0f-9d26-47be-a23f-1efca2c97d2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23949
53736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.2394953736
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.2737821132
Short name T674
Test name
Test status
Simulation time 1721673569 ps
CPU time 30.76 seconds
Started Aug 11 04:53:51 PM PDT 24
Finished Aug 11 04:54:22 PM PDT 24
Peak memory 255392 kb
Host smart-497cddaa-f04d-4a50-b418-62c6364cd2f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27378
21132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.2737821132
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.1985650745
Short name T392
Test name
Test status
Simulation time 314870119 ps
CPU time 18.03 seconds
Started Aug 11 04:53:45 PM PDT 24
Finished Aug 11 04:54:03 PM PDT 24
Peak memory 248128 kb
Host smart-c822b674-479d-4a14-a5c5-449a9483d7f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19856
50745 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.1985650745
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.961500150
Short name T50
Test name
Test status
Simulation time 15939543869 ps
CPU time 830.51 seconds
Started Aug 11 04:53:51 PM PDT 24
Finished Aug 11 05:07:42 PM PDT 24
Peak memory 268164 kb
Host smart-bd7547a2-fdec-4f69-91b8-b79fbf451be5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=961500150 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_han
dler_stress_all.961500150
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.513320934
Short name T216
Test name
Test status
Simulation time 114670144 ps
CPU time 3.77 seconds
Started Aug 11 04:53:07 PM PDT 24
Finished Aug 11 04:53:10 PM PDT 24
Peak memory 248820 kb
Host smart-b9ffb86c-2e4a-4281-9e71-cdf851f6b613
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=513320934 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.513320934
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.2074482721
Short name T548
Test name
Test status
Simulation time 65112401428 ps
CPU time 1040.91 seconds
Started Aug 11 04:53:08 PM PDT 24
Finished Aug 11 05:10:29 PM PDT 24
Peak memory 272564 kb
Host smart-ceaacf65-f746-4d8c-8266-2963410cbb33
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2074482721 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.2074482721
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.2279287414
Short name T250
Test name
Test status
Simulation time 742610210 ps
CPU time 35.06 seconds
Started Aug 11 04:53:06 PM PDT 24
Finished Aug 11 04:53:42 PM PDT 24
Peak memory 248212 kb
Host smart-70c86d51-d0a7-430b-865f-aefb4029de40
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2279287414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.2279287414
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.4100644833
Short name T574
Test name
Test status
Simulation time 585600125 ps
CPU time 22.57 seconds
Started Aug 11 04:53:08 PM PDT 24
Finished Aug 11 04:53:30 PM PDT 24
Peak memory 255048 kb
Host smart-941c7481-1be2-4b2e-9845-2a1b88d198c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41006
44833 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.4100644833
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.1655929483
Short name T464
Test name
Test status
Simulation time 2288126600 ps
CPU time 74.3 seconds
Started Aug 11 04:53:09 PM PDT 24
Finished Aug 11 04:54:23 PM PDT 24
Peak memory 256360 kb
Host smart-980941ea-fa68-4588-877d-5c3411974f75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16559
29483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.1655929483
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.417662795
Short name T690
Test name
Test status
Simulation time 21895979030 ps
CPU time 1513.99 seconds
Started Aug 11 04:53:08 PM PDT 24
Finished Aug 11 05:18:23 PM PDT 24
Peak memory 272188 kb
Host smart-34bbe833-9e10-4cbf-8f4e-b8dbfe943e3c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=417662795 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.417662795
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.843270548
Short name T74
Test name
Test status
Simulation time 17021733362 ps
CPU time 1771.93 seconds
Started Aug 11 04:53:07 PM PDT 24
Finished Aug 11 05:22:39 PM PDT 24
Peak memory 287568 kb
Host smart-9a284a50-0801-4bc1-9cf2-5b9b85d30ae8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=843270548 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.843270548
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.394318900
Short name T239
Test name
Test status
Simulation time 21163436610 ps
CPU time 229.27 seconds
Started Aug 11 04:53:07 PM PDT 24
Finished Aug 11 04:56:56 PM PDT 24
Peak memory 247120 kb
Host smart-e5d25cf7-3755-4549-b2e4-ccd3a97e94de
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=394318900 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.394318900
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.3342663848
Short name T610
Test name
Test status
Simulation time 288601156 ps
CPU time 21.4 seconds
Started Aug 11 04:53:09 PM PDT 24
Finished Aug 11 04:53:31 PM PDT 24
Peak memory 248244 kb
Host smart-e03b93f9-e5a6-4e6b-9168-41141f7ebe8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33426
63848 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.3342663848
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.1044524070
Short name T451
Test name
Test status
Simulation time 62734586 ps
CPU time 8.68 seconds
Started Aug 11 04:53:08 PM PDT 24
Finished Aug 11 04:53:17 PM PDT 24
Peak memory 247748 kb
Host smart-24bed320-33fd-44fe-aa75-61d0494e01c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10445
24070 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.1044524070
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.402231318
Short name T8
Test name
Test status
Simulation time 957736006 ps
CPU time 40.35 seconds
Started Aug 11 04:53:06 PM PDT 24
Finished Aug 11 04:53:47 PM PDT 24
Peak memory 270416 kb
Host smart-71e6e739-f6dd-483a-83ae-a7929bf2dd88
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=402231318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.402231318
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.4255574712
Short name T489
Test name
Test status
Simulation time 2962970120 ps
CPU time 49.53 seconds
Started Aug 11 04:53:09 PM PDT 24
Finished Aug 11 04:53:58 PM PDT 24
Peak memory 255580 kb
Host smart-819d9db3-c514-4cac-8f31-55c0fde27408
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42555
74712 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.4255574712
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.3185971774
Short name T542
Test name
Test status
Simulation time 1025023728 ps
CPU time 58.24 seconds
Started Aug 11 04:53:08 PM PDT 24
Finished Aug 11 04:54:07 PM PDT 24
Peak memory 255348 kb
Host smart-a81ca958-d85a-433c-a784-46d29c6bcd9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31859
71774 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.3185971774
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.1663245294
Short name T315
Test name
Test status
Simulation time 135226686043 ps
CPU time 1420.98 seconds
Started Aug 11 04:53:07 PM PDT 24
Finished Aug 11 05:16:48 PM PDT 24
Peak memory 267772 kb
Host smart-422b3a4b-e856-4898-a0cc-a2f3572392cb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663245294 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_han
dler_stress_all.1663245294
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.4243048305
Short name T519
Test name
Test status
Simulation time 36070194652 ps
CPU time 2063.51 seconds
Started Aug 11 04:53:50 PM PDT 24
Finished Aug 11 05:28:14 PM PDT 24
Peak memory 281032 kb
Host smart-81f6b572-9a22-41dd-87cd-78764bde37ed
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4243048305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.4243048305
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.1897305375
Short name T626
Test name
Test status
Simulation time 514929489 ps
CPU time 24.68 seconds
Started Aug 11 04:53:48 PM PDT 24
Finished Aug 11 04:54:13 PM PDT 24
Peak memory 255640 kb
Host smart-85267d78-458a-4ce6-a0f0-0723b782e820
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18973
05375 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.1897305375
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.427839673
Short name T524
Test name
Test status
Simulation time 35173991 ps
CPU time 5.18 seconds
Started Aug 11 04:53:56 PM PDT 24
Finished Aug 11 04:54:02 PM PDT 24
Peak memory 251636 kb
Host smart-f071af64-f8f8-4de9-8ba5-22f941d45885
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42783
9673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.427839673
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.771536277
Short name T1
Test name
Test status
Simulation time 532038116782 ps
CPU time 2748.86 seconds
Started Aug 11 04:53:49 PM PDT 24
Finished Aug 11 05:39:38 PM PDT 24
Peak memory 285144 kb
Host smart-561fc1f9-92af-4432-8832-6482b02c3c00
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=771536277 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.771536277
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.2662656485
Short name T109
Test name
Test status
Simulation time 90263010929 ps
CPU time 1392.28 seconds
Started Aug 11 04:53:52 PM PDT 24
Finished Aug 11 05:17:04 PM PDT 24
Peak memory 267636 kb
Host smart-0565eea5-4908-4976-bf0e-8bdd1a01ee98
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2662656485 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.2662656485
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.2590073123
Short name T323
Test name
Test status
Simulation time 9648057009 ps
CPU time 398.43 seconds
Started Aug 11 04:53:50 PM PDT 24
Finished Aug 11 05:00:29 PM PDT 24
Peak memory 247072 kb
Host smart-657525e9-9d9f-4776-80ee-16b9379eacb7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2590073123 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.2590073123
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.2853712996
Short name T593
Test name
Test status
Simulation time 374276286 ps
CPU time 23.68 seconds
Started Aug 11 04:53:51 PM PDT 24
Finished Aug 11 04:54:15 PM PDT 24
Peak memory 255656 kb
Host smart-8616e813-0cba-4cd4-a74b-729b6a4ae005
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28537
12996 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.2853712996
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.1198361742
Short name T102
Test name
Test status
Simulation time 6488885720 ps
CPU time 71.46 seconds
Started Aug 11 04:53:50 PM PDT 24
Finished Aug 11 04:55:02 PM PDT 24
Peak memory 247956 kb
Host smart-3ddae744-afe5-490b-a45b-cbc1c1d32b79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11983
61742 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.1198361742
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.1336867814
Short name T81
Test name
Test status
Simulation time 1197502060 ps
CPU time 20.07 seconds
Started Aug 11 04:53:51 PM PDT 24
Finished Aug 11 04:54:11 PM PDT 24
Peak memory 247256 kb
Host smart-14bc6bc5-143a-4233-ab21-4bcb83482d51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13368
67814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.1336867814
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.3589412576
Short name T447
Test name
Test status
Simulation time 390251829 ps
CPU time 29.98 seconds
Started Aug 11 04:53:50 PM PDT 24
Finished Aug 11 04:54:20 PM PDT 24
Peak memory 255580 kb
Host smart-e2a14877-ac08-446a-ba87-1a29fbaf4d37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35894
12576 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.3589412576
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.3178826622
Short name T694
Test name
Test status
Simulation time 82083907589 ps
CPU time 1540.1 seconds
Started Aug 11 04:53:49 PM PDT 24
Finished Aug 11 05:19:29 PM PDT 24
Peak memory 289108 kb
Host smart-a699d91e-afb1-4307-81ec-ab5553ddb11e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3178826622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_ha
ndler_stress_all.3178826622
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.2228249504
Short name T286
Test name
Test status
Simulation time 16737222178 ps
CPU time 782.93 seconds
Started Aug 11 04:53:56 PM PDT 24
Finished Aug 11 05:06:59 PM PDT 24
Peak memory 272840 kb
Host smart-826184b3-27d7-4bcf-af55-b553bd661786
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2228249504 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.2228249504
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.2026926242
Short name T523
Test name
Test status
Simulation time 1360178250 ps
CPU time 108.4 seconds
Started Aug 11 04:53:57 PM PDT 24
Finished Aug 11 04:55:46 PM PDT 24
Peak memory 256372 kb
Host smart-db3fbfdc-8bf4-4ef8-9882-4108388579e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20269
26242 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.2026926242
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.407720723
Short name T244
Test name
Test status
Simulation time 1246504893 ps
CPU time 11.39 seconds
Started Aug 11 04:53:56 PM PDT 24
Finished Aug 11 04:54:07 PM PDT 24
Peak memory 247752 kb
Host smart-959094ba-f690-4bc0-927c-9755024b7b39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40772
0723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.407720723
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.645265926
Short name T606
Test name
Test status
Simulation time 53378992324 ps
CPU time 2911.42 seconds
Started Aug 11 04:54:00 PM PDT 24
Finished Aug 11 05:42:32 PM PDT 24
Peak memory 289232 kb
Host smart-1d31a84b-45aa-4875-bb46-b22e21e92c53
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=645265926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.645265926
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.3950908549
Short name T644
Test name
Test status
Simulation time 35609399126 ps
CPU time 1804.51 seconds
Started Aug 11 04:53:57 PM PDT 24
Finished Aug 11 05:24:02 PM PDT 24
Peak memory 272736 kb
Host smart-1f504725-668e-4194-a7fc-03f0eee7bc2a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3950908549 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.3950908549
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.1807687717
Short name T335
Test name
Test status
Simulation time 18497348930 ps
CPU time 189.03 seconds
Started Aug 11 04:53:58 PM PDT 24
Finished Aug 11 04:57:07 PM PDT 24
Peak memory 248244 kb
Host smart-2dac96ba-f8e5-4deb-ad40-53b8e3179d89
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1807687717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.1807687717
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.3807240207
Short name T72
Test name
Test status
Simulation time 3613282173 ps
CPU time 52.91 seconds
Started Aug 11 04:53:50 PM PDT 24
Finished Aug 11 04:54:43 PM PDT 24
Peak memory 248232 kb
Host smart-7c4bf845-0c9d-499b-9715-175548ff8cd2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38072
40207 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.3807240207
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.1591557455
Short name T602
Test name
Test status
Simulation time 4573778133 ps
CPU time 75.34 seconds
Started Aug 11 04:53:48 PM PDT 24
Finished Aug 11 04:55:03 PM PDT 24
Peak memory 247560 kb
Host smart-9c9f310c-3e8a-4e9b-aa0b-5a271a57bb83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15915
57455 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.1591557455
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.966521996
Short name T466
Test name
Test status
Simulation time 253249056 ps
CPU time 40.51 seconds
Started Aug 11 04:53:56 PM PDT 24
Finished Aug 11 04:54:36 PM PDT 24
Peak memory 247748 kb
Host smart-5dc1ea99-136d-477c-b111-2bc2626c084d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96652
1996 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.966521996
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.553247470
Short name T529
Test name
Test status
Simulation time 827069301 ps
CPU time 42.79 seconds
Started Aug 11 04:53:51 PM PDT 24
Finished Aug 11 04:54:34 PM PDT 24
Peak memory 255704 kb
Host smart-eb5602c9-4e68-4755-b1f3-03c20c641d4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55324
7470 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.553247470
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.2953339168
Short name T516
Test name
Test status
Simulation time 3179169004 ps
CPU time 161.38 seconds
Started Aug 11 04:53:57 PM PDT 24
Finished Aug 11 04:56:38 PM PDT 24
Peak memory 256408 kb
Host smart-756f11e4-b02c-4d22-b52a-2573edafb9eb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2953339168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_ha
ndler_stress_all.2953339168
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all_with_rand_reset.1153915701
Short name T256
Test name
Test status
Simulation time 46597048682 ps
CPU time 3034.16 seconds
Started Aug 11 04:53:58 PM PDT 24
Finished Aug 11 05:44:32 PM PDT 24
Peak memory 297144 kb
Host smart-9a322cab-95d7-417c-9806-dd6634d6c7e5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1153915701 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.alert_handler_stress_all_with_rand_reset.1153915701
Directory /workspace/21.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.320890638
Short name T20
Test name
Test status
Simulation time 45010766292 ps
CPU time 1068.8 seconds
Started Aug 11 04:53:56 PM PDT 24
Finished Aug 11 05:11:45 PM PDT 24
Peak memory 280992 kb
Host smart-2723e52e-6699-4a3b-aa58-cd1d0f80a0be
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320890638 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.320890638
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.3372718610
Short name T59
Test name
Test status
Simulation time 132468350 ps
CPU time 18.71 seconds
Started Aug 11 04:53:59 PM PDT 24
Finished Aug 11 04:54:18 PM PDT 24
Peak memory 255900 kb
Host smart-c5c7e3de-8689-4e45-86c9-f65a9ea43c92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33727
18610 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.3372718610
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.2822344591
Short name T528
Test name
Test status
Simulation time 1182270025 ps
CPU time 43.89 seconds
Started Aug 11 04:53:55 PM PDT 24
Finished Aug 11 04:54:39 PM PDT 24
Peak memory 255896 kb
Host smart-d6712b3f-ad64-4f6d-a361-0e67583c6988
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28223
44591 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.2822344591
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.555429290
Short name T243
Test name
Test status
Simulation time 54655473111 ps
CPU time 1635.29 seconds
Started Aug 11 04:53:56 PM PDT 24
Finished Aug 11 05:21:12 PM PDT 24
Peak memory 288812 kb
Host smart-e456b154-30d9-4f99-a3d5-33eba00939cc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=555429290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.555429290
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.2862622272
Short name T597
Test name
Test status
Simulation time 55635704920 ps
CPU time 1230.06 seconds
Started Aug 11 04:53:56 PM PDT 24
Finished Aug 11 05:14:26 PM PDT 24
Peak memory 272816 kb
Host smart-c236ba70-088e-456e-a119-cdbaf3ff900c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2862622272 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.2862622272
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.701132642
Short name T654
Test name
Test status
Simulation time 8289512835 ps
CPU time 341.63 seconds
Started Aug 11 04:53:55 PM PDT 24
Finished Aug 11 04:59:37 PM PDT 24
Peak memory 248248 kb
Host smart-f1d9ce06-c8a8-49e2-aa17-d7299f6a80bd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=701132642 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.701132642
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.2994540412
Short name T485
Test name
Test status
Simulation time 469668258 ps
CPU time 9.27 seconds
Started Aug 11 04:53:55 PM PDT 24
Finished Aug 11 04:54:04 PM PDT 24
Peak memory 248248 kb
Host smart-42145aac-9d42-497c-9fa7-1983e0d8f072
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29945
40412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.2994540412
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.125206357
Short name T119
Test name
Test status
Simulation time 645946023 ps
CPU time 43.76 seconds
Started Aug 11 04:53:58 PM PDT 24
Finished Aug 11 04:54:42 PM PDT 24
Peak memory 255780 kb
Host smart-7cdd95d9-1818-4265-ad13-6e82c3c73066
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12520
6357 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.125206357
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.666914743
Short name T687
Test name
Test status
Simulation time 622499550 ps
CPU time 41.56 seconds
Started Aug 11 04:53:57 PM PDT 24
Finished Aug 11 04:54:39 PM PDT 24
Peak memory 256428 kb
Host smart-7e93a8bc-38f1-4465-b31f-631dccc88308
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66691
4743 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.666914743
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.2816801661
Short name T371
Test name
Test status
Simulation time 15527348521 ps
CPU time 46.44 seconds
Started Aug 11 04:53:58 PM PDT 24
Finished Aug 11 04:54:44 PM PDT 24
Peak memory 248208 kb
Host smart-318b44e3-7952-4b18-b022-03e9a71e6824
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28168
01661 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.2816801661
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.51685002
Short name T44
Test name
Test status
Simulation time 10348514389 ps
CPU time 257.19 seconds
Started Aug 11 04:53:55 PM PDT 24
Finished Aug 11 04:58:12 PM PDT 24
Peak memory 254484 kb
Host smart-2f1b74c6-2db7-49df-a981-16425a236bd2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51685002 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_hand
ler_stress_all.51685002
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all_with_rand_reset.992822654
Short name T518
Test name
Test status
Simulation time 29869587674 ps
CPU time 3414.32 seconds
Started Aug 11 04:53:55 PM PDT 24
Finished Aug 11 05:50:49 PM PDT 24
Peak memory 313960 kb
Host smart-e068035a-1c21-42da-9096-3fd1936fd26d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=992822654 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 22.alert_handler_stress_all_with_rand_reset.992822654
Directory /workspace/22.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.397058470
Short name T692
Test name
Test status
Simulation time 30917910337 ps
CPU time 689.5 seconds
Started Aug 11 04:54:02 PM PDT 24
Finished Aug 11 05:05:32 PM PDT 24
Peak memory 264608 kb
Host smart-a6049d32-34b9-4e66-8a08-4c381b419d8d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397058470 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.397058470
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.92528641
Short name T433
Test name
Test status
Simulation time 1991137736 ps
CPU time 116.98 seconds
Started Aug 11 04:54:05 PM PDT 24
Finished Aug 11 04:56:02 PM PDT 24
Peak memory 256352 kb
Host smart-05d58a3f-ab76-4c39-a4de-5278c42c45c7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92528
641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.92528641
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.3321010112
Short name T682
Test name
Test status
Simulation time 70381031 ps
CPU time 5.51 seconds
Started Aug 11 04:54:01 PM PDT 24
Finished Aug 11 04:54:06 PM PDT 24
Peak memory 239536 kb
Host smart-6fa686d7-222b-4516-8f56-c9e7e6775d59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33210
10112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.3321010112
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.1345461693
Short name T616
Test name
Test status
Simulation time 80603780504 ps
CPU time 2501.81 seconds
Started Aug 11 04:54:01 PM PDT 24
Finished Aug 11 05:35:43 PM PDT 24
Peak memory 280972 kb
Host smart-b37375b6-858c-48d8-9982-8586f233c1eb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1345461693 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.1345461693
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.2689355278
Short name T45
Test name
Test status
Simulation time 635721375 ps
CPU time 31.21 seconds
Started Aug 11 04:54:00 PM PDT 24
Finished Aug 11 04:54:32 PM PDT 24
Peak memory 248176 kb
Host smart-3993f215-d494-4052-a047-569b10db6076
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26893
55278 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.2689355278
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.3292329369
Short name T484
Test name
Test status
Simulation time 636556140 ps
CPU time 19.39 seconds
Started Aug 11 04:54:03 PM PDT 24
Finished Aug 11 04:54:22 PM PDT 24
Peak memory 247776 kb
Host smart-5e11d74c-611b-4eaa-8a4d-e80a78715a4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32923
29369 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.3292329369
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.3167285704
Short name T417
Test name
Test status
Simulation time 2380593788 ps
CPU time 37.35 seconds
Started Aug 11 04:54:01 PM PDT 24
Finished Aug 11 04:54:38 PM PDT 24
Peak memory 255908 kb
Host smart-dbc350e0-1cd7-4f40-afd2-c8cd727d1006
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31672
85704 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.3167285704
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.3908283100
Short name T402
Test name
Test status
Simulation time 972228499 ps
CPU time 14.8 seconds
Started Aug 11 04:53:55 PM PDT 24
Finished Aug 11 04:54:10 PM PDT 24
Peak memory 255984 kb
Host smart-7587667f-0822-410f-9dd3-a3ed529c57b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39082
83100 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.3908283100
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.3492073372
Short name T621
Test name
Test status
Simulation time 13633973874 ps
CPU time 1363.87 seconds
Started Aug 11 04:54:02 PM PDT 24
Finished Aug 11 05:16:46 PM PDT 24
Peak memory 284916 kb
Host smart-a1fb345c-ba7b-4f0e-81ab-dd6a2cfd1291
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3492073372 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_ha
ndler_stress_all.3492073372
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.1854454267
Short name T495
Test name
Test status
Simulation time 74232610059 ps
CPU time 2409.67 seconds
Started Aug 11 04:54:10 PM PDT 24
Finished Aug 11 05:34:20 PM PDT 24
Peak memory 288460 kb
Host smart-235c1c69-71bc-4c4f-b161-4b596a1026a8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1854454267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.1854454267
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.2908659011
Short name T415
Test name
Test status
Simulation time 1790851200 ps
CPU time 96.37 seconds
Started Aug 11 04:54:03 PM PDT 24
Finished Aug 11 04:55:39 PM PDT 24
Peak memory 255920 kb
Host smart-ca204916-08e9-4231-8a8c-8bc2a72e3fc5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29086
59011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.2908659011
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.1507421040
Short name T635
Test name
Test status
Simulation time 245006951 ps
CPU time 21.41 seconds
Started Aug 11 04:54:02 PM PDT 24
Finished Aug 11 04:54:23 PM PDT 24
Peak memory 248252 kb
Host smart-f8f400b4-c481-4407-9ce7-b53818a19f36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15074
21040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.1507421040
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.2156260112
Short name T683
Test name
Test status
Simulation time 213225988331 ps
CPU time 1434.82 seconds
Started Aug 11 04:54:09 PM PDT 24
Finished Aug 11 05:18:04 PM PDT 24
Peak memory 272156 kb
Host smart-e3dfd58c-dc25-4890-b6d5-2aaddc8c83ad
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2156260112 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.2156260112
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.2124864221
Short name T531
Test name
Test status
Simulation time 182189526745 ps
CPU time 2509.21 seconds
Started Aug 11 04:54:07 PM PDT 24
Finished Aug 11 05:35:56 PM PDT 24
Peak memory 281036 kb
Host smart-4ae51184-1638-41e8-afbe-1d6f3b73f94c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2124864221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.2124864221
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.3572589343
Short name T680
Test name
Test status
Simulation time 28807820860 ps
CPU time 148.7 seconds
Started Aug 11 04:54:08 PM PDT 24
Finished Aug 11 04:56:37 PM PDT 24
Peak memory 248224 kb
Host smart-8014cade-5ade-4616-a876-6998348e1c47
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3572589343 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.3572589343
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.1551370091
Short name T565
Test name
Test status
Simulation time 298012041 ps
CPU time 31.73 seconds
Started Aug 11 04:54:03 PM PDT 24
Finished Aug 11 04:54:35 PM PDT 24
Peak memory 255400 kb
Host smart-cc1aa37d-9454-460c-89c9-7544b917ed30
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15513
70091 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.1551370091
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.347908157
Short name T278
Test name
Test status
Simulation time 552676510 ps
CPU time 47.96 seconds
Started Aug 11 04:54:02 PM PDT 24
Finished Aug 11 04:54:50 PM PDT 24
Peak memory 248204 kb
Host smart-4975da5a-507b-459a-affb-eab3ef6a1875
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34790
8157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.347908157
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.2007526723
Short name T522
Test name
Test status
Simulation time 433125067 ps
CPU time 6.58 seconds
Started Aug 11 04:54:03 PM PDT 24
Finished Aug 11 04:54:09 PM PDT 24
Peak memory 240044 kb
Host smart-7bf4cd30-0440-482d-b911-d366fa0bf659
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20075
26723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.2007526723
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.3654413886
Short name T442
Test name
Test status
Simulation time 303265750 ps
CPU time 21.21 seconds
Started Aug 11 04:54:01 PM PDT 24
Finished Aug 11 04:54:22 PM PDT 24
Peak memory 255988 kb
Host smart-009a99cd-9256-4a26-9337-c8b2bc816396
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36544
13886 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.3654413886
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.3354586475
Short name T58
Test name
Test status
Simulation time 221229518175 ps
CPU time 3195.98 seconds
Started Aug 11 04:54:08 PM PDT 24
Finished Aug 11 05:47:24 PM PDT 24
Peak memory 288672 kb
Host smart-630d0e60-3346-4089-aa9a-5abf7405a970
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3354586475 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_ha
ndler_stress_all.3354586475
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.2871169968
Short name T653
Test name
Test status
Simulation time 35253959223 ps
CPU time 2113.04 seconds
Started Aug 11 04:54:07 PM PDT 24
Finished Aug 11 05:29:21 PM PDT 24
Peak memory 281956 kb
Host smart-38870ad9-7e85-4bc9-bdf2-ecde25443a0d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2871169968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.2871169968
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.1742192074
Short name T380
Test name
Test status
Simulation time 2756844963 ps
CPU time 120.38 seconds
Started Aug 11 04:54:08 PM PDT 24
Finished Aug 11 04:56:08 PM PDT 24
Peak memory 255724 kb
Host smart-80f73625-b0ff-4bbe-b828-fc37a68bbf1f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17421
92074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.1742192074
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.1625266518
Short name T246
Test name
Test status
Simulation time 1040481591 ps
CPU time 31.06 seconds
Started Aug 11 04:54:08 PM PDT 24
Finished Aug 11 04:54:39 PM PDT 24
Peak memory 256304 kb
Host smart-1b96a3d0-83bc-4a3f-b8cc-ea3c8147e517
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16252
66518 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.1625266518
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.3603363145
Short name T198
Test name
Test status
Simulation time 46750772083 ps
CPU time 1246.72 seconds
Started Aug 11 04:54:07 PM PDT 24
Finished Aug 11 05:14:54 PM PDT 24
Peak memory 271984 kb
Host smart-f0e02f9e-537f-4f7c-a899-1b2f064dc32e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3603363145 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.3603363145
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.3938154990
Short name T462
Test name
Test status
Simulation time 83632600565 ps
CPU time 2501.02 seconds
Started Aug 11 04:54:09 PM PDT 24
Finished Aug 11 05:35:51 PM PDT 24
Peak memory 283896 kb
Host smart-73000c16-ebf0-4416-85be-c822535a7896
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3938154990 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.3938154990
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.2601188083
Short name T14
Test name
Test status
Simulation time 30665269116 ps
CPU time 365.17 seconds
Started Aug 11 04:54:08 PM PDT 24
Finished Aug 11 05:00:13 PM PDT 24
Peak memory 254424 kb
Host smart-a1c95e73-1e57-4fbd-b202-9ed5bb365b88
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2601188083 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.2601188083
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.2193037744
Short name T195
Test name
Test status
Simulation time 908086520 ps
CPU time 52.63 seconds
Started Aug 11 04:54:08 PM PDT 24
Finished Aug 11 04:55:01 PM PDT 24
Peak memory 256372 kb
Host smart-8d6efeec-f629-475c-b1d0-0f8976ab61b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21930
37744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.2193037744
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.2554054460
Short name T302
Test name
Test status
Simulation time 1046694999 ps
CPU time 38.94 seconds
Started Aug 11 04:54:08 PM PDT 24
Finished Aug 11 04:54:47 PM PDT 24
Peak memory 256036 kb
Host smart-528ef586-3021-4441-9495-246e6cf028f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25540
54460 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.2554054460
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.1491749829
Short name T558
Test name
Test status
Simulation time 289289946 ps
CPU time 22.73 seconds
Started Aug 11 04:54:08 PM PDT 24
Finished Aug 11 04:54:31 PM PDT 24
Peak memory 247660 kb
Host smart-091d127d-ea54-4265-a03b-5393f059e731
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14917
49829 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.1491749829
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.4025581442
Short name T364
Test name
Test status
Simulation time 3727050935 ps
CPU time 64.28 seconds
Started Aug 11 04:54:06 PM PDT 24
Finished Aug 11 04:55:11 PM PDT 24
Peak memory 248192 kb
Host smart-59791957-c2ee-47da-ab97-56d9e1adc4a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40255
81442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.4025581442
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.3378178157
Short name T661
Test name
Test status
Simulation time 203920945473 ps
CPU time 2836.1 seconds
Started Aug 11 04:54:16 PM PDT 24
Finished Aug 11 05:41:32 PM PDT 24
Peak memory 289160 kb
Host smart-d08e93b1-1dcf-4ed1-a7e3-73b6e9df38cd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3378178157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.3378178157
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.971706846
Short name T556
Test name
Test status
Simulation time 2502800173 ps
CPU time 135.23 seconds
Started Aug 11 04:54:15 PM PDT 24
Finished Aug 11 04:56:30 PM PDT 24
Peak memory 256440 kb
Host smart-34d21857-34ae-417f-b034-ec5b2d1222ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97170
6846 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.971706846
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.461729398
Short name T2
Test name
Test status
Simulation time 420960945 ps
CPU time 12.87 seconds
Started Aug 11 04:54:14 PM PDT 24
Finished Aug 11 04:54:27 PM PDT 24
Peak memory 255356 kb
Host smart-28436141-d34d-42a8-a7de-3124048d4322
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46172
9398 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.461729398
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.4287519538
Short name T41
Test name
Test status
Simulation time 33308386335 ps
CPU time 2119.69 seconds
Started Aug 11 04:54:15 PM PDT 24
Finished Aug 11 05:29:35 PM PDT 24
Peak memory 285860 kb
Host smart-49dfd668-4476-421d-b514-d4c5ac16b932
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287519538 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.4287519538
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.3495718097
Short name T232
Test name
Test status
Simulation time 80150070124 ps
CPU time 2167.38 seconds
Started Aug 11 04:54:13 PM PDT 24
Finished Aug 11 05:30:21 PM PDT 24
Peak memory 288340 kb
Host smart-2307be44-ece3-467d-a21f-64c12bd265f6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3495718097 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.3495718097
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.1117151827
Short name T514
Test name
Test status
Simulation time 7622979146 ps
CPU time 78.78 seconds
Started Aug 11 04:54:14 PM PDT 24
Finished Aug 11 04:55:33 PM PDT 24
Peak memory 248192 kb
Host smart-74c6aaae-40f0-4982-8ec6-916f272105be
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1117151827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.1117151827
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.4198886681
Short name T500
Test name
Test status
Simulation time 342807704 ps
CPU time 15.88 seconds
Started Aug 11 04:54:16 PM PDT 24
Finished Aug 11 04:54:32 PM PDT 24
Peak memory 254500 kb
Host smart-08aa5ef7-b82a-4e86-bac2-fac700b1f821
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41988
86681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.4198886681
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.497125186
Short name T552
Test name
Test status
Simulation time 1117782439 ps
CPU time 33.55 seconds
Started Aug 11 04:54:15 PM PDT 24
Finished Aug 11 04:54:49 PM PDT 24
Peak memory 255660 kb
Host smart-e6813c67-adcb-429a-a1a0-b40396f6ba93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49712
5186 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.497125186
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.2914458266
Short name T89
Test name
Test status
Simulation time 1675511703 ps
CPU time 39.91 seconds
Started Aug 11 04:54:14 PM PDT 24
Finished Aug 11 04:54:54 PM PDT 24
Peak memory 255532 kb
Host smart-02ef9eb5-b573-4642-ad0f-df22676aa618
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29144
58266 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.2914458266
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.2052355975
Short name T230
Test name
Test status
Simulation time 180633098 ps
CPU time 13.65 seconds
Started Aug 11 04:54:17 PM PDT 24
Finished Aug 11 04:54:31 PM PDT 24
Peak memory 255984 kb
Host smart-e70e34d9-08ed-45c9-b1fc-f34a51f00de2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20523
55975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.2052355975
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.1705476332
Short name T564
Test name
Test status
Simulation time 30601301622 ps
CPU time 1947.78 seconds
Started Aug 11 04:54:16 PM PDT 24
Finished Aug 11 05:26:44 PM PDT 24
Peak memory 285496 kb
Host smart-9377e06b-dec9-4a5a-8cea-9c4a809ab310
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1705476332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_ha
ndler_stress_all.1705476332
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all_with_rand_reset.2615944478
Short name T397
Test name
Test status
Simulation time 26970060556 ps
CPU time 3025.39 seconds
Started Aug 11 04:54:14 PM PDT 24
Finished Aug 11 05:44:40 PM PDT 24
Peak memory 321476 kb
Host smart-a21132a0-fdb2-4ac7-a963-30ede45b05cf
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2615944478 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.alert_handler_stress_all_with_rand_reset.2615944478
Directory /workspace/26.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.926062369
Short name T431
Test name
Test status
Simulation time 6850879308 ps
CPU time 780.01 seconds
Started Aug 11 04:54:17 PM PDT 24
Finished Aug 11 05:07:17 PM PDT 24
Peak memory 272140 kb
Host smart-fe5fc58f-eaa9-490d-93ed-ace9a88c669e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=926062369 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.926062369
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.1361652930
Short name T693
Test name
Test status
Simulation time 2376337022 ps
CPU time 50.44 seconds
Started Aug 11 04:54:16 PM PDT 24
Finished Aug 11 04:55:06 PM PDT 24
Peak memory 256476 kb
Host smart-a81dc3d0-688e-4e9e-a2c5-dc34e82a40d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13616
52930 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.1361652930
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.3108915804
Short name T88
Test name
Test status
Simulation time 2838748924 ps
CPU time 51.22 seconds
Started Aug 11 04:54:16 PM PDT 24
Finished Aug 11 04:55:08 PM PDT 24
Peak memory 248252 kb
Host smart-29822b1c-4628-4369-bba0-5b0abd110e0a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31089
15804 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.3108915804
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.1700939239
Short name T287
Test name
Test status
Simulation time 172938567568 ps
CPU time 2911.81 seconds
Started Aug 11 04:54:13 PM PDT 24
Finished Aug 11 05:42:46 PM PDT 24
Peak memory 288908 kb
Host smart-a9f3c68c-36fa-41ab-bcb2-f48d9bb7e9e8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1700939239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.1700939239
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.317895242
Short name T18
Test name
Test status
Simulation time 37503376056 ps
CPU time 2279.2 seconds
Started Aug 11 04:54:16 PM PDT 24
Finished Aug 11 05:32:15 PM PDT 24
Peak memory 281012 kb
Host smart-e012e8bc-9dcc-4bbb-b1d9-4f2175382c3a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=317895242 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.317895242
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.1790105023
Short name T13
Test name
Test status
Simulation time 9223608567 ps
CPU time 204.18 seconds
Started Aug 11 04:54:17 PM PDT 24
Finished Aug 11 04:57:42 PM PDT 24
Peak memory 248224 kb
Host smart-44e61875-6da3-4af7-9bef-fb1e3b434434
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1790105023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.1790105023
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.2490303590
Short name T441
Test name
Test status
Simulation time 206436597 ps
CPU time 23.18 seconds
Started Aug 11 04:54:14 PM PDT 24
Finished Aug 11 04:54:37 PM PDT 24
Peak memory 255328 kb
Host smart-2a701ac6-feff-4904-ad24-280d0957c939
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24903
03590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.2490303590
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.877133905
Short name T390
Test name
Test status
Simulation time 1447550719 ps
CPU time 45.96 seconds
Started Aug 11 04:54:14 PM PDT 24
Finished Aug 11 04:55:00 PM PDT 24
Peak memory 248224 kb
Host smart-63ab87b0-e433-43af-b573-a3e26b1f2011
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87713
3905 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.877133905
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.692143507
Short name T65
Test name
Test status
Simulation time 3212258689 ps
CPU time 33.37 seconds
Started Aug 11 04:54:16 PM PDT 24
Finished Aug 11 04:54:49 PM PDT 24
Peak memory 248232 kb
Host smart-87a10299-6e11-483e-b4f9-beaeed455632
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69214
3507 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.692143507
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.2806425989
Short name T375
Test name
Test status
Simulation time 325706096 ps
CPU time 10.94 seconds
Started Aug 11 04:54:17 PM PDT 24
Finished Aug 11 04:54:28 PM PDT 24
Peak memory 255416 kb
Host smart-7d6562de-c7bb-4759-8f12-69b26b3bea8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28064
25989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.2806425989
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.515596185
Short name T298
Test name
Test status
Simulation time 22786950946 ps
CPU time 2237.16 seconds
Started Aug 11 04:54:15 PM PDT 24
Finished Aug 11 05:31:33 PM PDT 24
Peak memory 302944 kb
Host smart-918e272a-d4e8-4ea2-a911-d37b42776b57
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=515596185 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_han
dler_stress_all.515596185
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.1954930889
Short name T568
Test name
Test status
Simulation time 11848913306 ps
CPU time 983.96 seconds
Started Aug 11 04:54:25 PM PDT 24
Finished Aug 11 05:10:49 PM PDT 24
Peak memory 281968 kb
Host smart-7d086d60-cb98-48a0-a39d-9aa638e96201
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1954930889 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.1954930889
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.1016754174
Short name T67
Test name
Test status
Simulation time 1590685089 ps
CPU time 139.09 seconds
Started Aug 11 04:54:19 PM PDT 24
Finished Aug 11 04:56:38 PM PDT 24
Peak memory 255860 kb
Host smart-1ca2873f-4a18-4982-9ff0-a2bc7b4b1842
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10167
54174 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.1016754174
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.2938615472
Short name T486
Test name
Test status
Simulation time 579428844 ps
CPU time 37.76 seconds
Started Aug 11 04:54:15 PM PDT 24
Finished Aug 11 04:54:53 PM PDT 24
Peak memory 256072 kb
Host smart-1a946205-b1b3-4991-a03d-88b6ef270dc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29386
15472 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.2938615472
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.4084694292
Short name T554
Test name
Test status
Simulation time 11760491279 ps
CPU time 557.59 seconds
Started Aug 11 04:54:18 PM PDT 24
Finished Aug 11 05:03:36 PM PDT 24
Peak memory 272804 kb
Host smart-0d2bded4-5aa4-40fe-948c-86f6c2eb51a4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4084694292 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.4084694292
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.1549506819
Short name T458
Test name
Test status
Simulation time 61631937200 ps
CPU time 1801.4 seconds
Started Aug 11 04:54:20 PM PDT 24
Finished Aug 11 05:24:22 PM PDT 24
Peak memory 286924 kb
Host smart-18a1db65-c587-4f22-a179-8559d316c9cd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549506819 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.1549506819
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.4187515220
Short name T330
Test name
Test status
Simulation time 30399170244 ps
CPU time 333.29 seconds
Started Aug 11 04:54:22 PM PDT 24
Finished Aug 11 04:59:55 PM PDT 24
Peak memory 254036 kb
Host smart-6890277e-082a-48bc-abdb-1ce0bedb2b96
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4187515220 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.4187515220
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.1865353568
Short name T446
Test name
Test status
Simulation time 2633643751 ps
CPU time 28.7 seconds
Started Aug 11 04:54:18 PM PDT 24
Finished Aug 11 04:54:47 PM PDT 24
Peak memory 255660 kb
Host smart-6a644eb2-f352-45d8-afec-cd693ed9689a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18653
53568 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.1865353568
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.2729773768
Short name T525
Test name
Test status
Simulation time 645530159 ps
CPU time 48.43 seconds
Started Aug 11 04:54:15 PM PDT 24
Finished Aug 11 04:55:03 PM PDT 24
Peak memory 248212 kb
Host smart-cd1bbac2-ca91-4529-a69b-a95023d70646
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27297
73768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.2729773768
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.388227159
Short name T68
Test name
Test status
Simulation time 248073369 ps
CPU time 29.59 seconds
Started Aug 11 04:54:20 PM PDT 24
Finished Aug 11 04:54:50 PM PDT 24
Peak memory 247572 kb
Host smart-dad2ded6-ccb8-49a6-aa05-be7e59f8b5c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38822
7159 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.388227159
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.2238687708
Short name T573
Test name
Test status
Simulation time 270128887 ps
CPU time 23.79 seconds
Started Aug 11 04:54:18 PM PDT 24
Finished Aug 11 04:54:42 PM PDT 24
Peak memory 248576 kb
Host smart-e48254f4-943a-4c51-8ce6-d244f20f4499
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22386
87708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.2238687708
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.2195679664
Short name T449
Test name
Test status
Simulation time 20951529048 ps
CPU time 607.84 seconds
Started Aug 11 04:54:21 PM PDT 24
Finished Aug 11 05:04:29 PM PDT 24
Peak memory 264684 kb
Host smart-f0b1c321-613c-4fdd-a5ef-e2e9c1885578
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195679664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_ha
ndler_stress_all.2195679664
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all_with_rand_reset.2479714220
Short name T303
Test name
Test status
Simulation time 115341730266 ps
CPU time 5434.19 seconds
Started Aug 11 04:54:22 PM PDT 24
Finished Aug 11 06:24:57 PM PDT 24
Peak memory 338128 kb
Host smart-ed06164b-6bd4-475c-a1cf-ccf16b381295
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2479714220 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.alert_handler_stress_all_with_rand_reset.2479714220
Directory /workspace/28.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.2466664813
Short name T84
Test name
Test status
Simulation time 33643804929 ps
CPU time 2206.05 seconds
Started Aug 11 04:54:27 PM PDT 24
Finished Aug 11 05:31:13 PM PDT 24
Peak memory 288520 kb
Host smart-a6186e9f-abb2-420e-a4ce-d5ca07602451
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2466664813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.2466664813
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.209047894
Short name T63
Test name
Test status
Simulation time 9946004322 ps
CPU time 176.89 seconds
Started Aug 11 04:54:22 PM PDT 24
Finished Aug 11 04:57:19 PM PDT 24
Peak memory 256448 kb
Host smart-7a5a0f0c-500e-4bb3-852c-7c149d574a53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20904
7894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.209047894
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.3509074885
Short name T66
Test name
Test status
Simulation time 471004709 ps
CPU time 10.45 seconds
Started Aug 11 04:54:19 PM PDT 24
Finished Aug 11 04:54:30 PM PDT 24
Peak memory 247820 kb
Host smart-83eeae86-7110-4018-83f2-d9134ef7a6db
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35090
74885 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.3509074885
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.1135849729
Short name T651
Test name
Test status
Simulation time 655061688252 ps
CPU time 2222.77 seconds
Started Aug 11 04:54:28 PM PDT 24
Finished Aug 11 05:31:31 PM PDT 24
Peak memory 272776 kb
Host smart-db70d8cd-5730-4908-9f1d-c7b25dd015ed
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1135849729 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.1135849729
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.651836304
Short name T633
Test name
Test status
Simulation time 22146843470 ps
CPU time 227.06 seconds
Started Aug 11 04:54:27 PM PDT 24
Finished Aug 11 04:58:14 PM PDT 24
Peak memory 248236 kb
Host smart-0686ab5d-6e47-4e59-b253-c12fb3bdf4e0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=651836304 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.651836304
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.4120616001
Short name T196
Test name
Test status
Simulation time 450117690 ps
CPU time 29.31 seconds
Started Aug 11 04:54:25 PM PDT 24
Finished Aug 11 04:54:54 PM PDT 24
Peak memory 248140 kb
Host smart-c9d0d077-ce2b-4c53-af60-ee1c1e9e82cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41206
16001 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.4120616001
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.1987835344
Short name T57
Test name
Test status
Simulation time 526479253 ps
CPU time 27.42 seconds
Started Aug 11 04:54:19 PM PDT 24
Finished Aug 11 04:54:47 PM PDT 24
Peak memory 248228 kb
Host smart-b043f251-2428-4f1a-915e-b2fff6205b49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19878
35344 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.1987835344
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.3075946888
Short name T312
Test name
Test status
Simulation time 750872548 ps
CPU time 46.82 seconds
Started Aug 11 04:54:20 PM PDT 24
Finished Aug 11 04:55:07 PM PDT 24
Peak memory 249228 kb
Host smart-5c824c6d-47c1-441d-a1e5-de6e9a2b349a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30759
46888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.3075946888
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.413164010
Short name T546
Test name
Test status
Simulation time 3244239076 ps
CPU time 17.81 seconds
Started Aug 11 04:54:25 PM PDT 24
Finished Aug 11 04:54:43 PM PDT 24
Peak memory 248432 kb
Host smart-fa78790e-aaf1-4deb-bb00-583a42b8876b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41316
4010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.413164010
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all_with_rand_reset.898644055
Short name T43
Test name
Test status
Simulation time 55224604218 ps
CPU time 4198.96 seconds
Started Aug 11 04:54:28 PM PDT 24
Finished Aug 11 06:04:28 PM PDT 24
Peak memory 297552 kb
Host smart-dd0712ce-4762-4667-aa60-71a12e55852d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=898644055 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 29.alert_handler_stress_all_with_rand_reset.898644055
Directory /workspace/29.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.1681224539
Short name T217
Test name
Test status
Simulation time 14519268 ps
CPU time 2.72 seconds
Started Aug 11 04:53:14 PM PDT 24
Finished Aug 11 04:53:16 PM PDT 24
Peak memory 248420 kb
Host smart-756c3570-3fbf-42d0-8643-8c7825bd2138
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1681224539 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.1681224539
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.2720100044
Short name T281
Test name
Test status
Simulation time 84628557969 ps
CPU time 1593 seconds
Started Aug 11 04:53:13 PM PDT 24
Finished Aug 11 05:19:47 PM PDT 24
Peak memory 288132 kb
Host smart-e2c899cf-cdcc-490a-9376-168ecc3a5e22
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2720100044 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.2720100044
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.1129404412
Short name T576
Test name
Test status
Simulation time 1037803975 ps
CPU time 45.49 seconds
Started Aug 11 04:53:19 PM PDT 24
Finished Aug 11 04:54:05 PM PDT 24
Peak memory 248176 kb
Host smart-c9343670-d6d2-4a20-a814-4cacb91b9f74
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1129404412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.1129404412
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.882597064
Short name T619
Test name
Test status
Simulation time 4194279550 ps
CPU time 50.94 seconds
Started Aug 11 04:53:15 PM PDT 24
Finished Aug 11 04:54:06 PM PDT 24
Peak memory 255528 kb
Host smart-57d5c047-b4f6-4128-bb5e-ff7fc3626404
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88259
7064 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.882597064
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.2470412254
Short name T600
Test name
Test status
Simulation time 4589936445 ps
CPU time 46.82 seconds
Started Aug 11 04:53:18 PM PDT 24
Finished Aug 11 04:54:05 PM PDT 24
Peak memory 248320 kb
Host smart-1ad7c773-72a1-43bf-849d-8c9cb56c7428
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24704
12254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.2470412254
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.3487638483
Short name T412
Test name
Test status
Simulation time 10208520971 ps
CPU time 1236.31 seconds
Started Aug 11 04:53:15 PM PDT 24
Finished Aug 11 05:13:52 PM PDT 24
Peak memory 283128 kb
Host smart-fd2c25c4-79d5-4d37-b0ea-485855b12c26
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3487638483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.3487638483
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.606055976
Short name T453
Test name
Test status
Simulation time 29783210323 ps
CPU time 1362.03 seconds
Started Aug 11 04:53:13 PM PDT 24
Finished Aug 11 05:15:55 PM PDT 24
Peak memory 288364 kb
Host smart-12e62615-1c61-49bc-92ab-9ec376802681
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606055976 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.606055976
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.1812099541
Short name T599
Test name
Test status
Simulation time 35508942441 ps
CPU time 350.53 seconds
Started Aug 11 04:53:16 PM PDT 24
Finished Aug 11 04:59:07 PM PDT 24
Peak memory 248256 kb
Host smart-0cc73278-878f-4a79-bcb7-e99a2edc1c8c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1812099541 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.1812099541
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.678911564
Short name T483
Test name
Test status
Simulation time 11895938720 ps
CPU time 45.83 seconds
Started Aug 11 04:53:14 PM PDT 24
Finished Aug 11 04:54:00 PM PDT 24
Peak memory 255476 kb
Host smart-999d62ec-989d-4c15-90f2-12315ea20847
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67891
1564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.678911564
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.4215636885
Short name T434
Test name
Test status
Simulation time 1676577956 ps
CPU time 40.82 seconds
Started Aug 11 04:53:15 PM PDT 24
Finished Aug 11 04:53:55 PM PDT 24
Peak memory 248104 kb
Host smart-7d82042d-f880-4e47-a55b-b600176ed25e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42156
36885 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.4215636885
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.2488706393
Short name T296
Test name
Test status
Simulation time 2570322710 ps
CPU time 43.38 seconds
Started Aug 11 04:53:18 PM PDT 24
Finished Aug 11 04:54:01 PM PDT 24
Peak memory 255792 kb
Host smart-9587cfe7-2948-44ad-941b-dbc2eb2a8e37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24887
06393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.2488706393
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.1308760204
Short name T673
Test name
Test status
Simulation time 4993670252 ps
CPU time 67.15 seconds
Started Aug 11 04:53:19 PM PDT 24
Finished Aug 11 04:54:26 PM PDT 24
Peak memory 256352 kb
Host smart-6953766e-cee4-49b4-a6d5-2f16a19b9500
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13087
60204 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.1308760204
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.329409097
Short name T279
Test name
Test status
Simulation time 31710095940 ps
CPU time 1531.71 seconds
Started Aug 11 04:53:16 PM PDT 24
Finished Aug 11 05:18:48 PM PDT 24
Peak memory 289232 kb
Host smart-8318842f-c711-4ad7-a05c-a1932c78ef6b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=329409097 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_hand
ler_stress_all.329409097
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.2691839315
Short name T632
Test name
Test status
Simulation time 44570369619 ps
CPU time 2402.5 seconds
Started Aug 11 04:54:27 PM PDT 24
Finished Aug 11 05:34:30 PM PDT 24
Peak memory 284708 kb
Host smart-91740139-f4c2-431e-9ec2-89203f3dba08
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2691839315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.2691839315
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.4146353632
Short name T409
Test name
Test status
Simulation time 6044538695 ps
CPU time 117.71 seconds
Started Aug 11 04:54:28 PM PDT 24
Finished Aug 11 04:56:25 PM PDT 24
Peak memory 256484 kb
Host smart-f8b63446-ea03-4c97-b22a-8e062e7a8009
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41463
53632 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.4146353632
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.2045155171
Short name T666
Test name
Test status
Simulation time 1309923698 ps
CPU time 22.42 seconds
Started Aug 11 04:54:27 PM PDT 24
Finished Aug 11 04:54:50 PM PDT 24
Peak memory 247680 kb
Host smart-908be00e-db0b-4d28-8fe1-a0568b53287c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20451
55171 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.2045155171
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.797904178
Short name T347
Test name
Test status
Simulation time 36197800363 ps
CPU time 2211.35 seconds
Started Aug 11 04:54:28 PM PDT 24
Finished Aug 11 05:31:20 PM PDT 24
Peak memory 272380 kb
Host smart-4309462f-a188-4758-90ce-454ab1e9e11e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=797904178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.797904178
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.3149453143
Short name T99
Test name
Test status
Simulation time 103261143354 ps
CPU time 1502.44 seconds
Started Aug 11 04:54:27 PM PDT 24
Finished Aug 11 05:19:30 PM PDT 24
Peak memory 264660 kb
Host smart-c4fc8c4e-c48a-49e1-b10a-deb45876a431
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3149453143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.3149453143
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.2013445882
Short name T320
Test name
Test status
Simulation time 31597185702 ps
CPU time 340.92 seconds
Started Aug 11 04:54:26 PM PDT 24
Finished Aug 11 05:00:08 PM PDT 24
Peak memory 248224 kb
Host smart-e46a6e8b-825d-4736-8c67-eaba704ba889
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013445882 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.2013445882
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.1038365545
Short name T384
Test name
Test status
Simulation time 55049797 ps
CPU time 3.24 seconds
Started Aug 11 04:54:26 PM PDT 24
Finished Aug 11 04:54:30 PM PDT 24
Peak memory 250320 kb
Host smart-7880dcec-a478-4c81-8b43-54e59394ceff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10383
65545 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.1038365545
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.1021214251
Short name T369
Test name
Test status
Simulation time 3239669395 ps
CPU time 50.15 seconds
Started Aug 11 04:54:29 PM PDT 24
Finished Aug 11 04:55:19 PM PDT 24
Peak memory 255988 kb
Host smart-e4cabeac-98fd-4182-a93f-2f12ca5fbcc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10212
14251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.1021214251
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.1942031482
Short name T55
Test name
Test status
Simulation time 16514081915 ps
CPU time 78.33 seconds
Started Aug 11 04:54:27 PM PDT 24
Finished Aug 11 04:55:45 PM PDT 24
Peak memory 248860 kb
Host smart-73be969e-5000-40b1-9333-992f583d3b46
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19420
31482 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.1942031482
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.476782189
Short name T506
Test name
Test status
Simulation time 1121542065 ps
CPU time 71.32 seconds
Started Aug 11 04:54:28 PM PDT 24
Finished Aug 11 04:55:39 PM PDT 24
Peak memory 256372 kb
Host smart-6f53ce1b-450f-46ba-84c2-62ecd3bb8d96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47678
2189 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.476782189
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.4176370516
Short name T638
Test name
Test status
Simulation time 7016582338 ps
CPU time 133.28 seconds
Started Aug 11 04:54:27 PM PDT 24
Finished Aug 11 04:56:40 PM PDT 24
Peak memory 256412 kb
Host smart-82f40dc9-2352-43ee-b41e-cb0429385e4c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176370516 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_ha
ndler_stress_all.4176370516
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.1317855318
Short name T580
Test name
Test status
Simulation time 9381411890 ps
CPU time 885.76 seconds
Started Aug 11 04:54:33 PM PDT 24
Finished Aug 11 05:09:19 PM PDT 24
Peak memory 272748 kb
Host smart-3ba2b94b-5921-48dd-8bb9-ddc4efbfde0a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1317855318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.1317855318
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.957682369
Short name T70
Test name
Test status
Simulation time 3089176809 ps
CPU time 210.94 seconds
Started Aug 11 04:54:33 PM PDT 24
Finished Aug 11 04:58:04 PM PDT 24
Peak memory 256808 kb
Host smart-82cb59b5-d87d-4f12-ae7b-312aa3c37f48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95768
2369 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.957682369
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.1381474555
Short name T504
Test name
Test status
Simulation time 5801697282 ps
CPU time 45.19 seconds
Started Aug 11 04:54:27 PM PDT 24
Finished Aug 11 04:55:13 PM PDT 24
Peak memory 248320 kb
Host smart-3385b82f-9c24-47be-8a63-e8601fe1fce7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13814
74555 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.1381474555
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.1568135584
Short name T197
Test name
Test status
Simulation time 206589601242 ps
CPU time 1474.02 seconds
Started Aug 11 04:54:33 PM PDT 24
Finished Aug 11 05:19:08 PM PDT 24
Peak memory 288260 kb
Host smart-5134d6f6-84df-44cd-8e75-ed9f443d6794
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1568135584 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.1568135584
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.708983175
Short name T233
Test name
Test status
Simulation time 196366853318 ps
CPU time 1254.11 seconds
Started Aug 11 04:54:34 PM PDT 24
Finished Aug 11 05:15:28 PM PDT 24
Peak memory 289228 kb
Host smart-a2282dd8-37fe-468c-9b8f-3b2c8b3486b5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=708983175 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.708983175
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.3544602841
Short name T559
Test name
Test status
Simulation time 7759693105 ps
CPU time 325.89 seconds
Started Aug 11 04:54:34 PM PDT 24
Finished Aug 11 05:00:00 PM PDT 24
Peak memory 248244 kb
Host smart-4656c7a6-cb5e-4b5b-9373-48d21d3d7d0b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3544602841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.3544602841
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.3082435888
Short name T419
Test name
Test status
Simulation time 1101629929 ps
CPU time 35.75 seconds
Started Aug 11 04:54:29 PM PDT 24
Finished Aug 11 04:55:05 PM PDT 24
Peak memory 248172 kb
Host smart-48dc8862-9196-4061-af96-dfb617e3ee98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30824
35888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.3082435888
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.1696187722
Short name T507
Test name
Test status
Simulation time 485318738 ps
CPU time 11.66 seconds
Started Aug 11 04:54:26 PM PDT 24
Finished Aug 11 04:54:37 PM PDT 24
Peak memory 255432 kb
Host smart-4926668e-92d5-4a45-8cd8-5bb87eb0b695
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16961
87722 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.1696187722
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.93765621
Short name T108
Test name
Test status
Simulation time 504805240 ps
CPU time 31.97 seconds
Started Aug 11 04:54:27 PM PDT 24
Finished Aug 11 04:54:59 PM PDT 24
Peak memory 255412 kb
Host smart-1a7725e6-2708-4e02-8989-35f9fc21b33c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93765
621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.93765621
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.3730571946
Short name T270
Test name
Test status
Simulation time 75653970697 ps
CPU time 2296.97 seconds
Started Aug 11 04:54:33 PM PDT 24
Finished Aug 11 05:32:50 PM PDT 24
Peak memory 289164 kb
Host smart-b4e7c841-5f20-4fed-bed9-89b26663c164
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3730571946 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_ha
ndler_stress_all.3730571946
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all_with_rand_reset.3673056168
Short name T259
Test name
Test status
Simulation time 50223264195 ps
CPU time 3221.81 seconds
Started Aug 11 04:54:34 PM PDT 24
Finished Aug 11 05:48:16 PM PDT 24
Peak memory 305760 kb
Host smart-2b3980c6-1bbb-4a37-9870-d218e5515775
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3673056168 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 31.alert_handler_stress_all_with_rand_reset.3673056168
Directory /workspace/31.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.3403627149
Short name T604
Test name
Test status
Simulation time 14511563598 ps
CPU time 756.61 seconds
Started Aug 11 04:54:37 PM PDT 24
Finished Aug 11 05:07:14 PM PDT 24
Peak memory 267756 kb
Host smart-dbda71f2-6a9a-40e1-a187-d9564cafe137
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3403627149 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.3403627149
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.3197610813
Short name T399
Test name
Test status
Simulation time 12811130958 ps
CPU time 209.02 seconds
Started Aug 11 04:54:35 PM PDT 24
Finished Aug 11 04:58:04 PM PDT 24
Peak memory 256368 kb
Host smart-69c7c116-cbea-4411-844a-256f40d18a40
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31976
10813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.3197610813
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.665266337
Short name T377
Test name
Test status
Simulation time 193814669 ps
CPU time 2.95 seconds
Started Aug 11 04:54:34 PM PDT 24
Finished Aug 11 04:54:37 PM PDT 24
Peak memory 240044 kb
Host smart-b68f6a8a-af92-4242-9dbd-ae1716e4b92e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66526
6337 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.665266337
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.3471306259
Short name T650
Test name
Test status
Simulation time 30351767270 ps
CPU time 1230.97 seconds
Started Aug 11 04:54:32 PM PDT 24
Finished Aug 11 05:15:03 PM PDT 24
Peak memory 285500 kb
Host smart-f1c7c880-6fd0-4b15-9ca5-5e7304b78db0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3471306259 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.3471306259
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.541303463
Short name T503
Test name
Test status
Simulation time 31269771899 ps
CPU time 874.56 seconds
Started Aug 11 04:54:37 PM PDT 24
Finished Aug 11 05:09:12 PM PDT 24
Peak memory 282104 kb
Host smart-cf90f15c-82aa-4755-9ffd-0932d78b66a0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=541303463 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.541303463
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.1189425199
Short name T639
Test name
Test status
Simulation time 3804496220 ps
CPU time 24.71 seconds
Started Aug 11 04:54:35 PM PDT 24
Finished Aug 11 04:55:00 PM PDT 24
Peak memory 256328 kb
Host smart-fb6bc562-d995-43d0-a31a-1317c1bc53e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11894
25199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.1189425199
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.1777106191
Short name T660
Test name
Test status
Simulation time 1896470592 ps
CPU time 34 seconds
Started Aug 11 04:54:33 PM PDT 24
Finished Aug 11 04:55:07 PM PDT 24
Peak memory 248168 kb
Host smart-f864622c-be57-4196-90c1-472b0d8fe129
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17771
06191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.1777106191
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.1534078492
Short name T569
Test name
Test status
Simulation time 500497466 ps
CPU time 34.24 seconds
Started Aug 11 04:54:37 PM PDT 24
Finished Aug 11 04:55:12 PM PDT 24
Peak memory 248136 kb
Host smart-51cc779f-0a74-4f5f-b270-7e361ae836ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15340
78492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.1534078492
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.3619441314
Short name T12
Test name
Test status
Simulation time 2237166777 ps
CPU time 40.93 seconds
Started Aug 11 04:54:36 PM PDT 24
Finished Aug 11 04:55:17 PM PDT 24
Peak memory 256452 kb
Host smart-e13f64ba-6eb6-4235-9844-23b52f48be04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36194
41314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.3619441314
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.491274601
Short name T267
Test name
Test status
Simulation time 62745778686 ps
CPU time 1361.1 seconds
Started Aug 11 04:54:34 PM PDT 24
Finished Aug 11 05:17:15 PM PDT 24
Peak memory 288772 kb
Host smart-ecafc405-8d5d-41ea-b4ce-bc9ecde4d73c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=491274601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_han
dler_stress_all.491274601
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all_with_rand_reset.571507163
Short name T29
Test name
Test status
Simulation time 452510004985 ps
CPU time 10666.6 seconds
Started Aug 11 04:54:32 PM PDT 24
Finished Aug 11 07:52:20 PM PDT 24
Peak memory 363104 kb
Host smart-9cfb9291-8564-4296-956d-618ac24875cd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=571507163 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 32.alert_handler_stress_all_with_rand_reset.571507163
Directory /workspace/32.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.2284863121
Short name T475
Test name
Test status
Simulation time 114706249623 ps
CPU time 1238.9 seconds
Started Aug 11 04:54:44 PM PDT 24
Finished Aug 11 05:15:23 PM PDT 24
Peak memory 281808 kb
Host smart-214580db-d63f-4bcb-811e-da5e5cea1574
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2284863121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.2284863121
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.2121402338
Short name T261
Test name
Test status
Simulation time 4557127067 ps
CPU time 236.13 seconds
Started Aug 11 04:54:34 PM PDT 24
Finished Aug 11 04:58:30 PM PDT 24
Peak memory 256372 kb
Host smart-a7723e78-2f9d-4cdd-9830-3c0fdfdd6bc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21214
02338 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.2121402338
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.1622989658
Short name T289
Test name
Test status
Simulation time 479902103 ps
CPU time 29.74 seconds
Started Aug 11 04:54:35 PM PDT 24
Finished Aug 11 04:55:05 PM PDT 24
Peak memory 247604 kb
Host smart-44e8c797-dc7e-4a61-80e1-41a1b19ef60f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16229
89658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.1622989658
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.386655675
Short name T700
Test name
Test status
Simulation time 9009780909 ps
CPU time 935.71 seconds
Started Aug 11 04:54:44 PM PDT 24
Finished Aug 11 05:10:20 PM PDT 24
Peak memory 272132 kb
Host smart-3070f0d0-7ca1-4828-bcb2-720dceb04111
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=386655675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.386655675
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.1548798812
Short name T532
Test name
Test status
Simulation time 16697560269 ps
CPU time 1756.24 seconds
Started Aug 11 04:54:44 PM PDT 24
Finished Aug 11 05:24:00 PM PDT 24
Peak memory 288788 kb
Host smart-cf800385-0fb1-4f5c-8f1e-32fe38249cc2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548798812 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.1548798812
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.3905215812
Short name T629
Test name
Test status
Simulation time 5791016411 ps
CPU time 254.48 seconds
Started Aug 11 04:54:43 PM PDT 24
Finished Aug 11 04:58:58 PM PDT 24
Peak memory 247920 kb
Host smart-271c7d06-75be-4bd0-b0fa-05199ee1c0af
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3905215812 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.3905215812
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.449675651
Short name T473
Test name
Test status
Simulation time 900076610 ps
CPU time 46.14 seconds
Started Aug 11 04:54:34 PM PDT 24
Finished Aug 11 04:55:21 PM PDT 24
Peak memory 248304 kb
Host smart-d25e721d-8cb2-4beb-ae00-ff359d0e4f14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44967
5651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.449675651
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.2508282651
Short name T22
Test name
Test status
Simulation time 176689369 ps
CPU time 12.64 seconds
Started Aug 11 04:54:34 PM PDT 24
Finished Aug 11 04:54:46 PM PDT 24
Peak memory 247772 kb
Host smart-f27701ed-2a22-42ab-8ff5-72c1371fced6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25082
82651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.2508282651
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.1303463295
Short name T689
Test name
Test status
Simulation time 89373273 ps
CPU time 11.63 seconds
Started Aug 11 04:54:44 PM PDT 24
Finished Aug 11 04:54:56 PM PDT 24
Peak memory 248608 kb
Host smart-f72bd649-f66d-4e8a-be9a-eea5bcf39572
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13034
63295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.1303463295
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.4234356272
Short name T424
Test name
Test status
Simulation time 134687738 ps
CPU time 5.51 seconds
Started Aug 11 04:54:35 PM PDT 24
Finished Aug 11 04:54:40 PM PDT 24
Peak memory 252960 kb
Host smart-a3962332-b824-4ac1-bd70-9070f661cc45
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42343
56272 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.4234356272
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.1704196945
Short name T575
Test name
Test status
Simulation time 18407753644 ps
CPU time 109.8 seconds
Started Aug 11 04:54:44 PM PDT 24
Finished Aug 11 04:56:34 PM PDT 24
Peak memory 256464 kb
Host smart-4a3d0103-d92c-4cb3-99f8-717cc4962bdb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1704196945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_ha
ndler_stress_all.1704196945
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.2062367594
Short name T587
Test name
Test status
Simulation time 27042772812 ps
CPU time 749.37 seconds
Started Aug 11 04:54:44 PM PDT 24
Finished Aug 11 05:07:13 PM PDT 24
Peak memory 272200 kb
Host smart-8843e97d-2cbc-4830-85e9-257bf0665ec9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2062367594 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.2062367594
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.1452103736
Short name T383
Test name
Test status
Simulation time 10033227320 ps
CPU time 103.55 seconds
Started Aug 11 04:54:44 PM PDT 24
Finished Aug 11 04:56:27 PM PDT 24
Peak memory 256452 kb
Host smart-ad46f9e9-63c9-43b1-8369-dcfba22b94f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14521
03736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.1452103736
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.397882523
Short name T79
Test name
Test status
Simulation time 1143089071 ps
CPU time 69.26 seconds
Started Aug 11 04:54:43 PM PDT 24
Finished Aug 11 04:55:53 PM PDT 24
Peak memory 255612 kb
Host smart-9be2cafb-6bb5-466d-bacf-4ba8d48e582a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39788
2523 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.397882523
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.2060102510
Short name T73
Test name
Test status
Simulation time 25029268043 ps
CPU time 1317.73 seconds
Started Aug 11 04:54:44 PM PDT 24
Finished Aug 11 05:16:42 PM PDT 24
Peak memory 286456 kb
Host smart-192b5d88-6e76-48f7-ba9f-44684a469434
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2060102510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.2060102510
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.4040961798
Short name T472
Test name
Test status
Simulation time 154568089115 ps
CPU time 2282.62 seconds
Started Aug 11 04:54:43 PM PDT 24
Finished Aug 11 05:32:45 PM PDT 24
Peak memory 283828 kb
Host smart-f645afd9-67f1-489a-9c72-f7576cd52c96
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4040961798 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.4040961798
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.4288898729
Short name T572
Test name
Test status
Simulation time 24917546604 ps
CPU time 252.29 seconds
Started Aug 11 04:54:44 PM PDT 24
Finished Aug 11 04:58:56 PM PDT 24
Peak memory 247088 kb
Host smart-87a7604a-6d06-4eb7-9c8d-6455bf2ebf26
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4288898729 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.4288898729
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.1763491235
Short name T609
Test name
Test status
Simulation time 389429970 ps
CPU time 19.69 seconds
Started Aug 11 04:54:44 PM PDT 24
Finished Aug 11 04:55:04 PM PDT 24
Peak memory 255532 kb
Host smart-c01caf98-2448-4a0f-a328-2c29bd85b910
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17634
91235 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.1763491235
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.2815126966
Short name T526
Test name
Test status
Simulation time 392215703 ps
CPU time 26.82 seconds
Started Aug 11 04:54:43 PM PDT 24
Finished Aug 11 04:55:10 PM PDT 24
Peak memory 255156 kb
Host smart-7463bbfc-fb15-4493-84e1-7c2f3cdc61c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28151
26966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.2815126966
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.2490105463
Short name T567
Test name
Test status
Simulation time 788960550 ps
CPU time 28.98 seconds
Started Aug 11 04:54:45 PM PDT 24
Finished Aug 11 04:55:14 PM PDT 24
Peak memory 247664 kb
Host smart-5dfe4d13-e280-4f4a-b740-74237ffa6fe8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24901
05463 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.2490105463
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.3474202425
Short name T570
Test name
Test status
Simulation time 1747379817 ps
CPU time 27.81 seconds
Started Aug 11 04:54:44 PM PDT 24
Finished Aug 11 04:55:12 PM PDT 24
Peak memory 255400 kb
Host smart-f746cac1-a9ba-41f7-b0e2-c170d145fdfe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34742
02425 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.3474202425
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.450583801
Short name T117
Test name
Test status
Simulation time 27116314132 ps
CPU time 1861.47 seconds
Started Aug 11 04:54:44 PM PDT 24
Finished Aug 11 05:25:46 PM PDT 24
Peak memory 282760 kb
Host smart-98554674-7f2a-42fb-bb1a-36bc7b703fb0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=450583801 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_han
dler_stress_all.450583801
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.273679223
Short name T260
Test name
Test status
Simulation time 2247964590 ps
CPU time 175.04 seconds
Started Aug 11 04:54:44 PM PDT 24
Finished Aug 11 04:57:40 PM PDT 24
Peak memory 256136 kb
Host smart-ce4e0420-a248-4f4f-b15b-2c152ab7bc15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27367
9223 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.273679223
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.2686243215
Short name T584
Test name
Test status
Simulation time 110512064 ps
CPU time 12.05 seconds
Started Aug 11 04:54:45 PM PDT 24
Finished Aug 11 04:54:57 PM PDT 24
Peak memory 247696 kb
Host smart-f96cba90-8e95-40ab-ae5f-517d994a238a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26862
43215 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.2686243215
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.3302099532
Short name T681
Test name
Test status
Simulation time 79690734660 ps
CPU time 987.18 seconds
Started Aug 11 04:54:49 PM PDT 24
Finished Aug 11 05:11:16 PM PDT 24
Peak memory 272720 kb
Host smart-e47ffc25-ff77-4642-b43d-d2116f5dff9c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3302099532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.3302099532
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.2608068164
Short name T395
Test name
Test status
Simulation time 34597930617 ps
CPU time 911.16 seconds
Started Aug 11 04:54:51 PM PDT 24
Finished Aug 11 05:10:03 PM PDT 24
Peak memory 272828 kb
Host smart-22c89903-0b9f-4036-ac1d-19bbe0f045b3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2608068164 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.2608068164
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.4018027195
Short name T319
Test name
Test status
Simulation time 30590169855 ps
CPU time 662.5 seconds
Started Aug 11 04:54:44 PM PDT 24
Finished Aug 11 05:05:46 PM PDT 24
Peak memory 248216 kb
Host smart-007c51b5-2bd0-4016-af95-c2cd8e2b0b1f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4018027195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.4018027195
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.773240545
Short name T543
Test name
Test status
Simulation time 3034118143 ps
CPU time 44.82 seconds
Started Aug 11 04:54:44 PM PDT 24
Finished Aug 11 04:55:29 PM PDT 24
Peak memory 255444 kb
Host smart-2cf8a877-7855-4952-86f6-ae6435fab443
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77324
0545 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.773240545
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.2787423686
Short name T517
Test name
Test status
Simulation time 355867430 ps
CPU time 38.31 seconds
Started Aug 11 04:54:43 PM PDT 24
Finished Aug 11 04:55:21 PM PDT 24
Peak memory 256424 kb
Host smart-ae0f99ab-a6cf-40ca-a201-250aca7a8cbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27874
23686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.2787423686
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.3286314855
Short name T107
Test name
Test status
Simulation time 927591131 ps
CPU time 62.02 seconds
Started Aug 11 04:54:44 PM PDT 24
Finished Aug 11 04:55:46 PM PDT 24
Peak memory 256240 kb
Host smart-3c50e0c4-9d43-4594-8333-e3ca9055d6f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32863
14855 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.3286314855
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.3882536132
Short name T234
Test name
Test status
Simulation time 18068685990 ps
CPU time 64.07 seconds
Started Aug 11 04:54:43 PM PDT 24
Finished Aug 11 04:55:48 PM PDT 24
Peak memory 256388 kb
Host smart-4df7727a-0435-44b7-a349-76cbb01964f1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38825
36132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.3882536132
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all_with_rand_reset.599531111
Short name T263
Test name
Test status
Simulation time 184193862056 ps
CPU time 5367.7 seconds
Started Aug 11 04:54:49 PM PDT 24
Finished Aug 11 06:24:17 PM PDT 24
Peak memory 353804 kb
Host smart-73c2007b-3261-4d3a-b315-91b7f38a9585
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=599531111 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 35.alert_handler_stress_all_with_rand_reset.599531111
Directory /workspace/35.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.1190911820
Short name T450
Test name
Test status
Simulation time 46409996498 ps
CPU time 1241.52 seconds
Started Aug 11 04:54:52 PM PDT 24
Finished Aug 11 05:15:34 PM PDT 24
Peak memory 272712 kb
Host smart-faa11f00-6f0a-4589-99db-25fe1ed2abdd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1190911820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.1190911820
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.807939369
Short name T468
Test name
Test status
Simulation time 8669209108 ps
CPU time 122.46 seconds
Started Aug 11 04:54:48 PM PDT 24
Finished Aug 11 04:56:51 PM PDT 24
Peak memory 255980 kb
Host smart-854f56cc-195a-47f8-9502-3796a3fb9cea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80793
9369 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.807939369
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.2305922438
Short name T413
Test name
Test status
Simulation time 265043715 ps
CPU time 21.2 seconds
Started Aug 11 04:54:50 PM PDT 24
Finished Aug 11 04:55:12 PM PDT 24
Peak memory 248076 kb
Host smart-562de90a-3e05-4f4b-b309-7963a5260042
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23059
22438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.2305922438
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.2013513840
Short name T566
Test name
Test status
Simulation time 31890479769 ps
CPU time 1946.61 seconds
Started Aug 11 04:54:50 PM PDT 24
Finished Aug 11 05:27:17 PM PDT 24
Peak memory 272436 kb
Host smart-87ed8efb-8d13-4d40-886f-4db83b23ba91
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2013513840 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.2013513840
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.3129389129
Short name T328
Test name
Test status
Simulation time 63832913428 ps
CPU time 303.4 seconds
Started Aug 11 04:54:49 PM PDT 24
Finished Aug 11 04:59:52 PM PDT 24
Peak memory 247536 kb
Host smart-e9047acb-5432-4bf0-811b-5c45ff4b4fbb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129389129 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.3129389129
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.581388357
Short name T667
Test name
Test status
Simulation time 826212984 ps
CPU time 18.81 seconds
Started Aug 11 04:54:49 PM PDT 24
Finished Aug 11 04:55:08 PM PDT 24
Peak memory 256380 kb
Host smart-005f59aa-1adf-4e83-93a2-f83e811606e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58138
8357 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.581388357
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.1468279875
Short name T248
Test name
Test status
Simulation time 533908773 ps
CPU time 33.51 seconds
Started Aug 11 04:54:49 PM PDT 24
Finished Aug 11 04:55:22 PM PDT 24
Peak memory 256332 kb
Host smart-7cead380-e660-45f0-9d5c-3861fb93becc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14682
79875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.1468279875
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.1997741673
Short name T313
Test name
Test status
Simulation time 886110303 ps
CPU time 43.9 seconds
Started Aug 11 04:54:48 PM PDT 24
Finished Aug 11 04:55:32 PM PDT 24
Peak memory 255572 kb
Host smart-43d1a788-89d7-4343-a0b6-0f92fcd6b203
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19977
41673 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.1997741673
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.2401712209
Short name T590
Test name
Test status
Simulation time 1011725608 ps
CPU time 18.29 seconds
Started Aug 11 04:54:50 PM PDT 24
Finished Aug 11 04:55:09 PM PDT 24
Peak memory 254280 kb
Host smart-a88a8e2f-031e-4bab-bb8a-6a8bc5d427e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24017
12209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.2401712209
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.1952210460
Short name T106
Test name
Test status
Simulation time 17420760147 ps
CPU time 1583.24 seconds
Started Aug 11 04:54:51 PM PDT 24
Finished Aug 11 05:21:14 PM PDT 24
Peak memory 289120 kb
Host smart-4c5c72e8-f59a-46e0-af81-7e64276bf48c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952210460 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_ha
ndler_stress_all.1952210460
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all_with_rand_reset.3290643444
Short name T206
Test name
Test status
Simulation time 68844387866 ps
CPU time 6270.67 seconds
Started Aug 11 04:54:52 PM PDT 24
Finished Aug 11 06:39:23 PM PDT 24
Peak memory 370796 kb
Host smart-4b117e7e-3a17-415c-b18d-6b78c73d612e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3290643444 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.alert_handler_stress_all_with_rand_reset.3290643444
Directory /workspace/36.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.2306298847
Short name T545
Test name
Test status
Simulation time 18365776864 ps
CPU time 1405.96 seconds
Started Aug 11 04:54:51 PM PDT 24
Finished Aug 11 05:18:17 PM PDT 24
Peak memory 288416 kb
Host smart-183ddf40-b6ee-46e6-b5f2-7547f0c807e0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2306298847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.2306298847
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.1612184545
Short name T125
Test name
Test status
Simulation time 1757133785 ps
CPU time 42.36 seconds
Started Aug 11 04:54:50 PM PDT 24
Finished Aug 11 04:55:32 PM PDT 24
Peak memory 255940 kb
Host smart-5d61ef52-4c07-4d2d-9007-fbf7bfbf126c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16121
84545 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.1612184545
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.1568253105
Short name T77
Test name
Test status
Simulation time 90805797 ps
CPU time 11.39 seconds
Started Aug 11 04:54:52 PM PDT 24
Finished Aug 11 04:55:03 PM PDT 24
Peak memory 248148 kb
Host smart-403515a9-5a1c-4d4e-804e-512cabd00d51
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15682
53105 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.1568253105
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.459940138
Short name T655
Test name
Test status
Simulation time 15756021842 ps
CPU time 1504.84 seconds
Started Aug 11 04:54:56 PM PDT 24
Finished Aug 11 05:20:01 PM PDT 24
Peak memory 288480 kb
Host smart-62b1d417-c6fe-4a95-966d-cf1992364b2e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=459940138 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.459940138
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.4215725688
Short name T127
Test name
Test status
Simulation time 21449757276 ps
CPU time 1566.3 seconds
Started Aug 11 04:54:57 PM PDT 24
Finished Aug 11 05:21:03 PM PDT 24
Peak memory 288872 kb
Host smart-61fd6608-649c-4ff4-b053-4aa0dab60bb0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4215725688 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.4215725688
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.1751862135
Short name T15
Test name
Test status
Simulation time 23896165253 ps
CPU time 263.73 seconds
Started Aug 11 04:54:51 PM PDT 24
Finished Aug 11 04:59:15 PM PDT 24
Peak memory 254816 kb
Host smart-b49aca30-ebef-4cd7-9726-bb6946902ecb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1751862135 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.1751862135
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.2587226894
Short name T648
Test name
Test status
Simulation time 3340341470 ps
CPU time 58.73 seconds
Started Aug 11 04:54:50 PM PDT 24
Finished Aug 11 04:55:49 PM PDT 24
Peak memory 255728 kb
Host smart-15d1cead-61ea-4e83-8e33-b09b1aedf72e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25872
26894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.2587226894
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.2934121571
Short name T374
Test name
Test status
Simulation time 1140956130 ps
CPU time 61.43 seconds
Started Aug 11 04:54:48 PM PDT 24
Finished Aug 11 04:55:50 PM PDT 24
Peak memory 256324 kb
Host smart-b782cb88-6ea1-4b35-b91f-645d9c15052f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29341
21571 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.2934121571
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.1580893308
Short name T551
Test name
Test status
Simulation time 3180368914 ps
CPU time 50.15 seconds
Started Aug 11 04:54:50 PM PDT 24
Finished Aug 11 04:55:41 PM PDT 24
Peak memory 247804 kb
Host smart-f9c45eab-3618-44f9-b84a-b0141bde254a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15808
93308 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.1580893308
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.254579898
Short name T512
Test name
Test status
Simulation time 241630599 ps
CPU time 17.82 seconds
Started Aug 11 04:54:51 PM PDT 24
Finished Aug 11 04:55:09 PM PDT 24
Peak memory 256372 kb
Host smart-9b87bed7-3453-4421-ace3-a67f2a387793
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25457
9898 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.254579898
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.3660409687
Short name T521
Test name
Test status
Simulation time 67766846919 ps
CPU time 3849.5 seconds
Started Aug 11 04:54:56 PM PDT 24
Finished Aug 11 05:59:06 PM PDT 24
Peak memory 305748 kb
Host smart-ebbfab25-b434-417e-aff5-62b1cd429824
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660409687 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_ha
ndler_stress_all.3660409687
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all_with_rand_reset.3721918718
Short name T280
Test name
Test status
Simulation time 45347278113 ps
CPU time 3657.63 seconds
Started Aug 11 04:54:55 PM PDT 24
Finished Aug 11 05:55:53 PM PDT 24
Peak memory 297336 kb
Host smart-d606ad6e-4ee9-4dfb-b0eb-530fa30b6387
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3721918718 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 37.alert_handler_stress_all_with_rand_reset.3721918718
Directory /workspace/37.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.897585125
Short name T128
Test name
Test status
Simulation time 52948263300 ps
CPU time 769.71 seconds
Started Aug 11 04:54:56 PM PDT 24
Finished Aug 11 05:07:46 PM PDT 24
Peak memory 264652 kb
Host smart-1a8a90dd-b10b-42b5-b79a-1e5a81a9d530
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=897585125 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.897585125
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.319563731
Short name T510
Test name
Test status
Simulation time 431468810 ps
CPU time 51.37 seconds
Started Aug 11 04:55:00 PM PDT 24
Finished Aug 11 04:55:51 PM PDT 24
Peak memory 256324 kb
Host smart-1c06f5e0-0c39-4db3-ac53-f73929299ebe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31956
3731 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.319563731
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.1687497138
Short name T403
Test name
Test status
Simulation time 10109699408 ps
CPU time 50.93 seconds
Started Aug 11 04:54:55 PM PDT 24
Finished Aug 11 04:55:46 PM PDT 24
Peak memory 249228 kb
Host smart-f9d72f98-e416-474d-95ea-2ff64fc27207
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16874
97138 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.1687497138
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.3051221559
Short name T269
Test name
Test status
Simulation time 11252768044 ps
CPU time 934.97 seconds
Started Aug 11 04:54:57 PM PDT 24
Finished Aug 11 05:10:32 PM PDT 24
Peak memory 272840 kb
Host smart-41c57427-b245-4fe6-97b9-20c6c2fbb767
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3051221559 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.3051221559
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.2869742860
Short name T634
Test name
Test status
Simulation time 20689603355 ps
CPU time 225.11 seconds
Started Aug 11 04:54:56 PM PDT 24
Finished Aug 11 04:58:41 PM PDT 24
Peak memory 255152 kb
Host smart-0f0194bf-e1e0-46b4-8e1d-4b0e5635e97c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2869742860 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.2869742860
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.276243531
Short name T396
Test name
Test status
Simulation time 823754289 ps
CPU time 17.5 seconds
Started Aug 11 04:54:56 PM PDT 24
Finished Aug 11 04:55:14 PM PDT 24
Peak memory 255392 kb
Host smart-26172961-e12b-4b43-8502-8e7be428b51f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27624
3531 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.276243531
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.2635617509
Short name T46
Test name
Test status
Simulation time 1023160308 ps
CPU time 20.39 seconds
Started Aug 11 04:54:58 PM PDT 24
Finished Aug 11 04:55:18 PM PDT 24
Peak memory 247476 kb
Host smart-83f6ca75-0a4d-425c-b4b1-a23cabf33cf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26356
17509 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.2635617509
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.2057341105
Short name T367
Test name
Test status
Simulation time 83160401 ps
CPU time 7 seconds
Started Aug 11 04:55:00 PM PDT 24
Finished Aug 11 04:55:07 PM PDT 24
Peak memory 248556 kb
Host smart-253b6582-a65d-42f9-b702-2c4794c9fa2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20573
41105 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.2057341105
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.102166448
Short name T675
Test name
Test status
Simulation time 788300763 ps
CPU time 17.34 seconds
Started Aug 11 04:54:58 PM PDT 24
Finished Aug 11 04:55:15 PM PDT 24
Peak memory 248120 kb
Host smart-9ce85c8d-db6f-41b8-a29b-3f9d17611f5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10216
6448 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.102166448
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.172558953
Short name T285
Test name
Test status
Simulation time 78311178893 ps
CPU time 1233.32 seconds
Started Aug 11 04:54:58 PM PDT 24
Finished Aug 11 05:15:32 PM PDT 24
Peak memory 287432 kb
Host smart-d98ecf6d-2a96-4b39-a237-227907695b39
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=172558953 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_han
dler_stress_all.172558953
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.2687608745
Short name T254
Test name
Test status
Simulation time 43702552909 ps
CPU time 1623.05 seconds
Started Aug 11 04:54:56 PM PDT 24
Finished Aug 11 05:21:59 PM PDT 24
Peak memory 272804 kb
Host smart-abcfc56b-b350-4665-990a-1cefbe58268e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2687608745 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.2687608745
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.2900787579
Short name T393
Test name
Test status
Simulation time 438745214 ps
CPU time 16.88 seconds
Started Aug 11 04:54:56 PM PDT 24
Finished Aug 11 04:55:13 PM PDT 24
Peak memory 255904 kb
Host smart-c628de71-5b5e-46d6-9bc3-6202fbc38e8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29007
87579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.2900787579
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.1036649764
Short name T62
Test name
Test status
Simulation time 228776051 ps
CPU time 11.45 seconds
Started Aug 11 04:54:56 PM PDT 24
Finished Aug 11 04:55:08 PM PDT 24
Peak memory 248192 kb
Host smart-9c3a40cc-7257-4ba5-bac1-23bc495a8261
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10366
49764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.1036649764
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.2876369329
Short name T630
Test name
Test status
Simulation time 42392222381 ps
CPU time 2588.96 seconds
Started Aug 11 04:54:58 PM PDT 24
Finished Aug 11 05:38:07 PM PDT 24
Peak memory 283244 kb
Host smart-8c399bd3-4b9a-4a20-a197-e8f0d76bba6f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2876369329 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.2876369329
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.1204138914
Short name T394
Test name
Test status
Simulation time 31215691817 ps
CPU time 2049.25 seconds
Started Aug 11 04:54:59 PM PDT 24
Finished Aug 11 05:29:08 PM PDT 24
Peak memory 284872 kb
Host smart-dd780500-3a2c-43b2-97df-82ffa843cbf2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1204138914 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.1204138914
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.1063689677
Short name T696
Test name
Test status
Simulation time 14691252068 ps
CPU time 282.45 seconds
Started Aug 11 04:54:56 PM PDT 24
Finished Aug 11 04:59:39 PM PDT 24
Peak memory 247084 kb
Host smart-72273573-23cb-4211-998f-5f63cc9b80b7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1063689677 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.1063689677
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.3833861138
Short name T391
Test name
Test status
Simulation time 8640914356 ps
CPU time 43.15 seconds
Started Aug 11 04:54:56 PM PDT 24
Finished Aug 11 04:55:39 PM PDT 24
Peak memory 256412 kb
Host smart-18fed560-22a1-4fa9-9f23-260e0d24802d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38338
61138 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.3833861138
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.362346561
Short name T38
Test name
Test status
Simulation time 271464966 ps
CPU time 21.58 seconds
Started Aug 11 04:54:55 PM PDT 24
Finished Aug 11 04:55:16 PM PDT 24
Peak memory 248108 kb
Host smart-2321e1ef-e026-498e-a971-49a78b70f5a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36234
6561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.362346561
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.1762458655
Short name T469
Test name
Test status
Simulation time 460305550 ps
CPU time 14.74 seconds
Started Aug 11 04:54:56 PM PDT 24
Finished Aug 11 04:55:11 PM PDT 24
Peak memory 247528 kb
Host smart-44dabce4-0230-4612-b001-285f6c1d4dac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17624
58655 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.1762458655
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.2976956111
Short name T664
Test name
Test status
Simulation time 1435787624 ps
CPU time 30.56 seconds
Started Aug 11 04:54:56 PM PDT 24
Finished Aug 11 04:55:27 PM PDT 24
Peak memory 256368 kb
Host smart-db59fc5c-b874-4c14-9494-bab148abf0a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29769
56111 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.2976956111
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.1615834491
Short name T643
Test name
Test status
Simulation time 2462290860 ps
CPU time 275.23 seconds
Started Aug 11 04:55:02 PM PDT 24
Finished Aug 11 04:59:37 PM PDT 24
Peak memory 256488 kb
Host smart-443b64a6-6595-4926-880a-ab7daf38ef8c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1615834491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_ha
ndler_stress_all.1615834491
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.320983608
Short name T225
Test name
Test status
Simulation time 104688104 ps
CPU time 3.27 seconds
Started Aug 11 04:53:16 PM PDT 24
Finished Aug 11 04:53:20 PM PDT 24
Peak memory 248484 kb
Host smart-5412eb2f-dcbd-4175-8205-01130fdfb1c5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=320983608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.320983608
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.495017433
Short name T382
Test name
Test status
Simulation time 3742861558 ps
CPU time 206.52 seconds
Started Aug 11 04:53:15 PM PDT 24
Finished Aug 11 04:56:41 PM PDT 24
Peak memory 256792 kb
Host smart-427e38ad-e715-4ce9-9488-be1d8fc6d8eb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=49501
7433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.495017433
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.1700509356
Short name T665
Test name
Test status
Simulation time 509413975 ps
CPU time 29.2 seconds
Started Aug 11 04:53:17 PM PDT 24
Finished Aug 11 04:53:46 PM PDT 24
Peak memory 255728 kb
Host smart-883342c6-c5db-4ec6-aa58-e98392387c6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17005
09356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.1700509356
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.4106528744
Short name T241
Test name
Test status
Simulation time 178720664460 ps
CPU time 2472.64 seconds
Started Aug 11 04:53:17 PM PDT 24
Finished Aug 11 05:34:30 PM PDT 24
Peak memory 288872 kb
Host smart-3fd49421-c47d-4b88-88b6-5fb48f41a914
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4106528744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.4106528744
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.594266735
Short name T40
Test name
Test status
Simulation time 50744307476 ps
CPU time 2960.82 seconds
Started Aug 11 04:53:16 PM PDT 24
Finished Aug 11 05:42:37 PM PDT 24
Peak memory 288552 kb
Host smart-e72a17dd-d2bc-4aa1-9370-95bc1b6782a0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=594266735 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.594266735
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.1070586943
Short name T21
Test name
Test status
Simulation time 5329012149 ps
CPU time 49.75 seconds
Started Aug 11 04:53:15 PM PDT 24
Finished Aug 11 04:54:05 PM PDT 24
Peak memory 255728 kb
Host smart-004600c5-407c-42ea-aee1-339208e95527
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10705
86943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.1070586943
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.2067708290
Short name T131
Test name
Test status
Simulation time 1672416122 ps
CPU time 40.25 seconds
Started Aug 11 04:53:14 PM PDT 24
Finished Aug 11 04:53:55 PM PDT 24
Peak memory 255972 kb
Host smart-4174c350-2556-4bfe-a7ad-497f6b21d0ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20677
08290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.2067708290
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.4247191442
Short name T10
Test name
Test status
Simulation time 342814915 ps
CPU time 10.77 seconds
Started Aug 11 04:53:17 PM PDT 24
Finished Aug 11 04:53:28 PM PDT 24
Peak memory 273940 kb
Host smart-79a62893-ab33-4c27-9a1e-c5b26f401b64
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4247191442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.4247191442
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.865903180
Short name T308
Test name
Test status
Simulation time 626654287 ps
CPU time 45.57 seconds
Started Aug 11 04:53:14 PM PDT 24
Finished Aug 11 04:54:00 PM PDT 24
Peak memory 255484 kb
Host smart-95a9956b-9b9b-46cb-ba47-d9f78972afb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86590
3180 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.865903180
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.2845350452
Short name T242
Test name
Test status
Simulation time 747805917 ps
CPU time 17.57 seconds
Started Aug 11 04:53:18 PM PDT 24
Finished Aug 11 04:53:35 PM PDT 24
Peak memory 248172 kb
Host smart-5ae02655-6dbd-4f3a-9090-26334848638c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28453
50452 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.2845350452
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.1164471275
Short name T85
Test name
Test status
Simulation time 17075240126 ps
CPU time 244.89 seconds
Started Aug 11 04:53:16 PM PDT 24
Finished Aug 11 04:57:21 PM PDT 24
Peak memory 256452 kb
Host smart-1ffef948-f0ad-44af-b73a-8072fc799231
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1164471275 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_han
dler_stress_all.1164471275
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.3502652089
Short name T577
Test name
Test status
Simulation time 20938577766 ps
CPU time 1292.3 seconds
Started Aug 11 04:55:02 PM PDT 24
Finished Aug 11 05:16:35 PM PDT 24
Peak memory 282816 kb
Host smart-c460906b-d863-4f23-bfbc-43d23d952abd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3502652089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.3502652089
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.2633513794
Short name T444
Test name
Test status
Simulation time 14888382302 ps
CPU time 365 seconds
Started Aug 11 04:55:01 PM PDT 24
Finished Aug 11 05:01:06 PM PDT 24
Peak memory 256012 kb
Host smart-ddf83968-ce75-43dc-b359-9123332df0d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26335
13794 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.2633513794
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.149130579
Short name T544
Test name
Test status
Simulation time 233143717 ps
CPU time 25.33 seconds
Started Aug 11 04:55:03 PM PDT 24
Finished Aug 11 04:55:28 PM PDT 24
Peak memory 256044 kb
Host smart-01e31068-6a73-4a5d-b6ea-d505e27f0769
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14913
0579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.149130579
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.3891526303
Short name T411
Test name
Test status
Simulation time 31862991636 ps
CPU time 1699.48 seconds
Started Aug 11 04:55:04 PM PDT 24
Finished Aug 11 05:23:24 PM PDT 24
Peak memory 281876 kb
Host smart-987825c8-95bf-453a-b1f6-4ce4be850255
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3891526303 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.3891526303
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.4053448961
Short name T326
Test name
Test status
Simulation time 20097035509 ps
CPU time 384.24 seconds
Started Aug 11 04:55:01 PM PDT 24
Finished Aug 11 05:01:26 PM PDT 24
Peak memory 248344 kb
Host smart-906459c5-b0bf-40e1-ae83-62b602844838
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4053448961 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.4053448961
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.1551544660
Short name T550
Test name
Test status
Simulation time 668348236 ps
CPU time 36.37 seconds
Started Aug 11 04:55:01 PM PDT 24
Finished Aug 11 04:55:38 PM PDT 24
Peak memory 248204 kb
Host smart-7420b4fc-e489-49dd-8aae-3b165ebd09de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15515
44660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.1551544660
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.4053847438
Short name T51
Test name
Test status
Simulation time 829924519 ps
CPU time 50.53 seconds
Started Aug 11 04:55:01 PM PDT 24
Finished Aug 11 04:55:52 PM PDT 24
Peak memory 256392 kb
Host smart-d82bc503-bae2-4e8c-bb3e-9b249ed78382
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40538
47438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.4053847438
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.3021681120
Short name T628
Test name
Test status
Simulation time 1552845735 ps
CPU time 52.5 seconds
Started Aug 11 04:55:02 PM PDT 24
Finished Aug 11 04:55:55 PM PDT 24
Peak memory 255560 kb
Host smart-53535727-edfb-4f54-955b-c2e650dcc117
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30216
81120 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.3021681120
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.2838554978
Short name T275
Test name
Test status
Simulation time 45535199265 ps
CPU time 2747.68 seconds
Started Aug 11 04:55:02 PM PDT 24
Finished Aug 11 05:40:50 PM PDT 24
Peak memory 297092 kb
Host smart-277ae175-d481-4317-b675-8b036fe3c5ac
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838554978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_ha
ndler_stress_all.2838554978
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.320774480
Short name T677
Test name
Test status
Simulation time 40335061522 ps
CPU time 2267.54 seconds
Started Aug 11 04:55:02 PM PDT 24
Finished Aug 11 05:32:49 PM PDT 24
Peak memory 281048 kb
Host smart-686d99e2-1c22-4106-9007-4498253ff971
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320774480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.320774480
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.2546953649
Short name T498
Test name
Test status
Simulation time 12261823681 ps
CPU time 202.19 seconds
Started Aug 11 04:55:04 PM PDT 24
Finished Aug 11 04:58:26 PM PDT 24
Peak memory 255920 kb
Host smart-fe869837-f47a-413e-ab5d-4a844e992b14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25469
53649 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.2546953649
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.709492585
Short name T408
Test name
Test status
Simulation time 176232269 ps
CPU time 2.98 seconds
Started Aug 11 04:55:03 PM PDT 24
Finished Aug 11 04:55:06 PM PDT 24
Peak memory 239328 kb
Host smart-33e8f745-fe2c-4407-91c9-fc5ecc05644b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70949
2585 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.709492585
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.2763128715
Short name T594
Test name
Test status
Simulation time 44977809045 ps
CPU time 2584.5 seconds
Started Aug 11 04:55:07 PM PDT 24
Finished Aug 11 05:38:11 PM PDT 24
Peak memory 285004 kb
Host smart-2801ed05-2b36-41a4-a831-ec969aa61347
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2763128715 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.2763128715
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.3354595768
Short name T290
Test name
Test status
Simulation time 23062817848 ps
CPU time 339.33 seconds
Started Aug 11 04:55:08 PM PDT 24
Finished Aug 11 05:00:48 PM PDT 24
Peak memory 247556 kb
Host smart-694541e9-ef67-4cd8-a527-f7cce3cde8be
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3354595768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.3354595768
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.2353422093
Short name T420
Test name
Test status
Simulation time 219771535 ps
CPU time 12.29 seconds
Started Aug 11 04:55:04 PM PDT 24
Finished Aug 11 04:55:17 PM PDT 24
Peak memory 254196 kb
Host smart-fe633214-b9a7-417d-8fd1-bed7914a3268
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23534
22093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.2353422093
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.1729896075
Short name T120
Test name
Test status
Simulation time 2143050713 ps
CPU time 60.66 seconds
Started Aug 11 04:55:03 PM PDT 24
Finished Aug 11 04:56:03 PM PDT 24
Peak memory 255680 kb
Host smart-f10c2cb3-5cd5-4cf3-8a3c-c2c06646facf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17298
96075 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.1729896075
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.2324716699
Short name T601
Test name
Test status
Simulation time 202831169 ps
CPU time 22.82 seconds
Started Aug 11 04:55:04 PM PDT 24
Finished Aug 11 04:55:27 PM PDT 24
Peak memory 247728 kb
Host smart-08ca3b3e-859f-4b2e-8ddd-81501b7626a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23247
16699 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.2324716699
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.2886283259
Short name T398
Test name
Test status
Simulation time 813314052 ps
CPU time 18.48 seconds
Started Aug 11 04:55:02 PM PDT 24
Finished Aug 11 04:55:20 PM PDT 24
Peak memory 255424 kb
Host smart-2387c8a5-e96c-48f3-8380-c760f88d78b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28862
83259 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.2886283259
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.732655571
Short name T454
Test name
Test status
Simulation time 225642062 ps
CPU time 24.47 seconds
Started Aug 11 04:55:14 PM PDT 24
Finished Aug 11 04:55:38 PM PDT 24
Peak memory 247948 kb
Host smart-7d32005a-ee97-4222-82a1-3dc335ae62db
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=732655571 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_han
dler_stress_all.732655571
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all_with_rand_reset.1004247670
Short name T90
Test name
Test status
Simulation time 10199073716 ps
CPU time 1150.42 seconds
Started Aug 11 04:55:08 PM PDT 24
Finished Aug 11 05:14:18 PM PDT 24
Peak memory 288508 kb
Host smart-5ed05923-188d-4b0c-9616-9e25905d2717
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1004247670 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.alert_handler_stress_all_with_rand_reset.1004247670
Directory /workspace/41.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.3809079012
Short name T130
Test name
Test status
Simulation time 19582626426 ps
CPU time 1704.21 seconds
Started Aug 11 04:55:10 PM PDT 24
Finished Aug 11 05:23:34 PM PDT 24
Peak memory 288968 kb
Host smart-8a5ef6a8-c08c-413d-b40a-4d13ac49fd18
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3809079012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.3809079012
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.2624615528
Short name T111
Test name
Test status
Simulation time 5074562284 ps
CPU time 305.33 seconds
Started Aug 11 04:55:11 PM PDT 24
Finished Aug 11 05:00:17 PM PDT 24
Peak memory 255760 kb
Host smart-447576fc-0019-4b29-9788-34fdc6fd6299
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26246
15528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.2624615528
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.2964364434
Short name T463
Test name
Test status
Simulation time 185254203 ps
CPU time 16.29 seconds
Started Aug 11 04:55:08 PM PDT 24
Finished Aug 11 04:55:24 PM PDT 24
Peak memory 255764 kb
Host smart-33091213-dcd8-4cfa-b882-fb8d3d66dc23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29643
64434 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.2964364434
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.1059835191
Short name T351
Test name
Test status
Simulation time 342800713455 ps
CPU time 2103.69 seconds
Started Aug 11 04:55:08 PM PDT 24
Finished Aug 11 05:30:13 PM PDT 24
Peak memory 272144 kb
Host smart-3fe1a518-dad5-44f2-81f3-8420b5632c30
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1059835191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.1059835191
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.462768175
Short name T352
Test name
Test status
Simulation time 9279564316 ps
CPU time 1138.51 seconds
Started Aug 11 04:55:13 PM PDT 24
Finished Aug 11 05:14:12 PM PDT 24
Peak memory 288716 kb
Host smart-93dad4ec-1416-4959-b19a-26dd14e50910
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=462768175 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.462768175
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.2499322128
Short name T662
Test name
Test status
Simulation time 7614920786 ps
CPU time 292.34 seconds
Started Aug 11 04:55:09 PM PDT 24
Finished Aug 11 05:00:01 PM PDT 24
Peak memory 248036 kb
Host smart-0256c802-01a4-4be3-8444-d1429df2f689
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499322128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.2499322128
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.238401900
Short name T378
Test name
Test status
Simulation time 85020965 ps
CPU time 8.48 seconds
Started Aug 11 04:55:08 PM PDT 24
Finished Aug 11 04:55:16 PM PDT 24
Peak memory 254036 kb
Host smart-11b7a883-a8df-466c-adf5-ec81ef31b773
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23840
1900 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.238401900
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.598023670
Short name T508
Test name
Test status
Simulation time 1685023731 ps
CPU time 34.4 seconds
Started Aug 11 04:55:07 PM PDT 24
Finished Aug 11 04:55:41 PM PDT 24
Peak memory 256384 kb
Host smart-cdc806dc-a329-4977-bb02-38a00869ce05
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59802
3670 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.598023670
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.3771299463
Short name T547
Test name
Test status
Simulation time 248241974 ps
CPU time 17.55 seconds
Started Aug 11 04:55:09 PM PDT 24
Finished Aug 11 04:55:27 PM PDT 24
Peak memory 254364 kb
Host smart-b5a01f21-8651-4228-85b8-be319b2d4fa5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37712
99463 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.3771299463
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.2298694783
Short name T678
Test name
Test status
Simulation time 854077250 ps
CPU time 25.71 seconds
Started Aug 11 04:55:09 PM PDT 24
Finished Aug 11 04:55:34 PM PDT 24
Peak memory 256304 kb
Host smart-b9782037-e08b-4899-8366-fe19b0e2542d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22986
94783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.2298694783
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.541614761
Short name T581
Test name
Test status
Simulation time 1643341629 ps
CPU time 89.1 seconds
Started Aug 11 04:55:09 PM PDT 24
Finished Aug 11 04:56:38 PM PDT 24
Peak memory 249352 kb
Host smart-301adaa0-93b0-4483-830f-15986dda01c2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=541614761 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_han
dler_stress_all.541614761
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all_with_rand_reset.4278392705
Short name T273
Test name
Test status
Simulation time 645580479843 ps
CPU time 4097.97 seconds
Started Aug 11 04:55:08 PM PDT 24
Finished Aug 11 06:03:27 PM PDT 24
Peak memory 305640 kb
Host smart-e2f00f75-25b8-487c-8e41-1f6fd3f6b924
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4278392705 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.alert_handler_stress_all_with_rand_reset.4278392705
Directory /workspace/42.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.2879247776
Short name T251
Test name
Test status
Simulation time 58488804086 ps
CPU time 3359.44 seconds
Started Aug 11 04:55:14 PM PDT 24
Finished Aug 11 05:51:14 PM PDT 24
Peak memory 288568 kb
Host smart-c9b46c0f-6fc9-4857-8d3d-1a48275a7b4d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2879247776 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.2879247776
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.3840460728
Short name T202
Test name
Test status
Simulation time 160501634 ps
CPU time 11.12 seconds
Started Aug 11 04:55:16 PM PDT 24
Finished Aug 11 04:55:27 PM PDT 24
Peak memory 254436 kb
Host smart-2088a6f5-294a-4be8-9404-c64489eee8c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38404
60728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.3840460728
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.1841850998
Short name T406
Test name
Test status
Simulation time 371750409 ps
CPU time 14.67 seconds
Started Aug 11 04:55:14 PM PDT 24
Finished Aug 11 04:55:29 PM PDT 24
Peak memory 254168 kb
Host smart-8865f85b-fc84-4506-9aab-5738a867d8dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18418
50998 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.1841850998
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.2229154679
Short name T353
Test name
Test status
Simulation time 216963893106 ps
CPU time 3486.88 seconds
Started Aug 11 04:55:16 PM PDT 24
Finished Aug 11 05:53:23 PM PDT 24
Peak memory 288380 kb
Host smart-e605b88e-2af2-46e0-8635-193c09eab300
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2229154679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.2229154679
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.1007937714
Short name T456
Test name
Test status
Simulation time 58076892744 ps
CPU time 1214.78 seconds
Started Aug 11 04:55:16 PM PDT 24
Finished Aug 11 05:15:31 PM PDT 24
Peak memory 288236 kb
Host smart-88c62eed-7040-456f-807d-696bc574de2c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1007937714 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.1007937714
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.36257853
Short name T327
Test name
Test status
Simulation time 120711263269 ps
CPU time 415.47 seconds
Started Aug 11 04:55:17 PM PDT 24
Finished Aug 11 05:02:13 PM PDT 24
Peak memory 248236 kb
Host smart-5d81fbde-24e0-4fa7-a02e-283f9d95f567
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=36257853 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.36257853
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.2366986944
Short name T35
Test name
Test status
Simulation time 6753191966 ps
CPU time 53 seconds
Started Aug 11 04:55:08 PM PDT 24
Finished Aug 11 04:56:01 PM PDT 24
Peak memory 256460 kb
Host smart-39cfefbb-d612-4580-be35-12f09119a325
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23669
86944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.2366986944
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.1227358950
Short name T527
Test name
Test status
Simulation time 948616105 ps
CPU time 51.06 seconds
Started Aug 11 04:55:12 PM PDT 24
Finished Aug 11 04:56:04 PM PDT 24
Peak memory 248136 kb
Host smart-627fac62-723d-4423-9e89-7cb8d7909d4e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12273
58950 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.1227358950
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.3885346001
Short name T539
Test name
Test status
Simulation time 25097349 ps
CPU time 4.21 seconds
Started Aug 11 04:55:15 PM PDT 24
Finished Aug 11 04:55:19 PM PDT 24
Peak memory 239948 kb
Host smart-7aa016d9-6728-4f4e-afce-558884647b6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38853
46001 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.3885346001
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.3747749850
Short name T34
Test name
Test status
Simulation time 289935272 ps
CPU time 38.44 seconds
Started Aug 11 04:55:09 PM PDT 24
Finished Aug 11 04:55:47 PM PDT 24
Peak memory 256352 kb
Host smart-579d2617-4c07-40b9-86e1-d09bf91db77a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37477
49850 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.3747749850
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.1374231787
Short name T129
Test name
Test status
Simulation time 69934994262 ps
CPU time 4005.06 seconds
Started Aug 11 04:55:15 PM PDT 24
Finished Aug 11 06:02:01 PM PDT 24
Peak memory 305620 kb
Host smart-741748c7-5589-4755-ae96-dbfc0e758e84
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1374231787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_ha
ndler_stress_all.1374231787
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.1754449764
Short name T636
Test name
Test status
Simulation time 469977691649 ps
CPU time 1389.56 seconds
Started Aug 11 04:55:28 PM PDT 24
Finished Aug 11 05:18:38 PM PDT 24
Peak memory 272792 kb
Host smart-1e634bc1-c8a4-4309-bc93-1ca77542be67
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1754449764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.1754449764
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.1400528036
Short name T42
Test name
Test status
Simulation time 2825702647 ps
CPU time 57.37 seconds
Started Aug 11 04:55:15 PM PDT 24
Finished Aug 11 04:56:12 PM PDT 24
Peak memory 255880 kb
Host smart-e712c377-dfc6-4c04-bf3b-f1d80be9498c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14005
28036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.1400528036
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.1296151029
Short name T87
Test name
Test status
Simulation time 665777071 ps
CPU time 38.82 seconds
Started Aug 11 04:55:15 PM PDT 24
Finished Aug 11 04:55:54 PM PDT 24
Peak memory 248088 kb
Host smart-cd13e388-2104-4a40-862a-42cf9bd4f590
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12961
51029 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.1296151029
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.3043961021
Short name T501
Test name
Test status
Simulation time 17127276235 ps
CPU time 1410.54 seconds
Started Aug 11 04:55:21 PM PDT 24
Finished Aug 11 05:18:52 PM PDT 24
Peak memory 287876 kb
Host smart-e4cb3458-c880-42de-9090-4a59141ae124
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043961021 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.3043961021
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.236175491
Short name T571
Test name
Test status
Simulation time 49849329677 ps
CPU time 3134.31 seconds
Started Aug 11 04:55:21 PM PDT 24
Finished Aug 11 05:47:36 PM PDT 24
Peak memory 289016 kb
Host smart-f248b121-6412-44b4-ab74-4d47ccd2398f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236175491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.236175491
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.95895750
Short name T513
Test name
Test status
Simulation time 91165068773 ps
CPU time 247.75 seconds
Started Aug 11 04:55:22 PM PDT 24
Finished Aug 11 04:59:30 PM PDT 24
Peak memory 247804 kb
Host smart-25b26b21-360f-47dd-9791-938779604474
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=95895750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.95895750
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.3178081028
Short name T437
Test name
Test status
Simulation time 242694461 ps
CPU time 34.52 seconds
Started Aug 11 04:55:14 PM PDT 24
Finished Aug 11 04:55:49 PM PDT 24
Peak memory 256324 kb
Host smart-990b39a4-37b3-4cd2-a2b9-2eadec59455b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31780
81028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.3178081028
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.2583179450
Short name T560
Test name
Test status
Simulation time 138143621 ps
CPU time 15.26 seconds
Started Aug 11 04:55:13 PM PDT 24
Finished Aug 11 04:55:29 PM PDT 24
Peak memory 255472 kb
Host smart-203b1930-10b1-427e-a578-6e8e4dad4d81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25831
79450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.2583179450
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.1698212422
Short name T435
Test name
Test status
Simulation time 1049088198 ps
CPU time 31.51 seconds
Started Aug 11 04:55:17 PM PDT 24
Finished Aug 11 04:55:49 PM PDT 24
Peak memory 248380 kb
Host smart-058c5f62-2a98-4a13-ba8d-511d2de0d906
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16982
12422 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.1698212422
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.713273635
Short name T671
Test name
Test status
Simulation time 34283089822 ps
CPU time 2429.48 seconds
Started Aug 11 04:55:21 PM PDT 24
Finished Aug 11 05:35:51 PM PDT 24
Peak memory 288912 kb
Host smart-19812165-c873-43cc-8243-a7deecd7f8f2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=713273635 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_han
dler_stress_all.713273635
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.752374239
Short name T410
Test name
Test status
Simulation time 49570272130 ps
CPU time 2440.39 seconds
Started Aug 11 04:55:26 PM PDT 24
Finished Aug 11 05:36:07 PM PDT 24
Peak memory 288804 kb
Host smart-b374dd2c-9be7-4d38-980f-9031679c67f8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=752374239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.752374239
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.3106796354
Short name T373
Test name
Test status
Simulation time 1810687585 ps
CPU time 68.08 seconds
Started Aug 11 04:55:20 PM PDT 24
Finished Aug 11 04:56:29 PM PDT 24
Peak memory 255948 kb
Host smart-2a35889c-fb41-4a53-bc29-9a225d82907a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31067
96354 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.3106796354
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.3221172391
Short name T69
Test name
Test status
Simulation time 685772505 ps
CPU time 29.83 seconds
Started Aug 11 04:55:28 PM PDT 24
Finished Aug 11 04:55:58 PM PDT 24
Peak memory 256216 kb
Host smart-1640ebf7-854d-45a8-a96e-1a6464c3a277
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32211
72391 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.3221172391
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.3721052364
Short name T3
Test name
Test status
Simulation time 33357600392 ps
CPU time 988.48 seconds
Started Aug 11 04:55:22 PM PDT 24
Finished Aug 11 05:11:51 PM PDT 24
Peak memory 268652 kb
Host smart-6cc769ba-3460-4c88-b327-0aa483247ce5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3721052364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.3721052364
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.1551160414
Short name T97
Test name
Test status
Simulation time 260115150245 ps
CPU time 1365.25 seconds
Started Aug 11 04:55:28 PM PDT 24
Finished Aug 11 05:18:13 PM PDT 24
Peak memory 265644 kb
Host smart-8e6f0280-814e-4135-a158-3a7c1d9ba758
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1551160414 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.1551160414
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.194028795
Short name T282
Test name
Test status
Simulation time 56941963448 ps
CPU time 195.21 seconds
Started Aug 11 04:55:22 PM PDT 24
Finished Aug 11 04:58:37 PM PDT 24
Peak memory 254944 kb
Host smart-cc32d2ca-9699-4af9-8c77-215d56b2eb17
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194028795 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.194028795
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.2830857482
Short name T414
Test name
Test status
Simulation time 366350473 ps
CPU time 21.08 seconds
Started Aug 11 04:55:20 PM PDT 24
Finished Aug 11 04:55:41 PM PDT 24
Peak memory 255484 kb
Host smart-72cd869f-6295-447e-8695-50edd09de189
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28308
57482 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.2830857482
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.1917841119
Short name T39
Test name
Test status
Simulation time 161481753 ps
CPU time 11.75 seconds
Started Aug 11 04:55:22 PM PDT 24
Finished Aug 11 04:55:34 PM PDT 24
Peak memory 248240 kb
Host smart-303be865-f8b8-49db-99aa-021a1cd10922
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19178
41119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.1917841119
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.4227313385
Short name T53
Test name
Test status
Simulation time 660709376 ps
CPU time 43.12 seconds
Started Aug 11 04:55:21 PM PDT 24
Finished Aug 11 04:56:04 PM PDT 24
Peak memory 248220 kb
Host smart-a289534d-5a3a-4054-8c0e-cd5ab699f91e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42273
13385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.4227313385
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.3026253183
Short name T588
Test name
Test status
Simulation time 54613116 ps
CPU time 5.09 seconds
Started Aug 11 04:55:21 PM PDT 24
Finished Aug 11 04:55:27 PM PDT 24
Peak memory 251052 kb
Host smart-22aaae91-1a4b-4b88-903e-77a75405e737
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30262
53183 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.3026253183
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.91100060
Short name T91
Test name
Test status
Simulation time 16612589718 ps
CPU time 1141.56 seconds
Started Aug 11 04:55:27 PM PDT 24
Finished Aug 11 05:14:29 PM PDT 24
Peak memory 272420 kb
Host smart-bf16c646-bcc2-48ba-a747-6cfbb7c0c79b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=91100060 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.91100060
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.1884648260
Short name T436
Test name
Test status
Simulation time 23279062108 ps
CPU time 251.17 seconds
Started Aug 11 04:55:27 PM PDT 24
Finished Aug 11 04:59:38 PM PDT 24
Peak memory 255676 kb
Host smart-77134cad-1d70-4997-bbb2-e5f733094988
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18846
48260 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.1884648260
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.3995675934
Short name T83
Test name
Test status
Simulation time 3448083144 ps
CPU time 57.23 seconds
Started Aug 11 04:55:30 PM PDT 24
Finished Aug 11 04:56:27 PM PDT 24
Peak memory 248264 kb
Host smart-ecea6d37-0253-4419-9c36-541aebe46d4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39956
75934 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.3995675934
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.2436893050
Short name T276
Test name
Test status
Simulation time 113281878913 ps
CPU time 1909.5 seconds
Started Aug 11 04:55:29 PM PDT 24
Finished Aug 11 05:27:19 PM PDT 24
Peak memory 272232 kb
Host smart-38f2587e-f152-4e6c-a362-a9d7072075f8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2436893050 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.2436893050
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.2668315903
Short name T685
Test name
Test status
Simulation time 148678363641 ps
CPU time 2418.42 seconds
Started Aug 11 04:55:34 PM PDT 24
Finished Aug 11 05:35:53 PM PDT 24
Peak memory 289220 kb
Host smart-1d10a3e4-408e-4d42-8e73-fde45df74aa2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2668315903 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.2668315903
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.3772135074
Short name T71
Test name
Test status
Simulation time 1767754649 ps
CPU time 25.53 seconds
Started Aug 11 04:55:29 PM PDT 24
Finished Aug 11 04:55:55 PM PDT 24
Peak memory 255028 kb
Host smart-a7b1e8a1-4ff2-425c-b269-93927533d5b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37721
35074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.3772135074
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.3093441465
Short name T48
Test name
Test status
Simulation time 5042839969 ps
CPU time 56.75 seconds
Started Aug 11 04:55:29 PM PDT 24
Finished Aug 11 04:56:26 PM PDT 24
Peak memory 248148 kb
Host smart-86ee3579-18aa-4863-a2dd-235f0edffb25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30934
41465 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.3093441465
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.3643346734
Short name T688
Test name
Test status
Simulation time 11182130901 ps
CPU time 38.09 seconds
Started Aug 11 04:55:29 PM PDT 24
Finished Aug 11 04:56:07 PM PDT 24
Peak memory 255596 kb
Host smart-4867def4-c567-4004-b0cc-bea8ce412ed5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36433
46734 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.3643346734
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.389045120
Short name T585
Test name
Test status
Simulation time 39745890424 ps
CPU time 2458.78 seconds
Started Aug 11 04:55:34 PM PDT 24
Finished Aug 11 05:36:33 PM PDT 24
Peak memory 289004 kb
Host smart-728acc0b-c214-45a6-98f8-68548579c3d5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=389045120 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_han
dler_stress_all.389045120
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all_with_rand_reset.4148627566
Short name T311
Test name
Test status
Simulation time 59317140815 ps
CPU time 2039.22 seconds
Started Aug 11 04:55:33 PM PDT 24
Finished Aug 11 05:29:32 PM PDT 24
Peak memory 289252 kb
Host smart-332924af-e328-460c-af61-585f4e7b1a6e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4148627566 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.alert_handler_stress_all_with_rand_reset.4148627566
Directory /workspace/46.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.3190218645
Short name T36
Test name
Test status
Simulation time 17141255344 ps
CPU time 1103.59 seconds
Started Aug 11 04:55:33 PM PDT 24
Finished Aug 11 05:13:57 PM PDT 24
Peak memory 283816 kb
Host smart-f85dab5d-d69b-4366-9b49-aa5914ac2fae
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3190218645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.3190218645
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.1830396850
Short name T657
Test name
Test status
Simulation time 1914065845 ps
CPU time 156.49 seconds
Started Aug 11 04:55:35 PM PDT 24
Finished Aug 11 04:58:11 PM PDT 24
Peak memory 255864 kb
Host smart-6619a1c6-be64-4d26-b4ae-c36a4013b45d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18303
96850 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.1830396850
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.3793142864
Short name T426
Test name
Test status
Simulation time 218657799 ps
CPU time 14.55 seconds
Started Aug 11 04:55:34 PM PDT 24
Finished Aug 11 04:55:49 PM PDT 24
Peak memory 254528 kb
Host smart-9dd409b8-7241-4657-8d41-72617e87b600
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37931
42864 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.3793142864
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.4068120437
Short name T354
Test name
Test status
Simulation time 102267761211 ps
CPU time 2906.53 seconds
Started Aug 11 04:55:42 PM PDT 24
Finished Aug 11 05:44:09 PM PDT 24
Peak memory 288248 kb
Host smart-b7d75804-2c3a-4f9c-8f4b-f74549475e04
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068120437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.4068120437
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.167857557
Short name T28
Test name
Test status
Simulation time 63901940675 ps
CPU time 1439.74 seconds
Started Aug 11 04:55:47 PM PDT 24
Finished Aug 11 05:19:47 PM PDT 24
Peak memory 287436 kb
Host smart-4d745f39-dfa8-4c38-9032-2fe618ec23ba
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=167857557 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.167857557
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.3707383863
Short name T344
Test name
Test status
Simulation time 14517902708 ps
CPU time 159.59 seconds
Started Aug 11 04:55:41 PM PDT 24
Finished Aug 11 04:58:21 PM PDT 24
Peak memory 248100 kb
Host smart-e6729185-7af7-4c5a-84a3-2c690d9c8e1b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3707383863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.3707383863
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.2118791166
Short name T460
Test name
Test status
Simulation time 3610662990 ps
CPU time 64 seconds
Started Aug 11 04:55:33 PM PDT 24
Finished Aug 11 04:56:37 PM PDT 24
Peak memory 256392 kb
Host smart-08bebe0c-fc3f-41ef-92bf-e5d11ece24d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21187
91166 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.2118791166
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.1749030517
Short name T652
Test name
Test status
Simulation time 2359155559 ps
CPU time 43.09 seconds
Started Aug 11 04:55:33 PM PDT 24
Finished Aug 11 04:56:17 PM PDT 24
Peak memory 248068 kb
Host smart-96c2f137-3712-4ff4-93a5-165f2709ecc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17490
30517 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.1749030517
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.2882323583
Short name T345
Test name
Test status
Simulation time 433752341 ps
CPU time 13.82 seconds
Started Aug 11 04:55:35 PM PDT 24
Finished Aug 11 04:55:49 PM PDT 24
Peak memory 255592 kb
Host smart-3a4a82ed-d2e9-421e-9390-fe71d764c347
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28823
23583 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.2882323583
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.148810776
Short name T448
Test name
Test status
Simulation time 914721146 ps
CPU time 68.07 seconds
Started Aug 11 04:55:34 PM PDT 24
Finished Aug 11 04:56:42 PM PDT 24
Peak memory 255596 kb
Host smart-d8d65ae4-aeb2-488f-97d6-e4b14de6c67a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14881
0776 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.148810776
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.1499952901
Short name T668
Test name
Test status
Simulation time 643160896324 ps
CPU time 2025.26 seconds
Started Aug 11 04:55:45 PM PDT 24
Finished Aug 11 05:29:30 PM PDT 24
Peak memory 289124 kb
Host smart-cf756eab-82b4-4b2a-a93a-c3f737ff7de7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499952901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_ha
ndler_stress_all.1499952901
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.1055643336
Short name T118
Test name
Test status
Simulation time 81648017625 ps
CPU time 1448.88 seconds
Started Aug 11 04:55:45 PM PDT 24
Finished Aug 11 05:19:54 PM PDT 24
Peak memory 272732 kb
Host smart-430e7529-aa3c-4032-a334-8787a9053ebd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1055643336 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.1055643336
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.2999108467
Short name T457
Test name
Test status
Simulation time 7965965049 ps
CPU time 128.91 seconds
Started Aug 11 04:55:41 PM PDT 24
Finished Aug 11 04:57:50 PM PDT 24
Peak memory 256300 kb
Host smart-aef7385c-c630-48d9-8be4-a88ec6438e34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29991
08467 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.2999108467
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.1999399129
Short name T698
Test name
Test status
Simulation time 523905356 ps
CPU time 18.65 seconds
Started Aug 11 04:55:42 PM PDT 24
Finished Aug 11 04:56:01 PM PDT 24
Peak memory 247708 kb
Host smart-4790b6a7-ec32-4111-8721-0c34cd4566d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19993
99129 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.1999399129
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.3323019204
Short name T75
Test name
Test status
Simulation time 42731026932 ps
CPU time 1246.23 seconds
Started Aug 11 04:55:46 PM PDT 24
Finished Aug 11 05:16:33 PM PDT 24
Peak memory 271776 kb
Host smart-e36f3dfd-5f82-4128-b16d-125c302ab6c0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323019204 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.3323019204
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.4139519708
Short name T381
Test name
Test status
Simulation time 352597164 ps
CPU time 40.88 seconds
Started Aug 11 04:55:40 PM PDT 24
Finished Aug 11 04:56:21 PM PDT 24
Peak memory 248156 kb
Host smart-6e5c01d7-adfd-4eb8-9db5-b764fee1a77b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41395
19708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.4139519708
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.3556316061
Short name T637
Test name
Test status
Simulation time 469122637 ps
CPU time 16.36 seconds
Started Aug 11 04:55:43 PM PDT 24
Finished Aug 11 04:55:59 PM PDT 24
Peak memory 253876 kb
Host smart-db6d99ec-5bcf-4870-b0c1-6b951943150c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35563
16061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.3556316061
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.2512578154
Short name T401
Test name
Test status
Simulation time 717925691 ps
CPU time 47.11 seconds
Started Aug 11 04:55:40 PM PDT 24
Finished Aug 11 04:56:27 PM PDT 24
Peak memory 256396 kb
Host smart-f347d238-b6bb-4984-824b-01e746373f82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25125
78154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.2512578154
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.489951618
Short name T440
Test name
Test status
Simulation time 229760733 ps
CPU time 23.01 seconds
Started Aug 11 04:55:48 PM PDT 24
Finished Aug 11 04:56:11 PM PDT 24
Peak memory 256004 kb
Host smart-0f9a0381-75b4-47bc-981c-cd412417f0f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48995
1618 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.489951618
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all_with_rand_reset.2122230551
Short name T92
Test name
Test status
Simulation time 17445033581 ps
CPU time 2200.9 seconds
Started Aug 11 04:55:46 PM PDT 24
Finished Aug 11 05:32:28 PM PDT 24
Peak memory 304436 kb
Host smart-49f259ae-1336-40c9-8103-df55e06f327a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2122230551 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.alert_handler_stress_all_with_rand_reset.2122230551
Directory /workspace/48.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.2192797318
Short name T252
Test name
Test status
Simulation time 91584014776 ps
CPU time 2451.91 seconds
Started Aug 11 04:55:49 PM PDT 24
Finished Aug 11 05:36:41 PM PDT 24
Peak memory 289236 kb
Host smart-8f047c50-f4fb-4658-a5a3-6a327d37e2c8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2192797318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.2192797318
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.1689590577
Short name T388
Test name
Test status
Simulation time 853555623 ps
CPU time 70.85 seconds
Started Aug 11 04:55:47 PM PDT 24
Finished Aug 11 04:56:58 PM PDT 24
Peak memory 256380 kb
Host smart-b898ce1a-632f-4b71-9f4c-344d876cfa6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16895
90577 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.1689590577
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.3172494914
Short name T372
Test name
Test status
Simulation time 265917948 ps
CPU time 7.03 seconds
Started Aug 11 04:55:48 PM PDT 24
Finished Aug 11 04:55:55 PM PDT 24
Peak memory 250896 kb
Host smart-723b7765-1491-40ea-a7cd-6100dfd0a9ae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31724
94914 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.3172494914
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.3623084125
Short name T265
Test name
Test status
Simulation time 57837293467 ps
CPU time 3209.81 seconds
Started Aug 11 04:55:48 PM PDT 24
Finished Aug 11 05:49:18 PM PDT 24
Peak memory 288004 kb
Host smart-815dd86c-5894-4388-af0d-fbd86e41275f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3623084125 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.3623084125
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.936044596
Short name T631
Test name
Test status
Simulation time 177866623491 ps
CPU time 2881.12 seconds
Started Aug 11 04:55:48 PM PDT 24
Finished Aug 11 05:43:50 PM PDT 24
Peak memory 288832 kb
Host smart-15bb008b-97c6-4e5b-a26a-03106609d078
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=936044596 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.936044596
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.2356825334
Short name T505
Test name
Test status
Simulation time 4757857109 ps
CPU time 186.72 seconds
Started Aug 11 04:55:46 PM PDT 24
Finished Aug 11 04:58:53 PM PDT 24
Peak memory 248240 kb
Host smart-9c689e68-c203-4233-bbef-695504a5446d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2356825334 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.2356825334
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.1830955828
Short name T520
Test name
Test status
Simulation time 2041240714 ps
CPU time 74.71 seconds
Started Aug 11 04:55:40 PM PDT 24
Finished Aug 11 04:56:55 PM PDT 24
Peak memory 255612 kb
Host smart-aa275d11-18aa-4f7d-87fc-5a3b8d5ab6a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18309
55828 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.1830955828
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.1011804066
Short name T56
Test name
Test status
Simulation time 418135715 ps
CPU time 19.47 seconds
Started Aug 11 04:55:47 PM PDT 24
Finished Aug 11 04:56:07 PM PDT 24
Peak memory 255756 kb
Host smart-3acbade5-dc2f-4af3-9b39-7350379d7c29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10118
04066 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.1011804066
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.4006048779
Short name T309
Test name
Test status
Simulation time 127988458 ps
CPU time 17.76 seconds
Started Aug 11 04:55:48 PM PDT 24
Finished Aug 11 04:56:06 PM PDT 24
Peak memory 255780 kb
Host smart-1dc7671b-05b3-4331-94bc-49535668925e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40060
48779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.4006048779
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.1251205394
Short name T418
Test name
Test status
Simulation time 30693073 ps
CPU time 2.94 seconds
Started Aug 11 04:55:41 PM PDT 24
Finished Aug 11 04:55:44 PM PDT 24
Peak memory 248200 kb
Host smart-4ff6b977-b56b-4d04-81f8-3f7700f3559b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12512
05394 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.1251205394
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.2732353583
Short name T579
Test name
Test status
Simulation time 581335524302 ps
CPU time 2915.41 seconds
Started Aug 11 04:55:47 PM PDT 24
Finished Aug 11 05:44:23 PM PDT 24
Peak memory 288228 kb
Host smart-7eab45a5-f715-415f-aa2d-4827cef520a3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2732353583 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_ha
ndler_stress_all.2732353583
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.358167315
Short name T224
Test name
Test status
Simulation time 176574730 ps
CPU time 3.87 seconds
Started Aug 11 04:53:20 PM PDT 24
Finished Aug 11 04:53:23 PM PDT 24
Peak memory 248464 kb
Host smart-60e6d4ea-0b03-4974-9ddd-3b0524406a28
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=358167315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.358167315
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.670177976
Short name T376
Test name
Test status
Simulation time 53276399938 ps
CPU time 2063.93 seconds
Started Aug 11 04:53:13 PM PDT 24
Finished Aug 11 05:27:38 PM PDT 24
Peak memory 288588 kb
Host smart-744e53c5-eeeb-4cb6-9e67-b60d0b30c1de
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670177976 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.670177976
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.2033065038
Short name T491
Test name
Test status
Simulation time 3426527470 ps
CPU time 73.65 seconds
Started Aug 11 04:53:19 PM PDT 24
Finished Aug 11 04:54:33 PM PDT 24
Peak memory 248204 kb
Host smart-f4e1f040-e963-4505-9823-98cfc1cf8051
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2033065038 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.2033065038
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.1628318764
Short name T623
Test name
Test status
Simulation time 34256830593 ps
CPU time 325.25 seconds
Started Aug 11 04:53:12 PM PDT 24
Finished Aug 11 04:58:37 PM PDT 24
Peak memory 256424 kb
Host smart-bdd9946f-024d-4d9d-8fa2-b71c8fba4fbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16283
18764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.1628318764
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.302887720
Short name T86
Test name
Test status
Simulation time 2099572084 ps
CPU time 15.45 seconds
Started Aug 11 04:53:19 PM PDT 24
Finished Aug 11 04:53:34 PM PDT 24
Peak memory 248152 kb
Host smart-8f19b28f-7ece-4d4a-ba75-f7247d73f23f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30288
7720 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.302887720
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.4102076555
Short name T284
Test name
Test status
Simulation time 97387181796 ps
CPU time 1687.3 seconds
Started Aug 11 04:53:16 PM PDT 24
Finished Aug 11 05:21:24 PM PDT 24
Peak memory 272836 kb
Host smart-101bfcbb-ca9c-4052-8735-0c08d300bb9f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102076555 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.4102076555
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.1904708829
Short name T561
Test name
Test status
Simulation time 63094401903 ps
CPU time 2177.67 seconds
Started Aug 11 04:53:19 PM PDT 24
Finished Aug 11 05:29:37 PM PDT 24
Peak memory 283792 kb
Host smart-05040cea-52df-4ebb-a348-3bcdb00e1efa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1904708829 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.1904708829
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.1393749511
Short name T318
Test name
Test status
Simulation time 9483003449 ps
CPU time 389.47 seconds
Started Aug 11 04:53:17 PM PDT 24
Finished Aug 11 04:59:47 PM PDT 24
Peak memory 248184 kb
Host smart-f8d3f633-bdfe-46c0-8674-0d16fff15a2e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1393749511 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.1393749511
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.4153809456
Short name T549
Test name
Test status
Simulation time 135597480 ps
CPU time 14.87 seconds
Started Aug 11 04:53:19 PM PDT 24
Finished Aug 11 04:53:34 PM PDT 24
Peak memory 255564 kb
Host smart-4ad775d7-1cf8-48a4-a256-16e9ad813c36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41538
09456 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.4153809456
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.4171330106
Short name T26
Test name
Test status
Simulation time 1265622720 ps
CPU time 29.75 seconds
Started Aug 11 04:53:17 PM PDT 24
Finished Aug 11 04:53:47 PM PDT 24
Peak memory 256316 kb
Host smart-4e9846b1-e535-474e-a506-af61741f77ad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41713
30106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.4171330106
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.375174427
Short name T25
Test name
Test status
Simulation time 896878704 ps
CPU time 46.17 seconds
Started Aug 11 04:53:16 PM PDT 24
Finished Aug 11 04:54:02 PM PDT 24
Peak memory 249196 kb
Host smart-db5978a4-e681-406f-89cb-db611720a6be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37517
4427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.375174427
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.3055162098
Short name T607
Test name
Test status
Simulation time 981961374 ps
CPU time 66.37 seconds
Started Aug 11 04:53:16 PM PDT 24
Finished Aug 11 04:54:22 PM PDT 24
Peak memory 256352 kb
Host smart-36eaab9b-0eda-496f-81c5-42ea3a903d24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30551
62098 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.3055162098
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.4058758562
Short name T305
Test name
Test status
Simulation time 61155166776 ps
CPU time 3040.63 seconds
Started Aug 11 04:53:20 PM PDT 24
Finished Aug 11 05:44:01 PM PDT 24
Peak memory 297136 kb
Host smart-159795e5-f04e-4140-8583-5c84f94c9247
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4058758562 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_han
dler_stress_all.4058758562
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.338377867
Short name T208
Test name
Test status
Simulation time 17476859 ps
CPU time 2.62 seconds
Started Aug 11 04:53:25 PM PDT 24
Finished Aug 11 04:53:28 PM PDT 24
Peak memory 248384 kb
Host smart-1154df82-0721-4d54-ae62-d46c1b581610
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=338377867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.338377867
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.3052095254
Short name T235
Test name
Test status
Simulation time 93140461761 ps
CPU time 1427.86 seconds
Started Aug 11 04:53:19 PM PDT 24
Finished Aug 11 05:17:07 PM PDT 24
Peak memory 272360 kb
Host smart-32052ded-3bc2-4709-8a08-9b6ba5cfe8ec
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3052095254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.3052095254
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.1737098213
Short name T428
Test name
Test status
Simulation time 948652492 ps
CPU time 14.54 seconds
Started Aug 11 04:53:21 PM PDT 24
Finished Aug 11 04:53:36 PM PDT 24
Peak memory 248104 kb
Host smart-fefd7738-c826-40ac-8311-201fd0186d4c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1737098213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.1737098213
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.8675744
Short name T541
Test name
Test status
Simulation time 2137550196 ps
CPU time 43.73 seconds
Started Aug 11 04:53:23 PM PDT 24
Finished Aug 11 04:54:06 PM PDT 24
Peak memory 255880 kb
Host smart-44ddcfc1-8033-4ffa-9ba0-13b8f811dff7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86757
44 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.8675744
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.2990701559
Short name T430
Test name
Test status
Simulation time 653004304 ps
CPU time 37.3 seconds
Started Aug 11 04:53:19 PM PDT 24
Finished Aug 11 04:53:56 PM PDT 24
Peak memory 248540 kb
Host smart-86b93ebf-c3c7-4a61-a616-7fee8a398ef0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29907
01559 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.2990701559
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.3534490672
Short name T499
Test name
Test status
Simulation time 137110919306 ps
CPU time 1436.77 seconds
Started Aug 11 04:53:20 PM PDT 24
Finished Aug 11 05:17:17 PM PDT 24
Peak memory 288440 kb
Host smart-6d5c73a4-a28d-4e61-9eb0-3f95832f5356
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3534490672 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.3534490672
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.2248896799
Short name T95
Test name
Test status
Simulation time 18738708906 ps
CPU time 1151.8 seconds
Started Aug 11 04:53:25 PM PDT 24
Finished Aug 11 05:12:37 PM PDT 24
Peak memory 288636 kb
Host smart-058c024f-0aa4-4bb2-935d-67b9fd9a6664
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2248896799 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.2248896799
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.1725302974
Short name T497
Test name
Test status
Simulation time 3359339575 ps
CPU time 131.51 seconds
Started Aug 11 04:53:33 PM PDT 24
Finished Aug 11 04:55:45 PM PDT 24
Peak memory 248220 kb
Host smart-6ef85377-5c1a-4337-87d4-14c226b7afbe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1725302974 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.1725302974
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.2789757285
Short name T231
Test name
Test status
Simulation time 62133450 ps
CPU time 7.04 seconds
Started Aug 11 04:53:19 PM PDT 24
Finished Aug 11 04:53:26 PM PDT 24
Peak memory 248192 kb
Host smart-697cbde5-7a99-4f03-b6eb-7cb869b29151
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27897
57285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.2789757285
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.3213878604
Short name T404
Test name
Test status
Simulation time 1496816212 ps
CPU time 45.93 seconds
Started Aug 11 04:53:23 PM PDT 24
Finished Aug 11 04:54:09 PM PDT 24
Peak memory 248164 kb
Host smart-7c5971bf-c37b-4d51-91cc-38690fe30137
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32138
78604 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.3213878604
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.2694994531
Short name T563
Test name
Test status
Simulation time 961682995 ps
CPU time 23.72 seconds
Started Aug 11 04:53:25 PM PDT 24
Finished Aug 11 04:53:49 PM PDT 24
Peak memory 255640 kb
Host smart-e1f57c15-a1b6-4b01-b307-570c71cac3c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26949
94531 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.2694994531
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.384076068
Short name T240
Test name
Test status
Simulation time 418384954 ps
CPU time 35.72 seconds
Started Aug 11 04:53:22 PM PDT 24
Finished Aug 11 04:53:58 PM PDT 24
Peak memory 256232 kb
Host smart-3fb2482c-3906-4ba9-ab60-959e194c6a14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38407
6068 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.384076068
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.2404389962
Short name T101
Test name
Test status
Simulation time 3020949142 ps
CPU time 87.22 seconds
Started Aug 11 04:53:38 PM PDT 24
Finished Aug 11 04:55:05 PM PDT 24
Peak memory 251060 kb
Host smart-5e89927d-d637-4c59-beb4-680001fee3c4
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2404389962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_han
dler_stress_all.2404389962
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all_with_rand_reset.3915902880
Short name T540
Test name
Test status
Simulation time 25545597447 ps
CPU time 988.49 seconds
Started Aug 11 04:53:24 PM PDT 24
Finished Aug 11 05:09:53 PM PDT 24
Peak memory 272560 kb
Host smart-b35b6311-0bd4-4792-a5f8-906a63692bba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3915902880 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.alert_handler_stress_all_with_rand_reset.3915902880
Directory /workspace/6.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.186500268
Short name T214
Test name
Test status
Simulation time 13218557 ps
CPU time 2.79 seconds
Started Aug 11 04:53:24 PM PDT 24
Finished Aug 11 04:53:27 PM PDT 24
Peak memory 248560 kb
Host smart-3f83d600-1827-4979-920b-bff712d0d9a8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=186500268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.186500268
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.2254950247
Short name T557
Test name
Test status
Simulation time 30156433536 ps
CPU time 1406.4 seconds
Started Aug 11 04:53:19 PM PDT 24
Finished Aug 11 05:16:45 PM PDT 24
Peak memory 288388 kb
Host smart-5f721056-742f-4a44-8252-d1f2a86b89e0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254950247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.2254950247
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.619389623
Short name T432
Test name
Test status
Simulation time 363188447 ps
CPU time 12.03 seconds
Started Aug 11 04:53:29 PM PDT 24
Finished Aug 11 04:53:41 PM PDT 24
Peak memory 248124 kb
Host smart-0741d6aa-da9c-40ef-bd14-72298483f06f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=619389623 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.619389623
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.2518147935
Short name T659
Test name
Test status
Simulation time 1631480975 ps
CPU time 134.17 seconds
Started Aug 11 04:53:29 PM PDT 24
Finished Aug 11 04:55:43 PM PDT 24
Peak memory 256072 kb
Host smart-9e2285f9-c5f4-45a6-a7c4-9459afa2b982
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25181
47935 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.2518147935
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.2603186215
Short name T467
Test name
Test status
Simulation time 1474418979 ps
CPU time 15.39 seconds
Started Aug 11 04:53:24 PM PDT 24
Finished Aug 11 04:53:40 PM PDT 24
Peak memory 247812 kb
Host smart-0d830a00-dbe2-40aa-873a-9cc64715dd81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26031
86215 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.2603186215
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.799487350
Short name T350
Test name
Test status
Simulation time 149435535453 ps
CPU time 1791.37 seconds
Started Aug 11 04:53:25 PM PDT 24
Finished Aug 11 05:23:17 PM PDT 24
Peak memory 288116 kb
Host smart-a9e6eda4-7ed6-4e71-9e6f-46e99995766a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=799487350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.799487350
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.504397620
Short name T627
Test name
Test status
Simulation time 340557369793 ps
CPU time 1534.88 seconds
Started Aug 11 04:53:29 PM PDT 24
Finished Aug 11 05:19:04 PM PDT 24
Peak memory 281772 kb
Host smart-e0bfc491-4bfe-4d54-b5d3-39ce34094035
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=504397620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.504397620
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.2795081128
Short name T341
Test name
Test status
Simulation time 15273927867 ps
CPU time 475.67 seconds
Started Aug 11 04:53:33 PM PDT 24
Finished Aug 11 05:01:29 PM PDT 24
Peak memory 247096 kb
Host smart-929a62f8-1496-4ad8-95be-b466bcba050e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2795081128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.2795081128
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.1948105602
Short name T625
Test name
Test status
Simulation time 897914612 ps
CPU time 55.53 seconds
Started Aug 11 04:53:24 PM PDT 24
Finished Aug 11 04:54:19 PM PDT 24
Peak memory 255544 kb
Host smart-9d621c10-45c7-4e23-a9a7-b8c16cab5d18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19481
05602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.1948105602
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.3701647183
Short name T98
Test name
Test status
Simulation time 155214907 ps
CPU time 21.97 seconds
Started Aug 11 04:53:29 PM PDT 24
Finished Aug 11 04:53:51 PM PDT 24
Peak memory 247736 kb
Host smart-50eb9827-9c71-4757-b8b5-a55b26f63774
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37016
47183 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.3701647183
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.1251819780
Short name T533
Test name
Test status
Simulation time 234398442 ps
CPU time 7.21 seconds
Started Aug 11 04:53:21 PM PDT 24
Finished Aug 11 04:53:28 PM PDT 24
Peak memory 247664 kb
Host smart-d208292c-10eb-412a-9aa7-7bfdae096cc7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12518
19780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.1251819780
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.3343392382
Short name T476
Test name
Test status
Simulation time 36171637 ps
CPU time 5.72 seconds
Started Aug 11 04:53:28 PM PDT 24
Finished Aug 11 04:53:34 PM PDT 24
Peak memory 256380 kb
Host smart-54a7cb5a-3fac-4edb-b0cf-043c5d7ca80b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33433
92382 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.3343392382
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.2934001759
Short name T80
Test name
Test status
Simulation time 7742149815 ps
CPU time 220.66 seconds
Started Aug 11 04:53:33 PM PDT 24
Finished Aug 11 04:57:14 PM PDT 24
Peak memory 256536 kb
Host smart-e0abe13c-5530-4096-8f51-622d4ffbe999
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2934001759 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_han
dler_stress_all.2934001759
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.2911529557
Short name T212
Test name
Test status
Simulation time 16875501 ps
CPU time 2.58 seconds
Started Aug 11 04:53:36 PM PDT 24
Finished Aug 11 04:53:39 PM PDT 24
Peak memory 248408 kb
Host smart-d12e9e17-e9b8-4e78-8f36-8550a83529d7
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2911529557 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.2911529557
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.2022257575
Short name T494
Test name
Test status
Simulation time 143096711755 ps
CPU time 2366.56 seconds
Started Aug 11 04:53:30 PM PDT 24
Finished Aug 11 05:32:57 PM PDT 24
Peak memory 286536 kb
Host smart-2d3eca39-6b73-4c11-8469-7ff14f5e3e89
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022257575 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.2022257575
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.2632141866
Short name T583
Test name
Test status
Simulation time 87634308 ps
CPU time 6.41 seconds
Started Aug 11 04:53:30 PM PDT 24
Finished Aug 11 04:53:37 PM PDT 24
Peak memory 248176 kb
Host smart-1edf9bac-f3d8-4b7d-98f6-6ecb6337efd2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2632141866 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.2632141866
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.3461066203
Short name T11
Test name
Test status
Simulation time 8369562209 ps
CPU time 189.21 seconds
Started Aug 11 04:53:22 PM PDT 24
Finished Aug 11 04:56:32 PM PDT 24
Peak memory 250216 kb
Host smart-c3976fa0-4859-4ced-865f-3aee323fa72c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34610
66203 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.3461066203
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.1010429201
Short name T598
Test name
Test status
Simulation time 496889285 ps
CPU time 30.86 seconds
Started Aug 11 04:53:24 PM PDT 24
Finished Aug 11 04:53:55 PM PDT 24
Peak memory 247892 kb
Host smart-3e25b42d-d7fe-40ee-92ee-39b29ee3afc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10104
29201 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.1010429201
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.3649318981
Short name T339
Test name
Test status
Simulation time 9727454576 ps
CPU time 825.98 seconds
Started Aug 11 04:53:29 PM PDT 24
Finished Aug 11 05:07:15 PM PDT 24
Peak memory 271872 kb
Host smart-79c6b452-5726-4b5e-9085-8a82226a330a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3649318981 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.3649318981
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.653641538
Short name T421
Test name
Test status
Simulation time 7260434960 ps
CPU time 833.16 seconds
Started Aug 11 04:53:35 PM PDT 24
Finished Aug 11 05:07:28 PM PDT 24
Peak memory 272680 kb
Host smart-d09cf4bb-49c8-4b55-94e0-548556d42ecd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=653641538 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.653641538
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.3029601560
Short name T338
Test name
Test status
Simulation time 10272741924 ps
CPU time 103.55 seconds
Started Aug 11 04:53:27 PM PDT 24
Finished Aug 11 04:55:11 PM PDT 24
Peak memory 247992 kb
Host smart-87bb656f-711f-495e-9e03-d08c1382bddb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3029601560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.3029601560
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.680460960
Short name T582
Test name
Test status
Simulation time 2978724135 ps
CPU time 48.18 seconds
Started Aug 11 04:53:24 PM PDT 24
Finished Aug 11 04:54:12 PM PDT 24
Peak memory 248216 kb
Host smart-5fe28ec6-6e81-426a-86ea-36cc0e4aa698
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68046
0960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.680460960
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.3632588589
Short name T37
Test name
Test status
Simulation time 356136084 ps
CPU time 11.64 seconds
Started Aug 11 04:53:25 PM PDT 24
Finished Aug 11 04:53:37 PM PDT 24
Peak memory 254588 kb
Host smart-7c26b265-9e74-4019-ab1f-6a1fe880059e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36325
88589 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.3632588589
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.3855373445
Short name T701
Test name
Test status
Simulation time 136968444 ps
CPU time 12.5 seconds
Started Aug 11 04:53:35 PM PDT 24
Finished Aug 11 04:53:48 PM PDT 24
Peak memory 256364 kb
Host smart-bcdbbfe7-0dc7-4040-9f7e-58e01fd685ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38553
73445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.3855373445
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.1613954138
Short name T389
Test name
Test status
Simulation time 526454679 ps
CPU time 32.06 seconds
Started Aug 11 04:53:29 PM PDT 24
Finished Aug 11 04:54:01 PM PDT 24
Peak memory 255604 kb
Host smart-0d869c35-f178-4db7-b741-fc519b8617c4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16139
54138 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.1613954138
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.4130665014
Short name T291
Test name
Test status
Simulation time 57503017607 ps
CPU time 2038.39 seconds
Started Aug 11 04:53:31 PM PDT 24
Finished Aug 11 05:27:30 PM PDT 24
Peak memory 285124 kb
Host smart-49bdfd36-08ed-4b81-8292-ee1ed2d88f04
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4130665014 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_han
dler_stress_all.4130665014
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all_with_rand_reset.3757755606
Short name T617
Test name
Test status
Simulation time 133244180325 ps
CPU time 7354.62 seconds
Started Aug 11 04:53:25 PM PDT 24
Finished Aug 11 06:56:00 PM PDT 24
Peak memory 370048 kb
Host smart-260077a2-d40d-4040-8769-b2c192a69723
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3757755606 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.alert_handler_stress_all_with_rand_reset.3757755606
Directory /workspace/8.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.597949585
Short name T213
Test name
Test status
Simulation time 28796193 ps
CPU time 2.81 seconds
Started Aug 11 04:53:31 PM PDT 24
Finished Aug 11 04:53:34 PM PDT 24
Peak memory 248440 kb
Host smart-04ed9f9c-722c-4bf7-b584-b282ef5c5767
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=597949585 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.597949585
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.3000647363
Short name T493
Test name
Test status
Simulation time 592219361223 ps
CPU time 2043.08 seconds
Started Aug 11 04:53:30 PM PDT 24
Finished Aug 11 05:27:34 PM PDT 24
Peak memory 283384 kb
Host smart-7f764446-7049-492e-bfcc-abe24267a8b0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3000647363 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.3000647363
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.1858721608
Short name T672
Test name
Test status
Simulation time 172644006 ps
CPU time 5.9 seconds
Started Aug 11 04:53:32 PM PDT 24
Finished Aug 11 04:53:38 PM PDT 24
Peak memory 248116 kb
Host smart-082d6b34-72da-46f5-819f-6a8cd77a92d0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1858721608 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.1858721608
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.2215935344
Short name T538
Test name
Test status
Simulation time 367501076 ps
CPU time 14.05 seconds
Started Aug 11 04:53:27 PM PDT 24
Finished Aug 11 04:53:41 PM PDT 24
Peak memory 256376 kb
Host smart-043f4e33-194b-4d60-b6ed-1f335271d04a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22159
35344 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.2215935344
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.3433611790
Short name T64
Test name
Test status
Simulation time 310161464 ps
CPU time 18.81 seconds
Started Aug 11 04:53:35 PM PDT 24
Finished Aug 11 04:53:54 PM PDT 24
Peak memory 255580 kb
Host smart-d24ecbc0-fd4f-4f14-8a02-c8a385fb2264
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34336
11790 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.3433611790
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.2804666455
Short name T342
Test name
Test status
Simulation time 289047623221 ps
CPU time 2229.98 seconds
Started Aug 11 04:53:35 PM PDT 24
Finished Aug 11 05:30:45 PM PDT 24
Peak memory 288288 kb
Host smart-90ebe438-2d74-4213-9dbe-71a81e3cba03
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2804666455 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.2804666455
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.2712229428
Short name T645
Test name
Test status
Simulation time 126135181224 ps
CPU time 2151.54 seconds
Started Aug 11 04:53:25 PM PDT 24
Finished Aug 11 05:29:17 PM PDT 24
Peak memory 280992 kb
Host smart-7bf76752-28be-453c-9911-0086292d4a68
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2712229428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.2712229428
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.236169884
Short name T642
Test name
Test status
Simulation time 9143557472 ps
CPU time 370.96 seconds
Started Aug 11 04:53:32 PM PDT 24
Finished Aug 11 04:59:43 PM PDT 24
Peak memory 248236 kb
Host smart-5ebdf2f1-210b-41ac-a46e-cacb3831aecd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=236169884 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.236169884
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.2559872133
Short name T288
Test name
Test status
Simulation time 651916792 ps
CPU time 47.22 seconds
Started Aug 11 04:53:31 PM PDT 24
Finished Aug 11 04:54:18 PM PDT 24
Peak memory 256352 kb
Host smart-df051fab-4d10-454d-8d93-adfed055fdb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25598
72133 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.2559872133
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.3982237826
Short name T266
Test name
Test status
Simulation time 3669599587 ps
CPU time 54.81 seconds
Started Aug 11 04:53:27 PM PDT 24
Finished Aug 11 04:54:22 PM PDT 24
Peak memory 255780 kb
Host smart-294631da-dc8a-4d24-923c-43c156e4e418
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39822
37826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.3982237826
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.478092434
Short name T306
Test name
Test status
Simulation time 429872368 ps
CPU time 26.33 seconds
Started Aug 11 04:53:30 PM PDT 24
Finished Aug 11 04:53:57 PM PDT 24
Peak memory 255756 kb
Host smart-6a4884f7-6705-487d-a928-9e82a1283cc4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47809
2434 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.478092434
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.3487419297
Short name T647
Test name
Test status
Simulation time 2137768423 ps
CPU time 36.08 seconds
Started Aug 11 04:53:28 PM PDT 24
Finished Aug 11 04:54:04 PM PDT 24
Peak memory 248236 kb
Host smart-434eb4fa-bd68-4a8e-8da3-ff0eb9826cb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34874
19297 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.3487419297
Directory /workspace/9.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.884627994
Short name T314
Test name
Test status
Simulation time 28212728920 ps
CPU time 2009.18 seconds
Started Aug 11 04:53:25 PM PDT 24
Finished Aug 11 05:26:54 PM PDT 24
Peak memory 297356 kb
Host smart-72228a34-1247-41c6-9023-201848f1c21c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=884627994 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_hand
ler_stress_all.884627994
Directory /workspace/9.alert_handler_stress_all/latest
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