Unified Coverage Report :: Group :: tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

Group : tl_agent_pkg::tl_a_chan_cov_cg::SHAPE{(2 << ((valid_source_width - 1) - 1))=128}

SCORE	INSTANCES	WEIGHT	GOAL	AT LEAST	PER INSTANCE	AUTO BIN MAX	PRINT MISSING
100.00	100.00	1	100	1	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_tl_agent_0/tl_agent_cov.sv

1 Instances:

NAME	SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg	100.00	1	100	1	64	64

---

Group Instance : tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

---

Summary for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	134	0	134	100.00
Crosses	3	0	3	100.00

Variables for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_mask	1	0	1	100.00	100	1	1	0
cp_opcode	3	0	3	100.00	100	1	1	0
cp_size	1	0	1	100.00	100	1	1	0
cp_source	129	0	129	100.00	100	1	1	0

Crosses for Group Instance tl_agent_pkg.uvm_test_top.env.m_tl_agent_alert_handler_reg_block.cov::m_tl_a_chan_cov_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
tl_a_chan_cov_cg_cc	3	0	3	100.00	100	1	1	0

Summary for Variable cp_mask

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_mask

Excluded/Illegal bins

NAME	COUNT	STATUS
others	51081946	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_enables

24155041

1

T1

86132

T2

89837

T3

2853

---

Summary for Variable cp_opcode

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	3	0	3	100.00

User Defined Bins for cp_opcode

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x4]	11952942	1			T1	33583		T2	34795		T3	1276
values[0x0]	31594208	1			T1	119541		T2	123672		T3	3797
values[0x1]	31689837	1			T1	119033		T2	124220		T3	3787

---

Summary for Variable cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	1	0	1	100.00

User Defined Bins for cp_size

Excluded/Illegal bins

NAME	COUNT	STATUS
others	44476323	Excluded

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

biggest_size

30760664

1

T1

108745

T2

113466

T3

3589

---

Summary for Variable cp_source

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	129	0	129	100.00

User Defined Bins for cp_source

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
valid_sources[0x00]	506275	1			T1	1001		T10	24		T11	72
valid_sources[0x01]	239564	1			T1	1065		T10	17		T11	50
valid_sources[0x02]	234560	1			T1	1037		T10	26		T11	53
valid_sources[0x03]	234422	1			T1	1032		T10	71		T11	43
valid_sources[0x04]	233728	1			T1	1050		T10	40		T11	45
valid_sources[0x05]	242169	1			T1	1039		T10	13		T11	48
valid_sources[0x06]	244824	1			T1	1093		T10	33		T11	52
valid_sources[0x07]	241168	1			T1	1055		T10	22		T11	48
valid_sources[0x08]	232578	1			T1	1039		T10	12		T11	43
valid_sources[0x09]	241680	1			T1	1159		T10	66		T11	45
valid_sources[0x0a]	234384	1			T1	1025		T10	79		T11	60
valid_sources[0x0b]	554553	1			T1	1123		T10	13		T11	41
valid_sources[0x0c]	232401	1			T1	1100		T10	16		T11	43
valid_sources[0x0d]	233367	1			T1	1076		T10	12		T11	44
valid_sources[0x0e]	440266	1			T1	1070		T10	18		T11	49
valid_sources[0x0f]	243526	1			T1	1064		T11	48		T17	23
valid_sources[0x10]	232386	1			T1	983		T10	17		T11	40
valid_sources[0x11]	766070	1			T1	1055		T10	29		T11	44
valid_sources[0x12]	241987	1			T1	1077		T10	17		T11	52
valid_sources[0x13]	231792	1			T1	1069		T11	54		T17	20
valid_sources[0x14]	244485	1			T1	1056		T10	10		T11	47
valid_sources[0x15]	244861	1			T1	1051		T10	74		T11	69
valid_sources[0x16]	235322	1			T1	1022		T10	77		T11	56
valid_sources[0x17]	239261	1			T1	1068		T10	52		T11	51
valid_sources[0x18]	509636	1			T1	1062		T10	38		T11	33
valid_sources[0x19]	235071	1			T1	1037		T10	41		T11	52
valid_sources[0x1a]	234161	1			T1	1020		T10	12		T11	37
valid_sources[0x1b]	232720	1			T1	1031		T10	19		T11	51
valid_sources[0x1c]	235890	1			T1	1063		T10	14		T11	37
valid_sources[0x1d]	497633	1			T1	1078		T10	49		T11	36
valid_sources[0x1e]	242866	1			T1	1050		T10	1		T11	45
valid_sources[0x1f]	614974	1			T1	1095		T10	19		T11	43
valid_sources[0x20]	263250	1			T1	1056		T10	44		T11	43
valid_sources[0x21]	268800	1			T1	1026		T10	47		T11	40
valid_sources[0x22]	233805	1			T1	1019		T10	39		T11	46
valid_sources[0x23]	233008	1			T1	1038		T10	2		T11	41
valid_sources[0x24]	253709	1			T1	1072		T11	41		T17	19
valid_sources[0x25]	242520	1			T1	1096		T10	16		T11	46
valid_sources[0x26]	444664	1			T1	1040		T10	30		T11	53
valid_sources[0x27]	232509	1			T1	1011		T10	35		T11	49
valid_sources[0x28]	233308	1			T1	1061		T10	17		T11	55
valid_sources[0x29]	1101005	1			T1	1081		T10	25		T11	49
valid_sources[0x2a]	630617	1			T1	1057		T10	59		T11	51
valid_sources[0x2b]	234583	1			T1	1075		T10	26		T11	46
valid_sources[0x2c]	233208	1			T1	1007		T10	10		T11	57
valid_sources[0x2d]	727785	1			T1	1124		T10	30		T11	54
valid_sources[0x2e]	235884	1			T1	1047		T10	13		T11	36
valid_sources[0x2f]	242771	1			T1	1090		T10	35		T11	51
valid_sources[0x30]	235107	1			T1	1106		T10	16		T11	52
valid_sources[0x31]	237455	1			T1	1028		T10	8		T11	55
valid_sources[0x32]	250381	1			T1	1118		T10	34		T11	44
valid_sources[0x33]	600176	1			T1	1050		T10	67		T11	40
valid_sources[0x34]	235252	1			T1	1044		T10	31		T11	47
valid_sources[0x35]	247063	1			T1	1081		T10	3		T11	58
valid_sources[0x36]	235382	1			T1	1037		T10	126		T11	47
valid_sources[0x37]	232827	1			T1	1076		T11	37		T17	13
valid_sources[0x38]	235325	1			T1	1036		T10	46		T11	45
valid_sources[0x39]	234262	1			T1	1105		T10	143		T11	57
valid_sources[0x3a]	701264	1			T1	1089		T10	23		T11	48
valid_sources[0x3b]	233521	1			T1	1067		T10	12		T11	42
valid_sources[0x3c]	594319	1			T1	1127		T10	53		T11	58
valid_sources[0x3d]	239661	1			T1	1086		T10	51		T11	52
valid_sources[0x3e]	235505	1			T1	1114		T10	54		T11	49
valid_sources[0x3f]	234975	1			T1	1055		T10	11		T11	59
valid_sources[0x40]	233886	1			T1	1129		T10	45		T11	42
valid_sources[0x41]	237125	1			T1	1086		T10	2		T11	51
valid_sources[0x42]	236117	1			T1	1054		T10	41		T11	45
valid_sources[0x43]	238996	1			T1	1118		T10	11		T11	38
valid_sources[0x44]	776064	1			T1	1047		T10	8		T11	54
valid_sources[0x45]	276401	1			T1	1066		T10	45		T11	34
valid_sources[0x46]	233462	1			T1	1042		T10	55		T11	50
valid_sources[0x47]	666324	1			T1	1023		T10	26		T11	54
valid_sources[0x48]	236166	1			T1	1042		T10	10		T11	48
valid_sources[0x49]	236850	1			T1	1080		T10	2		T11	47
valid_sources[0x4a]	230750	1			T1	1109		T10	55		T11	50
valid_sources[0x4b]	235332	1			T1	1029		T10	38		T11	43
valid_sources[0x4c]	233082	1			T1	1061		T10	8		T11	51
valid_sources[0x4d]	241502	1			T1	1082		T10	17		T11	47
valid_sources[0x4e]	234905	1			T1	1061		T10	40		T11	55
valid_sources[0x4f]	230641	1			T1	1109		T10	28		T11	60
valid_sources[0x50]	234543	1			T1	1084		T10	55		T11	55
valid_sources[0x51]	233471	1			T1	1004		T11	51		T17	15
valid_sources[0x52]	707983	1			T1	1118		T10	8		T11	56
valid_sources[0x53]	234222	1			T1	1067		T10	9		T11	46
valid_sources[0x54]	475926	1			T1	1111		T10	24		T11	51
valid_sources[0x55]	723279	1			T1	1070		T10	38		T11	49
valid_sources[0x56]	253305	1			T1	1045		T10	38		T11	57
valid_sources[0x57]	243536	1			T1	1072		T10	68		T11	40
valid_sources[0x58]	234481	1			T1	1043		T10	30		T11	54
valid_sources[0x59]	231185	1			T1	1036		T10	19		T11	59
valid_sources[0x5a]	248990	1			T1	1039		T10	14		T11	53
valid_sources[0x5b]	236749	1			T1	1013		T10	23		T11	37
valid_sources[0x5c]	242809	1			T1	1075		T10	41		T11	44
valid_sources[0x5d]	243252	1			T1	1061		T10	18		T11	47
valid_sources[0x5e]	236623	1			T1	1113		T11	47		T17	4
valid_sources[0x5f]	235187	1			T1	1048		T10	13		T11	51
valid_sources[0x60]	233914	1			T1	1087		T11	51		T17	20
valid_sources[0x61]	236787	1			T1	1044		T10	89		T11	58
valid_sources[0x62]	238939	1			T1	1097		T10	55		T11	44
valid_sources[0x63]	274833	1			T1	983		T10	16		T11	47
valid_sources[0x64]	237453	1			T1	1039		T10	73		T11	42
valid_sources[0x65]	233354	1			T1	1050		T10	31		T11	43
valid_sources[0x66]	238296	1			T1	1038		T10	67		T11	55
valid_sources[0x67]	229709	1			T1	1007		T10	45		T11	44
valid_sources[0x68]	270868	1			T1	1000		T10	22		T11	48
valid_sources[0x69]	231556	1			T1	1077		T10	51		T11	45
valid_sources[0x6a]	234571	1			T1	1026		T10	61		T11	49
valid_sources[0x6b]	714728	1			T1	1128		T10	13		T11	57
valid_sources[0x6c]	234658	1			T1	1097		T10	21		T11	45
valid_sources[0x6d]	236597	1			T1	1096		T10	12		T11	49
valid_sources[0x6e]	246559	1			T1	1140		T3	8860		T10	7
valid_sources[0x6f]	234221	1			T1	1060		T10	51		T11	53
valid_sources[0x70]	235616	1			T1	1015		T10	37		T11	53
valid_sources[0x71]	231381	1			T1	1022		T10	35		T11	54
valid_sources[0x72]	234394	1			T1	1023		T10	53		T11	57
valid_sources[0x73]	240625	1			T1	1045		T10	18		T11	49
valid_sources[0x74]	257719	1			T1	1048		T10	29		T11	50
valid_sources[0x75]	244061	1			T1	1047		T10	3		T11	51
valid_sources[0x76]	240174	1			T1	1163		T10	56		T11	41
valid_sources[0x77]	231335	1			T1	1076		T10	47		T11	41
valid_sources[0x78]	239966	1			T1	1068		T10	53		T11	48
valid_sources[0x79]	236469	1			T1	1037		T10	40		T11	66
valid_sources[0x7a]	681869	1			T1	1123		T11	39		T17	13
valid_sources[0x7b]	241119	1			T1	1085		T10	38		T11	45
valid_sources[0x7c]	236732	1			T1	970		T10	42		T11	46
valid_sources[0x7d]	237518	1			T1	1103		T10	12		T11	52
valid_sources[0x7e]	233595	1			T1	1079		T10	59		T11	48
valid_sources[0x7f]	234536	1			T1	994		T10	21		T11	40
valid_sources[0x80]	278297	1			T1	1021		T10	35		T11	46

---

Summary for Cross tl_a_chan_cov_cg_cc

Samples crossed: cp_opcode cp_mask cp_size

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	3	0	3	100.00

Automatically Generated Cross Bins for tl_a_chan_cov_cg_cc

Bins

cp_opcode

cp_mask

cp_size

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

values[0x4]

all_enables

biggest_size

5728343

1

T1

16895

T2

17481

T3

655

values[0x0]

all_enables

biggest_size

11771173

1

T1

44272

T2

46104

T3

1403

values[0x1]

all_enables

biggest_size

6655525

1

T1

24965

T2

26252

T3

795