Unified Coverage Report :: Module :: alert_handler_accu

Module : alert_handler_accu

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[0].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[1].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[2].u_accu	100.00	100.00	100.00				100.00
tb.dut.gen_classes[3].u_accu	100.00	100.00	100.00				100.00

---

Module Instance : tb.dut.gen_classes[0].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[1].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[2].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

---

Module Instance : tb.dut.gen_classes[3].u_accu

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00				100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
100.00	100.00	100.00	100.00			100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	100.00			100.00

Line Coverage for Module : alert_handler_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Module : alert_handler_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T18,T125,T206
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	2147483647	13610	0	0
DisabledNoTrigBkwd_A	2147483647	720110	0	0
DisabledNoTrigFwd_A	2147483647	1154544846	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	13610	0	0
T4	177015	0	0	0
T12	65124	0	0	0
T14	270244	0	0	0
T18	3567	1133	0	0
T19	48066	0	0	0
T20	26304	0	0	0
T22	45629	0	0	0
T44	181262	0	0	0
T45	19380	0	0	0
T46	19696	0	0	0
T49	206262	0	0	0
T64	47559	0	0	0
T68	136440	0	0	0
T69	206347	0	0	0
T70	42766	0	0	0
T87	11080	0	0	0
T88	0	1291	0	0
T125	3161	741	0	0
T129	325806	0	0	0
T206	3895	787	0	0
T207	2858	397	0	0
T208	0	326	0	0
T209	0	976	0	0
T210	0	517	0	0
T211	0	506	0	0
T212	0	806	0	0
T213	0	152	0	0
T214	0	585	0	0
T215	0	234	0	0
T216	0	310	0	0
T217	0	1057	0	0
T218	0	829	0	0
T219	0	641	0	0
T220	0	728	0	0
T221	0	1315	0	0
T222	0	279	0	0
T223	329729	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	720110	0	0
T1	882516	1009	0	0
T2	997628	276	0	0
T3	3183200	2	0	0
T4	177015	9773	0	0
T5	0	1927	0	0
T10	100596	0	0	0
T11	491380	12	0	0
T12	260496	142	0	0
T13	0	2738	0	0
T15	0	27	0	0
T17	73284	35	0	0
T18	14268	21	0	0
T19	192264	56	0	0
T20	105216	149	0	0
T44	0	313	0	0
T45	0	7	0	0
T46	0	16	0	0
T47	0	23	0	0
T48	0	36	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	1154544846	0	0
T1	1176688	599409	0	0
T2	997628	526302	0	0
T3	3183200	1874752	0	0
T10	100596	31392	0	0
T11	491380	451175	0	0
T12	260496	106088	0	0
T17	73284	40737	0	0
T18	14268	8634	0	0
T19	192264	79725	0	0
T20	105216	15837	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T10,T11
1	1	Covered	T1,T3,T10

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T18,T206,T210
1	1	Covered	T1,T3,T10

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T10,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T11

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	541062723	5143	0	0
DisabledNoTrigBkwd_A	541062723	222454	0	0
DisabledNoTrigFwd_A	541062723	259573133	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541062723	5143	0	0
T4	177015	0	0	0
T12	65124	0	0	0
T14	270244	0	0	0
T18	3567	1133	0	0
T19	48066	0	0	0
T20	26304	0	0	0
T44	181262	0	0	0
T45	19380	0	0	0
T46	19696	0	0	0
T64	47559	0	0	0
T206	0	787	0	0
T210	0	517	0	0
T212	0	806	0	0
T214	0	585	0	0
T221	0	1315	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541062723	222454	0	0
T1	294172	536	0	0
T2	249407	0	0	0
T3	795800	0	0	0
T4	0	4874	0	0
T10	25149	0	0	0
T11	122845	12	0	0
T12	65124	27	0	0
T17	18321	14	0	0
T18	3567	21	0	0
T19	48066	18	0	0
T20	26304	33	0	0
T45	0	7	0	0
T46	0	9	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541062723	259573133	0	0
T1	294172	9028	0	0
T2	249407	30897	0	0
T3	795800	651806	0	0
T10	25149	4326	0	0
T11	122845	94085	0	0
T12	65124	10046	0	0
T17	18321	3673	0	0
T18	3567	2135	0	0
T19	48066	14796	0	0
T20	26304	582	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T10,T12

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T125,T209,T215
1	1	Covered	T2,T10,T12

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T10,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T12,T19

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	541062723	2989	0	0
DisabledNoTrigBkwd_A	541062723	175277	0	0
DisabledNoTrigFwd_A	541062723	297164597	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541062723	2989	0	0
T22	45629	0	0	0
T49	206262	0	0	0
T68	136440	0	0	0
T69	206347	0	0	0
T70	42766	0	0	0
T87	11080	0	0	0
T125	3161	741	0	0
T129	325806	0	0	0
T206	3895	0	0	0
T209	0	976	0	0
T215	0	234	0	0
T216	0	310	0	0
T220	0	728	0	0
T223	329729	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541062723	175277	0	0
T2	249407	2	0	0
T3	795800	0	0	0
T4	177015	836	0	0
T5	0	1669	0	0
T10	25149	0	0	0
T11	122845	0	0	0
T12	65124	80	0	0
T13	0	1235	0	0
T15	0	6	0	0
T17	18321	0	0	0
T18	3567	0	0	0
T19	48066	18	0	0
T20	26304	31	0	0
T44	0	181	0	0
T46	0	6	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541062723	297164597	0	0
T1	294172	292132	0	0
T2	249407	246190	0	0
T3	795800	48725	0	0
T10	25149	23052	0	0
T11	122845	111418	0	0
T12	65124	17772	0	0
T17	18321	18235	0	0
T18	3567	2149	0	0
T19	48066	2090	0	0
T20	26304	6428	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T2,T3,T10
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T207,T208,T213
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T12

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	541062723	3681	0	0
DisabledNoTrigBkwd_A	541062723	168573	0	0
DisabledNoTrigFwd_A	541062723	303186923	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541062723	3681	0	0
T28	306769	0	0	0
T55	66078	0	0	0
T83	49883	0	0	0
T207	2858	397	0	0
T208	0	326	0	0
T213	0	152	0	0
T217	0	1057	0	0
T218	0	829	0	0
T219	0	641	0	0
T222	0	279	0	0
T224	215885	0	0	0
T225	26918	0	0	0
T226	140233	0	0	0
T227	17999	0	0	0
T228	401062	0	0	0
T229	125218	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541062723	168573	0	0
T1	294172	471	0	0
T2	249407	2	0	0
T3	795800	0	0	0
T4	0	2079	0	0
T5	0	258	0	0
T10	25149	0	0	0
T11	122845	0	0	0
T12	65124	24	0	0
T13	0	1503	0	0
T17	18321	0	0	0
T18	3567	0	0	0
T19	48066	0	0	0
T20	26304	41	0	0
T44	0	132	0	0
T47	0	23	0	0
T48	0	36	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541062723	303186923	0	0
T1	294172	7317	0	0
T2	249407	247092	0	0
T3	795800	488848	0	0
T10	25149	2005	0	0
T11	122845	122836	0	0
T12	65124	21339	0	0
T17	18321	18235	0	0
T18	3567	2163	0	0
T19	48066	48008	0	0
T20	26304	8233	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Line No.	Total	Covered	Percent
TOTAL		3	3	100.00
CONT_ASSIGN	28	1	1	100.00
CONT_ASSIGN	29	1	1	100.00
CONT_ASSIGN	56	1	1	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_accu.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
28	1	1
29	1	1
56	1	1

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Covered	Percent
Conditions	9	9	100.00
Logical	9	9	100.00
Non-Logical	0	0
Event	0	0

 LINE       28
 EXPRESSION (class_trig_i & class_en_i)
             ------1-----   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T3,T10
1	1	Covered	T1,T2,T3

 LINE       29
 EXPRESSION (trig_gated && ((!(&accu_cnt_o))))
             -----1----    ---------2--------

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T88,T211
1	1	Covered	T1,T2,T3

 LINE       56
 EXPRESSION ((accu_cnt_o >= thresh_i) & trig_gated)
             ------------1-----------   -----2----

-1-	-2-	Status	Tests
0	1	Covered	T2,T3,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_accu

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	3	3	100.00	3	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	3	3	100.00	3	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
CountSaturateStable_A	541062723	1797	0	0
DisabledNoTrigBkwd_A	541062723	153806	0	0
DisabledNoTrigFwd_A	541062723	294620193	0	0

CountSaturateStable_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541062723	1797	0	0
T71	29963	0	0	0
T72	119620	0	0	0
T88	5519	1291	0	0
T89	288682	0	0	0
T90	12443	0	0	0
T91	347717	0	0	0
T92	123614	0	0	0
T93	892572	0	0	0
T94	7915	0	0	0
T211	0	506	0	0
T230	4339	0	0	0

DisabledNoTrigBkwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541062723	153806	0	0
T1	294172	2	0	0
T2	249407	272	0	0
T3	795800	2	0	0
T4	0	1984	0	0
T10	25149	0	0	0
T11	122845	0	0	0
T12	65124	11	0	0
T15	0	21	0	0
T17	18321	21	0	0
T18	3567	0	0	0
T19	48066	20	0	0
T20	26304	44	0	0
T46	0	1	0	0

DisabledNoTrigFwd_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541062723	294620193	0	0
T1	294172	290932	0	0
T2	249407	2123	0	0
T3	795800	685373	0	0
T10	25149	2009	0	0
T11	122845	122836	0	0
T12	65124	56931	0	0
T17	18321	594	0	0
T18	3567	2187	0	0
T19	48066	14831	0	0
T20	26304	594	0	0