Unified Coverage Report :: Module :: alert_handler_esc_timer

Module : alert_handler_esc_timer

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
92.30	100.00	91.49		70.00	100.00	100.00

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv

Module self-instances :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
tb.dut.gen_classes[1].u_esc_timer	98.67	100.00	93.33		100.00	100.00	100.00
tb.dut.gen_classes[0].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00
tb.dut.gen_classes[2].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00
tb.dut.gen_classes[3].u_esc_timer	99.11	100.00	95.56		100.00	100.00	100.00

---

Module Instance : tb.dut.gen_classes[1].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
98.67	100.00	93.33		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
93.65	100.00	93.33	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[0].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.02	100.00	95.56	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[2].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.02	100.00	95.56	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

---

Module Instance : tb.dut.gen_classes[3].u_esc_timer

Instance :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
99.11	100.00	95.56		100.00	100.00	100.00

Instance's subtree :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
94.02	100.00	95.56	68.57	100.00	100.00	100.00

Parent :

SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT	NAME
100.00	100.00		100.00			100.00	dut

Subtrees :

NAME	SCORE	LINE	COND	TOGGLE	FSM	BRANCH	ASSERT
u_prim_count	68.57			68.57
u_state_regs	100.00	100.00				100.00	100.00

Line Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Module : alert_handler_esc_timer

	Total	Covered	Percent
Conditions	47	43	91.49
Logical	47	43	91.49
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T1,T2,T3
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T10,T12,T20
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T10,T12,T20
1	1	1	Covered	T10,T12,T20

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T10,T12,T20
0	1	Covered	T12,T4,T22
1	0	Covered	T12,T4,T5

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T10,T12,T20
1	0	1	Not Covered
1	1	0	Not Covered
1	1	1	Covered	T12,T4,T5

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T12,T20
1	0	Covered	T4,T22,T23
1	1	Covered	T12,T4,T22

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T18,T12,T19

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T1,T12,T20

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T11
1	Covered	T1,T2,T17

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T17
1	Covered	T2,T11,T20

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T3

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T3

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T11,T17,T18

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T3,T11,T17

---

FSM Coverage for Module : alert_handler_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	20	14	70.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T7,T8,T9
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T3
Phase1St	198	Covered	T1,T2,T3
Phase2St	215	Covered	T1,T2,T3
Phase3St	233	Covered	T1,T2,T3
TerminalSt	249	Covered	T1,T2,T3
TimeoutSt	159	Covered	T10,T12,T20

transitions	Line No.	Covered	Tests
IdleSt->FsmErrorSt	284	Covered	T7,T8,T9
IdleSt->Phase0St	152	Covered	T1,T2,T3
IdleSt->TimeoutSt	159	Covered	T10,T12,T20
Phase0St->FsmErrorSt	284	Not Covered
Phase0St->IdleSt	194	Covered	T21,T24,T25
Phase0St->Phase1St	198	Covered	T1,T2,T3
Phase1St->FsmErrorSt	284	Not Covered
Phase1St->IdleSt	211	Covered	T20,T26,T27
Phase1St->Phase2St	215	Covered	T1,T2,T3
Phase2St->FsmErrorSt	284	Not Covered
Phase2St->IdleSt	229	Covered	T21,T26,T28
Phase2St->Phase3St	233	Covered	T1,T2,T3
Phase3St->FsmErrorSt	284	Not Covered
Phase3St->IdleSt	245	Covered	T20,T29,T30
Phase3St->TerminalSt	249	Covered	T1,T2,T3
TerminalSt->FsmErrorSt	284	Not Covered
TerminalSt->IdleSt	261	Covered	T3,T12,T19
TimeoutSt->FsmErrorSt	284	Not Covered
TimeoutSt->IdleSt	181	Covered	T10,T12,T20
TimeoutSt->Phase0St	172	Covered	T12,T4,T5

---

Branch Coverage for Module : alert_handler_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T12,T20
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T12,T4,T5
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T10,T12,T20
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T10,T12,T20
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T4,T21,T31
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T20,T27,T32
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T21,T28,T33
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T20,T29,T30
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T3,T12,T19
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Module : alert_handler_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	2147483647	818	0	0
CheckAccumTrig0_A	2147483647	2041	0	0
CheckAccumTrig1_A	2147483647	101	0	0
CheckClr_A	2147483647	890	0	0
CheckEn_A	2147483647	860104982	0	0
CheckPhase0_A	2147483647	2289	0	0
CheckPhase1_A	2147483647	2242	0	0
CheckPhase2_A	2147483647	2206	0	0
CheckPhase3_A	2147483647	2183	0	0
CheckTimeout0_A	2147483647	3258	0	0
CheckTimeoutSt1_A	2147483647	304607	0	0
CheckTimeoutSt2_A	2147483647	2953	0	0
CheckTimeoutStTrig_A	2147483647	197	0	0
ErrorStAllEscAsserted_A	2147483647	4565	0	0
ErrorStIsTerminal_A	2147483647	3725	0	0
EscStateOut_A	2147483647	2147483647	0	0
u_state_regs_A	2147483647	2147483647	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	818	0	0
T7	88800	138	0	0
T8	63064	100	0	0
T9	0	102	0	0
T34	0	218	0	0
T35	0	260	0	0
T36	3450760	0	0	0
T37	1329376	0	0	0
T38	510460	0	0	0
T39	60592	0	0	0
T40	496664	0	0	0
T41	2287548	0	0	0
T42	59600	0	0	0
T43	268452	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2041	0	0
T1	882516	3	0	0
T2	997628	3	0	0
T3	3183200	1	0	0
T4	177015	31	0	0
T5	0	8	0	0
T10	100596	0	0	0
T11	491380	1	0	0
T12	260496	4	0	0
T13	0	2	0	0
T15	0	3	0	0
T17	73284	2	0	0
T18	14268	1	0	0
T19	192264	7	0	0
T20	105216	7	0	0
T44	0	2	0	0
T45	0	1	0	0
T46	0	3	0	0
T47	0	2	0	0
T48	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	101	0	0
T4	531045	2	0	0
T5	161247	1	0	0
T6	98623	0	0	0
T12	65124	1	0	0
T13	1199348	0	0	0
T14	810732	0	0	0
T15	56274	0	0	0
T16	213663	0	0	0
T19	48066	0	0	0
T20	26304	0	0	0
T21	451369	0	0	0
T29	5254	0	0	0
T31	0	1	0	0
T32	0	1	0	0
T33	0	1	0	0
T44	543786	0	0	0
T45	58140	0	0	0
T46	59088	0	0	0
T47	28951	0	0	0
T48	84536	0	0	0
T49	0	1	0	0
T50	0	2	0	0
T51	0	1	0	0
T52	0	1	0	0
T53	0	2	0	0
T54	0	1	0	0
T55	0	2	0	0
T56	0	2	0	0
T57	0	2	0	0
T58	0	1	0	0
T59	0	2	0	0
T60	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	2	0	0
T64	142677	0	0	0
T65	15064	0	0	0
T66	96852	0	0	0
T67	332202	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	890	0	0
T3	795800	1	0	0
T4	708060	10	0	0
T5	0	3	0	0
T10	25149	0	0	0
T11	122845	0	0	0
T12	195372	2	0	0
T14	810732	0	0	0
T15	56274	1	0	0
T16	0	3	0	0
T17	18321	0	0	0
T18	3567	0	0	0
T19	144198	4	0	0
T20	105216	3	0	0
T21	0	11	0	0
T29	0	1	0	0
T30	0	1	0	0
T44	725048	0	0	0
T45	58140	0	0	0
T46	59088	0	0	0
T47	0	2	0	0
T50	0	3	0	0
T64	142677	0	0	0
T65	7532	0	0	0
T66	48426	0	0	0
T68	0	11	0	0
T69	0	1	0	0
T70	0	2	0	0
T71	0	1	0	0
T72	0	2	0	0
T73	0	3	0	0
T74	0	5	0	0
T75	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	860104982	0	0
T1	1176688	342253	0	0
T2	997628	68552	0	0
T3	3183200	1773873	0	0
T10	100596	31391	0	0
T11	491380	375596	0	0
T12	260496	39278	0	0
T17	73284	37644	0	0
T18	14268	8634	0	0
T19	192264	79724	0	0
T20	105216	15837	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2289	0	0
T1	882516	3	0	0
T2	997628	3	0	0
T3	3183200	1	0	0
T4	177015	33	0	0
T5	0	9	0	0
T10	100596	0	0	0
T11	491380	1	0	0
T12	260496	6	0	0
T13	0	2	0	0
T15	0	3	0	0
T17	73284	2	0	0
T18	14268	1	0	0
T19	192264	7	0	0
T20	105216	7	0	0
T44	0	2	0	0
T45	0	1	0	0
T46	0	3	0	0
T47	0	2	0	0
T48	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2242	0	0
T1	882516	3	0	0
T2	997628	3	0	0
T3	3183200	1	0	0
T4	177015	33	0	0
T5	0	9	0	0
T10	100596	0	0	0
T11	491380	1	0	0
T12	260496	6	0	0
T13	0	3	0	0
T15	0	3	0	0
T17	73284	2	0	0
T18	14268	1	0	0
T19	192264	7	0	0
T20	105216	6	0	0
T44	0	2	0	0
T45	0	1	0	0
T46	0	2	0	0
T47	0	2	0	0
T48	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2206	0	0
T1	882516	3	0	0
T2	997628	3	0	0
T3	3183200	1	0	0
T4	177015	32	0	0
T5	0	9	0	0
T10	100596	0	0	0
T11	491380	1	0	0
T12	260496	6	0	0
T13	0	3	0	0
T15	0	3	0	0
T17	73284	2	0	0
T18	14268	1	0	0
T19	192264	7	0	0
T20	105216	6	0	0
T44	0	2	0	0
T45	0	1	0	0
T46	0	2	0	0
T47	0	2	0	0
T48	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2183	0	0
T1	882516	3	0	0
T2	997628	3	0	0
T3	3183200	1	0	0
T4	177015	32	0	0
T5	0	9	0	0
T10	100596	0	0	0
T11	491380	1	0	0
T12	260496	6	0	0
T13	0	3	0	0
T15	0	3	0	0
T17	73284	2	0	0
T18	14268	1	0	0
T19	192264	7	0	0
T20	105216	5	0	0
T44	0	2	0	0
T45	0	1	0	0
T46	0	2	0	0
T47	0	2	0	0
T48	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3258	0	0
T4	708060	15	0	0
T5	0	18	0	0
T6	0	1	0	0
T10	100596	20	0	0
T11	491380	0	0	0
T12	260496	5	0	0
T15	0	2	0	0
T17	73284	0	0	0
T18	14268	0	0	0
T19	192264	0	0	0
T20	105216	2	0	0
T22	0	22	0	0
T26	0	1	0	0
T31	0	4	0	0
T44	725048	0	0	0
T45	77520	1	0	0
T46	0	1	0	0
T47	0	8	0	0
T49	0	5	0	0
T66	0	7	0	0
T68	0	6	0	0
T72	0	1	0	0
T76	0	1	0	0
T77	0	2	0	0
T78	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	304607	0	0
T4	708060	1847	0	0
T5	0	846	0	0
T6	0	60	0	0
T10	100596	1025	0	0
T11	491380	0	0	0
T12	260496	1679	0	0
T15	0	128	0	0
T17	73284	0	0	0
T18	14268	0	0	0
T19	192264	0	0	0
T20	105216	497	0	0
T22	0	2649	0	0
T26	0	151	0	0
T31	0	815	0	0
T44	725048	0	0	0
T45	77520	31	0	0
T46	0	25	0	0
T47	0	898	0	0
T49	0	558	0	0
T50	0	458	0	0
T66	0	1523	0	0
T68	0	900	0	0
T72	0	71	0	0
T76	0	229	0	0
T77	0	444	0	0
T78	0	114	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2953	0	0
T4	708060	12	0	0
T5	0	16	0	0
T6	0	1	0	0
T10	100596	20	0	0
T11	491380	0	0	0
T12	260496	3	0	0
T15	0	2	0	0
T17	73284	0	0	0
T18	14268	0	0	0
T19	192264	0	0	0
T20	105216	2	0	0
T22	0	20	0	0
T26	0	1	0	0
T31	0	6	0	0
T44	725048	0	0	0
T45	77520	1	0	0
T46	0	1	0	0
T47	0	8	0	0
T49	0	4	0	0
T50	0	3	0	0
T66	0	7	0	0
T68	0	6	0	0
T72	0	1	0	0
T76	0	1	0	0
T78	0	1	0	0
T79	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	197	0	0
T4	177015	1	0	0
T12	65124	1	0	0
T14	270244	0	0	0
T15	18758	0	0	0
T19	48066	0	0	0
T20	26304	0	0	0
T22	45629	2	0	0
T23	0	2	0	0
T25	0	2	0	0
T28	0	1	0	0
T31	0	1	0	0
T32	0	1	0	0
T33	0	3	0	0
T44	181262	0	0	0
T45	19380	0	0	0
T46	19696	0	0	0
T50	0	2	0	0
T55	0	1	0	0
T56	0	3	0	0
T57	0	6	0	0
T64	47559	0	0	0
T70	42766	0	0	0
T77	22922	2	0	0
T80	0	1	0	0
T81	0	2	0	0
T82	0	1	0	0
T83	0	1	0	0
T84	0	1	0	0
T85	0	1	0	0
T86	0	2	0	0
T87	11080	0	0	0
T88	5519	0	0	0
T89	288682	0	0	0
T90	12443	0	0	0
T91	347717	0	0	0
T92	123614	0	0	0
T93	892572	0	0	0
T94	7915	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	4565	0	0
T7	88800	664	0	0
T8	63064	611	0	0
T9	0	648	0	0
T34	0	1338	0	0
T35	0	1304	0	0
T36	3450760	0	0	0
T37	1329376	0	0	0
T38	510460	0	0	0
T39	60592	0	0	0
T40	496664	0	0	0
T41	2287548	0	0	0
T42	59600	0	0	0
T43	268452	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	3725	0	0
T7	88800	544	0	0
T8	63064	491	0	0
T9	0	528	0	0
T34	0	1098	0	0
T35	0	1064	0	0
T36	3450760	0	0	0
T37	1329376	0	0	0
T38	510460	0	0	0
T39	60592	0	0	0
T40	496664	0	0	0
T41	2287548	0	0	0
T42	59600	0	0	0
T43	268452	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1176688	1176656	0	0
T2	997628	997592	0	0
T3	3183200	3182960	0	0
T10	100596	100320	0	0
T11	491380	491344	0	0
T12	260496	260096	0	0
T17	73284	72940	0	0
T18	14268	13892	0	0
T19	192264	192032	0	0
T20	105216	104816	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	2147483647	2147483647	0	0
T1	1176688	1176656	0	0
T2	997628	997592	0	0
T3	3183200	3182960	0	0
T10	100596	100320	0	0
T11	491380	491344	0	0
T12	260496	260096	0	0
T17	73284	72940	0	0
T18	14268	13892	0	0
T19	192264	192032	0	0
T20	105216	104816	0	0

Line Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Covered	Percent
Conditions	45	42	93.33
Logical	45	42	93.33
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T2,T10,T12
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T2,T10,T12
1	0	Covered	T1,T2,T3
1	1	Covered	T2,T10,T12

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T2,T12,T19

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T10,T12,T20
1	0	1	Covered	T2,T4,T44
1	1	0	Covered	T10,T20,T4
1	1	1	Covered	T10,T12,T4

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T10,T12,T4
0	1	Covered	T22,T31,T25
1	0	Covered	T12,T5,T49

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T10,T12,T4
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T12,T5,T49

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T12,T4
1	0	Not Covered
1	1	Covered	T22,T31,T25

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T12,T20
1	Covered	T12,T19,T4

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T2,T12,T19
1	Covered	T20,T4,T5

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T12,T19
1	Covered	T12,T4,T44

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T12,T19,T20
1	Covered	T2,T4,T15

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T2,T12,T19

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T19,T20,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T12,T19,T20

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T12,T19,T20

---

FSM Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T7,T8,T9
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T2,T12,T19
Phase1St	198	Covered	T2,T12,T19
Phase2St	215	Covered	T2,T12,T19
Phase3St	233	Covered	T2,T12,T19
TerminalSt	249	Covered	T2,T12,T19
TimeoutSt	159	Covered	T10,T12,T4

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T7,T8,T9
IdleSt->Phase0St	152	Covered	T2,T12,T19
IdleSt->TimeoutSt	159	Covered	T10,T12,T4
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T24,T25,T95
Phase0St->Phase1St	198	Covered	T2,T12,T19
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T27,T96,T97
Phase1St->Phase2St	215	Covered	T2,T12,T19
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T28,T98,T99
Phase2St->Phase3St	233	Covered	T2,T12,T19
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T20,T30,T32
Phase3St->TerminalSt	249	Covered	T2,T12,T19
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T12,T4,T15
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T10,T12,T4
TimeoutSt->Phase0St	172	Covered	T12,T5,T49

---

Branch Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T2,T12,T19
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T12,T4
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T12,T5,T49
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T10,T12,T4
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T10,T12,T4
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T24,T25,T100
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T2,T12,T19
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T2,T12,T19
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T27,T96,T101
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T2,T12,T19
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T2,T12,T19
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T28,T98,T99
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T2,T12,T19
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T2,T12,T19
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T20,T30,T32
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T2,T12,T19
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T2,T12,T19
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T12,T4,T15
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T2,T12,T19
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[1].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	541062723	206	0	0
CheckAccumTrig0_A	541062723	449	0	0
CheckAccumTrig1_A	541062723	23	0	0
CheckClr_A	541062723	184	0	0
CheckEn_A	540829936	225526226	0	0
CheckPhase0_A	541062723	507	0	0
CheckPhase1_A	541062723	501	0	0
CheckPhase2_A	541062723	495	0	0
CheckPhase3_A	541062723	490	0	0
CheckTimeout0_A	541062723	869	0	0
CheckTimeoutSt1_A	541062723	78603	0	0
CheckTimeoutSt2_A	541062723	802	0	0
CheckTimeoutStTrig_A	541062723	41	0	0
ErrorStAllEscAsserted_A	541062723	1123	0	0
ErrorStIsTerminal_A	541062723	913	0	0
EscStateOut_A	540828786	540762043	0	0
u_state_regs_A	541062723	540905810	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541062723	206	0	0
T7	22200	30	0	0
T8	15766	16	0	0
T9	0	25	0	0
T34	0	64	0	0
T35	0	71	0	0
T36	862690	0	0	0
T37	332344	0	0	0
T38	127615	0	0	0
T39	15148	0	0	0
T40	124166	0	0	0
T41	571887	0	0	0
T42	14900	0	0	0
T43	67113	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541062723	449	0	0
T2	249407	1	0	0
T3	795800	0	0	0
T4	177015	10	0	0
T5	0	3	0	0
T10	25149	0	0	0
T11	122845	0	0	0
T12	65124	1	0	0
T13	0	1	0	0
T15	0	2	0	0
T17	18321	0	0	0
T18	3567	0	0	0
T19	48066	1	0	0
T20	26304	2	0	0
T44	0	1	0	0
T46	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541062723	23	0	0
T4	177015	0	0	0
T5	0	1	0	0
T12	65124	1	0	0
T14	270244	0	0	0
T15	18758	0	0	0
T19	48066	0	0	0
T20	26304	0	0	0
T31	0	1	0	0
T44	181262	0	0	0
T45	19380	0	0	0
T46	19696	0	0	0
T49	0	1	0	0
T51	0	1	0	0
T53	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T59	0	2	0	0
T60	0	1	0	0
T64	47559	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541062723	184	0	0
T4	177015	3	0	0
T5	0	1	0	0
T12	65124	1	0	0
T14	270244	0	0	0
T15	18758	1	0	0
T16	0	1	0	0
T19	48066	0	0	0
T20	26304	1	0	0
T21	0	1	0	0
T30	0	1	0	0
T44	181262	0	0	0
T45	19380	0	0	0
T46	19696	0	0	0
T64	47559	0	0	0
T70	0	1	0	0
T72	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	540829936	225526226	0	0
T1	294172	292132	0	0
T2	249407	14911	0	0
T3	795800	48725	0	0
T10	25149	23051	0	0
T11	122845	111418	0	0
T12	65124	9629	0	0
T17	18321	18234	0	0
T18	3567	2149	0	0
T19	48066	2090	0	0
T20	26304	6428	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541062723	507	0	0
T2	249407	1	0	0
T3	795800	0	0	0
T4	177015	10	0	0
T5	0	4	0	0
T10	25149	0	0	0
T11	122845	0	0	0
T12	65124	2	0	0
T13	0	1	0	0
T15	0	2	0	0
T17	18321	0	0	0
T18	3567	0	0	0
T19	48066	1	0	0
T20	26304	2	0	0
T44	0	1	0	0
T46	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541062723	501	0	0
T2	249407	1	0	0
T3	795800	0	0	0
T4	177015	10	0	0
T5	0	4	0	0
T10	25149	0	0	0
T11	122845	0	0	0
T12	65124	2	0	0
T13	0	1	0	0
T15	0	2	0	0
T17	18321	0	0	0
T18	3567	0	0	0
T19	48066	1	0	0
T20	26304	2	0	0
T44	0	1	0	0
T46	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541062723	495	0	0
T2	249407	1	0	0
T3	795800	0	0	0
T4	177015	10	0	0
T5	0	4	0	0
T10	25149	0	0	0
T11	122845	0	0	0
T12	65124	2	0	0
T13	0	1	0	0
T15	0	2	0	0
T17	18321	0	0	0
T18	3567	0	0	0
T19	48066	1	0	0
T20	26304	2	0	0
T44	0	1	0	0
T46	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541062723	490	0	0
T2	249407	1	0	0
T3	795800	0	0	0
T4	177015	10	0	0
T5	0	4	0	0
T10	25149	0	0	0
T11	122845	0	0	0
T12	65124	2	0	0
T13	0	1	0	0
T15	0	2	0	0
T17	18321	0	0	0
T18	3567	0	0	0
T19	48066	1	0	0
T20	26304	1	0	0
T44	0	1	0	0
T46	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541062723	869	0	0
T4	177015	2	0	0
T5	0	16	0	0
T10	25149	1	0	0
T11	122845	0	0	0
T12	65124	2	0	0
T15	0	1	0	0
T17	18321	0	0	0
T18	3567	0	0	0
T19	48066	0	0	0
T20	26304	0	0	0
T22	0	1	0	0
T26	0	1	0	0
T44	181262	0	0	0
T45	19380	0	0	0
T49	0	3	0	0
T68	0	2	0	0
T72	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541062723	78603	0	0
T4	177015	67	0	0
T5	0	794	0	0
T10	25149	41	0	0
T11	122845	0	0	0
T12	65124	59	0	0
T15	0	64	0	0
T17	18321	0	0	0
T18	3567	0	0	0
T19	48066	0	0	0
T20	26304	0	0	0
T22	0	104	0	0
T26	0	151	0	0
T44	181262	0	0	0
T45	19380	0	0	0
T49	0	284	0	0
T68	0	651	0	0
T72	0	71	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541062723	802	0	0
T4	177015	2	0	0
T5	0	15	0	0
T10	25149	1	0	0
T11	122845	0	0	0
T12	65124	1	0	0
T15	0	1	0	0
T17	18321	0	0	0
T18	3567	0	0	0
T19	48066	0	0	0
T20	26304	0	0	0
T26	0	1	0	0
T31	0	2	0	0
T44	181262	0	0	0
T45	19380	0	0	0
T49	0	2	0	0
T68	0	2	0	0
T72	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541062723	41	0	0
T22	45629	1	0	0
T25	0	1	0	0
T28	0	1	0	0
T31	0	1	0	0
T33	0	1	0	0
T57	0	1	0	0
T70	42766	0	0	0
T82	0	1	0	0
T83	0	1	0	0
T84	0	1	0	0
T86	0	1	0	0
T87	11080	0	0	0
T88	5519	0	0	0
T89	288682	0	0	0
T90	12443	0	0	0
T91	347717	0	0	0
T92	123614	0	0	0
T93	892572	0	0	0
T94	7915	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541062723	1123	0	0
T7	22200	167	0	0
T8	15766	158	0	0
T9	0	154	0	0
T34	0	311	0	0
T35	0	333	0	0
T36	862690	0	0	0
T37	332344	0	0	0
T38	127615	0	0	0
T39	15148	0	0	0
T40	124166	0	0	0
T41	571887	0	0	0
T42	14900	0	0	0
T43	67113	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541062723	913	0	0
T7	22200	137	0	0
T8	15766	128	0	0
T9	0	124	0	0
T34	0	251	0	0
T35	0	273	0	0
T36	862690	0	0	0
T37	332344	0	0	0
T38	127615	0	0	0
T39	15148	0	0	0
T40	124166	0	0	0
T41	571887	0	0	0
T42	14900	0	0	0
T43	67113	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	540828786	540762043	0	0
T1	294172	294164	0	0
T2	249407	249398	0	0
T3	795800	795740	0	0
T10	25149	25080	0	0
T11	122845	122836	0	0
T12	65124	65024	0	0
T17	18321	18235	0	0
T18	3567	3473	0	0
T19	48066	48008	0	0
T20	26304	26204	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541062723	540905810	0	0
T1	294172	294164	0	0
T2	249407	249398	0	0
T3	795800	795740	0	0
T10	25149	25080	0	0
T11	122845	122836	0	0
T12	65124	65024	0	0
T17	18321	18235	0	0
T18	3567	3473	0	0
T19	48066	48008	0	0
T20	26304	26204	0	0

Line Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T3,T10
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T10,T11
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T3,T10

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T3,T11

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T10,T12,T20
1	0	1	Covered	T1,T11,T18
1	1	0	Covered	T10,T12,T4
1	1	1	Covered	T10,T12,T20

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T10,T12,T20
0	1	Covered	T12,T4,T22
1	0	Covered	T4,T50,T52

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T10,T12,T20
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T4,T50,T52

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T12,T20
1	0	Covered	T4
1	1	Covered	T12,T4,T22

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T11,T17
1	Covered	T18,T19,T4

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T11,T17,T18
1	Covered	T1,T12,T4

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T11,T18
1	Covered	T17,T12,T4

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T17,T18
1	Covered	T11,T20,T4

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T11,T18

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T18,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T11,T17,T18

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T11,T18,T12

---

FSM Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T7,T8,T9
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T11,T17
Phase1St	198	Covered	T1,T11,T17
Phase2St	215	Covered	T1,T11,T17
Phase3St	233	Covered	T1,T11,T17
TerminalSt	249	Covered	T1,T11,T17
TimeoutSt	159	Covered	T10,T12,T20

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T7,T8,T9
IdleSt->Phase0St	152	Covered	T1,T11,T17
IdleSt->TimeoutSt	159	Covered	T10,T12,T20
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T21,T82,T102
Phase0St->Phase1St	198	Covered	T1,T11,T17
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T26,T32,T33
Phase1St->Phase2St	215	Covered	T1,T11,T17
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T21,T26,T33
Phase2St->Phase3St	233	Covered	T1,T11,T17
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T29,T81,T28
Phase3St->TerminalSt	249	Covered	T1,T11,T17
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T12,T19,T4
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T10,T12,T20
TimeoutSt->Phase0St	172	Covered	T12,T4,T22

---

Branch Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T3,T11
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T12,T20
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T12,T4,T22
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T10,T12,T20
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T10,T12,T20
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T21,T102,T103
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T11,T17
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T11,T17
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T32,T33,T58
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T11,T17
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T11,T17
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T21,T33,T104
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T11,T17
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T11,T17
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T29,T81,T28
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T11,T17
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T11,T17
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T12,T19,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T11,T17
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[0].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	541062723	204	0	0
CheckAccumTrig0_A	541062723	715	0	0
CheckAccumTrig1_A	541062723	36	0	0
CheckClr_A	541062723	315	0	0
CheckEn_A	540829936	178311702	0	0
CheckPhase0_A	541062723	785	0	0
CheckPhase1_A	541062723	766	0	0
CheckPhase2_A	541062723	753	0	0
CheckPhase3_A	541062723	747	0	0
CheckTimeout0_A	541062723	789	0	0
CheckTimeoutSt1_A	541062723	72004	0	0
CheckTimeoutSt2_A	541062723	692	0	0
CheckTimeoutStTrig_A	541062723	60	0	0
ErrorStAllEscAsserted_A	541062723	1204	0	0
ErrorStIsTerminal_A	541062723	994	0	0
EscStateOut_A	540828786	540762043	0	0
u_state_regs_A	541062723	540905810	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541062723	204	0	0
T7	22200	38	0	0
T8	15766	38	0	0
T9	0	13	0	0
T34	0	49	0	0
T35	0	66	0	0
T36	862690	0	0	0
T37	332344	0	0	0
T38	127615	0	0	0
T39	15148	0	0	0
T40	124166	0	0	0
T41	571887	0	0	0
T42	14900	0	0	0
T43	67113	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541062723	715	0	0
T1	294172	1	0	0
T2	249407	0	0	0
T3	795800	0	0	0
T4	0	7	0	0
T10	25149	0	0	0
T11	122845	1	0	0
T12	65124	1	0	0
T17	18321	1	0	0
T18	3567	1	0	0
T19	48066	3	0	0
T20	26304	1	0	0
T45	0	1	0	0
T46	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541062723	36	0	0
T4	177015	1	0	0
T13	599674	0	0	0
T14	270244	0	0	0
T15	18758	0	0	0
T33	0	1	0	0
T44	181262	0	0	0
T45	19380	0	0	0
T46	19696	0	0	0
T50	0	1	0	0
T52	0	1	0	0
T54	0	1	0	0
T55	0	2	0	0
T58	0	1	0	0
T61	0	1	0	0
T62	0	1	0	0
T63	0	1	0	0
T64	47559	0	0	0
T65	7532	0	0	0
T66	48426	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541062723	315	0	0
T4	177015	1	0	0
T12	65124	1	0	0
T14	270244	0	0	0
T15	18758	0	0	0
T16	0	1	0	0
T19	48066	2	0	0
T20	26304	0	0	0
T21	0	8	0	0
T29	0	1	0	0
T44	181262	0	0	0
T45	19380	0	0	0
T46	19696	0	0	0
T47	0	1	0	0
T64	47559	0	0	0
T68	0	8	0	0
T71	0	1	0	0
T73	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	540829936	178311702	0	0
T1	294172	9028	0	0
T2	249407	30897	0	0
T3	795800	651805	0	0
T10	25149	4326	0	0
T11	122845	18506	0	0
T12	65124	10046	0	0
T17	18321	582	0	0
T18	3567	2135	0	0
T19	48066	14796	0	0
T20	26304	582	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541062723	785	0	0
T1	294172	1	0	0
T2	249407	0	0	0
T3	795800	0	0	0
T4	0	9	0	0
T10	25149	0	0	0
T11	122845	1	0	0
T12	65124	2	0	0
T17	18321	1	0	0
T18	3567	1	0	0
T19	48066	3	0	0
T20	26304	1	0	0
T45	0	1	0	0
T46	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541062723	766	0	0
T1	294172	1	0	0
T2	249407	0	0	0
T3	795800	0	0	0
T4	0	9	0	0
T10	25149	0	0	0
T11	122845	1	0	0
T12	65124	2	0	0
T17	18321	1	0	0
T18	3567	1	0	0
T19	48066	3	0	0
T20	26304	1	0	0
T45	0	1	0	0
T46	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541062723	753	0	0
T1	294172	1	0	0
T2	249407	0	0	0
T3	795800	0	0	0
T4	0	9	0	0
T10	25149	0	0	0
T11	122845	1	0	0
T12	65124	2	0	0
T17	18321	1	0	0
T18	3567	1	0	0
T19	48066	3	0	0
T20	26304	1	0	0
T45	0	1	0	0
T46	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541062723	747	0	0
T1	294172	1	0	0
T2	249407	0	0	0
T3	795800	0	0	0
T4	0	9	0	0
T10	25149	0	0	0
T11	122845	1	0	0
T12	65124	2	0	0
T17	18321	1	0	0
T18	3567	1	0	0
T19	48066	3	0	0
T20	26304	1	0	0
T45	0	1	0	0
T46	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541062723	789	0	0
T4	177015	7	0	0
T6	0	1	0	0
T10	25149	5	0	0
T11	122845	0	0	0
T12	65124	3	0	0
T17	18321	0	0	0
T18	3567	0	0	0
T19	48066	0	0	0
T20	26304	2	0	0
T22	0	5	0	0
T44	181262	0	0	0
T45	19380	1	0	0
T47	0	1	0	0
T66	0	3	0	0
T68	0	2	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541062723	72004	0	0
T4	177015	932	0	0
T6	0	60	0	0
T10	25149	264	0	0
T11	122845	0	0	0
T12	65124	1620	0	0
T17	18321	0	0	0
T18	3567	0	0	0
T19	48066	0	0	0
T20	26304	497	0	0
T22	0	693	0	0
T44	181262	0	0	0
T45	19380	31	0	0
T47	0	121	0	0
T66	0	569	0	0
T68	0	101	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541062723	692	0	0
T4	177015	5	0	0
T6	0	1	0	0
T10	25149	5	0	0
T11	122845	0	0	0
T12	65124	2	0	0
T17	18321	0	0	0
T18	3567	0	0	0
T19	48066	0	0	0
T20	26304	2	0	0
T22	0	4	0	0
T44	181262	0	0	0
T45	19380	1	0	0
T47	0	1	0	0
T66	0	3	0	0
T68	0	2	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541062723	60	0	0
T4	177015	1	0	0
T12	65124	1	0	0
T14	270244	0	0	0
T15	18758	0	0	0
T19	48066	0	0	0
T20	26304	0	0	0
T22	0	1	0	0
T32	0	1	0	0
T33	0	1	0	0
T44	181262	0	0	0
T45	19380	0	0	0
T46	19696	0	0	0
T50	0	2	0	0
T55	0	1	0	0
T57	0	5	0	0
T64	47559	0	0	0
T77	0	1	0	0
T81	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541062723	1204	0	0
T7	22200	166	0	0
T8	15766	167	0	0
T9	0	174	0	0
T34	0	361	0	0
T35	0	336	0	0
T36	862690	0	0	0
T37	332344	0	0	0
T38	127615	0	0	0
T39	15148	0	0	0
T40	124166	0	0	0
T41	571887	0	0	0
T42	14900	0	0	0
T43	67113	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541062723	994	0	0
T7	22200	136	0	0
T8	15766	137	0	0
T9	0	144	0	0
T34	0	301	0	0
T35	0	276	0	0
T36	862690	0	0	0
T37	332344	0	0	0
T38	127615	0	0	0
T39	15148	0	0	0
T40	124166	0	0	0
T41	571887	0	0	0
T42	14900	0	0	0
T43	67113	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	540828786	540762043	0	0
T1	294172	294164	0	0
T2	249407	249398	0	0
T3	795800	795740	0	0
T10	25149	25080	0	0
T11	122845	122836	0	0
T12	65124	65024	0	0
T17	18321	18235	0	0
T18	3567	3473	0	0
T19	48066	48008	0	0
T20	26304	26204	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541062723	540905810	0	0
T1	294172	294164	0	0
T2	249407	249398	0	0
T3	795800	795740	0	0
T10	25149	25080	0	0
T11	122845	122836	0	0
T12	65124	65024	0	0
T17	18321	18235	0	0
T18	3567	3473	0	0
T19	48066	48008	0	0
T20	26304	26204	0	0

Line Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T10
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T10
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T10

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T12

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T10,T12,T20
1	0	1	Covered	T1,T2,T3
1	1	0	Covered	T12,T20,T4
1	1	1	Covered	T10,T4,T15

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T10,T4,T15
0	1	Covered	T77,T25,T80
1	0	Covered	T4,T50,T53

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T10,T4,T15
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T4,T50,T53

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T4,T15
1	0	Covered	T23
1	1	Covered	T77,T25,T80

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T12
1	Covered	T4,T13,T5

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T12
1	Covered	T4,T44,T47

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T4,T44,T13
1	Covered	T1,T2,T12

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T12
1	Covered	T4,T5,T68

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T12,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T12

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T20,T4,T5

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T12,T20,T4

---

FSM Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T7,T8,T9
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T12
Phase1St	198	Covered	T1,T2,T12
Phase2St	215	Covered	T1,T2,T12
Phase3St	233	Covered	T1,T2,T12
TerminalSt	249	Covered	T1,T2,T12
TimeoutSt	159	Covered	T10,T4,T15

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T7,T8,T9
IdleSt->Phase0St	152	Covered	T1,T2,T12
IdleSt->TimeoutSt	159	Covered	T10,T4,T15
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T105,T106,T107
Phase0St->Phase1St	198	Covered	T1,T2,T12
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T20,T28,T108
Phase1St->Phase2St	215	Covered	T1,T2,T12
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T28,T108,T109
Phase2St->Phase3St	233	Covered	T1,T2,T12
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T28,T108,T107
Phase3St->TerminalSt	249	Covered	T1,T2,T12
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T20,T4,T5
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T10,T4,T15
TimeoutSt->Phase0St	172	Covered	T4,T77,T50

---

Branch Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T12
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T4,T15
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T4,T77,T50
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T10,T4,T15
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T10,T4,T15
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T105,T106,T107
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T12
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T12
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T20,T28,T108
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T12
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T12
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T28,T108,T109
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T12
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T12
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T28,T108,T107
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T12
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T12
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T20,T4,T5
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T12
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[2].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	541062723	202	0	0
CheckAccumTrig0_A	541062723	439	0	0
CheckAccumTrig1_A	541062723	24	0	0
CheckClr_A	541062723	202	0	0
CheckEn_A	540829936	218314891	0	0
CheckPhase0_A	541062723	511	0	0
CheckPhase1_A	541062723	499	0	0
CheckPhase2_A	541062723	489	0	0
CheckPhase3_A	541062723	483	0	0
CheckTimeout0_A	541062723	343	0	0
CheckTimeoutSt1_A	541062723	42419	0	0
CheckTimeoutSt2_A	541062723	263	0	0
CheckTimeoutStTrig_A	541062723	55	0	0
ErrorStAllEscAsserted_A	541062723	1128	0	0
ErrorStIsTerminal_A	541062723	918	0	0
EscStateOut_A	540828786	540762043	0	0
u_state_regs_A	541062723	540905810	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541062723	202	0	0
T7	22200	38	0	0
T8	15766	15	0	0
T9	0	29	0	0
T34	0	59	0	0
T35	0	61	0	0
T36	862690	0	0	0
T37	332344	0	0	0
T38	127615	0	0	0
T39	15148	0	0	0
T40	124166	0	0	0
T41	571887	0	0	0
T42	14900	0	0	0
T43	67113	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541062723	439	0	0
T1	294172	1	0	0
T2	249407	1	0	0
T3	795800	0	0	0
T4	0	8	0	0
T5	0	5	0	0
T10	25149	0	0	0
T11	122845	0	0	0
T12	65124	1	0	0
T13	0	1	0	0
T17	18321	0	0	0
T18	3567	0	0	0
T19	48066	0	0	0
T20	26304	3	0	0
T44	0	1	0	0
T47	0	2	0	0
T48	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541062723	24	0	0
T4	177015	1	0	0
T13	599674	0	0	0
T14	270244	0	0	0
T15	18758	0	0	0
T28	0	1	0	0
T32	0	1	0	0
T44	181262	0	0	0
T45	19380	0	0	0
T46	19696	0	0	0
T50	0	1	0	0
T53	0	1	0	0
T56	0	1	0	0
T57	0	1	0	0
T63	0	1	0	0
T64	47559	0	0	0
T65	7532	0	0	0
T66	48426	0	0	0
T95	0	1	0	0
T110	0	1	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541062723	202	0	0
T4	177015	3	0	0
T5	0	1	0	0
T14	270244	0	0	0
T15	18758	0	0	0
T20	26304	2	0	0
T21	0	2	0	0
T44	181262	0	0	0
T45	19380	0	0	0
T46	19696	0	0	0
T47	0	1	0	0
T50	0	3	0	0
T64	47559	0	0	0
T65	7532	0	0	0
T66	48426	0	0	0
T68	0	2	0	0
T69	0	1	0	0
T74	0	5	0	0
T75	0	1	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	540829936	218314891	0	0
T1	294172	7317	0	0
T2	249407	20621	0	0
T3	795800	488847	0	0
T10	25149	2005	0	0
T11	122845	122836	0	0
T12	65124	9796	0	0
T17	18321	18234	0	0
T18	3567	2163	0	0
T19	48066	48007	0	0
T20	26304	8233	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541062723	511	0	0
T1	294172	1	0	0
T2	249407	1	0	0
T3	795800	0	0	0
T4	0	9	0	0
T5	0	5	0	0
T10	25149	0	0	0
T11	122845	0	0	0
T12	65124	1	0	0
T13	0	1	0	0
T17	18321	0	0	0
T18	3567	0	0	0
T19	48066	0	0	0
T20	26304	3	0	0
T44	0	1	0	0
T47	0	2	0	0
T48	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541062723	499	0	0
T1	294172	1	0	0
T2	249407	1	0	0
T3	795800	0	0	0
T4	0	9	0	0
T5	0	5	0	0
T10	25149	0	0	0
T11	122845	0	0	0
T12	65124	1	0	0
T13	0	1	0	0
T17	18321	0	0	0
T18	3567	0	0	0
T19	48066	0	0	0
T20	26304	2	0	0
T44	0	1	0	0
T47	0	2	0	0
T48	0	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541062723	489	0	0
T1	294172	1	0	0
T2	249407	1	0	0
T3	795800	0	0	0
T4	0	9	0	0
T5	0	5	0	0
T10	25149	0	0	0
T11	122845	0	0	0
T12	65124	1	0	0
T13	0	1	0	0
T17	18321	0	0	0
T18	3567	0	0	0
T19	48066	0	0	0
T20	26304	2	0	0
T44	0	1	0	0
T47	0	2	0	0
T48	0	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541062723	483	0	0
T1	294172	1	0	0
T2	249407	1	0	0
T3	795800	0	0	0
T4	0	9	0	0
T5	0	5	0	0
T10	25149	0	0	0
T11	122845	0	0	0
T12	65124	1	0	0
T13	0	1	0	0
T17	18321	0	0	0
T18	3567	0	0	0
T19	48066	0	0	0
T20	26304	2	0	0
T44	0	1	0	0
T47	0	2	0	0
T48	0	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541062723	343	0	0
T4	177015	3	0	0
T5	0	1	0	0
T10	25149	7	0	0
T11	122845	0	0	0
T12	65124	0	0	0
T15	0	1	0	0
T17	18321	0	0	0
T18	3567	0	0	0
T19	48066	0	0	0
T20	26304	0	0	0
T22	0	11	0	0
T44	181262	0	0	0
T45	19380	0	0	0
T49	0	2	0	0
T66	0	1	0	0
T68	0	2	0	0
T76	0	1	0	0
T77	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541062723	42419	0	0
T4	177015	178	0	0
T5	0	52	0	0
T10	25149	351	0	0
T11	122845	0	0	0
T12	65124	0	0	0
T15	0	64	0	0
T17	18321	0	0	0
T18	3567	0	0	0
T19	48066	0	0	0
T20	26304	0	0	0
T22	0	1253	0	0
T44	181262	0	0	0
T45	19380	0	0	0
T49	0	274	0	0
T66	0	320	0	0
T68	0	148	0	0
T76	0	229	0	0
T77	0	71	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541062723	263	0	0
T4	177015	2	0	0
T5	0	1	0	0
T10	25149	7	0	0
T11	122845	0	0	0
T12	65124	0	0	0
T15	0	1	0	0
T17	18321	0	0	0
T18	3567	0	0	0
T19	48066	0	0	0
T20	26304	0	0	0
T22	0	11	0	0
T31	0	2	0	0
T44	181262	0	0	0
T45	19380	0	0	0
T49	0	2	0	0
T66	0	1	0	0
T68	0	2	0	0
T76	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541062723	55	0	0
T23	0	2	0	0
T24	897892	0	0	0
T25	0	1	0	0
T31	140307	0	0	0
T33	0	1	0	0
T56	0	3	0	0
T74	413449	0	0	0
T77	22922	1	0	0
T78	115894	0	0	0
T80	0	1	0	0
T81	0	1	0	0
T85	0	1	0	0
T86	0	1	0	0
T107	0	3	0	0
T111	42360	0	0	0
T112	8732	0	0	0
T113	518429	0	0	0
T114	81200	0	0	0
T115	75175	0	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541062723	1128	0	0
T7	22200	171	0	0
T8	15766	143	0	0
T9	0	164	0	0
T34	0	336	0	0
T35	0	314	0	0
T36	862690	0	0	0
T37	332344	0	0	0
T38	127615	0	0	0
T39	15148	0	0	0
T40	124166	0	0	0
T41	571887	0	0	0
T42	14900	0	0	0
T43	67113	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541062723	918	0	0
T7	22200	141	0	0
T8	15766	113	0	0
T9	0	134	0	0
T34	0	276	0	0
T35	0	254	0	0
T36	862690	0	0	0
T37	332344	0	0	0
T38	127615	0	0	0
T39	15148	0	0	0
T40	124166	0	0	0
T41	571887	0	0	0
T42	14900	0	0	0
T43	67113	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	540828786	540762043	0	0
T1	294172	294164	0	0
T2	249407	249398	0	0
T3	795800	795740	0	0
T10	25149	25080	0	0
T11	122845	122836	0	0
T12	65124	65024	0	0
T17	18321	18235	0	0
T18	3567	3473	0	0
T19	48066	48008	0	0
T20	26304	26204	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541062723	540905810	0	0
T1	294172	294164	0	0
T2	249407	249398	0	0
T3	795800	795740	0	0
T10	25149	25080	0	0
T11	122845	122836	0	0
T12	65124	65024	0	0
T17	18321	18235	0	0
T18	3567	3473	0	0
T19	48066	48008	0	0
T20	26304	26204	0	0

Line Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
TOTAL		101	101	100.00
CONT_ASSIGN	85	1	1	100.00
ALWAYS	134	89	89	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	292	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
CONT_ASSIGN	295	1	1	100.00
ALWAYS	305	3	3	100.00

WARNING: The source file '/workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' was not found, so annotated line coverage report could not be generated.

Line No.	Covered	Statements
85	1	1
134	1	1
135	1	1
136	1	1
137	1	1
138	1	1
139	1	1
140	1	1
141	1	1
142	1	1
144	1	1
148	1	1
149	1	1
151	1	1
152	1	1
153	1	1
154	1	1
157	1	1
158	1	1
159	1	1
			MISSING_ELSE
169	1	1
171	1	1
172	1	1
173	1	1
174	1	1
175	1	1
178	1	1
179	1	1
181	1	1
182	1	1
187	1	1
188	1	1
189	1	1
190	1	1
191	1	1
193	1	1
194	1	1
195	1	1
196	1	1
197	1	1
198	1	1
199	1	1
200	1	1
			MISSING_ELSE
204	1	1
205	1	1
206	1	1
207	1	1
208	1	1
210	1	1
211	1	1
212	1	1
213	1	1
214	1	1
215	1	1
216	1	1
217	1	1
			MISSING_ELSE
221	1	1
222	1	1
223	1	1
224	1	1
225	1	1
228	1	1
229	1	1
230	1	1
231	1	1
232	1	1
233	1	1
234	1	1
			MISSING_ELSE
238	1	1
239	1	1
240	1	1
241	1	1
242	1	1
244	1	1
245	1	1
246	1	1
247	1	1
248	1	1
249	1	1
250	1	1
251	1	1
			MISSING_ELSE
258	1	1
259	1	1
260	1	1
261	1	1
			MISSING_ELSE
268	1	1
269	1	1
283	1	1
284	1	1
285	1	1
			MISSING_ELSE
292	4	4
295	4	4
305	3	3

---

Cond Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Covered	Percent
Conditions	45	43	95.56
Logical	45	43	95.56
Non-Logical	0	0
Event	0	0

 LINE       66
 EXPRESSION (cnt_clr && ((!cnt_en)))
             ---1---    -----2-----

-1-	-2-	Status	Tests
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       66
 EXPRESSION (cnt_clr && cnt_en)
             ---1---    ---2--

-1-	-2-	Status	Tests
0	1	Covered	T1,T2,T3
1	0	Covered	T1,T2,T3
1	1	Covered	T1,T2,T3

 LINE       151
 EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
             -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T1,T2,T3
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T1,T2,T3

 LINE       157
 EXPRESSION (timeout_en_i && ((!cnt_ge)) && en_i)
             ------1-----    -----2-----    --3-

-1-	-2-	-3-	Status	Tests
0	1	1	Covered	T10,T12,T20
1	0	1	Covered	T46,T13,T5
1	1	0	Covered	T12,T4,T46
1	1	1	Covered	T10,T4,T46

 LINE       171
 EXPRESSION ((accu_trig_i && en_i && ((!clr_i))) || (cnt_ge && timeout_en_i))
             -----------------1-----------------    ------------2-----------

-1-	-2-	Status	Tests
0	0	Covered	T10,T4,T46
0	1	Covered	T77,T31,T79
1	0	Covered	T5,T50,T116

 LINE       171
 SUB-EXPRESSION (accu_trig_i && en_i && ((!clr_i)))
                 -----1-----    --2-    -----3----

-1-	-2-	-3-	Status	Tests	Exclude Annotation
0	1	1	Covered	T10,T4,T46
1	0	1	Excluded		VC_COV_UNR
1	1	0	Not Covered
1	1	1	Covered	T5,T50,T116

 LINE       171
 SUB-EXPRESSION (cnt_ge && timeout_en_i)
                 ---1--    ------2-----

-1-	-2-	Status	Tests
0	1	Covered	T10,T4,T46
1	0	Covered	T22
1	1	Covered	T77,T31,T79

 LINE       191
 EXPRESSION (crashdump_phase_i == 2'b0)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T12,T4,T13

 LINE       208
 EXPRESSION (crashdump_phase_i == 2'b1)
            -------------1-------------

-1-	Status	Tests
0	Covered	T1,T3,T17
1	Covered	T2,T20,T4

 LINE       225
 EXPRESSION (crashdump_phase_i == 2'b10)
            --------------1-------------

-1-	Status	Tests
0	Covered	T1,T2,T3
1	Covered	T17,T4,T5

 LINE       242
 EXPRESSION (crashdump_phase_i == 2'b11)
            --------------1-------------

-1-	Status	Tests
0	Covered	T2,T17,T12
1	Covered	T1,T3,T19

 LINE       283
 EXPRESSION (accu_fail_i || cnt_error)
             -----1-----    ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T7,T8,T9

 LINE       295
 EXPRESSION (((|(esc_map_oh[0] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T3,T12,T4

 LINE       295
 EXPRESSION (((|(esc_map_oh[1] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T3

 LINE       295
 EXPRESSION (((|(esc_map_oh[2] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T1,T2,T3

 LINE       295
 EXPRESSION (((|(esc_map_oh[3] & phase_oh))) | fsm_error)
             ---------------1---------------   ----2----

-1-	-2-	Status	Tests
0	0	Covered	T1,T2,T3
0	1	Covered	T7,T8,T9
1	0	Covered	T3,T17,T12

---

FSM Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

Summary for FSM :: state_q

	Total	Covered	Percent
States	8	8	100.00	(Not included in score)
Transitions	14	14	100.00
Sequences	0	0

State, Transition and Sequence Details for FSM :: state_q

---

states	Line No.	Covered	Tests
FsmErrorSt	284	Covered	T7,T8,T9
IdleSt	181	Covered	T1,T2,T3
Phase0St	152	Covered	T1,T2,T3
Phase1St	198	Covered	T1,T2,T3
Phase2St	215	Covered	T1,T2,T3
Phase3St	233	Covered	T1,T2,T3
TerminalSt	249	Covered	T1,T2,T3
TimeoutSt	159	Covered	T10,T4,T46

transitions	Line No.	Covered	Tests	Exclude Annotation
IdleSt->FsmErrorSt	284	Covered	T7,T8,T9
IdleSt->Phase0St	152	Covered	T1,T2,T3
IdleSt->TimeoutSt	159	Covered	T10,T4,T46
Phase0St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase0St->IdleSt	194	Covered	T4,T31,T28
Phase0St->Phase1St	198	Covered	T1,T2,T3
Phase1St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase1St->IdleSt	211	Covered	T46,T28,T108
Phase1St->Phase2St	215	Covered	T1,T2,T3
Phase2St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase2St->IdleSt	229	Covered	T4,T73,T117
Phase2St->Phase3St	233	Covered	T1,T2,T3
Phase3St->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
Phase3St->IdleSt	245	Covered	T97,T118,T119
Phase3St->TerminalSt	249	Covered	T1,T2,T3
TerminalSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TerminalSt->IdleSt	261	Covered	T3,T19,T4
TimeoutSt->FsmErrorSt	284	Excluded		[LOW_RISK]: Forcing from any state other than IdleSt to FSMErrorSt is covered in FPV.
TimeoutSt->IdleSt	181	Covered	T10,T4,T46
TimeoutSt->Phase0St	172	Covered	T5,T77,T31

---

Branch Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Line No.	Total	Covered	Percent
Branches		26	26	100.00
CASE	144	22	22	100.00
IF	283	2	2	100.00
IF	305	2	2	100.00

WARNING: The source file /workspace/default/sim-vcs/../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv' or '../src/lowrisc_ip_alert_handler_component_0.1/rtl/alert_handler_esc_timer.sv was not found/opened, so annotated branch coverage report could not be generated.

	LineNo.	Expression
-1-:	144	case (state_q)
-2-:	151	if (((accu_trig_i && en_i) && (!clr_i)))
-3-:	157	if (((timeout_en_i && (!cnt_ge)) && en_i))
-4-:	171	if ((((accu_trig_i && en_i) && (!clr_i)) || (cnt_ge && timeout_en_i)))
-5-:	178	if (timeout_en_i)
-6-:	193	if (clr_i)
-7-:	197	if (cnt_ge)
-8-:	210	if (clr_i)
-9-:	214	if (cnt_ge)
-10-:	228	if (clr_i)
-11-:	232	if (cnt_ge)
-12-:	244	if (clr_i)
-13-:	248	if (cnt_ge)
-14-:	260	if (clr_i)

Branches:

-1-	-2-	-3-	-4-	-5-	-6-	-7-	-8-	-9-	-10-	-11-	-12-	-13-	-14-	Status	Tests
IdleSt	1	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
IdleSt	0	1	-	-	-	-	-	-	-	-	-	-	-	Covered	T10,T4,T46
IdleSt	0	0	-	-	-	-	-	-	-	-	-	-	-	Covered	T1,T2,T3
TimeoutSt	-	-	1	-	-	-	-	-	-	-	-	-	-	Covered	T5,T77,T31
TimeoutSt	-	-	0	1	-	-	-	-	-	-	-	-	-	Covered	T10,T4,T46
TimeoutSt	-	-	0	0	-	-	-	-	-	-	-	-	-	Covered	T10,T4,T46
Phase0St	-	-	-	-	1	-	-	-	-	-	-	-	-	Covered	T4,T31,T28
Phase0St	-	-	-	-	0	1	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase0St	-	-	-	-	0	0	-	-	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	1	-	-	-	-	-	-	Covered	T46,T28,T108
Phase1St	-	-	-	-	-	-	0	1	-	-	-	-	-	Covered	T1,T2,T3
Phase1St	-	-	-	-	-	-	0	0	-	-	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	1	-	-	-	-	Covered	T4,T73,T117
Phase2St	-	-	-	-	-	-	-	-	0	1	-	-	-	Covered	T1,T2,T3
Phase2St	-	-	-	-	-	-	-	-	0	0	-	-	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	1	-	-	Covered	T97,T119,T120
Phase3St	-	-	-	-	-	-	-	-	-	-	0	1	-	Covered	T1,T2,T3
Phase3St	-	-	-	-	-	-	-	-	-	-	0	0	-	Covered	T1,T2,T3
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	1	Covered	T3,T19,T4
TerminalSt	-	-	-	-	-	-	-	-	-	-	-	-	0	Covered	T1,T2,T3
FsmErrorSt	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9
default	-	-	-	-	-	-	-	-	-	-	-	-	-	Covered	T7,T8,T9

	LineNo.	Expression
-1-:	283	if ((accu_fail_i || cnt_error))

Branches:

-1-	Status	Tests
1	Covered	T7,T8,T9
0	Covered	T1,T2,T3

	LineNo.	Expression
-1-:	305	if ((!rst_ni))

Branches:

-1-	Status	Tests
1	Covered	T1,T2,T3
0	Covered	T1,T2,T3

---

Assert Coverage for Instance : tb.dut.gen_classes[3].u_esc_timer

	Total	Attempted	Percent	Succeeded/Matched	Percent
Assertions	17	17	100.00	17	100.00
Cover properties	0	0		0
Cover sequences	0	0		0
Total	17	17	100.00	17	100.00

---

Assertion Details

Name	Attempts	Real Successes	Failures	Incomplete
AccuFailToFsmError_A	541062723	206	0	0
CheckAccumTrig0_A	541062723	438	0	0
CheckAccumTrig1_A	541062723	18	0	0
CheckClr_A	541062723	189	0	0
CheckEn_A	540829936	237952163	0	0
CheckPhase0_A	541062723	486	0	0
CheckPhase1_A	541062723	476	0	0
CheckPhase2_A	541062723	469	0	0
CheckPhase3_A	541062723	463	0	0
CheckTimeout0_A	541062723	1257	0	0
CheckTimeoutSt1_A	541062723	111581	0	0
CheckTimeoutSt2_A	541062723	1196	0	0
CheckTimeoutStTrig_A	541062723	41	0	0
ErrorStAllEscAsserted_A	541062723	1110	0	0
ErrorStIsTerminal_A	541062723	900	0	0
EscStateOut_A	540828786	540762043	0	0
u_state_regs_A	541062723	540905810	0	0

AccuFailToFsmError_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541062723	206	0	0
T7	22200	32	0	0
T8	15766	31	0	0
T9	0	35	0	0
T34	0	46	0	0
T35	0	62	0	0
T36	862690	0	0	0
T37	332344	0	0	0
T38	127615	0	0	0
T39	15148	0	0	0
T40	124166	0	0	0
T41	571887	0	0	0
T42	14900	0	0	0
T43	67113	0	0	0

CheckAccumTrig0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541062723	438	0	0
T1	294172	1	0	0
T2	249407	1	0	0
T3	795800	1	0	0
T4	0	6	0	0
T10	25149	0	0	0
T11	122845	0	0	0
T12	65124	1	0	0
T15	0	1	0	0
T17	18321	1	0	0
T18	3567	0	0	0
T19	48066	3	0	0
T20	26304	1	0	0
T46	0	1	0	0

CheckAccumTrig1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541062723	18	0	0
T5	161247	1	0	0
T6	98623	0	0	0
T16	213663	0	0	0
T21	451369	0	0	0
T29	5254	0	0	0
T30	62725	0	0	0
T47	28951	0	0	0
T48	84536	0	0	0
T50	0	1	0	0
T56	0	1	0	0
T63	0	1	0	0
T67	332202	0	0	0
T81	0	1	0	0
T116	0	1	0	0
T121	0	1	0	0
T122	0	1	0	0
T123	0	1	0	0
T124	0	1	0	0
T125	3161	0	0	0

CheckClr_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541062723	189	0	0
T3	795800	1	0	0
T4	177015	3	0	0
T5	0	1	0	0
T10	25149	0	0	0
T11	122845	0	0	0
T12	65124	0	0	0
T16	0	1	0	0
T17	18321	0	0	0
T18	3567	0	0	0
T19	48066	2	0	0
T20	26304	0	0	0
T31	0	1	0	0
T44	181262	0	0	0
T46	0	1	0	0
T68	0	1	0	0
T70	0	1	0	0
T73	0	2	0	0

CheckEn_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	540829936	237952163	0	0
T1	294172	33776	0	0
T2	249407	2123	0	0
T3	795800	584496	0	0
T10	25149	2009	0	0
T11	122845	122836	0	0
T12	65124	9807	0	0
T17	18321	594	0	0
T18	3567	2187	0	0
T19	48066	14831	0	0
T20	26304	594	0	0

CheckPhase0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541062723	486	0	0
T1	294172	1	0	0
T2	249407	1	0	0
T3	795800	1	0	0
T4	0	5	0	0
T10	25149	0	0	0
T11	122845	0	0	0
T12	65124	1	0	0
T15	0	1	0	0
T17	18321	1	0	0
T18	3567	0	0	0
T19	48066	3	0	0
T20	26304	1	0	0
T46	0	1	0	0

CheckPhase1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541062723	476	0	0
T1	294172	1	0	0
T2	249407	1	0	0
T3	795800	1	0	0
T4	0	5	0	0
T10	25149	0	0	0
T11	122845	0	0	0
T12	65124	1	0	0
T13	0	1	0	0
T15	0	1	0	0
T17	18321	1	0	0
T18	3567	0	0	0
T19	48066	3	0	0
T20	26304	1	0	0

CheckPhase2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541062723	469	0	0
T1	294172	1	0	0
T2	249407	1	0	0
T3	795800	1	0	0
T4	0	4	0	0
T10	25149	0	0	0
T11	122845	0	0	0
T12	65124	1	0	0
T13	0	1	0	0
T15	0	1	0	0
T17	18321	1	0	0
T18	3567	0	0	0
T19	48066	3	0	0
T20	26304	1	0	0

CheckPhase3_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541062723	463	0	0
T1	294172	1	0	0
T2	249407	1	0	0
T3	795800	1	0	0
T4	0	4	0	0
T10	25149	0	0	0
T11	122845	0	0	0
T12	65124	1	0	0
T13	0	1	0	0
T15	0	1	0	0
T17	18321	1	0	0
T18	3567	0	0	0
T19	48066	3	0	0
T20	26304	1	0	0

CheckTimeout0_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541062723	1257	0	0
T4	177015	3	0	0
T5	0	1	0	0
T10	25149	7	0	0
T11	122845	0	0	0
T12	65124	0	0	0
T17	18321	0	0	0
T18	3567	0	0	0
T19	48066	0	0	0
T20	26304	0	0	0
T22	0	5	0	0
T31	0	4	0	0
T44	181262	0	0	0
T45	19380	0	0	0
T46	0	1	0	0
T47	0	7	0	0
T66	0	3	0	0
T77	0	1	0	0
T78	0	1	0	0

CheckTimeoutSt1_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541062723	111581	0	0
T4	177015	670	0	0
T10	25149	369	0	0
T11	122845	0	0	0
T12	65124	0	0	0
T17	18321	0	0	0
T18	3567	0	0	0
T19	48066	0	0	0
T20	26304	0	0	0
T22	0	599	0	0
T31	0	815	0	0
T44	181262	0	0	0
T45	19380	0	0	0
T46	0	25	0	0
T47	0	777	0	0
T50	0	458	0	0
T66	0	634	0	0
T77	0	373	0	0
T78	0	114	0	0

CheckTimeoutSt2_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541062723	1196	0	0
T4	177015	3	0	0
T10	25149	7	0	0
T11	122845	0	0	0
T12	65124	0	0	0
T17	18321	0	0	0
T18	3567	0	0	0
T19	48066	0	0	0
T20	26304	0	0	0
T22	0	5	0	0
T31	0	2	0	0
T44	181262	0	0	0
T45	19380	0	0	0
T46	0	1	0	0
T47	0	7	0	0
T50	0	3	0	0
T66	0	3	0	0
T78	0	1	0	0
T79	0	1	0	0

CheckTimeoutStTrig_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541062723	41	0	0
T24	897892	0	0	0
T28	0	3	0	0
T31	140307	2	0	0
T33	0	1	0	0
T57	0	2	0	0
T74	413449	0	0	0
T77	22922	1	0	0
T78	115894	0	0	0
T79	0	1	0	0
T86	0	1	0	0
T111	42360	0	0	0
T112	8732	0	0	0
T113	518429	0	0	0
T114	81200	0	0	0
T115	75175	0	0	0
T126	0	1	0	0
T127	0	2	0	0
T128	0	1	0	0

ErrorStAllEscAsserted_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541062723	1110	0	0
T7	22200	160	0	0
T8	15766	143	0	0
T9	0	156	0	0
T34	0	330	0	0
T35	0	321	0	0
T36	862690	0	0	0
T37	332344	0	0	0
T38	127615	0	0	0
T39	15148	0	0	0
T40	124166	0	0	0
T41	571887	0	0	0
T42	14900	0	0	0
T43	67113	0	0	0

ErrorStIsTerminal_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541062723	900	0	0
T7	22200	130	0	0
T8	15766	113	0	0
T9	0	126	0	0
T34	0	270	0	0
T35	0	261	0	0
T36	862690	0	0	0
T37	332344	0	0	0
T38	127615	0	0	0
T39	15148	0	0	0
T40	124166	0	0	0
T41	571887	0	0	0
T42	14900	0	0	0
T43	67113	0	0	0

EscStateOut_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	540828786	540762043	0	0
T1	294172	294164	0	0
T2	249407	249398	0	0
T3	795800	795740	0	0
T10	25149	25080	0	0
T11	122845	122836	0	0
T12	65124	65024	0	0
T17	18321	18235	0	0
T18	3567	3473	0	0
T19	48066	48008	0	0
T20	26304	26204	0	0

u_state_regs_A

Name	Attempts	Real Successes	Failures	Incomplete
Total	541062723	540905810	0	0
T1	294172	294164	0	0
T2	249407	249398	0	0
T3	795800	795740	0	0
T10	25149	25080	0	0
T11	122845	122836	0	0
T12	65124	65024	0	0
T17	18321	18235	0	0
T18	3567	3473	0	0
T19	48066	48008	0	0
T20	26304	26204	0	0