Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	45173	1			T3	4		T4	5		T5	1579
class_i[0x1]	35046	1			T3	9		T8	4		T4	69
class_i[0x2]	52069	1			T3	18		T8	3		T4	399
class_i[0x3]	31195	1			T3	5		T8	1		T4	15

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	40856	1			T3	9		T8	4		T4	32
alert[0x1]	38829	1			T3	9		T8	4		T4	24
alert[0x2]	39860	1			T3	10		T4	16		T5	1
alert[0x3]	43938	1			T3	8		T4	416		T5	5

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

163241

1

T3

25

T8

6

T4

488

esc_ping_fail

242

1

T3

11

T8

2

T16

1

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	40783	1			T3	6		T8	3		T4	32
esc_integrity_fail	alert[0x1]	38762	1			T3	6		T8	3		T4	24
esc_integrity_fail	alert[0x2]	39807	1			T3	8		T4	16		T5	1
esc_integrity_fail	alert[0x3]	43889	1			T3	5		T4	416		T5	5
esc_ping_fail	alert[0x0]	73	1			T3	3		T8	1		T16	1
esc_ping_fail	alert[0x1]	67	1			T3	3		T8	1		T127	1
esc_ping_fail	alert[0x2]	53	1			T3	2		T42	1		T301	1
esc_ping_fail	alert[0x3]	49	1			T3	3		T301	1		T127	2

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	45119	1			T3	3		T4	5		T5	1579
esc_integrity_fail	class_i[0x1]	34963	1			T8	3		T4	69		T44	3
esc_integrity_fail	class_i[0x2]	52032	1			T3	17		T8	3		T4	399
esc_integrity_fail	class_i[0x3]	31127	1			T3	5		T4	15		T5	11
esc_ping_fail	class_i[0x0]	54	1			T3	1		T16	1		T301	1
esc_ping_fail	class_i[0x1]	83	1			T3	9		T8	1		T301	4
esc_ping_fail	class_i[0x2]	37	1			T3	1		T42	2		T304	1
esc_ping_fail	class_i[0x3]	68	1			T8	1		T127	7		T317	3