Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	538519207	0	0	619
tb.dut.u_edn_req.u_prim_packer_fifo.ValidOPairedWithReadyI_A	0	0	538519207	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AckPKnownO_A	0	0	538519207	538365906	0	0
tb.dut.CheckAccuCntDw	0	0	619	619	0	0
tb.dut.CheckEscCntDw	0	0	619	619	0	0
tb.dut.CheckNAlerts	0	0	619	619	0	0
tb.dut.CheckNClasses	0	0	619	619	0	0
tb.dut.CheckNEscSev	0	0	619	619	0	0
tb.dut.CrashdumpKnownO_A	0	0	538519207	538365906	0	0
tb.dut.EdnKnownO_A	0	0	538519207	538365906	0	0
tb.dut.EscPKnownO_A	0	0	538519207	538365906	0	0
tb.dut.FpvSecCmPingTimerCnterCheck_A	0	0	538519207	70	0	0
tb.dut.FpvSecCmPingTimerDoubleLfsrCheck_A	0	0	538519207	70	0	0
tb.dut.FpvSecCmPingTimerEscCnterCheck_A	0	0	538519207	70	0	0
tb.dut.FpvSecCmPingTimerFsmCheck_A	0	0	538519207	70	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	538519207	70	0	0
tb.dut.IrqAKnownO_A	0	0	538519207	538365906	0	0
tb.dut.IrqBKnownO_A	0	0	538519207	538365906	0	0
tb.dut.IrqCKnownO_A	0	0	538519207	538365906	0	0
tb.dut.IrqDKnownO_A	0	0	538519207	538365906	0	0
tb.dut.TlAReadyKnownO_A	0	0	538519207	538365906	0	0
tb.dut.TlDValidKnownO_A	0	0	538519207	538365906	0	0
tb.dut.alert_handler_csr_assert.TlulOOBAddrErr_A	0	0	563288698	163008	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_0_rd_A	0	0	563288698	17678	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_10_rd_A	0	0	563288698	16959	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_11_rd_A	0	0	563288698	17676	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_12_rd_A	0	0	563288698	17014	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_13_rd_A	0	0	563288698	18236	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_14_rd_A	0	0	563288698	17128	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_15_rd_A	0	0	563288698	16847	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_16_rd_A	0	0	563288698	18120	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_17_rd_A	0	0	563288698	18824	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_18_rd_A	0	0	563288698	18052	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_19_rd_A	0	0	563288698	18421	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_1_rd_A	0	0	563288698	19156	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_20_rd_A	0	0	563288698	16837	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_21_rd_A	0	0	563288698	17167	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_22_rd_A	0	0	563288698	18350	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_23_rd_A	0	0	563288698	17979	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_24_rd_A	0	0	563288698	18390	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_25_rd_A	0	0	563288698	16980	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_26_rd_A	0	0	563288698	18637	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_27_rd_A	0	0	563288698	20284	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_28_rd_A	0	0	563288698	17211	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_29_rd_A	0	0	563288698	18147	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_2_rd_A	0	0	563288698	18228	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_30_rd_A	0	0	563288698	19408	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_31_rd_A	0	0	563288698	18273	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_32_rd_A	0	0	563288698	16924	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_33_rd_A	0	0	563288698	19514	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_34_rd_A	0	0	563288698	19862	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_35_rd_A	0	0	563288698	18118	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_36_rd_A	0	0	563288698	17114	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_37_rd_A	0	0	563288698	18736	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_38_rd_A	0	0	563288698	20555	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_39_rd_A	0	0	563288698	18926	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_3_rd_A	0	0	563288698	18162	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_40_rd_A	0	0	563288698	20627	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_41_rd_A	0	0	563288698	19369	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_42_rd_A	0	0	563288698	18281	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_43_rd_A	0	0	563288698	18365	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_44_rd_A	0	0	563288698	16910	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_45_rd_A	0	0	563288698	18557	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_46_rd_A	0	0	563288698	18973	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_47_rd_A	0	0	563288698	18683	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_48_rd_A	0	0	563288698	17842	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_49_rd_A	0	0	563288698	20179	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_4_rd_A	0	0	563288698	18356	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_50_rd_A	0	0	563288698	18195	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_51_rd_A	0	0	563288698	16939	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_52_rd_A	0	0	563288698	19647	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_53_rd_A	0	0	563288698	17575	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_54_rd_A	0	0	563288698	17091	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_55_rd_A	0	0	563288698	19393	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_56_rd_A	0	0	563288698	17802	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_57_rd_A	0	0	563288698	17070	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_58_rd_A	0	0	563288698	17300	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_59_rd_A	0	0	563288698	18821	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_5_rd_A	0	0	563288698	16880	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_60_rd_A	0	0	563288698	18089	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_61_rd_A	0	0	563288698	17425	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_62_rd_A	0	0	563288698	18071	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_63_rd_A	0	0	563288698	17732	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_64_rd_A	0	0	563288698	18768	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_6_rd_A	0	0	563288698	18957	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_7_rd_A	0	0	563288698	18367	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_8_rd_A	0	0	563288698	18217	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_9_rd_A	0	0	563288698	17136	0	0
tb.dut.alert_handler_csr_assert.classa_regwen_rd_A	0	0	563288698	16668	0	0
tb.dut.alert_handler_csr_assert.classb_regwen_rd_A	0	0	563288698	16947	0	0
tb.dut.alert_handler_csr_assert.classc_regwen_rd_A	0	0	563288698	19278	0	0
tb.dut.alert_handler_csr_assert.classd_regwen_rd_A	0	0	563288698	16955	0	0
tb.dut.alert_handler_csr_assert.intr_enable_rd_A	0	0	563288698	36397	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_0_rd_A	0	0	563288698	18789	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_1_rd_A	0	0	563288698	18233	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_2_rd_A	0	0	563288698	17543	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_3_rd_A	0	0	563288698	17456	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_4_rd_A	0	0	563288698	17761	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_5_rd_A	0	0	563288698	18002	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_6_rd_A	0	0	563288698	16976	0	0
tb.dut.alert_handler_csr_assert.ping_timer_regwen_rd_A	0	0	563288698	18614	0	0
tb.dut.gen_classes[0].FpvSecCmAccuCnterCheck_A	0	0	538519207	70	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerCnterCheck_A	0	0	538519207	70	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerFsmCheck_A	0	0	538519207	70	0	0
tb.dut.gen_classes[0].u_accu.CountSaturateStable_A	0	0	538519207	5083	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigBkwd_A	0	0	538519207	141765	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigFwd_A	0	0	538519207	290651222	0	0
tb.dut.gen_classes[0].u_esc_timer.AccuFailToFsmError_A	0	0	538519207	187	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig0_A	0	0	538519207	744	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig1_A	0	0	538519207	37	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckClr_A	0	0	538519207	366	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckEn_A	0	0	538302192	218852325	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase0_A	0	0	538519207	815	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase1_A	0	0	538519207	797	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase2_A	0	0	538519207	773	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase3_A	0	0	538519207	753	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeout0_A	0	0	538519207	641	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt1_A	0	0	538519207	76827	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt2_A	0	0	538519207	548	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutStTrig_A	0	0	538519207	53	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStAllEscAsserted_A	0	0	538519207	1174	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStIsTerminal_A	0	0	538519207	964	0	0
tb.dut.gen_classes[0].u_esc_timer.EscStateOut_A	0	0	538300810	538236448	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs.AssertConnected_A	0	0	619	619	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs_A	0	0	538519207	538365906	0	0
tb.dut.gen_classes[1].FpvSecCmAccuCnterCheck_A	0	0	538519207	70	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerCnterCheck_A	0	0	538519207	70	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerFsmCheck_A	0	0	538519207	70	0	0
tb.dut.gen_classes[1].u_accu.CountSaturateStable_A	0	0	538519207	4452	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigBkwd_A	0	0	538519207	136699	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigFwd_A	0	0	538519207	267173628	0	0
tb.dut.gen_classes[1].u_esc_timer.AccuFailToFsmError_A	0	0	538519207	213	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig0_A	0	0	538519207	415	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig1_A	0	0	538519207	10	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckClr_A	0	0	538519207	173	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckEn_A	0	0	538302192	212680772	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase0_A	0	0	538519207	482	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase1_A	0	0	538519207	468	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase2_A	0	0	538519207	461	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase3_A	0	0	538519207	457	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeout0_A	0	0	538519207	354	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt1_A	0	0	538519207	50911	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt2_A	0	0	538519207	279	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutStTrig_A	0	0	538519207	64	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStAllEscAsserted_A	0	0	538519207	1135	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStIsTerminal_A	0	0	538519207	925	0	0
tb.dut.gen_classes[1].u_esc_timer.EscStateOut_A	0	0	538300810	538236448	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs.AssertConnected_A	0	0	619	619	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs_A	0	0	538519207	538365906	0	0
tb.dut.gen_classes[2].FpvSecCmAccuCnterCheck_A	0	0	538519207	70	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerCnterCheck_A	0	0	538519207	70	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerFsmCheck_A	0	0	538519207	70	0	0
tb.dut.gen_classes[2].u_accu.CountSaturateStable_A	0	0	538519207	2197	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigBkwd_A	0	0	538519207	199034	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigFwd_A	0	0	538519207	291479663	0	0
tb.dut.gen_classes[2].u_esc_timer.AccuFailToFsmError_A	0	0	538519207	221	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig0_A	0	0	538519207	395	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig1_A	0	0	538519207	12	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckClr_A	0	0	538519207	145	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckEn_A	0	0	538302192	242358238	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase0_A	0	0	538519207	427	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase1_A	0	0	538519207	419	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase2_A	0	0	538519207	414	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase3_A	0	0	538519207	407	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeout0_A	0	0	538519207	721	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt1_A	0	0	538519207	90700	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt2_A	0	0	538519207	668	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutStTrig_A	0	0	538519207	36	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStAllEscAsserted_A	0	0	538519207	1159	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStIsTerminal_A	0	0	538519207	949	0	0
tb.dut.gen_classes[2].u_esc_timer.EscStateOut_A	0	0	538300810	538236448	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs.AssertConnected_A	0	0	619	619	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs_A	0	0	538519207	538365906	0	0
tb.dut.gen_classes[3].FpvSecCmAccuCnterCheck_A	0	0	538519207	70	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerCnterCheck_A	0	0	538519207	70	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerFsmCheck_A	0	0	538519207	70	0	0
tb.dut.gen_classes[3].u_accu.CountSaturateStable_A	0	0	538519207	1908	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigBkwd_A	0	0	538519207	159480	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigFwd_A	0	0	538519207	323113447	0	0
tb.dut.gen_classes[3].u_esc_timer.AccuFailToFsmError_A	0	0	538519207	228	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig0_A	0	0	538519207	444	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig1_A	0	0	538519207	19	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckClr_A	0	0	538519207	196	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckEn_A	0	0	538302192	246711923	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase0_A	0	0	538519207	494	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase1_A	0	0	538519207	476	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase2_A	0	0	538519207	470	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase3_A	0	0	538519207	460	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeout0_A	0	0	538519207	434	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt1_A	0	0	538519207	52054	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt2_A	0	0	538519207	370	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutStTrig_A	0	0	538519207	43	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStAllEscAsserted_A	0	0	538519207	1192	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStIsTerminal_A	0	0	538519207	982	0	0
tb.dut.gen_classes[3].u_esc_timer.EscStateOut_A	0	0	538300810	538236448	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs.AssertConnected_A	0	0	619	619	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs_A	0	0	538519207	538365906	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	563288698	79706042	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	563288698	562641512	0	0
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