Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
90.74	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	5	35	87.50

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	5	35	87.50	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	53	1			T12	1		T4	1		T5	1
class_index[0x1]	64	1			T12	1		T71	1		T74	1
class_index[0x2]	36	1			T4	1		T67	1		T78	1
class_index[0x3]	43	1			T4	1		T73	1		T71	1

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	69	1			T12	1		T67	1		T25	1
intr_timeout_cnt[1]	46	1			T12	1		T4	1		T41	1
intr_timeout_cnt[2]	23	1			T4	1		T71	1		T74	1
intr_timeout_cnt[3]	13	1			T4	1		T5	1		T78	1
intr_timeout_cnt[4]	10	1			T81	1		T51	1		T246	2
intr_timeout_cnt[5]	9	1			T49	4		T247	1		T104	1
intr_timeout_cnt[6]	5	1			T71	1		T248	1		T249	1
intr_timeout_cnt[7]	7	1			T28	1		T52	1		T249	1
intr_timeout_cnt[8]	8	1			T71	1		T51	1		T52	1
intr_timeout_cnt[9]	6	1			T76	1		T107	1		T250	1

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	5	35	87.50	5

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x0]]	[intr_timeout_cnt[4]]	0	1	1
[class_index[0x2]]	[intr_timeout_cnt[5]]	0	1	1
[class_index[0x2]]	[intr_timeout_cnt[8]]	0	1	1
[class_index[0x3]]	[intr_timeout_cnt[7]]	0	1	1
[class_index[0x3]]	[intr_timeout_cnt[9]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	29	1			T12	1		T25	1		T79	1
class_index[0x0]	intr_timeout_cnt[1]	8	1			T4	1		T41	1		T68	2
class_index[0x0]	intr_timeout_cnt[2]	8	1			T81	1		T109	1		T114	1
class_index[0x0]	intr_timeout_cnt[3]	2	1			T5	1		T249	1		-	-
class_index[0x0]	intr_timeout_cnt[5]	1	1			T104	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[6]	1	1			T251	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[7]	1	1			T52	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[8]	2	1			T71	1		T51	1		-	-
class_index[0x0]	intr_timeout_cnt[9]	1	1			T76	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[0]	18	1			T74	1		T82	1		T33	1
class_index[0x1]	intr_timeout_cnt[1]	22	1			T12	1		T80	1		T24	1
class_index[0x1]	intr_timeout_cnt[2]	6	1			T71	1		T84	1		T49	1
class_index[0x1]	intr_timeout_cnt[3]	1	1			T88	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[4]	4	1			T81	1		T51	1		T246	1
class_index[0x1]	intr_timeout_cnt[5]	2	1			T57	1		T92	1		-	-
class_index[0x1]	intr_timeout_cnt[6]	1	1			T248	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[7]	4	1			T249	1		T247	1		T252	2
class_index[0x1]	intr_timeout_cnt[8]	3	1			T52	1		T250	1		T87	1
class_index[0x1]	intr_timeout_cnt[9]	3	1			T253	2		T251	1		-	-
class_index[0x2]	intr_timeout_cnt[0]	9	1			T67	1		T83	1		T37	1
class_index[0x2]	intr_timeout_cnt[1]	7	1			T24	1		T85	1		T254	1
class_index[0x2]	intr_timeout_cnt[2]	5	1			T4	1		T255	1		T256	1
class_index[0x2]	intr_timeout_cnt[3]	5	1			T78	1		T49	1		T253	1
class_index[0x2]	intr_timeout_cnt[4]	5	1			T246	1		T257	3		T258	1
class_index[0x2]	intr_timeout_cnt[6]	1	1			T250	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[7]	2	1			T28	1		T259	1		-	-
class_index[0x2]	intr_timeout_cnt[9]	2	1			T107	1		T250	1		-	-
class_index[0x3]	intr_timeout_cnt[0]	13	1			T22	1		T74	1		T90	1
class_index[0x3]	intr_timeout_cnt[1]	9	1			T73	1		T108	1		T260	1
class_index[0x3]	intr_timeout_cnt[2]	4	1			T74	1		T129	2		T261	1
class_index[0x3]	intr_timeout_cnt[3]	5	1			T4	1		T109	1		T90	1
class_index[0x3]	intr_timeout_cnt[4]	1	1			T262	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[5]	6	1			T49	4		T247	1		T263	1
class_index[0x3]	intr_timeout_cnt[6]	2	1			T71	1		T249	1		-	-
class_index[0x3]	intr_timeout_cnt[8]	3	1			T256	1		T264	1		T257	1