Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	281287	1			T1	75		T3	61		T8	13
all_values[1]	281287	1			T1	75		T3	61		T8	13
all_values[2]	281287	1			T1	75		T3	61		T8	13
all_values[3]	281287	1			T1	75		T3	61		T8	13

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

559855

1

T1

150

T12

30

T4

985

auto[1]

565293

1

T1

150

T3

244

T8

52

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

670506

1

T1

153

T3

204

T8

45

auto[1]

454642

1

T1

147

T3

40

T8

7

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	81418	1			T1	15		T12	4		T4	129
all_values[0]	auto[0]	auto[1]	58706	1			T1	15		T12	2		T4	127
all_values[0]	auto[1]	auto[0]	82421	1			T1	24		T3	58		T8	11
all_values[0]	auto[1]	auto[1]	58742	1			T1	21		T3	3		T8	2
all_values[1]	auto[0]	auto[0]	84049	1			T1	22		T12	3		T4	116
all_values[1]	auto[0]	auto[1]	55958	1			T1	21		T12	3		T4	112
all_values[1]	auto[1]	auto[0]	84903	1			T1	16		T3	38		T8	11
all_values[1]	auto[1]	auto[1]	56377	1			T1	16		T3	23		T8	2
all_values[2]	auto[0]	auto[0]	82166	1			T1	13		T12	4		T4	132
all_values[2]	auto[0]	auto[1]	57249	1			T1	13		T12	3		T4	109
all_values[2]	auto[1]	auto[0]	84077	1			T1	25		T3	50		T8	11
all_values[2]	auto[1]	auto[1]	57795	1			T1	24		T3	11		T8	2
all_values[3]	auto[0]	auto[0]	85329	1			T1	26		T12	6		T4	136
all_values[3]	auto[0]	auto[1]	54980	1			T1	25		T12	5		T4	124
all_values[3]	auto[1]	auto[0]	86143	1			T1	12		T3	58		T8	12
all_values[3]	auto[1]	auto[1]	54835	1			T1	12		T3	3		T8	1