Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	281287	1			T1	75		T3	61		T8	13
all_pins[1]	281287	1			T1	75		T3	61		T8	13
all_pins[2]	281287	1			T1	75		T3	61		T8	13
all_pins[3]	281287	1			T1	75		T3	61		T8	13

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	897399	1			T1	227		T3	204		T8	45
values[0x1]	227749	1			T1	73		T3	40		T8	7
transitions[0x0=>0x1]	151181	1			T1	47		T3	32		T8	6
transitions[0x1=>0x0]	151410	1			T1	48		T3	32		T8	6

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	222545	1			T1	54		T3	58		T8	11
all_pins[0]	values[0x1]	58742	1			T1	21		T3	3		T8	2
all_pins[0]	transitions[0x0=>0x1]	58279	1			T1	20		T3	3		T8	2
all_pins[0]	transitions[0x1=>0x0]	54601	1			T1	12		T3	3		T8	1
all_pins[1]	values[0x0]	224910	1			T1	59		T3	38		T8	11
all_pins[1]	values[0x1]	56377	1			T1	16		T3	23		T8	2
all_pins[1]	transitions[0x0=>0x1]	31205	1			T1	8		T3	23		T8	2
all_pins[1]	transitions[0x1=>0x0]	33570	1			T1	13		T3	3		T8	2
all_pins[2]	values[0x0]	223492	1			T1	51		T3	50		T8	11
all_pins[2]	values[0x1]	57795	1			T1	24		T3	11		T8	2
all_pins[2]	transitions[0x0=>0x1]	32099	1			T1	14		T3	3		T8	2
all_pins[2]	transitions[0x1=>0x0]	30681	1			T1	6		T3	15		T8	2
all_pins[3]	values[0x0]	226452	1			T1	63		T3	58		T8	12
all_pins[3]	values[0x1]	54835	1			T1	12		T3	3		T8	1
all_pins[3]	transitions[0x0=>0x1]	29598	1			T1	5		T3	3		T4	41
all_pins[3]	transitions[0x1=>0x0]	32558	1			T1	17		T3	11		T8	1