Unified Coverage Report :: Group :: cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2
cp_intr_test	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_test_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_test_cg_cc	24	0	24	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	269	1			T170	4		T171	7		T172	4
all_values[1]	269	1			T170	4		T171	7		T172	4
all_values[2]	269	1			T170	4		T171	7		T172	4
all_values[3]	269	1			T170	4		T171	7		T172	4

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

616

1

T170

5

T171

20

T172

10

auto[1]

460

1

T170

11

T171

8

T172

6

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

444

1

T170

10

T171

11

T172

3

auto[1]

632

1

T170

6

T171

17

T172

13

---

Summary for Variable cp_intr_test

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_test

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

620

1

T170

12

T171

16

T172

10

auto[1]

456

1

T170

4

T171

12

T172

6

---

Summary for Cross intr_test_cg_cc

Samples crossed: cp_intr cp_intr_test cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
TOTAL	24	0	24	100.00
Automatically Generated Cross Bins	24	0	24	100.00
User Defined Cross Bins	0	0	0

Automatically Generated Cross Bins for intr_test_cg_cc

Bins

cp_intr

cp_intr_test

cp_intr_en

cp_intr_state

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

all_values[0]

auto[0]

auto[0]

auto[0]

63

1

T170

3

T171

4

T227

2

all_values[0]

auto[0]

auto[0]

auto[1]

23

1

T171

1

T172

1

T227

1

all_values[0]

auto[0]

auto[1]

auto[0]

50

1

T170

1

T172

1

T240

2

all_values[0]

auto[0]

auto[1]

auto[1]

24

1

T172

1

T350

1

T240

1

all_values[0]

auto[1]

auto[0]

auto[1]

67

1

T171

2

T172

1

T227

1

all_values[0]

auto[1]

auto[1]

auto[1]

42

1

T240

1

T351

2

T352

1

all_values[1]

auto[0]

auto[0]

auto[0]

65

1

T170

1

T171

3

T227

4

all_values[1]

auto[0]

auto[0]

auto[1]

27

1

T172

2

T353

1

T351

1

all_values[1]

auto[0]

auto[1]

auto[0]

39

1

T170

1

T171

2

T350

2

all_values[1]

auto[0]

auto[1]

auto[1]

22

1

T170

1

T172

1

T353

1

all_values[1]

auto[1]

auto[0]

auto[1]

67

1

T171

1

T172

1

T353

2

all_values[1]

auto[1]

auto[1]

auto[1]

49

1

T170

1

T171

1

T350

2

all_values[2]

auto[0]

auto[0]

auto[0]

69

1

T170

1

T171

1

T172

2

all_values[2]

auto[0]

auto[0]

auto[1]

24

1

T171

1

T351

1

T354

1

all_values[2]

auto[0]

auto[1]

auto[0]

47

1

T170

2

T227

1

T350

1

all_values[2]

auto[0]

auto[1]

auto[1]

16

1

T350

1

T351

1

T355

1

all_values[2]

auto[1]

auto[0]

auto[1]

70

1

T171

5

T172

1

T350

2

all_values[2]

auto[1]

auto[1]

auto[1]

43

1

T170

1

T172

1

T353

1

all_values[3]

auto[0]

auto[0]

auto[0]

65

1

T227

1

T350

4

T240

1

all_values[3]

auto[0]

auto[0]

auto[1]

18

1

T171

1

T227

1

T354

2

all_values[3]

auto[0]

auto[1]

auto[0]

46

1

T170

1

T171

1

T227

1

all_values[3]

auto[0]

auto[1]

auto[1]

22

1

T170

1

T171

2

T172

2

all_values[3]

auto[1]

auto[0]

auto[1]

58

1

T171

1

T172

2

T240

1

all_values[3]

auto[1]

auto[1]

auto[1]

60

1

T170

2

T171

2

T227

1

User Defined Cross Bins for intr_test_cg_cc

Excluded/Illegal bins

NAME	COUNT	STATUS
test_1_state_0	0	Illegal