Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	83264	1			T5	1799		T7	600		T14	1599
accum_cnt_1000	172850	1			T4	187		T5	1978		T7	803
accum_cnt_100	17314	1			T1	9		T4	56		T5	147
accum_cnt_50	49600	1			T1	19		T12	6		T4	241
accum_cnt_10	163216	1			T1	51		T3	91		T8	3
accum_cnt_0	309588	1			T1	69		T3	121		T8	33

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	207941	1			T1	37		T3	53		T8	9
class_index[0x1]	207941	1			T1	37		T3	53		T8	9
class_index[0x2]	207941	1			T1	37		T3	53		T8	9
class_index[0x3]	207941	1			T1	37		T3	53		T8	9

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	20770	1			T5	610		T7	237		T14	600
class_index[0x0]	accum_cnt_1000	45494	1			T4	58		T5	801		T7	199
class_index[0x0]	accum_cnt_100	4859	1			T4	14		T5	67		T7	8
class_index[0x0]	accum_cnt_50	17739	1			T4	159		T5	50		T7	11
class_index[0x0]	accum_cnt_10	37732	1			T1	37		T3	44		T12	13
class_index[0x0]	accum_cnt_0	75316	1			T3	9		T8	9		T12	1
class_index[0x1]	accum_cnt_2000	23487	1			T5	630		T15	608		T17	499
class_index[0x1]	accum_cnt_1000	45265	1			T5	672		T15	523		T17	438
class_index[0x1]	accum_cnt_100	4204	1			T1	9		T5	52		T15	29
class_index[0x1]	accum_cnt_50	11424	1			T1	19		T4	23		T5	36
class_index[0x1]	accum_cnt_10	39260	1			T1	8		T8	3		T12	10
class_index[0x1]	accum_cnt_0	77661	1			T1	1		T3	53		T8	6
class_index[0x2]	accum_cnt_2000	19439	1			T14	582		T15	575		T17	336
class_index[0x2]	accum_cnt_1000	45040	1			T4	50		T14	510		T15	518
class_index[0x2]	accum_cnt_100	4117	1			T4	24		T14	27		T15	26
class_index[0x2]	accum_cnt_50	9577	1			T4	34		T14	16		T19	21
class_index[0x2]	accum_cnt_10	36689	1			T4	154		T5	1645		T7	1054
class_index[0x2]	accum_cnt_0	79852	1			T1	37		T3	53		T8	9
class_index[0x3]	accum_cnt_2000	19568	1			T5	559		T7	363		T14	417
class_index[0x3]	accum_cnt_1000	37051	1			T4	79		T5	505		T7	604
class_index[0x3]	accum_cnt_100	4134	1			T4	18		T5	28		T7	33
class_index[0x3]	accum_cnt_50	10860	1			T12	6		T4	25		T5	193
class_index[0x3]	accum_cnt_10	49535	1			T1	6		T3	47		T12	7
class_index[0x3]	accum_cnt_0	76759	1			T1	31		T3	6		T8	9