Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	1955	1			T7	25		T42	1		T44	5
alert[0x1]	3424	1			T66	273		T67	56		T73	27
alert[0x2]	2016	1			T44	1		T67	938		T80	2
alert[0x3]	1399	1			T44	4		T71	2		T74	1
alert[0x4]	2061	1			T3	1		T42	1		T73	5
alert[0x5]	3788	1			T3	1		T67	130		T45	21
alert[0x6]	1574	1			T3	1		T16	1		T66	39
alert[0x7]	4024	1			T4	9		T5	1		T7	302
alert[0x8]	4906	1			T5	8		T7	71		T16	1
alert[0x9]	2067	1			T7	82		T73	8		T22	433
alert[0xa]	7744	1			T4	5		T7	16		T42	1
alert[0xb]	3574	1			T8	1		T66	212		T67	397
alert[0xc]	1322	1			T7	13		T66	238		T67	25
alert[0xd]	2676	1			T5	5		T7	37		T66	94
alert[0xe]	865	1			T67	17		T301	1		T22	92
alert[0xf]	2793	1			T3	1		T44	1		T66	19
alert[0x10]	3059	1			T7	13		T41	8		T66	103
alert[0x11]	9482	1			T7	689		T44	4		T67	137
alert[0x12]	3274	1			T7	668		T41	1		T66	893
alert[0x13]	10904	1			T7	350		T44	5		T45	26
alert[0x14]	2014	1			T7	461		T16	1		T45	2
alert[0x15]	2077	1			T5	1		T7	254		T67	43
alert[0x16]	1855	1			T5	1		T66	165		T67	29
alert[0x17]	1673	1			T5	14		T7	656		T16	1
alert[0x18]	1500	1			T3	1		T4	10		T66	292
alert[0x19]	1061	1			T7	64		T73	149		T45	91
alert[0x1a]	2168	1			T4	39		T7	26		T66	65
alert[0x1b]	7181	1			T5	3		T21	1		T73	7
alert[0x1c]	1967	1			T3	1		T7	36		T44	24
alert[0x1d]	5222	1			T7	123		T73	2		T45	21
alert[0x1e]	4626	1			T8	1		T66	17		T45	603
alert[0x1f]	9275	1			T41	75		T45	507		T22	2529
alert[0x20]	4143	1			T4	7		T7	44		T41	21
alert[0x21]	9410	1			T3	1		T42	1		T67	56
alert[0x22]	1074	1			T4	34		T42	1		T66	131
alert[0x23]	2894	1			T8	1		T67	14		T301	1
alert[0x24]	2744	1			T5	3		T7	122		T66	372
alert[0x25]	1995	1			T3	1		T7	20		T41	8
alert[0x26]	3275	1			T73	6		T45	205		T22	190
alert[0x27]	3055	1			T7	47		T44	3		T45	683
alert[0x28]	3905	1			T3	2		T5	30		T67	15
alert[0x29]	4662	1			T3	1		T7	327		T66	2141
alert[0x2a]	11688	1			T4	1		T7	157		T16	1
alert[0x2b]	6080	1			T3	1		T7	170		T66	49
alert[0x2c]	1388	1			T5	3		T66	24		T67	11
alert[0x2d]	2727	1			T7	5		T44	1		T66	223
alert[0x2e]	1573	1			T3	1		T7	35		T66	8
alert[0x2f]	1571	1			T44	6		T67	67		T73	15
alert[0x30]	4076	1			T3	1		T45	8		T71	5
alert[0x31]	8473	1			T41	2		T66	51		T67	58
alert[0x32]	3103	1			T4	1		T41	16		T73	1
alert[0x33]	4425	1			T5	2		T7	41		T66	468
alert[0x34]	4135	1			T8	1		T66	24		T71	3
alert[0x35]	2810	1			T7	646		T41	2		T73	5
alert[0x36]	2821	1			T66	29		T22	934		T228	3
alert[0x37]	2593	1			T4	1		T7	17		T44	2
alert[0x38]	2152	1			T4	1		T5	64		T44	2
alert[0x39]	3492	1			T3	3		T4	9		T7	14
alert[0x3a]	1908	1			T4	1		T7	19		T67	42
alert[0x3b]	3935	1			T7	131		T66	44		T67	6
alert[0x3c]	3500	1			T3	2		T4	1		T44	1
alert[0x3d]	5310	1			T5	1		T66	229		T45	4
alert[0x3e]	3444	1			T5	13		T67	15		T45	554
alert[0x3f]	1393	1			T5	2		T7	17		T67	39
alert[0x40]	1730	1			T7	10		T67	18		T45	71

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	27955	1			T3	2		T8	2		T4	74
class_i[0x1]	8254	1			T3	14		T8	1		T4	27
class_i[0x2]	101474	1			T3	2		T8	1		T4	18
class_i[0x3]	97327	1			T3	1		T5	25		T41	6

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

234443

1

T4

119

T5

151

T7

5708

alert_ping_fail

567

1

T3

19

T8

4

T16

5

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	1946	1			T7	25		T44	5		T66	225
alert_integrity_fail	alert[0x1]	3418	1			T66	273		T67	56		T73	27
alert_integrity_fail	alert[0x2]	2005	1			T44	1		T67	938		T80	2
alert_integrity_fail	alert[0x3]	1388	1			T44	4		T71	2		T74	1
alert_integrity_fail	alert[0x4]	2051	1			T73	5		T74	1		T228	24
alert_integrity_fail	alert[0x5]	3773	1			T67	130		T45	21		T71	1
alert_integrity_fail	alert[0x6]	1566	1			T66	39		T67	54		T73	51
alert_integrity_fail	alert[0x7]	4014	1			T4	9		T5	1		T7	302
alert_integrity_fail	alert[0x8]	4898	1			T5	8		T7	71		T41	4
alert_integrity_fail	alert[0x9]	2055	1			T7	82		T73	8		T22	433
alert_integrity_fail	alert[0xa]	7738	1			T4	5		T7	16		T44	1
alert_integrity_fail	alert[0xb]	3567	1			T66	212		T67	397		T71	96
alert_integrity_fail	alert[0xc]	1315	1			T7	13		T66	238		T67	25
alert_integrity_fail	alert[0xd]	2669	1			T5	5		T7	37		T66	94
alert_integrity_fail	alert[0xe]	855	1			T67	17		T22	92		T228	35
alert_integrity_fail	alert[0xf]	2786	1			T44	1		T66	19		T73	1
alert_integrity_fail	alert[0x10]	3053	1			T7	13		T41	8		T66	103
alert_integrity_fail	alert[0x11]	9474	1			T7	689		T44	4		T67	137
alert_integrity_fail	alert[0x12]	3266	1			T7	668		T41	1		T66	893
alert_integrity_fail	alert[0x13]	10899	1			T7	350		T44	5		T45	26
alert_integrity_fail	alert[0x14]	2005	1			T7	461		T45	2		T22	25
alert_integrity_fail	alert[0x15]	2052	1			T5	1		T7	254		T67	43
alert_integrity_fail	alert[0x16]	1843	1			T5	1		T66	165		T67	29
alert_integrity_fail	alert[0x17]	1665	1			T5	14		T7	656		T67	44
alert_integrity_fail	alert[0x18]	1490	1			T4	10		T66	292		T67	40
alert_integrity_fail	alert[0x19]	1051	1			T7	64		T73	149		T45	91
alert_integrity_fail	alert[0x1a]	2161	1			T4	39		T7	26		T66	65
alert_integrity_fail	alert[0x1b]	7170	1			T5	3		T21	1		T73	7
alert_integrity_fail	alert[0x1c]	1959	1			T7	36		T44	24		T67	215
alert_integrity_fail	alert[0x1d]	5210	1			T7	123		T73	2		T45	21
alert_integrity_fail	alert[0x1e]	4618	1			T66	17		T45	603		T71	1
alert_integrity_fail	alert[0x1f]	9265	1			T41	75		T45	507		T22	2529
alert_integrity_fail	alert[0x20]	4137	1			T4	7		T7	44		T41	21
alert_integrity_fail	alert[0x21]	9402	1			T67	56		T45	488		T71	1
alert_integrity_fail	alert[0x22]	1057	1			T4	34		T66	131		T67	175
alert_integrity_fail	alert[0x23]	2880	1			T67	14		T74	7		T76	39
alert_integrity_fail	alert[0x24]	2740	1			T5	3		T7	122		T66	372
alert_integrity_fail	alert[0x25]	1989	1			T7	20		T41	8		T66	11
alert_integrity_fail	alert[0x26]	3272	1			T73	6		T45	205		T22	190
alert_integrity_fail	alert[0x27]	3045	1			T7	47		T44	3		T45	683
alert_integrity_fail	alert[0x28]	3897	1			T5	30		T67	15		T73	3
alert_integrity_fail	alert[0x29]	4656	1			T7	327		T66	2141		T45	904
alert_integrity_fail	alert[0x2a]	11683	1			T4	1		T7	157		T44	1
alert_integrity_fail	alert[0x2b]	6072	1			T7	170		T66	49		T67	38
alert_integrity_fail	alert[0x2c]	1376	1			T5	3		T66	24		T67	11
alert_integrity_fail	alert[0x2d]	2721	1			T7	5		T44	1		T66	223
alert_integrity_fail	alert[0x2e]	1565	1			T7	35		T66	8		T67	593
alert_integrity_fail	alert[0x2f]	1559	1			T44	6		T67	67		T73	15
alert_integrity_fail	alert[0x30]	4067	1			T45	8		T71	5		T79	1
alert_integrity_fail	alert[0x31]	8468	1			T41	2		T66	51		T67	58
alert_integrity_fail	alert[0x32]	3096	1			T4	1		T41	16		T73	1
alert_integrity_fail	alert[0x33]	4419	1			T5	2		T7	41		T66	468
alert_integrity_fail	alert[0x34]	4122	1			T66	24		T71	3		T76	271
alert_integrity_fail	alert[0x35]	2803	1			T7	646		T41	2		T73	5
alert_integrity_fail	alert[0x36]	2811	1			T66	29		T22	934		T228	3
alert_integrity_fail	alert[0x37]	2588	1			T4	1		T7	17		T44	2
alert_integrity_fail	alert[0x38]	2140	1			T4	1		T5	64		T44	2
alert_integrity_fail	alert[0x39]	3480	1			T4	9		T7	14		T66	58
alert_integrity_fail	alert[0x3a]	1900	1			T4	1		T7	19		T67	42
alert_integrity_fail	alert[0x3b]	3931	1			T7	131		T66	44		T67	6
alert_integrity_fail	alert[0x3c]	3487	1			T4	1		T44	1		T67	10
alert_integrity_fail	alert[0x3d]	5299	1			T5	1		T66	229		T45	4
alert_integrity_fail	alert[0x3e]	3439	1			T5	13		T67	15		T45	554
alert_integrity_fail	alert[0x3f]	1392	1			T5	2		T7	17		T67	39
alert_integrity_fail	alert[0x40]	1725	1			T7	10		T67	18		T45	71
alert_ping_fail	alert[0x0]	9	1			T42	1		T270	1		T36	1
alert_ping_fail	alert[0x1]	6	1			T301	1		T302	1		T303	1
alert_ping_fail	alert[0x2]	11	1			T302	2		T304	1		T305	1
alert_ping_fail	alert[0x3]	11	1			T306	1		T304	1		T305	1
alert_ping_fail	alert[0x4]	10	1			T3	1		T42	1		T301	1
alert_ping_fail	alert[0x5]	15	1			T3	1		T127	1		T270	1
alert_ping_fail	alert[0x6]	8	1			T3	1		T16	1		T296	1
alert_ping_fail	alert[0x7]	10	1			T295	1		T270	1		T307	1
alert_ping_fail	alert[0x8]	8	1			T16	1		T18	1		T42	1
alert_ping_fail	alert[0x9]	12	1			T306	1		T234	2		T308	1
alert_ping_fail	alert[0xa]	6	1			T42	1		T270	1		T302	1
alert_ping_fail	alert[0xb]	7	1			T8	1		T305	2		T234	1
alert_ping_fail	alert[0xc]	7	1			T302	1		T305	1		T234	1
alert_ping_fail	alert[0xd]	7	1			T270	1		T303	1		T309	1
alert_ping_fail	alert[0xe]	10	1			T301	1		T302	1		T310	1
alert_ping_fail	alert[0xf]	7	1			T3	1		T222	1		T270	1
alert_ping_fail	alert[0x10]	6	1			T310	1		T311	1		T312	1
alert_ping_fail	alert[0x11]	8	1			T301	1		T270	1		T307	1
alert_ping_fail	alert[0x12]	8	1			T311	1		T309	1		T313	1
alert_ping_fail	alert[0x13]	5	1			T314	1		T311	1		T315	1
alert_ping_fail	alert[0x14]	9	1			T16	1		T299	1		T316	1
alert_ping_fail	alert[0x15]	25	1			T301	1		T127	1		T317	1
alert_ping_fail	alert[0x16]	12	1			T232	1		T318	1		T311	1
alert_ping_fail	alert[0x17]	8	1			T16	1		T127	1		T317	1
alert_ping_fail	alert[0x18]	10	1			T3	1		T127	1		T36	1
alert_ping_fail	alert[0x19]	10	1			T222	1		T302	1		T319	1
alert_ping_fail	alert[0x1a]	7	1			T36	1		T304	1		T234	1
alert_ping_fail	alert[0x1b]	11	1			T127	1		T222	1		T306	1
alert_ping_fail	alert[0x1c]	8	1			T3	1		T301	1		T307	1
alert_ping_fail	alert[0x1d]	12	1			T319	1		T311	1		T312	1
alert_ping_fail	alert[0x1e]	8	1			T8	1		T270	1		T311	1
alert_ping_fail	alert[0x1f]	10	1			T320	1		T319	1		T321	1
alert_ping_fail	alert[0x20]	6	1			T311	1		T322	1		T323	1
alert_ping_fail	alert[0x21]	8	1			T3	1		T42	1		T301	1
alert_ping_fail	alert[0x22]	17	1			T42	1		T36	1		T225	1
alert_ping_fail	alert[0x23]	14	1			T8	1		T301	1		T222	1
alert_ping_fail	alert[0x24]	4	1			T322	1		T324	1		T325	1
alert_ping_fail	alert[0x25]	6	1			T3	1		T36	1		T302	1
alert_ping_fail	alert[0x26]	3	1			T310	1		T326	1		T327	1
alert_ping_fail	alert[0x27]	10	1			T302	1		T309	1		T326	1
alert_ping_fail	alert[0x28]	8	1			T3	2		T36	1		T320	1
alert_ping_fail	alert[0x29]	6	1			T3	1		T301	1		T305	1
alert_ping_fail	alert[0x2a]	5	1			T16	1		T299	1		T311	1
alert_ping_fail	alert[0x2b]	8	1			T3	1		T306	1		T312	1
alert_ping_fail	alert[0x2c]	12	1			T317	1		T36	1		T319	1
alert_ping_fail	alert[0x2d]	6	1			T270	1		T34	2		T307	2
alert_ping_fail	alert[0x2e]	8	1			T3	1		T296	1		T328	2
alert_ping_fail	alert[0x2f]	12	1			T317	2		T270	1		T34	1
alert_ping_fail	alert[0x30]	9	1			T3	1		T127	1		T329	1
alert_ping_fail	alert[0x31]	5	1			T301	1		T234	1		T327	2
alert_ping_fail	alert[0x32]	7	1			T270	1		T234	1		T326	1
alert_ping_fail	alert[0x33]	6	1			T311	1		T330	1		T326	1
alert_ping_fail	alert[0x34]	13	1			T8	1		T301	1		T222	1
alert_ping_fail	alert[0x35]	7	1			T127	1		T317	1		T302	1
alert_ping_fail	alert[0x36]	10	1			T270	1		T36	1		T306	1
alert_ping_fail	alert[0x37]	5	1			T270	1		T322	1		T331	1
alert_ping_fail	alert[0x38]	12	1			T222	1		T270	1		T305	1
alert_ping_fail	alert[0x39]	12	1			T3	3		T222	1		T306	1
alert_ping_fail	alert[0x3a]	8	1			T301	1		T302	1		T306	1
alert_ping_fail	alert[0x3b]	4	1			T302	1		T234	1		T332	1
alert_ping_fail	alert[0x3c]	13	1			T3	2		T317	1		T306	1
alert_ping_fail	alert[0x3d]	11	1			T302	1		T306	1		T307	1
alert_ping_fail	alert[0x3e]	5	1			T127	1		T317	1		T36	1
alert_ping_fail	alert[0x3f]	1	1			T325	1		-	-		-	-
alert_ping_fail	alert[0x40]	5	1			T270	1		T234	1		T316	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	27840	1			T4	74		T5	14		T7	5708
alert_integrity_fail	class_i[0x1]	8071	1			T4	27		T5	112		T41	3
alert_integrity_fail	class_i[0x2]	101355	1			T4	18		T41	119		T44	22
alert_integrity_fail	class_i[0x3]	97177	1			T5	25		T41	6		T44	20
alert_ping_fail	class_i[0x0]	115	1			T3	2		T8	2		T16	5
alert_ping_fail	class_i[0x1]	183	1			T3	14		T8	1		T18	1
alert_ping_fail	class_i[0x2]	119	1			T3	2		T8	1		T42	2
alert_ping_fail	class_i[0x3]	150	1			T3	1		T42	1		T127	7