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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.23 99.99 98.71 97.09 100.00 100.00 99.38 99.44


Total test records in report: 824
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T766 /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.1370124025 Aug 13 05:45:10 PM PDT 24 Aug 13 05:49:42 PM PDT 24 2141833902 ps
T179 /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.4004399177 Aug 13 05:44:58 PM PDT 24 Aug 13 05:45:02 PM PDT 24 51251109 ps
T767 /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.2491823454 Aug 13 05:44:57 PM PDT 24 Aug 13 05:44:59 PM PDT 24 18732508 ps
T768 /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.3039724805 Aug 13 05:44:59 PM PDT 24 Aug 13 05:45:02 PM PDT 24 62046907 ps
T769 /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.727454564 Aug 13 05:45:01 PM PDT 24 Aug 13 05:45:19 PM PDT 24 938827743 ps
T770 /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.400313450 Aug 13 05:45:10 PM PDT 24 Aug 13 05:45:12 PM PDT 24 15684587 ps
T771 /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.3507990014 Aug 13 05:45:05 PM PDT 24 Aug 13 05:45:16 PM PDT 24 89547038 ps
T772 /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.2366615278 Aug 13 05:44:52 PM PDT 24 Aug 13 05:45:01 PM PDT 24 227343946 ps
T160 /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.3997121873 Aug 13 05:45:05 PM PDT 24 Aug 13 05:55:42 PM PDT 24 9680680416 ps
T773 /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.2369833863 Aug 13 05:45:12 PM PDT 24 Aug 13 05:45:14 PM PDT 24 7526320 ps
T774 /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.3171013868 Aug 13 05:44:55 PM PDT 24 Aug 13 05:45:19 PM PDT 24 175668181 ps
T157 /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.531708422 Aug 13 05:45:12 PM PDT 24 Aug 13 05:50:22 PM PDT 24 63381720385 ps
T775 /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.3567659485 Aug 13 05:45:23 PM PDT 24 Aug 13 05:45:25 PM PDT 24 6497952 ps
T776 /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.1609559881 Aug 13 05:45:24 PM PDT 24 Aug 13 05:45:25 PM PDT 24 7143615 ps
T777 /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.2478429807 Aug 13 05:45:09 PM PDT 24 Aug 13 05:45:14 PM PDT 24 61685048 ps
T163 /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.2793936687 Aug 13 05:45:06 PM PDT 24 Aug 13 05:48:50 PM PDT 24 2010202541 ps
T778 /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.3115401889 Aug 13 05:45:21 PM PDT 24 Aug 13 05:45:22 PM PDT 24 6746945 ps
T176 /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.2145317244 Aug 13 05:45:04 PM PDT 24 Aug 13 05:45:08 PM PDT 24 148631902 ps
T779 /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.3116539488 Aug 13 05:45:05 PM PDT 24 Aug 13 05:45:11 PM PDT 24 69953785 ps
T780 /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.1038041743 Aug 13 05:44:59 PM PDT 24 Aug 13 05:45:09 PM PDT 24 1099992565 ps
T178 /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.574043501 Aug 13 05:45:03 PM PDT 24 Aug 13 05:45:39 PM PDT 24 1825393837 ps
T781 /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.790329107 Aug 13 05:45:06 PM PDT 24 Aug 13 05:45:30 PM PDT 24 1359677722 ps
T184 /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.2898303308 Aug 13 05:45:08 PM PDT 24 Aug 13 05:45:30 PM PDT 24 635143014 ps
T782 /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.3556190061 Aug 13 05:45:14 PM PDT 24 Aug 13 05:45:25 PM PDT 24 436570968 ps
T783 /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.3698069330 Aug 13 05:45:00 PM PDT 24 Aug 13 05:45:01 PM PDT 24 9724680 ps
T784 /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.1061258115 Aug 13 05:45:06 PM PDT 24 Aug 13 05:45:13 PM PDT 24 68377178 ps
T785 /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.1899170503 Aug 13 05:44:55 PM PDT 24 Aug 13 05:44:58 PM PDT 24 23132635 ps
T786 /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.3940789960 Aug 13 05:45:09 PM PDT 24 Aug 13 05:45:16 PM PDT 24 1676538457 ps
T787 /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.3508030095 Aug 13 05:45:12 PM PDT 24 Aug 13 05:45:13 PM PDT 24 7352830 ps
T788 /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.1198343617 Aug 13 05:44:54 PM PDT 24 Aug 13 05:51:43 PM PDT 24 22792652639 ps
T789 /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.151441418 Aug 13 05:45:00 PM PDT 24 Aug 13 05:45:02 PM PDT 24 6853261 ps
T790 /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.3379573927 Aug 13 05:45:13 PM PDT 24 Aug 13 05:45:22 PM PDT 24 57601595 ps
T791 /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.2737790222 Aug 13 05:44:57 PM PDT 24 Aug 13 05:44:59 PM PDT 24 20413595 ps
T792 /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.1423799697 Aug 13 05:45:09 PM PDT 24 Aug 13 05:45:16 PM PDT 24 542403258 ps
T793 /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.1693877872 Aug 13 05:45:04 PM PDT 24 Aug 13 05:45:15 PM PDT 24 147528842 ps
T794 /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.1246026328 Aug 13 05:45:22 PM PDT 24 Aug 13 05:45:24 PM PDT 24 10293914 ps
T795 /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.787565627 Aug 13 05:44:58 PM PDT 24 Aug 13 05:45:10 PM PDT 24 1655847971 ps
T796 /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.3512074626 Aug 13 05:45:05 PM PDT 24 Aug 13 05:45:11 PM PDT 24 179627541 ps
T797 /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.1062092978 Aug 13 05:44:58 PM PDT 24 Aug 13 05:45:09 PM PDT 24 167558958 ps
T798 /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.4002881147 Aug 13 05:45:06 PM PDT 24 Aug 13 05:45:11 PM PDT 24 94753993 ps
T799 /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.1941544033 Aug 13 05:45:08 PM PDT 24 Aug 13 05:45:24 PM PDT 24 311796609 ps
T800 /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.4172927292 Aug 13 05:45:20 PM PDT 24 Aug 13 05:45:37 PM PDT 24 1075209552 ps
T175 /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.2716201187 Aug 13 05:45:06 PM PDT 24 Aug 13 05:45:10 PM PDT 24 141429695 ps
T357 /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.2632784217 Aug 13 05:44:59 PM PDT 24 Aug 13 06:05:42 PM PDT 24 17298650747 ps
T801 /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.165295538 Aug 13 05:45:21 PM PDT 24 Aug 13 05:45:25 PM PDT 24 24138818 ps
T802 /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.1116994416 Aug 13 05:45:13 PM PDT 24 Aug 13 05:45:18 PM PDT 24 126654516 ps
T166 /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.1873885178 Aug 13 05:44:55 PM PDT 24 Aug 13 06:03:36 PM PDT 24 72965461555 ps
T803 /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.1764796096 Aug 13 05:45:06 PM PDT 24 Aug 13 05:45:12 PM PDT 24 38059879 ps
T804 /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.3167433723 Aug 13 05:44:57 PM PDT 24 Aug 13 05:44:58 PM PDT 24 6272765 ps
T805 /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.3842387209 Aug 13 05:45:06 PM PDT 24 Aug 13 05:45:14 PM PDT 24 202048311 ps
T165 /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.864542718 Aug 13 05:45:09 PM PDT 24 Aug 13 05:53:55 PM PDT 24 29739811501 ps
T189 /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.3888552135 Aug 13 05:45:00 PM PDT 24 Aug 13 05:45:03 PM PDT 24 88514659 ps
T806 /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.2869828857 Aug 13 05:44:59 PM PDT 24 Aug 13 05:47:07 PM PDT 24 855649353 ps
T807 /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.3070110347 Aug 13 05:45:21 PM PDT 24 Aug 13 05:45:22 PM PDT 24 20180243 ps
T808 /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.1010794039 Aug 13 05:45:09 PM PDT 24 Aug 13 05:45:16 PM PDT 24 230151526 ps
T809 /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.2950611634 Aug 13 05:44:57 PM PDT 24 Aug 13 05:45:07 PM PDT 24 129169868 ps
T158 /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.3281474215 Aug 13 05:45:15 PM PDT 24 Aug 13 05:48:23 PM PDT 24 1627492602 ps
T161 /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.1586030489 Aug 13 05:44:56 PM PDT 24 Aug 13 06:03:27 PM PDT 24 29073182781 ps
T358 /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.3099522234 Aug 13 05:44:55 PM PDT 24 Aug 13 05:54:17 PM PDT 24 15731174936 ps
T810 /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.3220377257 Aug 13 05:44:58 PM PDT 24 Aug 13 05:44:59 PM PDT 24 23199961 ps
T811 /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.3059149109 Aug 13 05:45:02 PM PDT 24 Aug 13 05:45:08 PM PDT 24 93125736 ps
T812 /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.1885543894 Aug 13 05:45:00 PM PDT 24 Aug 13 05:45:05 PM PDT 24 336308746 ps
T813 /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.2772816676 Aug 13 05:45:23 PM PDT 24 Aug 13 05:45:24 PM PDT 24 17422444 ps
T814 /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.1345923974 Aug 13 05:45:09 PM PDT 24 Aug 13 05:45:29 PM PDT 24 165432019 ps
T815 /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.2650684876 Aug 13 05:44:52 PM PDT 24 Aug 13 05:44:59 PM PDT 24 392347059 ps
T816 /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.825692328 Aug 13 05:45:22 PM PDT 24 Aug 13 05:45:23 PM PDT 24 17595553 ps
T817 /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.2212183268 Aug 13 05:45:19 PM PDT 24 Aug 13 05:45:21 PM PDT 24 11079538 ps
T818 /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.1031349601 Aug 13 05:44:51 PM PDT 24 Aug 13 05:46:46 PM PDT 24 3352185022 ps
T819 /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.3809476878 Aug 13 05:45:25 PM PDT 24 Aug 13 05:45:26 PM PDT 24 16022599 ps
T820 /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.1816395081 Aug 13 05:45:05 PM PDT 24 Aug 13 05:45:19 PM PDT 24 749496549 ps
T821 /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.3489965175 Aug 13 05:45:03 PM PDT 24 Aug 13 05:45:26 PM PDT 24 1395455490 ps
T822 /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.3903380436 Aug 13 05:44:53 PM PDT 24 Aug 13 05:45:17 PM PDT 24 752987699 ps
T823 /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.1331682781 Aug 13 05:44:59 PM PDT 24 Aug 13 05:45:06 PM PDT 24 145205224 ps
T824 /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.2883424316 Aug 13 05:44:59 PM PDT 24 Aug 13 05:45:08 PM PDT 24 405947304 ps

Test location /workspace/coverage/default/0.alert_handler_stress_all.976799992
Short name T5
Test name
Test status
Simulation time 89763655980 ps
CPU time 1807.32 seconds
Started Aug 13 05:45:29 PM PDT 24
Finished Aug 13 06:15:36 PM PDT 24
Peak memory 305376 kb
Host smart-5ead7e85-b212-44d4-913c-cc83a910cefb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=976799992 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_hand
ler_stress_all.976799992
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.3906255266
Short name T22
Test name
Test status
Simulation time 321339485189 ps
CPU time 4115.58 seconds
Started Aug 13 05:45:40 PM PDT 24
Finished Aug 13 06:54:16 PM PDT 24
Peak memory 305460 kb
Host smart-46c4e4b2-5aed-4b82-b6dd-f154bcf659d2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3906255266 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_han
dler_stress_all.3906255266
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all_with_rand_reset.3535134797
Short name T21
Test name
Test status
Simulation time 789255511 ps
CPU time 55.87 seconds
Started Aug 13 05:48:16 PM PDT 24
Finished Aug 13 05:49:12 PM PDT 24
Peak memory 265328 kb
Host smart-7fb0ba6d-19d6-483f-810d-8029ec688fed
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3535134797 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.alert_handler_stress_all_with_rand_reset.3535134797
Directory /workspace/47.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.3224804881
Short name T9
Test name
Test status
Simulation time 1734841895 ps
CPU time 25.08 seconds
Started Aug 13 05:45:43 PM PDT 24
Finished Aug 13 05:46:08 PM PDT 24
Peak memory 278436 kb
Host smart-dc2699e5-4c6d-44eb-8302-6862a8ec9290
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3224804881 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.3224804881
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.405765192
Short name T169
Test name
Test status
Simulation time 10337548991 ps
CPU time 43.78 seconds
Started Aug 13 05:45:11 PM PDT 24
Finished Aug 13 05:45:55 PM PDT 24
Peak memory 240776 kb
Host smart-ded34ba5-e7e0-4be3-94eb-532913c016d6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=405765192 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.405765192
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.2950591362
Short name T4
Test name
Test status
Simulation time 4876130419 ps
CPU time 492.9 seconds
Started Aug 13 05:46:49 PM PDT 24
Finished Aug 13 05:55:02 PM PDT 24
Peak memory 265152 kb
Host smart-a757757a-a1b5-43b5-a5c6-e44349e32576
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950591362 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_ha
ndler_stress_all.2950591362
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all_with_rand_reset.4247806881
Short name T90
Test name
Test status
Simulation time 6465346376 ps
CPU time 694.22 seconds
Started Aug 13 05:45:41 PM PDT 24
Finished Aug 13 05:57:15 PM PDT 24
Peak memory 273636 kb
Host smart-42605215-2a7f-443f-9dc0-9b98453df3a5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4247806881 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.alert_handler_stress_all_with_rand_reset.4247806881
Directory /workspace/6.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.547295924
Short name T132
Test name
Test status
Simulation time 1661023443 ps
CPU time 189.78 seconds
Started Aug 13 05:44:59 PM PDT 24
Finished Aug 13 05:48:09 PM PDT 24
Peak memory 265612 kb
Host smart-fc3173b2-dcc1-4d3f-9efd-39478439ca8f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=547295924 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_error
s.547295924
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.3298386527
Short name T297
Test name
Test status
Simulation time 167117488762 ps
CPU time 1551.12 seconds
Started Aug 13 05:45:45 PM PDT 24
Finished Aug 13 06:11:36 PM PDT 24
Peak memory 272620 kb
Host smart-5fdb20b2-37bd-43be-8bc8-53f1ea5e4a89
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3298386527 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.3298386527
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.447237478
Short name T3
Test name
Test status
Simulation time 13242526353 ps
CPU time 564.76 seconds
Started Aug 13 05:47:03 PM PDT 24
Finished Aug 13 05:56:28 PM PDT 24
Peak memory 248708 kb
Host smart-17a29c6a-c716-40b2-957a-22008f6b663e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=447237478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.447237478
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.2259902843
Short name T135
Test name
Test status
Simulation time 69093296236 ps
CPU time 1109.26 seconds
Started Aug 13 05:44:59 PM PDT 24
Finished Aug 13 06:03:29 PM PDT 24
Peak memory 273864 kb
Host smart-e74b6f24-6923-42e9-aff5-b66305b12143
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2259902843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.2259902843
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.3660776092
Short name T80
Test name
Test status
Simulation time 71654855581 ps
CPU time 2156.23 seconds
Started Aug 13 05:45:39 PM PDT 24
Finished Aug 13 06:21:36 PM PDT 24
Peak memory 272852 kb
Host smart-b34965da-00e6-4585-8583-d4263c57c6f9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660776092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_han
dler_stress_all.3660776092
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.1031287390
Short name T111
Test name
Test status
Simulation time 170593408212 ps
CPU time 2090.39 seconds
Started Aug 13 05:47:43 PM PDT 24
Finished Aug 13 06:22:34 PM PDT 24
Peak memory 273380 kb
Host smart-42f41f96-2bbd-4b48-8cf5-288dd62eec58
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1031287390 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.1031287390
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.929846855
Short name T45
Test name
Test status
Simulation time 32699726841 ps
CPU time 1996.1 seconds
Started Aug 13 05:47:14 PM PDT 24
Finished Aug 13 06:20:31 PM PDT 24
Peak memory 286976 kb
Host smart-14acc2eb-e73a-4185-b2de-6181c636bc86
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=929846855 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.929846855
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.1541534137
Short name T148
Test name
Test status
Simulation time 8834819597 ps
CPU time 356.16 seconds
Started Aug 13 05:45:05 PM PDT 24
Finished Aug 13 05:51:02 PM PDT 24
Peak memory 265704 kb
Host smart-b6ce099d-9983-4ef8-a033-61dc381e6621
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1541534137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_err
ors.1541534137
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.4202765834
Short name T257
Test name
Test status
Simulation time 55228255368 ps
CPU time 1787.42 seconds
Started Aug 13 05:45:55 PM PDT 24
Finished Aug 13 06:15:43 PM PDT 24
Peak memory 286972 kb
Host smart-718019b1-c8bb-4349-8cc7-c5a795f59696
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202765834 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_ha
ndler_stress_all.4202765834
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.1410222361
Short name T56
Test name
Test status
Simulation time 43057398535 ps
CPU time 2607.04 seconds
Started Aug 13 05:47:16 PM PDT 24
Finished Aug 13 06:30:43 PM PDT 24
Peak memory 289628 kb
Host smart-82e403c3-a8cc-45df-aa34-a4b9b5324102
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1410222361 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_ha
ndler_stress_all.1410222361
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.3601003746
Short name T152
Test name
Test status
Simulation time 65340113367 ps
CPU time 651.84 seconds
Started Aug 13 05:45:06 PM PDT 24
Finished Aug 13 05:55:58 PM PDT 24
Peak memory 273548 kb
Host smart-3a31ce64-498d-48ce-b8ba-c62d8c1f2535
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3601003746 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.3601003746
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.3026850918
Short name T351
Test name
Test status
Simulation time 9314440 ps
CPU time 1.49 seconds
Started Aug 13 05:45:22 PM PDT 24
Finished Aug 13 05:45:23 PM PDT 24
Peak memory 237752 kb
Host smart-52bd0cb3-105e-431c-9ab4-db647fa11657
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3026850918 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.3026850918
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.1860060412
Short name T76
Test name
Test status
Simulation time 737278954470 ps
CPU time 3101.11 seconds
Started Aug 13 05:48:32 PM PDT 24
Finished Aug 13 06:40:14 PM PDT 24
Peak memory 289208 kb
Host smart-a925b3ee-5416-4de3-ba49-4ce8a238ef4d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1860060412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_ha
ndler_stress_all.1860060412
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.2964110296
Short name T140
Test name
Test status
Simulation time 15842964527 ps
CPU time 1033.23 seconds
Started Aug 13 05:45:00 PM PDT 24
Finished Aug 13 06:02:14 PM PDT 24
Peak memory 265680 kb
Host smart-1db82314-11f5-4d21-815b-552332371177
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2964110296 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.2964110296
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.3691535473
Short name T337
Test name
Test status
Simulation time 220353842240 ps
CPU time 3041.57 seconds
Started Aug 13 05:48:26 PM PDT 24
Finished Aug 13 06:39:08 PM PDT 24
Peak memory 289832 kb
Host smart-eb61fe33-2d4e-40cf-be6b-67e8d3f3ab95
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3691535473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.3691535473
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.3281474215
Short name T158
Test name
Test status
Simulation time 1627492602 ps
CPU time 188.05 seconds
Started Aug 13 05:45:15 PM PDT 24
Finished Aug 13 05:48:23 PM PDT 24
Peak memory 265600 kb
Host smart-507b0604-6af3-4c37-8182-39d2ede53aa7
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3281474215 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_err
ors.3281474215
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.856797114
Short name T134
Test name
Test status
Simulation time 17889609122 ps
CPU time 651.28 seconds
Started Aug 13 05:45:08 PM PDT 24
Finished Aug 13 05:55:59 PM PDT 24
Peak memory 272740 kb
Host smart-901abb5c-b6a1-4bcc-87f5-86ff6bcda480
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=856797114 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.856797114
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.3625574222
Short name T299
Test name
Test status
Simulation time 44071995944 ps
CPU time 2622.93 seconds
Started Aug 13 05:46:09 PM PDT 24
Finished Aug 13 06:29:53 PM PDT 24
Peak memory 289844 kb
Host smart-62dbfda3-d44b-44c5-a610-0ce030b94ac9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3625574222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.3625574222
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.441375883
Short name T325
Test name
Test status
Simulation time 10463602712 ps
CPU time 448.46 seconds
Started Aug 13 05:46:24 PM PDT 24
Finished Aug 13 05:53:53 PM PDT 24
Peak memory 248844 kb
Host smart-462b2436-2bc1-4f12-9229-80fe134c5e57
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=441375883 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.441375883
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.750142961
Short name T44
Test name
Test status
Simulation time 206301711743 ps
CPU time 2584.08 seconds
Started Aug 13 05:45:31 PM PDT 24
Finished Aug 13 06:28:36 PM PDT 24
Peak memory 287984 kb
Host smart-431c0e42-e1d5-43b0-b137-47f0c76e5339
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=750142961 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_hand
ler_stress_all.750142961
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.2070646824
Short name T139
Test name
Test status
Simulation time 6804753644 ps
CPU time 218.35 seconds
Started Aug 13 05:44:57 PM PDT 24
Finished Aug 13 05:48:35 PM PDT 24
Peak memory 265676 kb
Host smart-2983b8f5-f8a9-4e2c-b658-c2d78e2df8f9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2070646824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_err
ors.2070646824
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.2735075664
Short name T302
Test name
Test status
Simulation time 10538651383 ps
CPU time 418.46 seconds
Started Aug 13 05:47:28 PM PDT 24
Finished Aug 13 05:54:27 PM PDT 24
Peak memory 248212 kb
Host smart-9025fdcb-ee4f-4058-8e0b-97e0b4a56135
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2735075664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.2735075664
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.448176031
Short name T346
Test name
Test status
Simulation time 92157302395 ps
CPU time 2206.84 seconds
Started Aug 13 05:45:56 PM PDT 24
Finished Aug 13 06:22:43 PM PDT 24
Peak memory 289280 kb
Host smart-13bb6c2a-a26a-4950-a7ef-f9dc0e9efd68
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448176031 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.448176031
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.1873885178
Short name T166
Test name
Test status
Simulation time 72965461555 ps
CPU time 1119.95 seconds
Started Aug 13 05:44:55 PM PDT 24
Finished Aug 13 06:03:36 PM PDT 24
Peak memory 265460 kb
Host smart-12da5c26-2e90-41af-9c1e-167044c785ea
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1873885178 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.1873885178
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.3175825937
Short name T270
Test name
Test status
Simulation time 15809595787 ps
CPU time 370.61 seconds
Started Aug 13 05:48:24 PM PDT 24
Finished Aug 13 05:54:35 PM PDT 24
Peak memory 256792 kb
Host smart-c8cc130c-117c-4e03-80d2-e56c479ae24b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3175825937 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.3175825937
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.40655800
Short name T49
Test name
Test status
Simulation time 156168237586 ps
CPU time 3216.04 seconds
Started Aug 13 05:46:23 PM PDT 24
Finished Aug 13 06:40:00 PM PDT 24
Peak memory 305108 kb
Host smart-c43d3889-9691-46f8-aba4-7d3c10dbceca
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40655800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_hand
ler_stress_all.40655800
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.2430248780
Short name T320
Test name
Test status
Simulation time 197401668888 ps
CPU time 3039.54 seconds
Started Aug 13 05:46:04 PM PDT 24
Finished Aug 13 06:36:44 PM PDT 24
Peak memory 289628 kb
Host smart-dd7d0ba4-ab70-432d-8ee3-909fb7c7611f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2430248780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.2430248780
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.2172750005
Short name T311
Test name
Test status
Simulation time 10048294929 ps
CPU time 393.97 seconds
Started Aug 13 05:46:24 PM PDT 24
Finished Aug 13 05:52:58 PM PDT 24
Peak memory 248888 kb
Host smart-2cdc0652-2b00-4bc1-b90d-3d4afea401d0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2172750005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.2172750005
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.3703566966
Short name T146
Test name
Test status
Simulation time 5283282953 ps
CPU time 685.68 seconds
Started Aug 13 05:44:59 PM PDT 24
Finished Aug 13 05:56:25 PM PDT 24
Peak memory 265556 kb
Host smart-005ac214-6115-4cc8-b398-c22ae6e54c6b
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3703566966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.3703566966
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.4235232858
Short name T227
Test name
Test status
Simulation time 8156699 ps
CPU time 1.52 seconds
Started Aug 13 05:45:12 PM PDT 24
Finished Aug 13 05:45:14 PM PDT 24
Peak memory 237684 kb
Host smart-83c3c3d8-b58f-41de-b103-295f2c6071b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4235232858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.4235232858
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.2168541142
Short name T249
Test name
Test status
Simulation time 178167245655 ps
CPU time 2809.17 seconds
Started Aug 13 05:45:55 PM PDT 24
Finished Aug 13 06:32:44 PM PDT 24
Peak memory 289608 kb
Host smart-322a2946-6ccf-4087-a170-f0d548e82f71
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2168541142 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_ha
ndler_stress_all.2168541142
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all_with_rand_reset.3161477483
Short name T74
Test name
Test status
Simulation time 8304096396 ps
CPU time 298.22 seconds
Started Aug 13 05:47:45 PM PDT 24
Finished Aug 13 05:52:44 PM PDT 24
Peak memory 267592 kb
Host smart-e5700c4d-fc78-4c3c-8701-0ae9c826d4fa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3161477483 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.alert_handler_stress_all_with_rand_reset.3161477483
Directory /workspace/42.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.3782930128
Short name T150
Test name
Test status
Simulation time 3863238419 ps
CPU time 151.07 seconds
Started Aug 13 05:45:09 PM PDT 24
Finished Aug 13 05:47:40 PM PDT 24
Peak memory 265536 kb
Host smart-2148b122-8d80-41b7-987b-a9bd364c9c5b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3782930128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_err
ors.3782930128
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.3136510782
Short name T338
Test name
Test status
Simulation time 96554303685 ps
CPU time 2658.35 seconds
Started Aug 13 05:45:30 PM PDT 24
Finished Aug 13 06:29:49 PM PDT 24
Peak memory 285804 kb
Host smart-717ee7d8-856f-456b-9086-8c89f91b1002
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136510782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.3136510782
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.3071145121
Short name T322
Test name
Test status
Simulation time 49500884681 ps
CPU time 512.56 seconds
Started Aug 13 05:47:04 PM PDT 24
Finished Aug 13 05:55:37 PM PDT 24
Peak memory 247768 kb
Host smart-27e9ad4d-2ad2-463c-8bf1-4afd6371ffa4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3071145121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.3071145121
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.261308958
Short name T167
Test name
Test status
Simulation time 111349939 ps
CPU time 3.17 seconds
Started Aug 13 05:44:57 PM PDT 24
Finished Aug 13 05:45:00 PM PDT 24
Peak memory 237700 kb
Host smart-c66064e6-7d8d-448e-ac2b-9aafaae82b3a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=261308958 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.261308958
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.2481008115
Short name T136
Test name
Test status
Simulation time 18836424657 ps
CPU time 679.76 seconds
Started Aug 13 05:45:01 PM PDT 24
Finished Aug 13 05:56:21 PM PDT 24
Peak memory 273864 kb
Host smart-693afe63-4839-41f8-ae06-6840fa95f92d
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2481008115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.2481008115
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.140618773
Short name T250
Test name
Test status
Simulation time 64206209734 ps
CPU time 2244.58 seconds
Started Aug 13 05:46:00 PM PDT 24
Finished Aug 13 06:23:25 PM PDT 24
Peak memory 289336 kb
Host smart-c9293d7b-c737-4644-a4ed-d9fd62c91f35
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=140618773 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_han
dler_stress_all.140618773
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.943066928
Short name T34
Test name
Test status
Simulation time 47985736577 ps
CPU time 2422.72 seconds
Started Aug 13 05:45:59 PM PDT 24
Finished Aug 13 06:26:23 PM PDT 24
Peak memory 283160 kb
Host smart-77aebcd1-9109-4611-96c3-6220ffa1dcf7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=943066928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.943066928
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.4131369361
Short name T251
Test name
Test status
Simulation time 603596616 ps
CPU time 46.27 seconds
Started Aug 13 05:46:30 PM PDT 24
Finished Aug 13 05:47:16 PM PDT 24
Peak memory 248200 kb
Host smart-23796c5a-dbed-411c-a7dc-c31aee5f56fd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41313
69361 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.4131369361
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all_with_rand_reset.3556960852
Short name T122
Test name
Test status
Simulation time 3509774420 ps
CPU time 232.35 seconds
Started Aug 13 05:46:37 PM PDT 24
Finished Aug 13 05:50:30 PM PDT 24
Peak memory 266880 kb
Host smart-7896c68b-a762-45ce-9812-4840e8afbd0f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556960852 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.alert_handler_stress_all_with_rand_reset.3556960852
Directory /workspace/25.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.1415622424
Short name T67
Test name
Test status
Simulation time 38300971421 ps
CPU time 810.9 seconds
Started Aug 13 05:47:57 PM PDT 24
Finished Aug 13 06:01:28 PM PDT 24
Peak memory 266216 kb
Host smart-2d9fe310-926a-48a3-ad85-a0a6d81242ca
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1415622424 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.1415622424
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.864542718
Short name T165
Test name
Test status
Simulation time 29739811501 ps
CPU time 525.65 seconds
Started Aug 13 05:45:09 PM PDT 24
Finished Aug 13 05:53:55 PM PDT 24
Peak memory 270592 kb
Host smart-9bb6068c-a66f-40ca-a8ea-39d518d9b5ba
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=864542718 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.864542718
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.3836740395
Short name T118
Test name
Test status
Simulation time 3725181575 ps
CPU time 116.84 seconds
Started Aug 13 05:47:16 PM PDT 24
Finished Aug 13 05:49:13 PM PDT 24
Peak memory 256956 kb
Host smart-159621c1-ca99-4d84-afdf-d8a1f4515710
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38367
40395 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.3836740395
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.651977767
Short name T60
Test name
Test status
Simulation time 356929227 ps
CPU time 3.56 seconds
Started Aug 13 05:45:29 PM PDT 24
Finished Aug 13 05:45:32 PM PDT 24
Peak memory 248984 kb
Host smart-217197a0-00b7-4cce-89fb-af2c3aedd9f5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=651977767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.651977767
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.1558494697
Short name T212
Test name
Test status
Simulation time 42953719 ps
CPU time 4.09 seconds
Started Aug 13 05:45:29 PM PDT 24
Finished Aug 13 05:45:33 PM PDT 24
Peak memory 248932 kb
Host smart-5ddd8782-96e6-4b19-8414-5a990f77939d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1558494697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.1558494697
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.2156824124
Short name T35
Test name
Test status
Simulation time 17317900 ps
CPU time 2.58 seconds
Started Aug 13 05:45:51 PM PDT 24
Finished Aug 13 05:45:53 PM PDT 24
Peak memory 249024 kb
Host smart-b4141304-ea67-457d-a9f1-e81eab53fe63
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2156824124 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.2156824124
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.889874652
Short name T215
Test name
Test status
Simulation time 399504970 ps
CPU time 3.37 seconds
Started Aug 13 05:45:55 PM PDT 24
Finished Aug 13 05:45:58 PM PDT 24
Peak memory 249052 kb
Host smart-b8a035a4-3a1b-4d5e-b166-0caccf464318
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=889874652 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.889874652
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.397983450
Short name T310
Test name
Test status
Simulation time 20524908797 ps
CPU time 210.03 seconds
Started Aug 13 05:46:11 PM PDT 24
Finished Aug 13 05:49:41 PM PDT 24
Peak memory 248868 kb
Host smart-51710d33-7edd-4abb-93c7-27cbe88a4c72
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=397983450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.397983450
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all_with_rand_reset.3816666284
Short name T51
Test name
Test status
Simulation time 2384019377 ps
CPU time 168.84 seconds
Started Aug 13 05:45:31 PM PDT 24
Finished Aug 13 05:48:20 PM PDT 24
Peak memory 265680 kb
Host smart-4c47bc7b-ee48-4f2e-8dcd-35bb27c37286
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3816666284 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.alert_handler_stress_all_with_rand_reset.3816666284
Directory /workspace/2.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.593043032
Short name T259
Test name
Test status
Simulation time 1520011105 ps
CPU time 19.6 seconds
Started Aug 13 05:46:25 PM PDT 24
Finished Aug 13 05:46:45 PM PDT 24
Peak memory 248636 kb
Host smart-d0364f71-59b9-4469-81f0-8f5b82bec8e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59304
3032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.593043032
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.2893625499
Short name T234
Test name
Test status
Simulation time 40351053445 ps
CPU time 409.5 seconds
Started Aug 13 05:45:39 PM PDT 24
Finished Aug 13 05:52:29 PM PDT 24
Peak memory 255744 kb
Host smart-078ce42f-2455-4faa-a531-154ce0c466dc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2893625499 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.2893625499
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.2351888347
Short name T182
Test name
Test status
Simulation time 1294212147 ps
CPU time 86.44 seconds
Started Aug 13 05:44:55 PM PDT 24
Finished Aug 13 05:46:22 PM PDT 24
Peak memory 240708 kb
Host smart-05ecf493-e689-4afc-82f1-6711cc11cb23
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2351888347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.2351888347
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.3396767724
Short name T137
Test name
Test status
Simulation time 15395817268 ps
CPU time 354.05 seconds
Started Aug 13 05:45:04 PM PDT 24
Finished Aug 13 05:50:59 PM PDT 24
Peak memory 265704 kb
Host smart-02b00d67-8043-4c6f-9769-0895515a0bae
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3396767724 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_erro
rs.3396767724
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.3266166973
Short name T170
Test name
Test status
Simulation time 23221476 ps
CPU time 2.04 seconds
Started Aug 13 05:45:11 PM PDT 24
Finished Aug 13 05:45:13 PM PDT 24
Peak memory 235892 kb
Host smart-f902036c-b66f-48f6-9448-760f9a721b2f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3266166973 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.3266166973
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.3529816632
Short name T62
Test name
Test status
Simulation time 502032817 ps
CPU time 34.51 seconds
Started Aug 13 05:45:33 PM PDT 24
Finished Aug 13 05:46:07 PM PDT 24
Peak memory 256060 kb
Host smart-e8cfdd65-f001-4960-b6f4-cf81f0564b43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35298
16632 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.3529816632
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all_with_rand_reset.1586407557
Short name T92
Test name
Test status
Simulation time 2862659829 ps
CPU time 325.08 seconds
Started Aug 13 05:45:48 PM PDT 24
Finished Aug 13 05:51:13 PM PDT 24
Peak memory 267700 kb
Host smart-5851c6ec-d77c-4d8c-906d-93a4b30348e2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586407557 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.alert_handler_stress_all_with_rand_reset.1586407557
Directory /workspace/10.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all_with_rand_reset.1895779945
Short name T292
Test name
Test status
Simulation time 2019199554 ps
CPU time 280.08 seconds
Started Aug 13 05:46:00 PM PDT 24
Finished Aug 13 05:50:40 PM PDT 24
Peak memory 265372 kb
Host smart-c4733ed7-23fb-4b05-a89e-c2b37fd91638
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1895779945 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 11.alert_handler_stress_all_with_rand_reset.1895779945
Directory /workspace/11.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.2432326218
Short name T514
Test name
Test status
Simulation time 1117737168 ps
CPU time 69.5 seconds
Started Aug 13 05:45:56 PM PDT 24
Finished Aug 13 05:47:06 PM PDT 24
Peak memory 248504 kb
Host smart-4fbcbbfd-c43b-4142-abb1-4fe7e567037e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24323
26218 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.2432326218
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.766471533
Short name T323
Test name
Test status
Simulation time 4766686701 ps
CPU time 197.06 seconds
Started Aug 13 05:45:55 PM PDT 24
Finished Aug 13 05:49:12 PM PDT 24
Peak memory 248796 kb
Host smart-436d8f63-d655-4e16-9cac-bff3480461ac
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=766471533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.766471533
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.4119956277
Short name T340
Test name
Test status
Simulation time 102585882356 ps
CPU time 2359.74 seconds
Started Aug 13 05:46:05 PM PDT 24
Finished Aug 13 06:25:25 PM PDT 24
Peak memory 289680 kb
Host smart-dcbd192d-b779-41bd-8349-823a3b161642
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4119956277 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.4119956277
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.2390096007
Short name T349
Test name
Test status
Simulation time 34996058629 ps
CPU time 1253.67 seconds
Started Aug 13 05:46:12 PM PDT 24
Finished Aug 13 06:07:06 PM PDT 24
Peak memory 282264 kb
Host smart-269bcc86-cba2-4544-b83d-9f3020572e87
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2390096007 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.2390096007
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.1464909434
Short name T248
Test name
Test status
Simulation time 1499606755 ps
CPU time 45.27 seconds
Started Aug 13 05:46:10 PM PDT 24
Finished Aug 13 05:46:55 PM PDT 24
Peak memory 257016 kb
Host smart-6ce4fb1d-75c1-476c-8c9f-f4cc111e2afc
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1464909434 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_ha
ndler_stress_all.1464909434
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.1549967842
Short name T328
Test name
Test status
Simulation time 239633034393 ps
CPU time 2309.72 seconds
Started Aug 13 05:46:13 PM PDT 24
Finished Aug 13 06:24:43 PM PDT 24
Peak memory 289384 kb
Host smart-3708a8ea-a804-4a87-a098-4f245007b984
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1549967842 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.1549967842
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.2455037669
Short name T294
Test name
Test status
Simulation time 372670482907 ps
CPU time 2894.35 seconds
Started Aug 13 05:46:53 PM PDT 24
Finished Aug 13 06:35:07 PM PDT 24
Peak memory 287620 kb
Host smart-7c913278-6464-4c76-9a85-def527fa8391
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2455037669 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.2455037669
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all_with_rand_reset.4198045453
Short name T88
Test name
Test status
Simulation time 10046614795 ps
CPU time 641.09 seconds
Started Aug 13 05:47:03 PM PDT 24
Finished Aug 13 05:57:44 PM PDT 24
Peak memory 271704 kb
Host smart-069df9cf-9faf-4e12-aa6e-011b9724950c
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4198045453 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.alert_handler_stress_all_with_rand_reset.4198045453
Directory /workspace/28.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all_with_rand_reset.1276696527
Short name T277
Test name
Test status
Simulation time 8959694136 ps
CPU time 169.24 seconds
Started Aug 13 05:47:06 PM PDT 24
Finished Aug 13 05:49:55 PM PDT 24
Peak memory 265676 kb
Host smart-2f5a1498-c7f7-4465-9a20-ec72a062abdd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1276696527 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.alert_handler_stress_all_with_rand_reset.1276696527
Directory /workspace/30.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.1319168724
Short name T104
Test name
Test status
Simulation time 581218365 ps
CPU time 18.64 seconds
Started Aug 13 05:47:03 PM PDT 24
Finished Aug 13 05:47:22 PM PDT 24
Peak memory 248640 kb
Host smart-71d5a968-3644-43e9-a576-67749cfd628d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13191
68724 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.1319168724
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.2754208541
Short name T52
Test name
Test status
Simulation time 30984659354 ps
CPU time 1098.11 seconds
Started Aug 13 05:48:17 PM PDT 24
Finished Aug 13 06:06:35 PM PDT 24
Peak memory 283872 kb
Host smart-1d17de53-89cc-4e21-9859-9040f5f3877a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2754208541 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_ha
ndler_stress_all.2754208541
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.1464978096
Short name T262
Test name
Test status
Simulation time 584571840 ps
CPU time 23.56 seconds
Started Aug 13 05:45:38 PM PDT 24
Finished Aug 13 05:46:02 PM PDT 24
Peak memory 247936 kb
Host smart-9f3ca950-08d0-4a09-b7aa-2e0538e1aaba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14649
78096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.1464978096
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.4062399519
Short name T102
Test name
Test status
Simulation time 10559919645 ps
CPU time 1372.37 seconds
Started Aug 13 05:45:45 PM PDT 24
Finished Aug 13 06:08:37 PM PDT 24
Peak memory 289796 kb
Host smart-027eb6b4-d0bb-4763-9bff-13f15b16685e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4062399519 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.4062399519
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.3847279975
Short name T91
Test name
Test status
Simulation time 74332969746 ps
CPU time 2415.51 seconds
Started Aug 13 05:45:53 PM PDT 24
Finished Aug 13 06:26:09 PM PDT 24
Peak memory 288960 kb
Host smart-7aa94618-9d15-4291-8ab5-093f18fe2b89
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3847279975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.3847279975
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.2145317244
Short name T176
Test name
Test status
Simulation time 148631902 ps
CPU time 3.56 seconds
Started Aug 13 05:45:04 PM PDT 24
Finished Aug 13 05:45:08 PM PDT 24
Peak memory 237688 kb
Host smart-fd699b01-078f-421f-a3c4-a25e389eacd2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2145317244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.2145317244
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.2793936687
Short name T163
Test name
Test status
Simulation time 2010202541 ps
CPU time 223.53 seconds
Started Aug 13 05:45:06 PM PDT 24
Finished Aug 13 05:48:50 PM PDT 24
Peak memory 273220 kb
Host smart-66522a50-8b9a-4035-9db7-45f52df7ee67
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2793936687 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_err
ors.2793936687
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.4004399177
Short name T179
Test name
Test status
Simulation time 51251109 ps
CPU time 3.72 seconds
Started Aug 13 05:44:58 PM PDT 24
Finished Aug 13 05:45:02 PM PDT 24
Peak memory 237772 kb
Host smart-d091e5c6-ab91-407c-ac1e-f9b43f67d9ca
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4004399177 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.4004399177
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.3112046025
Short name T183
Test name
Test status
Simulation time 663607566 ps
CPU time 22.43 seconds
Started Aug 13 05:45:12 PM PDT 24
Finished Aug 13 05:45:34 PM PDT 24
Peak memory 240720 kb
Host smart-548b5d05-ac43-44f0-9a7e-e166183d7527
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3112046025 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.3112046025
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.3827461158
Short name T133
Test name
Test status
Simulation time 3756936772 ps
CPU time 310.04 seconds
Started Aug 13 05:45:09 PM PDT 24
Finished Aug 13 05:50:19 PM PDT 24
Peak memory 265540 kb
Host smart-4b37edee-2b4b-4cc8-ab70-2f563559d32a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3827461158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_err
ors.3827461158
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.2898303308
Short name T184
Test name
Test status
Simulation time 635143014 ps
CPU time 21.98 seconds
Started Aug 13 05:45:08 PM PDT 24
Finished Aug 13 05:45:30 PM PDT 24
Peak memory 240720 kb
Host smart-6122b7d7-8270-4dd3-b9e6-4925300ff52a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2898303308 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.2898303308
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.3607467604
Short name T168
Test name
Test status
Simulation time 455916243 ps
CPU time 33.68 seconds
Started Aug 13 05:45:00 PM PDT 24
Finished Aug 13 05:45:34 PM PDT 24
Peak memory 240708 kb
Host smart-efff6c84-224a-496b-aa9b-13154afbb68e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3607467604 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.3607467604
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.91984173
Short name T142
Test name
Test status
Simulation time 118629199443 ps
CPU time 469.13 seconds
Started Aug 13 05:44:54 PM PDT 24
Finished Aug 13 05:52:43 PM PDT 24
Peak memory 265656 kb
Host smart-2a1651c8-f2ca-4e0c-af3a-455cacea7fc1
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91984173 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -
cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.91984173
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.1983783179
Short name T174
Test name
Test status
Simulation time 294516983 ps
CPU time 45.52 seconds
Started Aug 13 05:44:57 PM PDT 24
Finished Aug 13 05:45:43 PM PDT 24
Peak memory 240704 kb
Host smart-fa8efa42-7c2c-4255-bc61-429de9c46c1a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1983783179 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.1983783179
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.3888552135
Short name T189
Test name
Test status
Simulation time 88514659 ps
CPU time 2.35 seconds
Started Aug 13 05:45:00 PM PDT 24
Finished Aug 13 05:45:03 PM PDT 24
Peak memory 238152 kb
Host smart-b1bde69e-0720-4939-93d2-82cf05f8c9cf
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3888552135 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.3888552135
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.1785198928
Short name T177
Test name
Test status
Simulation time 1395422066 ps
CPU time 43.8 seconds
Started Aug 13 05:44:58 PM PDT 24
Finished Aug 13 05:45:42 PM PDT 24
Peak memory 240740 kb
Host smart-3eea4c6b-1ec3-4f4d-8e72-facf843de205
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1785198928 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.1785198928
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.2494019500
Short name T173
Test name
Test status
Simulation time 3666551896 ps
CPU time 52.71 seconds
Started Aug 13 05:44:58 PM PDT 24
Finished Aug 13 05:45:51 PM PDT 24
Peak memory 238264 kb
Host smart-b6030ad0-f6fa-4b04-8498-7f982b50544a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2494019500 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.2494019500
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.574043501
Short name T178
Test name
Test status
Simulation time 1825393837 ps
CPU time 35.66 seconds
Started Aug 13 05:45:03 PM PDT 24
Finished Aug 13 05:45:39 PM PDT 24
Peak memory 240724 kb
Host smart-5708dea1-a309-4a8e-9f98-7366285e9bd5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=574043501 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.574043501
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.2716201187
Short name T175
Test name
Test status
Simulation time 141429695 ps
CPU time 4.7 seconds
Started Aug 13 05:45:06 PM PDT 24
Finished Aug 13 05:45:10 PM PDT 24
Peak memory 238148 kb
Host smart-28bd1573-815e-4628-bb05-b320fc514a07
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2716201187 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.2716201187
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.1120682963
Short name T185
Test name
Test status
Simulation time 62776786 ps
CPU time 2.41 seconds
Started Aug 13 05:45:09 PM PDT 24
Finished Aug 13 05:45:11 PM PDT 24
Peak memory 237624 kb
Host smart-0e4bd471-6bf3-46db-81ab-d09e12bdf9e5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1120682963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.1120682963
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.2215661591
Short name T188
Test name
Test status
Simulation time 4007812722 ps
CPU time 76.02 seconds
Started Aug 13 05:45:12 PM PDT 24
Finished Aug 13 05:46:29 PM PDT 24
Peak memory 240668 kb
Host smart-a52ab574-5de0-423b-b8d2-7618cd36da8e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2215661591 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.2215661591
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.50972257
Short name T181
Test name
Test status
Simulation time 492848968 ps
CPU time 35.11 seconds
Started Aug 13 05:45:14 PM PDT 24
Finished Aug 13 05:45:49 PM PDT 24
Peak memory 240660 kb
Host smart-4141bb35-9934-457a-9239-670f2f05b547
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=50972257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.50972257
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.3886519939
Short name T180
Test name
Test status
Simulation time 1222949359 ps
CPU time 37 seconds
Started Aug 13 05:45:01 PM PDT 24
Finished Aug 13 05:45:38 PM PDT 24
Peak memory 240708 kb
Host smart-7becdc4a-abf5-4e14-82df-8a016ed3ab4a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3886519939 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.3886519939
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.3144163438
Short name T20
Test name
Test status
Simulation time 1634822450 ps
CPU time 34.95 seconds
Started Aug 13 05:45:41 PM PDT 24
Finished Aug 13 05:46:16 PM PDT 24
Peak memory 257008 kb
Host smart-a81d2c75-5ae9-4763-9665-b7e425f50a16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31441
63438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.3144163438
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.4059982117
Short name T7
Test name
Test status
Simulation time 22968648470 ps
CPU time 1236.08 seconds
Started Aug 13 05:45:45 PM PDT 24
Finished Aug 13 06:06:21 PM PDT 24
Peak memory 289580 kb
Host smart-1f7954a8-ac6e-44b4-8b78-4264e8c7393c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4059982117 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.4059982117
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.1025516055
Short name T729
Test name
Test status
Simulation time 5737019842 ps
CPU time 91.96 seconds
Started Aug 13 05:44:59 PM PDT 24
Finished Aug 13 05:46:31 PM PDT 24
Peak memory 237744 kb
Host smart-b847e9e8-68e5-4355-a2d6-29dd3025d2d0
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1025516055 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.1025516055
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.2869828857
Short name T806
Test name
Test status
Simulation time 855649353 ps
CPU time 128.04 seconds
Started Aug 13 05:44:59 PM PDT 24
Finished Aug 13 05:47:07 PM PDT 24
Peak memory 240684 kb
Host smart-58f598b9-862f-4dcd-9f4b-c7fd0f41f5b4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2869828857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.2869828857
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.665331094
Short name T742
Test name
Test status
Simulation time 1585692964 ps
CPU time 8.25 seconds
Started Aug 13 05:44:51 PM PDT 24
Finished Aug 13 05:45:00 PM PDT 24
Peak memory 240664 kb
Host smart-67d735a5-9db5-4f3f-bcbb-286b1879ff40
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=665331094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.665331094
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.2366615278
Short name T772
Test name
Test status
Simulation time 227343946 ps
CPU time 8.84 seconds
Started Aug 13 05:44:52 PM PDT 24
Finished Aug 13 05:45:01 PM PDT 24
Peak memory 238544 kb
Host smart-2a666625-bd99-4171-bba2-73cad8b6474f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2366615278 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 0.alert_handler_csr_mem_rw_with_rand_reset.2366615278
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.120179350
Short name T748
Test name
Test status
Simulation time 63912267 ps
CPU time 3.89 seconds
Started Aug 13 05:44:58 PM PDT 24
Finished Aug 13 05:45:02 PM PDT 24
Peak memory 239668 kb
Host smart-f5726126-1049-424a-8496-c6b5ecedb26b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=120179350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.120179350
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.347600249
Short name T754
Test name
Test status
Simulation time 6513825 ps
CPU time 1.51 seconds
Started Aug 13 05:44:59 PM PDT 24
Finished Aug 13 05:45:01 PM PDT 24
Peak memory 236892 kb
Host smart-848a38e4-175a-4938-a87e-e0840a9152ef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=347600249 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.347600249
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.3993230815
Short name T197
Test name
Test status
Simulation time 749856301 ps
CPU time 14.18 seconds
Started Aug 13 05:44:58 PM PDT 24
Finished Aug 13 05:45:13 PM PDT 24
Peak memory 245944 kb
Host smart-d1613af2-648c-42c6-874c-501e244a81ce
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3993230815 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_out
standing.3993230815
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.3155373603
Short name T147
Test name
Test status
Simulation time 3223836206 ps
CPU time 133.22 seconds
Started Aug 13 05:44:54 PM PDT 24
Finished Aug 13 05:47:07 PM PDT 24
Peak memory 257512 kb
Host smart-bb66ef45-7eac-4b7d-bf4f-7488126a4729
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3155373603 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_erro
rs.3155373603
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.1018509319
Short name T709
Test name
Test status
Simulation time 78177882 ps
CPU time 7.36 seconds
Started Aug 13 05:44:58 PM PDT 24
Finished Aug 13 05:45:06 PM PDT 24
Peak memory 248784 kb
Host smart-2e3d4c94-563b-46fb-baaf-ccd5233fea57
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1018509319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.1018509319
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.1834451728
Short name T201
Test name
Test status
Simulation time 3740149423 ps
CPU time 249.55 seconds
Started Aug 13 05:44:58 PM PDT 24
Finished Aug 13 05:49:08 PM PDT 24
Peak memory 240748 kb
Host smart-9bf5c7d2-51aa-47c0-9f0d-37de8dcc466a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1834451728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.1834451728
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.2480711494
Short name T735
Test name
Test status
Simulation time 18566886599 ps
CPU time 281.94 seconds
Started Aug 13 05:45:00 PM PDT 24
Finished Aug 13 05:49:42 PM PDT 24
Peak memory 240768 kb
Host smart-a06368e3-8f5d-4081-aca0-bb9a2f4377ec
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2480711494 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.2480711494
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.1397220759
Short name T749
Test name
Test status
Simulation time 73174959 ps
CPU time 7.68 seconds
Started Aug 13 05:44:59 PM PDT 24
Finished Aug 13 05:45:07 PM PDT 24
Peak memory 249228 kb
Host smart-c3972b1f-793e-484f-bcd2-51190f3899c6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1397220759 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.1397220759
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.1288989502
Short name T187
Test name
Test status
Simulation time 370547760 ps
CPU time 14.75 seconds
Started Aug 13 05:45:00 PM PDT 24
Finished Aug 13 05:45:15 PM PDT 24
Peak memory 252060 kb
Host smart-1c3b721f-07b7-4e74-a202-9e39c9a63ada
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1288989502 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 1.alert_handler_csr_mem_rw_with_rand_reset.1288989502
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.539802217
Short name T195
Test name
Test status
Simulation time 56608735 ps
CPU time 5.04 seconds
Started Aug 13 05:44:55 PM PDT 24
Finished Aug 13 05:45:00 PM PDT 24
Peak memory 237732 kb
Host smart-8083712e-e418-44c7-8934-91f9bd576322
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=539802217 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.539802217
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.3202047556
Short name T752
Test name
Test status
Simulation time 37293185 ps
CPU time 1.47 seconds
Started Aug 13 05:45:00 PM PDT 24
Finished Aug 13 05:45:02 PM PDT 24
Peak memory 236780 kb
Host smart-62fdc6cf-f40b-40a9-a721-80df55f88a1c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3202047556 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.3202047556
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.4260075431
Short name T193
Test name
Test status
Simulation time 1978343697 ps
CPU time 36.21 seconds
Started Aug 13 05:45:00 PM PDT 24
Finished Aug 13 05:45:36 PM PDT 24
Peak memory 245080 kb
Host smart-82e687fc-e4b5-4878-9dce-37ea2cb61746
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4260075431 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_out
standing.4260075431
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.766635991
Short name T131
Test name
Test status
Simulation time 1015240221 ps
CPU time 100.96 seconds
Started Aug 13 05:44:54 PM PDT 24
Finished Aug 13 05:46:35 PM PDT 24
Peak memory 257432 kb
Host smart-da19069b-0330-419b-8498-56575ba5a1a6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=766635991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_error
s.766635991
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.787565627
Short name T795
Test name
Test status
Simulation time 1655847971 ps
CPU time 12.49 seconds
Started Aug 13 05:44:58 PM PDT 24
Finished Aug 13 05:45:10 PM PDT 24
Peak memory 248936 kb
Host smart-cea488ea-2f04-4945-b409-b28d5f3f51cd
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=787565627 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.787565627
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.3940789960
Short name T786
Test name
Test status
Simulation time 1676538457 ps
CPU time 7.2 seconds
Started Aug 13 05:45:09 PM PDT 24
Finished Aug 13 05:45:16 PM PDT 24
Peak memory 240768 kb
Host smart-f8a90f79-7f2b-41ec-b5e5-1abf1374c21b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3940789960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 10.alert_handler_csr_mem_rw_with_rand_reset.3940789960
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.1899170503
Short name T785
Test name
Test status
Simulation time 23132635 ps
CPU time 3.49 seconds
Started Aug 13 05:44:55 PM PDT 24
Finished Aug 13 05:44:58 PM PDT 24
Peak memory 236884 kb
Host smart-60934146-c6c3-4f36-977e-94857855cebf
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1899170503 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.1899170503
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.4287253564
Short name T753
Test name
Test status
Simulation time 670597260 ps
CPU time 25.95 seconds
Started Aug 13 05:45:06 PM PDT 24
Finished Aug 13 05:45:32 PM PDT 24
Peak memory 248924 kb
Host smart-161b7286-7ffe-4483-9b01-06b06743a82e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4287253564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_ou
tstanding.4287253564
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.2676449635
Short name T145
Test name
Test status
Simulation time 37726596402 ps
CPU time 172.34 seconds
Started Aug 13 05:44:59 PM PDT 24
Finished Aug 13 05:47:52 PM PDT 24
Peak memory 266568 kb
Host smart-111a1155-4cce-47ef-a47a-37086897e431
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2676449635 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_err
ors.2676449635
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.1068662908
Short name T236
Test name
Test status
Simulation time 119927805 ps
CPU time 9.22 seconds
Started Aug 13 05:45:02 PM PDT 24
Finished Aug 13 05:45:11 PM PDT 24
Peak memory 248880 kb
Host smart-8dd92367-e1eb-41c5-90aa-5c5f32773c53
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1068662908 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.1068662908
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.2478429807
Short name T777
Test name
Test status
Simulation time 61685048 ps
CPU time 5.5 seconds
Started Aug 13 05:45:09 PM PDT 24
Finished Aug 13 05:45:14 PM PDT 24
Peak memory 242628 kb
Host smart-4ffa651a-c565-4489-a5c0-b3aa58addc66
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2478429807 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.alert_handler_csr_mem_rw_with_rand_reset.2478429807
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.1333732901
Short name T194
Test name
Test status
Simulation time 196733387 ps
CPU time 7.56 seconds
Started Aug 13 05:45:09 PM PDT 24
Finished Aug 13 05:45:17 PM PDT 24
Peak memory 236908 kb
Host smart-e5e407f4-eaca-4364-bed7-faa925a38768
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1333732901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.1333732901
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.3508030095
Short name T787
Test name
Test status
Simulation time 7352830 ps
CPU time 1.48 seconds
Started Aug 13 05:45:12 PM PDT 24
Finished Aug 13 05:45:13 PM PDT 24
Peak memory 237796 kb
Host smart-bcd9aa41-e839-4adc-aaca-ed42292ac2f5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3508030095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.3508030095
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.1683574029
Short name T762
Test name
Test status
Simulation time 96105639 ps
CPU time 11.83 seconds
Started Aug 13 05:45:06 PM PDT 24
Finished Aug 13 05:45:18 PM PDT 24
Peak memory 246000 kb
Host smart-caa38de0-aebc-45b7-9f55-53833d8d7652
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1683574029 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_ou
tstanding.1683574029
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.2783640478
Short name T162
Test name
Test status
Simulation time 8585984720 ps
CPU time 581.88 seconds
Started Aug 13 05:45:11 PM PDT 24
Finished Aug 13 05:54:54 PM PDT 24
Peak memory 265896 kb
Host smart-6b27f257-caf3-4dbf-ae55-4eee011a868c
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2783640478 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.2783640478
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.2664521018
Short name T229
Test name
Test status
Simulation time 154242669 ps
CPU time 10.94 seconds
Started Aug 13 05:45:09 PM PDT 24
Finished Aug 13 05:45:20 PM PDT 24
Peak memory 248772 kb
Host smart-23e49cb6-3334-4fb5-9a3a-1140c7b3dd8a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2664521018 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.2664521018
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.4202349258
Short name T203
Test name
Test status
Simulation time 123934847 ps
CPU time 5.6 seconds
Started Aug 13 05:45:03 PM PDT 24
Finished Aug 13 05:45:09 PM PDT 24
Peak memory 240848 kb
Host smart-8cf79fae-51dc-455d-aff4-4d1fdb74d19f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4202349258 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 12.alert_handler_csr_mem_rw_with_rand_reset.4202349258
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.1910053156
Short name T738
Test name
Test status
Simulation time 67326948 ps
CPU time 5.59 seconds
Started Aug 13 05:45:05 PM PDT 24
Finished Aug 13 05:45:10 PM PDT 24
Peak memory 237648 kb
Host smart-d6a5bce6-c822-49cd-87fa-dc2f76a8ca5d
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1910053156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.1910053156
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.3220377257
Short name T810
Test name
Test status
Simulation time 23199961 ps
CPU time 1.46 seconds
Started Aug 13 05:44:58 PM PDT 24
Finished Aug 13 05:44:59 PM PDT 24
Peak memory 236980 kb
Host smart-e86ea19d-ed18-49ec-86d7-af0b3a7c1574
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3220377257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.3220377257
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.1083633076
Short name T757
Test name
Test status
Simulation time 631665434 ps
CPU time 22.12 seconds
Started Aug 13 05:45:04 PM PDT 24
Finished Aug 13 05:45:27 PM PDT 24
Peak memory 248940 kb
Host smart-b8459da6-ac67-4377-b735-b9a9c9859037
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1083633076 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_ou
tstanding.1083633076
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.3383319447
Short name T159
Test name
Test status
Simulation time 25771059438 ps
CPU time 463.76 seconds
Started Aug 13 05:45:09 PM PDT 24
Finished Aug 13 05:52:52 PM PDT 24
Peak memory 269300 kb
Host smart-404facd7-0e4f-4f4e-a710-8230071eeebb
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3383319447 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.3383319447
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.672222776
Short name T728
Test name
Test status
Simulation time 183088441 ps
CPU time 12.5 seconds
Started Aug 13 05:45:11 PM PDT 24
Finished Aug 13 05:45:24 PM PDT 24
Peak memory 248608 kb
Host smart-ae72b55e-fdbf-4d19-b2f8-7360ef684633
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=672222776 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.672222776
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.1764796096
Short name T803
Test name
Test status
Simulation time 38059879 ps
CPU time 5.75 seconds
Started Aug 13 05:45:06 PM PDT 24
Finished Aug 13 05:45:12 PM PDT 24
Peak memory 253404 kb
Host smart-11a288ec-e1f3-440d-b7a7-eafb7b6f67f5
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1764796096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 13.alert_handler_csr_mem_rw_with_rand_reset.1764796096
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.3116539488
Short name T779
Test name
Test status
Simulation time 69953785 ps
CPU time 5.77 seconds
Started Aug 13 05:45:05 PM PDT 24
Finished Aug 13 05:45:11 PM PDT 24
Peak memory 237772 kb
Host smart-926ef560-8fdb-4eb6-8c43-e29fcb1ca096
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3116539488 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.3116539488
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.76157528
Short name T764
Test name
Test status
Simulation time 22102120 ps
CPU time 1.41 seconds
Started Aug 13 05:45:04 PM PDT 24
Finished Aug 13 05:45:05 PM PDT 24
Peak memory 236760 kb
Host smart-07369253-8b14-4856-93fa-31e5ec31c177
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=76157528 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.76157528
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.1345923974
Short name T814
Test name
Test status
Simulation time 165432019 ps
CPU time 19.72 seconds
Started Aug 13 05:45:09 PM PDT 24
Finished Aug 13 05:45:29 PM PDT 24
Peak memory 248892 kb
Host smart-591b5589-8138-4b6e-9eb3-837c7fd11e61
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1345923974 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_ou
tstanding.1345923974
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.1370124025
Short name T766
Test name
Test status
Simulation time 2141833902 ps
CPU time 271.61 seconds
Started Aug 13 05:45:10 PM PDT 24
Finished Aug 13 05:49:42 PM PDT 24
Peak memory 268536 kb
Host smart-d0fdca88-33f7-48ff-879e-25d9500ccdad
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1370124025 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.1370124025
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.3512074626
Short name T796
Test name
Test status
Simulation time 179627541 ps
CPU time 6.54 seconds
Started Aug 13 05:45:05 PM PDT 24
Finished Aug 13 05:45:11 PM PDT 24
Peak memory 248884 kb
Host smart-5e770b7c-b252-483b-adcc-53aff667f27b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3512074626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.3512074626
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.73354236
Short name T715
Test name
Test status
Simulation time 104109079 ps
CPU time 8.92 seconds
Started Aug 13 05:45:07 PM PDT 24
Finished Aug 13 05:45:16 PM PDT 24
Peak memory 251576 kb
Host smart-e33461b4-b498-4a65-9f9e-b331b772487e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73354236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 14.alert_handler_csr_mem_rw_with_rand_reset.73354236
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.3089341952
Short name T740
Test name
Test status
Simulation time 444223440 ps
CPU time 8.75 seconds
Started Aug 13 05:45:10 PM PDT 24
Finished Aug 13 05:45:19 PM PDT 24
Peak memory 240748 kb
Host smart-4fe37aed-bf76-4a67-a666-37a96c851385
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3089341952 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.3089341952
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.1676790990
Short name T734
Test name
Test status
Simulation time 15731920 ps
CPU time 1.8 seconds
Started Aug 13 05:45:10 PM PDT 24
Finished Aug 13 05:45:12 PM PDT 24
Peak memory 237816 kb
Host smart-387ba22f-9bb1-4898-af2b-629b03c917b1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1676790990 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.1676790990
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.555901644
Short name T199
Test name
Test status
Simulation time 474479030 ps
CPU time 18.29 seconds
Started Aug 13 05:45:08 PM PDT 24
Finished Aug 13 05:45:26 PM PDT 24
Peak memory 240732 kb
Host smart-41c277c6-9dd1-4b13-a29f-5181a785b4c9
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=555901644 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_out
standing.555901644
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.1693877872
Short name T793
Test name
Test status
Simulation time 147528842 ps
CPU time 10.85 seconds
Started Aug 13 05:45:04 PM PDT 24
Finished Aug 13 05:45:15 PM PDT 24
Peak memory 248968 kb
Host smart-bc789578-e534-4b70-923c-f03f4ae23ff6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1693877872 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.1693877872
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.2680414246
Short name T186
Test name
Test status
Simulation time 142523916 ps
CPU time 5.78 seconds
Started Aug 13 05:45:07 PM PDT 24
Finished Aug 13 05:45:13 PM PDT 24
Peak memory 248964 kb
Host smart-57baa0e1-8890-40df-9c7c-4965e2a5938c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2680414246 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 15.alert_handler_csr_mem_rw_with_rand_reset.2680414246
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.1305102218
Short name T722
Test name
Test status
Simulation time 421454364 ps
CPU time 4.56 seconds
Started Aug 13 05:45:04 PM PDT 24
Finished Aug 13 05:45:09 PM PDT 24
Peak memory 237772 kb
Host smart-6ad977b8-7896-4c45-bb99-167b6113b559
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1305102218 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.1305102218
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.3207392520
Short name T765
Test name
Test status
Simulation time 20312384 ps
CPU time 1.49 seconds
Started Aug 13 05:45:10 PM PDT 24
Finished Aug 13 05:45:11 PM PDT 24
Peak memory 237804 kb
Host smart-f4c1490c-a318-4ce2-8372-fd9ab9c5e837
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3207392520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.3207392520
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.790329107
Short name T781
Test name
Test status
Simulation time 1359677722 ps
CPU time 23.22 seconds
Started Aug 13 05:45:06 PM PDT 24
Finished Aug 13 05:45:30 PM PDT 24
Peak memory 245876 kb
Host smart-b87f283b-4dd9-4d51-b921-b0b7091befe6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=790329107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_out
standing.790329107
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.1916103038
Short name T155
Test name
Test status
Simulation time 16461891009 ps
CPU time 172.43 seconds
Started Aug 13 05:45:09 PM PDT 24
Finished Aug 13 05:48:01 PM PDT 24
Peak memory 265832 kb
Host smart-aa6b900c-309d-4caf-8c8f-a84324dc80c1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1916103038 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_err
ors.1916103038
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.3997121873
Short name T160
Test name
Test status
Simulation time 9680680416 ps
CPU time 637.14 seconds
Started Aug 13 05:45:05 PM PDT 24
Finished Aug 13 05:55:42 PM PDT 24
Peak memory 265900 kb
Host smart-14039b1f-fd97-4065-996b-9b41b2b9aebc
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3997121873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.3997121873
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.1518104722
Short name T238
Test name
Test status
Simulation time 416658639 ps
CPU time 6.58 seconds
Started Aug 13 05:45:06 PM PDT 24
Finished Aug 13 05:45:12 PM PDT 24
Peak memory 250772 kb
Host smart-cd40851b-cdc5-410c-84db-b2c2e020f59d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1518104722 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.1518104722
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.3842387209
Short name T805
Test name
Test status
Simulation time 202048311 ps
CPU time 8.5 seconds
Started Aug 13 05:45:06 PM PDT 24
Finished Aug 13 05:45:14 PM PDT 24
Peak memory 250012 kb
Host smart-1c006064-a80d-45c5-90f8-1d0955077bca
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3842387209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 16.alert_handler_csr_mem_rw_with_rand_reset.3842387209
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.4002881147
Short name T798
Test name
Test status
Simulation time 94753993 ps
CPU time 4.73 seconds
Started Aug 13 05:45:06 PM PDT 24
Finished Aug 13 05:45:11 PM PDT 24
Peak memory 240652 kb
Host smart-35ae2a57-3024-4122-95d3-981a768b07f3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4002881147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.4002881147
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.1010702510
Short name T718
Test name
Test status
Simulation time 10399126 ps
CPU time 1.29 seconds
Started Aug 13 05:45:06 PM PDT 24
Finished Aug 13 05:45:07 PM PDT 24
Peak memory 236908 kb
Host smart-1b39603d-ac6e-4c17-8a3e-175ff591d659
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1010702510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.1010702510
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.3507990014
Short name T771
Test name
Test status
Simulation time 89547038 ps
CPU time 11.47 seconds
Started Aug 13 05:45:05 PM PDT 24
Finished Aug 13 05:45:16 PM PDT 24
Peak memory 245040 kb
Host smart-ede53a73-cbc9-45c6-bb7f-b21141fc5071
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3507990014 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_ou
tstanding.3507990014
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.725824537
Short name T138
Test name
Test status
Simulation time 16628161717 ps
CPU time 767.39 seconds
Started Aug 13 05:45:05 PM PDT 24
Finished Aug 13 05:57:52 PM PDT 24
Peak memory 265620 kb
Host smart-d3220d99-96f3-40ed-b2ed-2cfc63a51385
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=725824537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.725824537
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.1816395081
Short name T820
Test name
Test status
Simulation time 749496549 ps
CPU time 13.95 seconds
Started Aug 13 05:45:05 PM PDT 24
Finished Aug 13 05:45:19 PM PDT 24
Peak memory 248864 kb
Host smart-b5bb7077-a183-4ad2-8bc5-33d573fd8f63
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1816395081 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.1816395081
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.1311440056
Short name T759
Test name
Test status
Simulation time 116382804 ps
CPU time 5.61 seconds
Started Aug 13 05:45:14 PM PDT 24
Finished Aug 13 05:45:19 PM PDT 24
Peak memory 257092 kb
Host smart-09c59013-2086-4afa-94c1-17d0749d3a9b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1311440056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 17.alert_handler_csr_mem_rw_with_rand_reset.1311440056
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.392770167
Short name T230
Test name
Test status
Simulation time 71290051 ps
CPU time 5.54 seconds
Started Aug 13 05:45:10 PM PDT 24
Finished Aug 13 05:45:16 PM PDT 24
Peak memory 237792 kb
Host smart-359a994e-2d77-4ed3-9403-e2e25cf71071
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=392770167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.392770167
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.3010896880
Short name T710
Test name
Test status
Simulation time 8976137 ps
CPU time 1.52 seconds
Started Aug 13 05:45:03 PM PDT 24
Finished Aug 13 05:45:05 PM PDT 24
Peak memory 236856 kb
Host smart-6157549a-47d2-4600-91dc-abaa6a52a170
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3010896880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.3010896880
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.2729431078
Short name T751
Test name
Test status
Simulation time 982258080 ps
CPU time 41.02 seconds
Started Aug 13 05:45:12 PM PDT 24
Finished Aug 13 05:45:53 PM PDT 24
Peak memory 245932 kb
Host smart-a7456f7a-1e46-4dab-9f2a-6c4ebfdcbe14
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2729431078 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_ou
tstanding.2729431078
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.828852921
Short name T156
Test name
Test status
Simulation time 890168480 ps
CPU time 97.42 seconds
Started Aug 13 05:45:05 PM PDT 24
Finished Aug 13 05:46:43 PM PDT 24
Peak memory 257328 kb
Host smart-38bb7724-85dd-4609-a25a-ff6bb3504b16
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=828852921 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_erro
rs.828852921
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.1317322804
Short name T237
Test name
Test status
Simulation time 286375829 ps
CPU time 18.24 seconds
Started Aug 13 05:45:09 PM PDT 24
Finished Aug 13 05:45:28 PM PDT 24
Peak memory 248248 kb
Host smart-8aff6164-edc1-4f61-b225-78593263a486
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1317322804 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.1317322804
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.1886051332
Short name T741
Test name
Test status
Simulation time 1822697033 ps
CPU time 20.81 seconds
Started Aug 13 05:45:08 PM PDT 24
Finished Aug 13 05:45:29 PM PDT 24
Peak memory 237888 kb
Host smart-a1ca30b8-0b33-48c6-ac5e-a4dbbe526d7b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1886051332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.1886051332
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.4172927292
Short name T800
Test name
Test status
Simulation time 1075209552 ps
CPU time 17.14 seconds
Started Aug 13 05:45:20 PM PDT 24
Finished Aug 13 05:45:37 PM PDT 24
Peak memory 250028 kb
Host smart-2d88fe04-5068-43a8-a815-12b27abd870b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4172927292 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 18.alert_handler_csr_mem_rw_with_rand_reset.4172927292
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.1116994416
Short name T802
Test name
Test status
Simulation time 126654516 ps
CPU time 4.96 seconds
Started Aug 13 05:45:13 PM PDT 24
Finished Aug 13 05:45:18 PM PDT 24
Peak memory 236876 kb
Host smart-11bf08c7-7bca-4aab-af7d-a2710f4a4545
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1116994416 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.1116994416
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.300479267
Short name T354
Test name
Test status
Simulation time 13454312 ps
CPU time 1.48 seconds
Started Aug 13 05:45:20 PM PDT 24
Finished Aug 13 05:45:21 PM PDT 24
Peak memory 237804 kb
Host smart-1cfcc360-3b18-428b-b43c-67d2f9b77c08
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=300479267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.300479267
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.352302046
Short name T202
Test name
Test status
Simulation time 556002906 ps
CPU time 20.22 seconds
Started Aug 13 05:45:11 PM PDT 24
Finished Aug 13 05:45:32 PM PDT 24
Peak memory 245052 kb
Host smart-7484df10-fb32-40b6-98d2-2ccb03bc58fb
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=352302046 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_out
standing.352302046
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.3352389891
Short name T143
Test name
Test status
Simulation time 96679577485 ps
CPU time 520.84 seconds
Started Aug 13 05:45:12 PM PDT 24
Finished Aug 13 05:53:53 PM PDT 24
Peak memory 268264 kb
Host smart-25c59d7b-759a-4813-8584-30ee115c8d7a
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3352389891 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.3352389891
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.3379573927
Short name T790
Test name
Test status
Simulation time 57601595 ps
CPU time 8.43 seconds
Started Aug 13 05:45:13 PM PDT 24
Finished Aug 13 05:45:22 PM PDT 24
Peak memory 248996 kb
Host smart-0476e819-c104-4c98-9b31-780a3bc29dfb
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3379573927 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.3379573927
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.3556190061
Short name T782
Test name
Test status
Simulation time 436570968 ps
CPU time 10.97 seconds
Started Aug 13 05:45:14 PM PDT 24
Finished Aug 13 05:45:25 PM PDT 24
Peak memory 252176 kb
Host smart-741d0e12-0779-409d-9b13-dd382f438c89
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3556190061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 19.alert_handler_csr_mem_rw_with_rand_reset.3556190061
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.165295538
Short name T801
Test name
Test status
Simulation time 24138818 ps
CPU time 4.08 seconds
Started Aug 13 05:45:21 PM PDT 24
Finished Aug 13 05:45:25 PM PDT 24
Peak memory 240648 kb
Host smart-a6f82464-e9f2-4d5f-a980-440bbd3a709b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=165295538 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.165295538
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.2369833863
Short name T773
Test name
Test status
Simulation time 7526320 ps
CPU time 1.53 seconds
Started Aug 13 05:45:12 PM PDT 24
Finished Aug 13 05:45:14 PM PDT 24
Peak memory 235816 kb
Host smart-4febe8d1-d345-47df-986d-33788d04a984
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2369833863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.2369833863
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.854329315
Short name T196
Test name
Test status
Simulation time 92084916 ps
CPU time 11.4 seconds
Started Aug 13 05:45:15 PM PDT 24
Finished Aug 13 05:45:26 PM PDT 24
Peak memory 245076 kb
Host smart-0119ead9-bb11-49dd-a85f-f2c6b1885323
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=854329315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_out
standing.854329315
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.531708422
Short name T157
Test name
Test status
Simulation time 63381720385 ps
CPU time 309.69 seconds
Started Aug 13 05:45:12 PM PDT 24
Finished Aug 13 05:50:22 PM PDT 24
Peak memory 272112 kb
Host smart-ceaaa726-0837-4c8c-97f3-1fa174f0f122
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=531708422 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_erro
rs.531708422
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.3393487965
Short name T144
Test name
Test status
Simulation time 69075340455 ps
CPU time 549.74 seconds
Started Aug 13 05:45:14 PM PDT 24
Finished Aug 13 05:54:23 PM PDT 24
Peak memory 265592 kb
Host smart-1a5cc32c-d5fb-43ff-b303-b831090513d2
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3393487965 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.3393487965
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.3680426243
Short name T756
Test name
Test status
Simulation time 713990562 ps
CPU time 11.53 seconds
Started Aug 13 05:45:12 PM PDT 24
Finished Aug 13 05:45:24 PM PDT 24
Peak memory 254708 kb
Host smart-05cffa01-f4e5-4f2d-b60e-e528c609d2e0
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3680426243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.3680426243
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.3027664489
Short name T750
Test name
Test status
Simulation time 4139089819 ps
CPU time 292.7 seconds
Started Aug 13 05:44:55 PM PDT 24
Finished Aug 13 05:49:48 PM PDT 24
Peak memory 241936 kb
Host smart-405c8536-dc6e-4329-b151-211f5011de37
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3027664489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.3027664489
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.2671276376
Short name T745
Test name
Test status
Simulation time 28418434900 ps
CPU time 178.32 seconds
Started Aug 13 05:44:58 PM PDT 24
Finished Aug 13 05:47:57 PM PDT 24
Peak memory 236824 kb
Host smart-16c0c77e-ced7-4b0d-b95a-4d513e062ece
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2671276376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.2671276376
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.3386462203
Short name T736
Test name
Test status
Simulation time 537887965 ps
CPU time 11.28 seconds
Started Aug 13 05:44:54 PM PDT 24
Finished Aug 13 05:45:05 PM PDT 24
Peak memory 240748 kb
Host smart-98602f62-58c7-494c-bb18-02197e3a284d
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3386462203 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.3386462203
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.2650684876
Short name T815
Test name
Test status
Simulation time 392347059 ps
CPU time 7.19 seconds
Started Aug 13 05:44:52 PM PDT 24
Finished Aug 13 05:44:59 PM PDT 24
Peak memory 240068 kb
Host smart-114fcaba-de5c-45d7-b1e5-8bb0db90f254
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2650684876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.alert_handler_csr_mem_rw_with_rand_reset.2650684876
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.1885543894
Short name T812
Test name
Test status
Simulation time 336308746 ps
CPU time 5.2 seconds
Started Aug 13 05:45:00 PM PDT 24
Finished Aug 13 05:45:05 PM PDT 24
Peak memory 236892 kb
Host smart-de920ba4-0df0-4507-ba4b-4be5bb2d88c7
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1885543894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.1885543894
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.151441418
Short name T789
Test name
Test status
Simulation time 6853261 ps
CPU time 1.48 seconds
Started Aug 13 05:45:00 PM PDT 24
Finished Aug 13 05:45:02 PM PDT 24
Peak memory 237808 kb
Host smart-f55b2f90-1b04-4004-a4a3-5c50a623932e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=151441418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.151441418
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.3171013868
Short name T774
Test name
Test status
Simulation time 175668181 ps
CPU time 23.65 seconds
Started Aug 13 05:44:55 PM PDT 24
Finished Aug 13 05:45:19 PM PDT 24
Peak memory 245108 kb
Host smart-79da5cf7-5668-422f-8a70-226d0444681d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3171013868 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_out
standing.3171013868
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.795213976
Short name T130
Test name
Test status
Simulation time 8575699892 ps
CPU time 178.57 seconds
Started Aug 13 05:44:58 PM PDT 24
Finished Aug 13 05:47:57 PM PDT 24
Peak memory 265680 kb
Host smart-bbc58c99-f650-4da5-8570-6f54b15fc397
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=795213976 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_error
s.795213976
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.3099522234
Short name T358
Test name
Test status
Simulation time 15731174936 ps
CPU time 562 seconds
Started Aug 13 05:44:55 PM PDT 24
Finished Aug 13 05:54:17 PM PDT 24
Peak memory 265680 kb
Host smart-d5896feb-d6b8-45e6-a412-4f38fa39c2fc
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3099522234 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.3099522234
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.1689661463
Short name T743
Test name
Test status
Simulation time 37163651 ps
CPU time 6.85 seconds
Started Aug 13 05:44:58 PM PDT 24
Finished Aug 13 05:45:05 PM PDT 24
Peak memory 253524 kb
Host smart-8e167fa5-2ae2-443d-a806-8b4fd5939b1c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1689661463 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.1689661463
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.2709327850
Short name T747
Test name
Test status
Simulation time 12605809 ps
CPU time 1.41 seconds
Started Aug 13 05:45:12 PM PDT 24
Finished Aug 13 05:45:14 PM PDT 24
Peak memory 237752 kb
Host smart-e7198185-701c-49b4-a466-27417689ea9f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2709327850 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.2709327850
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.400313450
Short name T770
Test name
Test status
Simulation time 15684587 ps
CPU time 1.77 seconds
Started Aug 13 05:45:10 PM PDT 24
Finished Aug 13 05:45:12 PM PDT 24
Peak memory 237784 kb
Host smart-cb1b39da-3322-4f22-ab8c-633358c0bab6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=400313450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.400313450
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.83598696
Short name T733
Test name
Test status
Simulation time 8176810 ps
CPU time 1.44 seconds
Started Aug 13 05:45:12 PM PDT 24
Finished Aug 13 05:45:14 PM PDT 24
Peak memory 236924 kb
Host smart-3539e6bd-eb85-48d3-a527-b0e9c8ec1d69
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=83598696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.83598696
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.279298449
Short name T717
Test name
Test status
Simulation time 8621985 ps
CPU time 1.5 seconds
Started Aug 13 05:45:22 PM PDT 24
Finished Aug 13 05:45:23 PM PDT 24
Peak memory 237792 kb
Host smart-27ae117c-2060-4990-901b-42439548da77
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=279298449 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.279298449
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.2772816676
Short name T813
Test name
Test status
Simulation time 17422444 ps
CPU time 1.41 seconds
Started Aug 13 05:45:23 PM PDT 24
Finished Aug 13 05:45:24 PM PDT 24
Peak memory 237788 kb
Host smart-0b02ecd5-0e00-4f40-9184-829b8b2a0239
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2772816676 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.2772816676
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.313180555
Short name T355
Test name
Test status
Simulation time 16166484 ps
CPU time 1.37 seconds
Started Aug 13 05:45:22 PM PDT 24
Finished Aug 13 05:45:23 PM PDT 24
Peak memory 235820 kb
Host smart-bbec9b38-76fd-4077-93f3-51a828def99d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=313180555 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.313180555
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.825692328
Short name T816
Test name
Test status
Simulation time 17595553 ps
CPU time 1.32 seconds
Started Aug 13 05:45:22 PM PDT 24
Finished Aug 13 05:45:23 PM PDT 24
Peak memory 237752 kb
Host smart-3d3a2e16-3bba-4d2c-a96b-53fe391ae1a2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=825692328 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.825692328
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.3809476878
Short name T819
Test name
Test status
Simulation time 16022599 ps
CPU time 1.34 seconds
Started Aug 13 05:45:25 PM PDT 24
Finished Aug 13 05:45:26 PM PDT 24
Peak memory 236928 kb
Host smart-ffe73c51-2312-41fc-a74e-959f59e9e0a7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3809476878 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.3809476878
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.2997468628
Short name T200
Test name
Test status
Simulation time 12288496562 ps
CPU time 182.79 seconds
Started Aug 13 05:45:02 PM PDT 24
Finished Aug 13 05:48:05 PM PDT 24
Peak memory 242212 kb
Host smart-9960821c-3f1a-4e76-af33-2a8cab9fb812
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2997468628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.2997468628
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.3837864805
Short name T731
Test name
Test status
Simulation time 17123053534 ps
CPU time 270.09 seconds
Started Aug 13 05:44:51 PM PDT 24
Finished Aug 13 05:49:21 PM PDT 24
Peak memory 237968 kb
Host smart-89320249-403d-427e-b373-66238ea4bb52
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3837864805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.3837864805
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.291548263
Short name T719
Test name
Test status
Simulation time 207095688 ps
CPU time 9.43 seconds
Started Aug 13 05:45:03 PM PDT 24
Finished Aug 13 05:45:12 PM PDT 24
Peak memory 240984 kb
Host smart-1f892454-bddc-487b-a948-9499cfbab649
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=291548263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.291548263
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.1019587427
Short name T730
Test name
Test status
Simulation time 517080390 ps
CPU time 6.38 seconds
Started Aug 13 05:45:09 PM PDT 24
Finished Aug 13 05:45:16 PM PDT 24
Peak memory 242616 kb
Host smart-e7aedf27-5ca9-43b5-b9b8-9e2e1afe6582
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1019587427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.alert_handler_csr_mem_rw_with_rand_reset.1019587427
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.3059149109
Short name T811
Test name
Test status
Simulation time 93125736 ps
CPU time 5.27 seconds
Started Aug 13 05:45:02 PM PDT 24
Finished Aug 13 05:45:08 PM PDT 24
Peak memory 237780 kb
Host smart-1c4c171d-e024-463a-a784-ac9a1bf6d4f1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3059149109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.3059149109
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.2045085406
Short name T760
Test name
Test status
Simulation time 15916991 ps
CPU time 1.56 seconds
Started Aug 13 05:45:10 PM PDT 24
Finished Aug 13 05:45:11 PM PDT 24
Peak memory 237800 kb
Host smart-01ceb2aa-b184-4a23-bdde-a2b2d063ab20
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2045085406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.2045085406
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.3001384947
Short name T732
Test name
Test status
Simulation time 711292093 ps
CPU time 26.77 seconds
Started Aug 13 05:44:55 PM PDT 24
Finished Aug 13 05:45:22 PM PDT 24
Peak memory 245972 kb
Host smart-a2c416a9-b525-480c-bdd7-34f6a163bb22
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3001384947 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_out
standing.3001384947
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.3905789031
Short name T149
Test name
Test status
Simulation time 902719960 ps
CPU time 99.46 seconds
Started Aug 13 05:44:55 PM PDT 24
Finished Aug 13 05:46:35 PM PDT 24
Peak memory 265452 kb
Host smart-15d5ebbb-f85b-47c5-8497-8385a780d10e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3905789031 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_erro
rs.3905789031
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.3489965175
Short name T821
Test name
Test status
Simulation time 1395455490 ps
CPU time 23.54 seconds
Started Aug 13 05:45:03 PM PDT 24
Finished Aug 13 05:45:26 PM PDT 24
Peak memory 248992 kb
Host smart-969c4b45-08b8-4774-a08e-680913a20ef4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3489965175 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.3489965175
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.757898980
Short name T171
Test name
Test status
Simulation time 15590047 ps
CPU time 1.86 seconds
Started Aug 13 05:45:21 PM PDT 24
Finished Aug 13 05:45:23 PM PDT 24
Peak memory 236892 kb
Host smart-b370a0e1-6807-4638-b63e-1b9bed7f5668
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=757898980 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.757898980
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.3257642168
Short name T763
Test name
Test status
Simulation time 15224112 ps
CPU time 1.8 seconds
Started Aug 13 05:45:20 PM PDT 24
Finished Aug 13 05:45:22 PM PDT 24
Peak memory 237736 kb
Host smart-57715c6f-6075-484f-adec-391835eee9e4
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3257642168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.3257642168
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.1124952824
Short name T724
Test name
Test status
Simulation time 20117629 ps
CPU time 1.4 seconds
Started Aug 13 05:45:22 PM PDT 24
Finished Aug 13 05:45:23 PM PDT 24
Peak memory 237768 kb
Host smart-fc8638df-2c9a-4167-baab-452ca8aad973
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1124952824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.1124952824
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.3070110347
Short name T807
Test name
Test status
Simulation time 20180243 ps
CPU time 1.32 seconds
Started Aug 13 05:45:21 PM PDT 24
Finished Aug 13 05:45:22 PM PDT 24
Peak memory 237804 kb
Host smart-3e47ba17-19de-4b1d-b016-bfcd017ce672
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3070110347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.3070110347
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.1609559881
Short name T776
Test name
Test status
Simulation time 7143615 ps
CPU time 1.49 seconds
Started Aug 13 05:45:24 PM PDT 24
Finished Aug 13 05:45:25 PM PDT 24
Peak memory 236800 kb
Host smart-32f01fc2-3fc0-4730-817e-afa72cb22a52
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1609559881 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.1609559881
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.3378999820
Short name T725
Test name
Test status
Simulation time 6789371 ps
CPU time 1.48 seconds
Started Aug 13 05:45:22 PM PDT 24
Finished Aug 13 05:45:23 PM PDT 24
Peak memory 236724 kb
Host smart-30daf1a8-131f-4c49-8939-0641c2753c97
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3378999820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.3378999820
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.2408566449
Short name T240
Test name
Test status
Simulation time 7923556 ps
CPU time 1.51 seconds
Started Aug 13 05:45:18 PM PDT 24
Finished Aug 13 05:45:20 PM PDT 24
Peak memory 235784 kb
Host smart-7c1fa2e7-8395-4649-af8f-96e8ec334558
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2408566449 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.2408566449
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.1246026328
Short name T794
Test name
Test status
Simulation time 10293914 ps
CPU time 1.67 seconds
Started Aug 13 05:45:22 PM PDT 24
Finished Aug 13 05:45:24 PM PDT 24
Peak memory 237804 kb
Host smart-a11a192a-c8f2-4615-ba4f-d5be92524244
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1246026328 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.1246026328
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.898896369
Short name T352
Test name
Test status
Simulation time 11738293 ps
CPU time 1.35 seconds
Started Aug 13 05:45:20 PM PDT 24
Finished Aug 13 05:45:22 PM PDT 24
Peak memory 236908 kb
Host smart-cf468086-42de-498a-9ba9-93e1e7d193cb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=898896369 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.898896369
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.1029875512
Short name T712
Test name
Test status
Simulation time 9864599 ps
CPU time 1.34 seconds
Started Aug 13 05:45:18 PM PDT 24
Finished Aug 13 05:45:20 PM PDT 24
Peak memory 236908 kb
Host smart-0e00f201-7ce4-494a-ac91-e271883c113e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1029875512 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.1029875512
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.1031349601
Short name T818
Test name
Test status
Simulation time 3352185022 ps
CPU time 114.3 seconds
Started Aug 13 05:44:51 PM PDT 24
Finished Aug 13 05:46:46 PM PDT 24
Peak memory 240736 kb
Host smart-2cd852dd-7d71-49c1-b678-1bfc1515a50a
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1031349601 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.1031349601
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.1198343617
Short name T788
Test name
Test status
Simulation time 22792652639 ps
CPU time 409.07 seconds
Started Aug 13 05:44:54 PM PDT 24
Finished Aug 13 05:51:43 PM PDT 24
Peak memory 237844 kb
Host smart-328b8ea5-164b-4d55-afcf-22c87b12503f
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1198343617 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.1198343617
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.1038041743
Short name T780
Test name
Test status
Simulation time 1099992565 ps
CPU time 10.53 seconds
Started Aug 13 05:44:59 PM PDT 24
Finished Aug 13 05:45:09 PM PDT 24
Peak memory 249364 kb
Host smart-6add0c81-2375-468d-ad99-aea701859438
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1038041743 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.1038041743
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.1040938036
Short name T356
Test name
Test status
Simulation time 306980202 ps
CPU time 12.53 seconds
Started Aug 13 05:45:09 PM PDT 24
Finished Aug 13 05:45:21 PM PDT 24
Peak memory 256536 kb
Host smart-88c38383-5014-4a2d-9eef-6565dc8d071f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1040938036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.alert_handler_csr_mem_rw_with_rand_reset.1040938036
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.1010794039
Short name T808
Test name
Test status
Simulation time 230151526 ps
CPU time 6.38 seconds
Started Aug 13 05:45:09 PM PDT 24
Finished Aug 13 05:45:16 PM PDT 24
Peak memory 237776 kb
Host smart-fc6973df-bf82-4552-b070-f6a59c4c758f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1010794039 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.1010794039
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.1334686767
Short name T746
Test name
Test status
Simulation time 41143983 ps
CPU time 1.39 seconds
Started Aug 13 05:45:09 PM PDT 24
Finished Aug 13 05:45:11 PM PDT 24
Peak memory 237664 kb
Host smart-1d99056c-b1c9-4311-b0e5-fd85dc3ae7ab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1334686767 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.1334686767
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.1856961672
Short name T239
Test name
Test status
Simulation time 347587963 ps
CPU time 21.63 seconds
Started Aug 13 05:45:10 PM PDT 24
Finished Aug 13 05:45:31 PM PDT 24
Peak memory 245984 kb
Host smart-2ef8a08e-a677-4b41-a6d6-19209bcf5520
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1856961672 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_out
standing.1856961672
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.2324499802
Short name T141
Test name
Test status
Simulation time 8183342095 ps
CPU time 143.33 seconds
Started Aug 13 05:45:10 PM PDT 24
Finished Aug 13 05:47:33 PM PDT 24
Peak memory 265692 kb
Host smart-f12b31d2-fd59-4501-873f-5e6043a5101b
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2324499802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_erro
rs.2324499802
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.1423799697
Short name T792
Test name
Test status
Simulation time 542403258 ps
CPU time 6.36 seconds
Started Aug 13 05:45:09 PM PDT 24
Finished Aug 13 05:45:16 PM PDT 24
Peak memory 248988 kb
Host smart-88f2031a-5700-4fd8-abbf-19be2fa9777e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1423799697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.1423799697
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.524505185
Short name T353
Test name
Test status
Simulation time 23801021 ps
CPU time 1.51 seconds
Started Aug 13 05:45:23 PM PDT 24
Finished Aug 13 05:45:24 PM PDT 24
Peak memory 237788 kb
Host smart-0f450630-92c3-4a42-8464-5b2e76f053a3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=524505185 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.524505185
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.2212183268
Short name T817
Test name
Test status
Simulation time 11079538 ps
CPU time 1.73 seconds
Started Aug 13 05:45:19 PM PDT 24
Finished Aug 13 05:45:21 PM PDT 24
Peak memory 237792 kb
Host smart-94801484-cea5-450d-b6ff-3a1fd831dfea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2212183268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.2212183268
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.3567659485
Short name T775
Test name
Test status
Simulation time 6497952 ps
CPU time 1.52 seconds
Started Aug 13 05:45:23 PM PDT 24
Finished Aug 13 05:45:25 PM PDT 24
Peak memory 235788 kb
Host smart-fedb3105-7542-41bf-acc2-815736538367
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3567659485 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.3567659485
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.3220289481
Short name T716
Test name
Test status
Simulation time 10089160 ps
CPU time 1.55 seconds
Started Aug 13 05:45:20 PM PDT 24
Finished Aug 13 05:45:22 PM PDT 24
Peak memory 237792 kb
Host smart-84a8cf3e-9581-4135-aefe-8936de931819
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3220289481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.3220289481
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.1129620865
Short name T720
Test name
Test status
Simulation time 11518357 ps
CPU time 1.53 seconds
Started Aug 13 05:45:21 PM PDT 24
Finished Aug 13 05:45:22 PM PDT 24
Peak memory 236804 kb
Host smart-b6c426ea-a880-4bfa-a992-52a7200b176e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1129620865 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.1129620865
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.3857530587
Short name T172
Test name
Test status
Simulation time 8184048 ps
CPU time 1.52 seconds
Started Aug 13 05:45:21 PM PDT 24
Finished Aug 13 05:45:22 PM PDT 24
Peak memory 236928 kb
Host smart-47a2873e-6837-4de4-b7c8-39d6979adabd
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3857530587 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.3857530587
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.3115401889
Short name T778
Test name
Test status
Simulation time 6746945 ps
CPU time 1.52 seconds
Started Aug 13 05:45:21 PM PDT 24
Finished Aug 13 05:45:22 PM PDT 24
Peak memory 236832 kb
Host smart-7a0b1fb2-f982-4f53-80f6-94d41519f91e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3115401889 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.3115401889
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.105122772
Short name T714
Test name
Test status
Simulation time 17884887 ps
CPU time 1.54 seconds
Started Aug 13 05:45:20 PM PDT 24
Finished Aug 13 05:45:22 PM PDT 24
Peak memory 237776 kb
Host smart-23a481f4-fcd0-4a80-8be8-e22a54c8f651
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=105122772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.105122772
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.2499207737
Short name T241
Test name
Test status
Simulation time 10957848 ps
CPU time 1.42 seconds
Started Aug 13 05:45:21 PM PDT 24
Finished Aug 13 05:45:23 PM PDT 24
Peak memory 235820 kb
Host smart-3964f5f6-5dc8-456d-9d11-b1682b49bda8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2499207737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.2499207737
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.1028272009
Short name T350
Test name
Test status
Simulation time 15422917 ps
CPU time 1.24 seconds
Started Aug 13 05:45:28 PM PDT 24
Finished Aug 13 05:45:30 PM PDT 24
Peak memory 236908 kb
Host smart-5be5672f-efd3-4a57-ba72-0573503bbe11
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1028272009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.1028272009
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.1362328778
Short name T721
Test name
Test status
Simulation time 309695109 ps
CPU time 7.53 seconds
Started Aug 13 05:45:09 PM PDT 24
Finished Aug 13 05:45:16 PM PDT 24
Peak memory 241076 kb
Host smart-6cf5afe0-f8f1-4898-908b-2a7e625967bd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1362328778 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 5.alert_handler_csr_mem_rw_with_rand_reset.1362328778
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.2129624555
Short name T726
Test name
Test status
Simulation time 348441699 ps
CPU time 9.4 seconds
Started Aug 13 05:44:59 PM PDT 24
Finished Aug 13 05:45:09 PM PDT 24
Peak memory 237784 kb
Host smart-4df3774b-9823-494f-8f09-d2d7203df6d9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2129624555 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.2129624555
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.2737790222
Short name T791
Test name
Test status
Simulation time 20413595 ps
CPU time 1.32 seconds
Started Aug 13 05:44:57 PM PDT 24
Finished Aug 13 05:44:59 PM PDT 24
Peak memory 237668 kb
Host smart-bd5307d6-21ac-45bd-a2ba-40f18be569bf
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2737790222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.2737790222
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.2248473082
Short name T198
Test name
Test status
Simulation time 89723922 ps
CPU time 11.28 seconds
Started Aug 13 05:44:54 PM PDT 24
Finished Aug 13 05:45:05 PM PDT 24
Peak memory 245092 kb
Host smart-12830e0e-1cf3-48d9-8603-1fb18d5be16a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2248473082 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_out
standing.2248473082
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.3087345558
Short name T154
Test name
Test status
Simulation time 59350420102 ps
CPU time 661.53 seconds
Started Aug 13 05:44:54 PM PDT 24
Finished Aug 13 05:55:56 PM PDT 24
Peak memory 272236 kb
Host smart-ce6d5eee-df31-4298-903a-58662619034e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3087345558 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.3087345558
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.3903380436
Short name T822
Test name
Test status
Simulation time 752987699 ps
CPU time 23.9 seconds
Started Aug 13 05:44:53 PM PDT 24
Finished Aug 13 05:45:17 PM PDT 24
Peak memory 248080 kb
Host smart-47cbe692-3c1d-4a2b-8f0f-d40565bd18a9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3903380436 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.3903380436
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.2883424316
Short name T824
Test name
Test status
Simulation time 405947304 ps
CPU time 8.71 seconds
Started Aug 13 05:44:59 PM PDT 24
Finished Aug 13 05:45:08 PM PDT 24
Peak memory 251584 kb
Host smart-5b855526-b7cc-43d6-915f-9763e7e05fd9
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2883424316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.alert_handler_csr_mem_rw_with_rand_reset.2883424316
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.2544870130
Short name T727
Test name
Test status
Simulation time 34679090 ps
CPU time 3.71 seconds
Started Aug 13 05:44:59 PM PDT 24
Finished Aug 13 05:45:03 PM PDT 24
Peak memory 237732 kb
Host smart-fa871eb1-a035-41ac-92da-c1c88262fafc
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2544870130 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.2544870130
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.3167433723
Short name T804
Test name
Test status
Simulation time 6272765 ps
CPU time 1.38 seconds
Started Aug 13 05:44:57 PM PDT 24
Finished Aug 13 05:44:58 PM PDT 24
Peak memory 237804 kb
Host smart-ff702ef1-5100-434e-bd73-fb00e8812dd9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3167433723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.3167433723
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.1062092978
Short name T797
Test name
Test status
Simulation time 167558958 ps
CPU time 10.17 seconds
Started Aug 13 05:44:58 PM PDT 24
Finished Aug 13 05:45:09 PM PDT 24
Peak memory 245104 kb
Host smart-8035c6e2-1e20-404f-a055-9e905196262a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1062092978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_out
standing.1062092978
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.618591638
Short name T151
Test name
Test status
Simulation time 8395295736 ps
CPU time 144.51 seconds
Started Aug 13 05:44:57 PM PDT 24
Finished Aug 13 05:47:22 PM PDT 24
Peak memory 267668 kb
Host smart-0ff41214-a22f-433a-a470-a3f6429b6fce
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=618591638 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_error
s.618591638
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.727454564
Short name T769
Test name
Test status
Simulation time 938827743 ps
CPU time 18.05 seconds
Started Aug 13 05:45:01 PM PDT 24
Finished Aug 13 05:45:19 PM PDT 24
Peak memory 249004 kb
Host smart-2a82169a-12b2-4a6e-97a9-372e5327e63a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=727454564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.727454564
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.3420236113
Short name T755
Test name
Test status
Simulation time 525488211 ps
CPU time 10.06 seconds
Started Aug 13 05:44:58 PM PDT 24
Finished Aug 13 05:45:08 PM PDT 24
Peak memory 240424 kb
Host smart-491fa8a2-d3dd-49d7-a042-bfe6b36cbd12
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3420236113 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 7.alert_handler_csr_mem_rw_with_rand_reset.3420236113
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.4210294589
Short name T723
Test name
Test status
Simulation time 19733767 ps
CPU time 3.73 seconds
Started Aug 13 05:45:22 PM PDT 24
Finished Aug 13 05:45:26 PM PDT 24
Peak memory 240620 kb
Host smart-7846d616-b863-4572-bc19-186750ec40ff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4210294589 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.4210294589
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.2491823454
Short name T767
Test name
Test status
Simulation time 18732508 ps
CPU time 1.33 seconds
Started Aug 13 05:44:57 PM PDT 24
Finished Aug 13 05:44:59 PM PDT 24
Peak memory 237564 kb
Host smart-fe652177-e338-47c0-b4a7-e83479632e8a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2491823454 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.2491823454
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.1941544033
Short name T799
Test name
Test status
Simulation time 311796609 ps
CPU time 14.93 seconds
Started Aug 13 05:45:08 PM PDT 24
Finished Aug 13 05:45:24 PM PDT 24
Peak memory 245952 kb
Host smart-aea1ebb1-248e-463a-9ea1-ac48fd4a4a8f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1941544033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_out
standing.1941544033
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.1817866978
Short name T711
Test name
Test status
Simulation time 66615283 ps
CPU time 6.55 seconds
Started Aug 13 05:45:05 PM PDT 24
Finished Aug 13 05:45:11 PM PDT 24
Peak memory 249004 kb
Host smart-8709986f-74ac-46b7-81ec-957698cede8b
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1817866978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.1817866978
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.3039724805
Short name T768
Test name
Test status
Simulation time 62046907 ps
CPU time 2.81 seconds
Started Aug 13 05:44:59 PM PDT 24
Finished Aug 13 05:45:02 PM PDT 24
Peak memory 237764 kb
Host smart-55930475-71b8-4f5e-b68c-d298d38ed123
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3039724805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.3039724805
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.1331682781
Short name T823
Test name
Test status
Simulation time 145205224 ps
CPU time 6.59 seconds
Started Aug 13 05:44:59 PM PDT 24
Finished Aug 13 05:45:06 PM PDT 24
Peak memory 256764 kb
Host smart-e297ffbc-0b76-4918-a553-c05b48a500d7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1331682781 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.alert_handler_csr_mem_rw_with_rand_reset.1331682781
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.2950611634
Short name T809
Test name
Test status
Simulation time 129169868 ps
CPU time 9.38 seconds
Started Aug 13 05:44:57 PM PDT 24
Finished Aug 13 05:45:07 PM PDT 24
Peak memory 237768 kb
Host smart-974e5487-3789-4ed1-8602-aba4dca5ced1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2950611634 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.2950611634
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.3698069330
Short name T783
Test name
Test status
Simulation time 9724680 ps
CPU time 1.58 seconds
Started Aug 13 05:45:00 PM PDT 24
Finished Aug 13 05:45:01 PM PDT 24
Peak memory 236804 kb
Host smart-6fe1b08a-6bdf-4879-8f82-478d61486dc2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3698069330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.3698069330
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.4192107290
Short name T737
Test name
Test status
Simulation time 1046658898 ps
CPU time 35.09 seconds
Started Aug 13 05:45:09 PM PDT 24
Finished Aug 13 05:45:44 PM PDT 24
Peak memory 248892 kb
Host smart-614453bf-650e-4a95-80e2-63492fa445c7
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4192107290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_out
standing.4192107290
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.1719189215
Short name T153
Test name
Test status
Simulation time 7717605356 ps
CPU time 157.76 seconds
Started Aug 13 05:45:12 PM PDT 24
Finished Aug 13 05:47:50 PM PDT 24
Peak memory 265020 kb
Host smart-f20b3354-c348-4b59-8379-04f803bbeb33
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1719189215 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_erro
rs.1719189215
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.1586030489
Short name T161
Test name
Test status
Simulation time 29073182781 ps
CPU time 1110.82 seconds
Started Aug 13 05:44:56 PM PDT 24
Finished Aug 13 06:03:27 PM PDT 24
Peak memory 265652 kb
Host smart-b294983a-5811-414b-82b2-0516bd64d622
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586030489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.1586030489
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.1189023867
Short name T758
Test name
Test status
Simulation time 42060891 ps
CPU time 5.51 seconds
Started Aug 13 05:44:57 PM PDT 24
Finished Aug 13 05:45:03 PM PDT 24
Peak memory 253344 kb
Host smart-4f46aff8-2fcd-439f-b882-997c514bfded
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1189023867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.1189023867
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.185787323
Short name T739
Test name
Test status
Simulation time 56104172 ps
CPU time 4.93 seconds
Started Aug 13 05:44:59 PM PDT 24
Finished Aug 13 05:45:04 PM PDT 24
Peak memory 240388 kb
Host smart-1b121aa1-a668-4a41-af46-bed6ab92dc39
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=185787323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 9.alert_handler_csr_mem_rw_with_rand_reset.185787323
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.1061258115
Short name T784
Test name
Test status
Simulation time 68377178 ps
CPU time 6.76 seconds
Started Aug 13 05:45:06 PM PDT 24
Finished Aug 13 05:45:13 PM PDT 24
Peak memory 240744 kb
Host smart-f8ae40bc-1ed9-49e7-9d3a-805a05997b98
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1061258115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.1061258115
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.2675774936
Short name T761
Test name
Test status
Simulation time 12590545 ps
CPU time 1.45 seconds
Started Aug 13 05:45:09 PM PDT 24
Finished Aug 13 05:45:10 PM PDT 24
Peak memory 236932 kb
Host smart-b1e70980-fcd7-44c6-a1d5-56b8b635994f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2675774936 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.2675774936
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.1084609746
Short name T744
Test name
Test status
Simulation time 751637607 ps
CPU time 20.7 seconds
Started Aug 13 05:45:08 PM PDT 24
Finished Aug 13 05:45:29 PM PDT 24
Peak memory 245068 kb
Host smart-d20c7a8c-1e8f-4562-a01c-a11530c1a8aa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1084609746 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_out
standing.1084609746
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.955991387
Short name T164
Test name
Test status
Simulation time 3519569345 ps
CPU time 141.47 seconds
Started Aug 13 05:44:58 PM PDT 24
Finished Aug 13 05:47:20 PM PDT 24
Peak memory 257484 kb
Host smart-a1843e32-353e-4a09-bceb-082adcb6bc02
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=955991387 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_error
s.955991387
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.2632784217
Short name T357
Test name
Test status
Simulation time 17298650747 ps
CPU time 1241.95 seconds
Started Aug 13 05:44:59 PM PDT 24
Finished Aug 13 06:05:42 PM PDT 24
Peak memory 265660 kb
Host smart-3e32eec1-a065-440f-8a87-036775f85bce
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2632784217 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.2632784217
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.2877752559
Short name T713
Test name
Test status
Simulation time 575750730 ps
CPU time 10.09 seconds
Started Aug 13 05:45:05 PM PDT 24
Finished Aug 13 05:45:15 PM PDT 24
Peak memory 249004 kb
Host smart-f7da74b3-e1d5-4090-b7a1-ff2d8a1cf559
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2877752559 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.2877752559
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.274158877
Short name T39
Test name
Test status
Simulation time 12698278840 ps
CPU time 1417.07 seconds
Started Aug 13 05:45:31 PM PDT 24
Finished Aug 13 06:09:08 PM PDT 24
Peak memory 289448 kb
Host smart-70c155a9-af49-4feb-9db9-c47324fd3bc6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=274158877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.274158877
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.2358348733
Short name T679
Test name
Test status
Simulation time 323589634 ps
CPU time 15.85 seconds
Started Aug 13 05:45:32 PM PDT 24
Finished Aug 13 05:45:48 PM PDT 24
Peak memory 248692 kb
Host smart-fe776b59-03ab-4f89-8d89-a88c4783f7e8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2358348733 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.2358348733
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.1520501993
Short name T673
Test name
Test status
Simulation time 2644128100 ps
CPU time 163.79 seconds
Started Aug 13 05:45:21 PM PDT 24
Finished Aug 13 05:48:05 PM PDT 24
Peak memory 257108 kb
Host smart-da1ab0cd-59c6-4188-9cbe-e3745be38764
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15205
01993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.1520501993
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.1021442186
Short name T84
Test name
Test status
Simulation time 1993880041 ps
CPU time 58.28 seconds
Started Aug 13 05:45:21 PM PDT 24
Finished Aug 13 05:46:19 PM PDT 24
Peak memory 248620 kb
Host smart-9388fde3-4e7d-49a1-9824-8dba79ba0836
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10214
42186 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.1021442186
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.2975056712
Short name T701
Test name
Test status
Simulation time 107498450727 ps
CPU time 1648.33 seconds
Started Aug 13 05:45:27 PM PDT 24
Finished Aug 13 06:12:56 PM PDT 24
Peak memory 272988 kb
Host smart-679cd143-2cfc-478e-a133-9a342b211204
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2975056712 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.2975056712
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.3366124152
Short name T585
Test name
Test status
Simulation time 16341149268 ps
CPU time 1345.36 seconds
Started Aug 13 05:45:31 PM PDT 24
Finished Aug 13 06:07:57 PM PDT 24
Peak memory 287096 kb
Host smart-f6b66d41-12ef-4a12-869e-9fa1b7c51181
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3366124152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.3366124152
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.432315408
Short name T308
Test name
Test status
Simulation time 25162226106 ps
CPU time 298.63 seconds
Started Aug 13 05:45:30 PM PDT 24
Finished Aug 13 05:50:28 PM PDT 24
Peak memory 248664 kb
Host smart-6668bd4b-dcba-41a2-a1e2-532c32c70b8c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=432315408 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.432315408
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.471824487
Short name T46
Test name
Test status
Simulation time 2373468014 ps
CPU time 30.43 seconds
Started Aug 13 05:45:20 PM PDT 24
Finished Aug 13 05:45:51 PM PDT 24
Peak memory 256424 kb
Host smart-c6f2948f-c95a-4694-b333-5af3d778be7e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47182
4487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.471824487
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.2861868991
Short name T93
Test name
Test status
Simulation time 371470345 ps
CPU time 36.7 seconds
Started Aug 13 05:45:22 PM PDT 24
Finished Aug 13 05:45:58 PM PDT 24
Peak memory 248336 kb
Host smart-ac8a92a0-41dc-4d46-a817-a15670defb04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28618
68991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.2861868991
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.676978647
Short name T11
Test name
Test status
Simulation time 347121709 ps
CPU time 12.19 seconds
Started Aug 13 05:45:29 PM PDT 24
Finished Aug 13 05:45:41 PM PDT 24
Peak memory 271276 kb
Host smart-98baedbb-4f6e-4261-ad5b-24606d08e845
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=676978647 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.676978647
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.444054186
Short name T264
Test name
Test status
Simulation time 682072832 ps
CPU time 21.8 seconds
Started Aug 13 05:45:29 PM PDT 24
Finished Aug 13 05:45:51 PM PDT 24
Peak memory 255500 kb
Host smart-1a4bd423-e0bc-4474-84a1-5e75eaf6b8b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44405
4186 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.444054186
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.290257647
Short name T508
Test name
Test status
Simulation time 371577292 ps
CPU time 35.16 seconds
Started Aug 13 05:45:21 PM PDT 24
Finished Aug 13 05:45:56 PM PDT 24
Peak memory 256936 kb
Host smart-e7c42c2c-2272-4165-bd83-42051f70849d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29025
7647 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.290257647
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all_with_rand_reset.861249713
Short name T94
Test name
Test status
Simulation time 27521919231 ps
CPU time 285.21 seconds
Started Aug 13 05:45:29 PM PDT 24
Finished Aug 13 05:50:14 PM PDT 24
Peak memory 273588 kb
Host smart-b1edd9e9-bb31-4c17-a915-5edbb6196fa8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=861249713 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 0.alert_handler_stress_all_with_rand_reset.861249713
Directory /workspace/0.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.291045319
Short name T66
Test name
Test status
Simulation time 22795281373 ps
CPU time 1630.75 seconds
Started Aug 13 05:45:31 PM PDT 24
Finished Aug 13 06:12:42 PM PDT 24
Peak memory 281620 kb
Host smart-851e725e-cf18-4626-bd48-2c114c998cd8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=291045319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.291045319
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.3234389627
Short name T224
Test name
Test status
Simulation time 1752036551 ps
CPU time 35.82 seconds
Started Aug 13 05:45:29 PM PDT 24
Finished Aug 13 05:46:05 PM PDT 24
Peak memory 248796 kb
Host smart-8682b089-e2f9-4e54-9115-9d9cfd3e5f0c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3234389627 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.3234389627
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.4000640700
Short name T366
Test name
Test status
Simulation time 3318144305 ps
CPU time 50.04 seconds
Started Aug 13 05:45:32 PM PDT 24
Finished Aug 13 05:46:22 PM PDT 24
Peak memory 255948 kb
Host smart-917ed8a7-19a0-477f-a374-6c4532955673
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40006
40700 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.4000640700
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.666351200
Short name T598
Test name
Test status
Simulation time 227683505 ps
CPU time 5.31 seconds
Started Aug 13 05:45:32 PM PDT 24
Finished Aug 13 05:45:37 PM PDT 24
Peak memory 240584 kb
Host smart-06a8272c-f6c5-42a5-955c-8c12b5a489d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=66635
1200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.666351200
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.337423846
Short name T225
Test name
Test status
Simulation time 15624040444 ps
CPU time 1099.7 seconds
Started Aug 13 05:45:26 PM PDT 24
Finished Aug 13 06:03:46 PM PDT 24
Peak memory 289880 kb
Host smart-533dc79c-1888-43ba-ada0-7671451998ef
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=337423846 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.337423846
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.338210377
Short name T450
Test name
Test status
Simulation time 31986971359 ps
CPU time 1928.33 seconds
Started Aug 13 05:45:32 PM PDT 24
Finished Aug 13 06:17:41 PM PDT 24
Peak memory 273016 kb
Host smart-a4e3c58c-a208-47c9-9ee1-77cb223c7dcc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338210377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.338210377
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.39757089
Short name T331
Test name
Test status
Simulation time 46758069822 ps
CPU time 359.01 seconds
Started Aug 13 05:45:30 PM PDT 24
Finished Aug 13 05:51:29 PM PDT 24
Peak memory 247896 kb
Host smart-cde2a725-edb2-4f12-ac8b-36c9ace0cbde
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=39757089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.39757089
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.3183369677
Short name T47
Test name
Test status
Simulation time 2301412233 ps
CPU time 36.33 seconds
Started Aug 13 05:45:31 PM PDT 24
Finished Aug 13 05:46:07 PM PDT 24
Peak memory 248816 kb
Host smart-4cc5d573-ac74-497e-bed4-05a856b3f8c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31833
69677 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.3183369677
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.1649922884
Short name T50
Test name
Test status
Simulation time 567615489 ps
CPU time 14.46 seconds
Started Aug 13 05:45:30 PM PDT 24
Finished Aug 13 05:45:45 PM PDT 24
Peak memory 248472 kb
Host smart-ecc7d417-c367-4005-bd00-393ad25a5354
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16499
22884 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.1649922884
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.1971597508
Short name T10
Test name
Test status
Simulation time 1207326011 ps
CPU time 51.32 seconds
Started Aug 13 05:45:29 PM PDT 24
Finished Aug 13 05:46:21 PM PDT 24
Peak memory 270128 kb
Host smart-2f8aa032-3222-407b-95fc-137bef4e8473
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1971597508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.1971597508
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.325241145
Short name T519
Test name
Test status
Simulation time 865399142 ps
CPU time 10.71 seconds
Started Aug 13 05:45:27 PM PDT 24
Finished Aug 13 05:45:38 PM PDT 24
Peak memory 248320 kb
Host smart-d1f96192-1552-488b-ac18-34472a2ba8ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32524
1145 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.325241145
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.2142118557
Short name T565
Test name
Test status
Simulation time 195922481 ps
CPU time 11.94 seconds
Started Aug 13 05:45:48 PM PDT 24
Finished Aug 13 05:46:00 PM PDT 24
Peak memory 248796 kb
Host smart-ee05e79b-4b05-486e-a3ef-619952805c66
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2142118557 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.2142118557
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.3036651032
Short name T675
Test name
Test status
Simulation time 1684178453 ps
CPU time 74.19 seconds
Started Aug 13 05:45:46 PM PDT 24
Finished Aug 13 05:47:00 PM PDT 24
Peak memory 256624 kb
Host smart-fd82261b-99cb-4815-aadc-f7378682f755
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30366
51032 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.3036651032
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.803555038
Short name T534
Test name
Test status
Simulation time 1460463070 ps
CPU time 28.22 seconds
Started Aug 13 05:45:53 PM PDT 24
Finished Aug 13 05:46:21 PM PDT 24
Peak memory 248428 kb
Host smart-ce9cbb90-fafe-490c-b94c-e8f6b96d2913
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80355
5038 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.803555038
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.3167549567
Short name T269
Test name
Test status
Simulation time 12395439524 ps
CPU time 1214.6 seconds
Started Aug 13 05:45:49 PM PDT 24
Finished Aug 13 06:06:04 PM PDT 24
Peak memory 283044 kb
Host smart-f6b91868-8333-476d-8dab-f50338defb45
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3167549567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.3167549567
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.2146617355
Short name T96
Test name
Test status
Simulation time 61527070518 ps
CPU time 1460.3 seconds
Started Aug 13 05:45:47 PM PDT 24
Finished Aug 13 06:10:08 PM PDT 24
Peak memory 281644 kb
Host smart-1dc36bd0-f2e1-4d8b-b004-9e4a4dd510e5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2146617355 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.2146617355
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.3671737256
Short name T602
Test name
Test status
Simulation time 24409537625 ps
CPU time 265.34 seconds
Started Aug 13 05:45:55 PM PDT 24
Finished Aug 13 05:50:21 PM PDT 24
Peak memory 248868 kb
Host smart-1892fabb-34ff-4ddb-a44d-a5dc4b0366d1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3671737256 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.3671737256
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.3358377065
Short name T456
Test name
Test status
Simulation time 1871600455 ps
CPU time 67.76 seconds
Started Aug 13 05:45:48 PM PDT 24
Finished Aug 13 05:46:56 PM PDT 24
Peak memory 256260 kb
Host smart-03240213-0773-410a-a50c-2b6a26ca684d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33583
77065 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.3358377065
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.3214586999
Short name T19
Test name
Test status
Simulation time 1648236509 ps
CPU time 53.82 seconds
Started Aug 13 05:45:53 PM PDT 24
Finished Aug 13 05:46:47 PM PDT 24
Peak memory 248624 kb
Host smart-7b9cc490-8233-40ea-9016-13c40c3cca22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32145
86999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.3214586999
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.3665050417
Short name T573
Test name
Test status
Simulation time 1104234735 ps
CPU time 22.77 seconds
Started Aug 13 05:45:52 PM PDT 24
Finished Aug 13 05:46:15 PM PDT 24
Peak memory 256544 kb
Host smart-54039225-c36c-4a72-aa9e-eee58103792c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36650
50417 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.3665050417
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.3305862133
Short name T705
Test name
Test status
Simulation time 672562699 ps
CPU time 31.85 seconds
Started Aug 13 05:45:50 PM PDT 24
Finished Aug 13 05:46:22 PM PDT 24
Peak memory 256564 kb
Host smart-ce483970-558c-4997-85d2-02ddad551396
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33058
62133 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.3305862133
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.4128539218
Short name T253
Test name
Test status
Simulation time 9300708509 ps
CPU time 586.9 seconds
Started Aug 13 05:45:53 PM PDT 24
Finished Aug 13 05:55:40 PM PDT 24
Peak memory 265140 kb
Host smart-70b9f4ab-392c-473c-95eb-b7f0a5b2e638
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4128539218 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_ha
ndler_stress_all.4128539218
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.2753104593
Short name T216
Test name
Test status
Simulation time 61195079 ps
CPU time 3.6 seconds
Started Aug 13 05:45:54 PM PDT 24
Finished Aug 13 05:45:58 PM PDT 24
Peak memory 248996 kb
Host smart-bd6c33b6-4aa5-4082-b1c5-3397566f3921
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2753104593 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.2753104593
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.2052173452
Short name T706
Test name
Test status
Simulation time 183968874581 ps
CPU time 1045.64 seconds
Started Aug 13 05:45:46 PM PDT 24
Finished Aug 13 06:03:12 PM PDT 24
Peak memory 265296 kb
Host smart-c1a2e08e-4b2a-470a-bf5f-4d5b82ff7a50
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2052173452 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.2052173452
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.2778441134
Short name T220
Test name
Test status
Simulation time 698566475 ps
CPU time 9.34 seconds
Started Aug 13 05:45:53 PM PDT 24
Finished Aug 13 05:46:03 PM PDT 24
Peak memory 248728 kb
Host smart-de76f50d-bd94-425e-adba-86baa977d1a4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2778441134 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.2778441134
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.876341777
Short name T535
Test name
Test status
Simulation time 1345506703 ps
CPU time 124.18 seconds
Started Aug 13 05:45:47 PM PDT 24
Finished Aug 13 05:47:52 PM PDT 24
Peak memory 256988 kb
Host smart-2600c63d-b786-474f-bfcc-6ed97b1dc8d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87634
1777 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.876341777
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.2671424259
Short name T466
Test name
Test status
Simulation time 672550491 ps
CPU time 29.32 seconds
Started Aug 13 05:45:48 PM PDT 24
Finished Aug 13 05:46:17 PM PDT 24
Peak memory 256544 kb
Host smart-eba78943-db92-47bc-b319-20d57391e10f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26714
24259 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.2671424259
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.3186813839
Short name T405
Test name
Test status
Simulation time 21489258655 ps
CPU time 1463.9 seconds
Started Aug 13 05:45:47 PM PDT 24
Finished Aug 13 06:10:12 PM PDT 24
Peak memory 273148 kb
Host smart-376f7f2d-37d0-4a45-9b76-fcdeef45bac9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3186813839 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.3186813839
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.479228975
Short name T319
Test name
Test status
Simulation time 21314858535 ps
CPU time 178.56 seconds
Started Aug 13 05:45:43 PM PDT 24
Finished Aug 13 05:48:42 PM PDT 24
Peak memory 248884 kb
Host smart-d6a8ebd1-d46b-40a8-94cb-5be189e1b883
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=479228975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.479228975
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.1085002310
Short name T381
Test name
Test status
Simulation time 391839512 ps
CPU time 29.32 seconds
Started Aug 13 05:45:46 PM PDT 24
Finished Aug 13 05:46:15 PM PDT 24
Peak memory 256240 kb
Host smart-3318cd5a-0998-44ca-8e64-d52324cbb8ca
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10850
02310 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.1085002310
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.3932109918
Short name T510
Test name
Test status
Simulation time 1571318897 ps
CPU time 25.97 seconds
Started Aug 13 05:45:45 PM PDT 24
Finished Aug 13 05:46:11 PM PDT 24
Peak memory 256200 kb
Host smart-65fde159-f4cb-4a1d-9151-be13398873ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39321
09918 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.3932109918
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.3464610874
Short name T256
Test name
Test status
Simulation time 1010581913 ps
CPU time 33.3 seconds
Started Aug 13 05:45:43 PM PDT 24
Finished Aug 13 05:46:16 PM PDT 24
Peak memory 248232 kb
Host smart-f69d3bab-7e3a-4e83-bcb4-350c2f447fa9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34646
10874 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.3464610874
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.3699233556
Short name T471
Test name
Test status
Simulation time 843265432 ps
CPU time 22.26 seconds
Started Aug 13 05:45:53 PM PDT 24
Finished Aug 13 05:46:16 PM PDT 24
Peak memory 248700 kb
Host smart-e52c9b5c-7113-40c8-a66a-fea962d7d66a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36992
33556 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.3699233556
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.2672343794
Short name T207
Test name
Test status
Simulation time 30719302 ps
CPU time 3.07 seconds
Started Aug 13 05:45:55 PM PDT 24
Finished Aug 13 05:45:58 PM PDT 24
Peak memory 248952 kb
Host smart-87827fe4-5f1e-47d4-8cb1-4add4e321cf5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2672343794 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.2672343794
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.1058014264
Short name T55
Test name
Test status
Simulation time 58110588999 ps
CPU time 1306.68 seconds
Started Aug 13 05:45:56 PM PDT 24
Finished Aug 13 06:07:42 PM PDT 24
Peak memory 288856 kb
Host smart-a24077b4-df9b-4535-95e4-97589fa3b80e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1058014264 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.1058014264
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.3727620610
Short name T370
Test name
Test status
Simulation time 1105408534 ps
CPU time 11.66 seconds
Started Aug 13 05:46:00 PM PDT 24
Finished Aug 13 05:46:12 PM PDT 24
Peak memory 248764 kb
Host smart-e9248581-698a-4f8c-a98d-cf5669c5bf08
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3727620610 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.3727620610
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.390130264
Short name T707
Test name
Test status
Simulation time 1534732344 ps
CPU time 93.28 seconds
Started Aug 13 05:45:56 PM PDT 24
Finished Aug 13 05:47:29 PM PDT 24
Peak memory 256480 kb
Host smart-b0e57908-de33-4588-80ae-f008affff984
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39013
0264 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.390130264
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.2683690218
Short name T63
Test name
Test status
Simulation time 119238107 ps
CPU time 9.33 seconds
Started Aug 13 05:45:54 PM PDT 24
Finished Aug 13 05:46:04 PM PDT 24
Peak memory 248684 kb
Host smart-592b82b1-0bdb-4da7-89d9-9cf0ed5d58ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26836
90218 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.2683690218
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.3933911723
Short name T296
Test name
Test status
Simulation time 57136780228 ps
CPU time 1805.56 seconds
Started Aug 13 05:45:59 PM PDT 24
Finished Aug 13 06:16:05 PM PDT 24
Peak memory 283508 kb
Host smart-04fd77cf-6511-4083-8b46-16832e7d5265
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3933911723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.3933911723
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.3779713167
Short name T632
Test name
Test status
Simulation time 10682345239 ps
CPU time 223.32 seconds
Started Aug 13 05:45:56 PM PDT 24
Finished Aug 13 05:49:39 PM PDT 24
Peak memory 248852 kb
Host smart-4987a787-b20e-46d0-947b-36aa9b9f21bf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3779713167 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.3779713167
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.3171335074
Short name T54
Test name
Test status
Simulation time 1571220520 ps
CPU time 53.91 seconds
Started Aug 13 05:45:56 PM PDT 24
Finished Aug 13 05:46:50 PM PDT 24
Peak memory 256236 kb
Host smart-e8d14835-30d6-4cbc-9942-6e825d0ec596
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31713
35074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.3171335074
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.3152566185
Short name T594
Test name
Test status
Simulation time 1824745474 ps
CPU time 39.01 seconds
Started Aug 13 05:46:00 PM PDT 24
Finished Aug 13 05:46:39 PM PDT 24
Peak memory 248884 kb
Host smart-bde63ad3-7069-4f10-b01d-3782d8942473
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31525
66185 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.3152566185
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.2820607127
Short name T107
Test name
Test status
Simulation time 5092003070 ps
CPU time 38.97 seconds
Started Aug 13 05:45:55 PM PDT 24
Finished Aug 13 05:46:34 PM PDT 24
Peak memory 249128 kb
Host smart-f63a6d5e-bece-4b9c-844e-319ecb7d7a9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28206
07127 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.2820607127
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.3668948118
Short name T586
Test name
Test status
Simulation time 1071342099 ps
CPU time 31.34 seconds
Started Aug 13 05:45:55 PM PDT 24
Finished Aug 13 05:46:26 PM PDT 24
Peak memory 256980 kb
Host smart-891fe5ec-7dc6-461a-8d04-4ab8d6223f75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36689
48118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.3668948118
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.2499222781
Short name T455
Test name
Test status
Simulation time 113719737693 ps
CPU time 2114.13 seconds
Started Aug 13 05:45:58 PM PDT 24
Finished Aug 13 06:21:12 PM PDT 24
Peak memory 273164 kb
Host smart-bb1aa447-9189-4a44-a825-c692e48c9aca
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2499222781 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.2499222781
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.2065047033
Short name T422
Test name
Test status
Simulation time 1436663319 ps
CPU time 13.73 seconds
Started Aug 13 05:45:58 PM PDT 24
Finished Aug 13 05:46:12 PM PDT 24
Peak memory 248844 kb
Host smart-733e51bc-e0d0-4f39-85a2-bc5c64f8eda7
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2065047033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.2065047033
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.2460175925
Short name T400
Test name
Test status
Simulation time 746366595 ps
CPU time 63.43 seconds
Started Aug 13 05:45:56 PM PDT 24
Finished Aug 13 05:47:00 PM PDT 24
Peak memory 256552 kb
Host smart-b0b5c642-b484-46c3-9ffc-4dcef0dabf03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24601
75925 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.2460175925
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.1255045307
Short name T267
Test name
Test status
Simulation time 21942295149 ps
CPU time 1273.34 seconds
Started Aug 13 05:45:56 PM PDT 24
Finished Aug 13 06:07:10 PM PDT 24
Peak memory 272888 kb
Host smart-d496f573-941f-464d-9d1b-56628af1f317
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1255045307 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.1255045307
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.4170238195
Short name T625
Test name
Test status
Simulation time 41161793671 ps
CPU time 438.24 seconds
Started Aug 13 05:46:00 PM PDT 24
Finished Aug 13 05:53:18 PM PDT 24
Peak memory 248872 kb
Host smart-310f22a6-3132-42e8-9852-03b2fdd39f4b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4170238195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.4170238195
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.3142551255
Short name T486
Test name
Test status
Simulation time 923310358 ps
CPU time 31.26 seconds
Started Aug 13 05:45:55 PM PDT 24
Finished Aug 13 05:46:27 PM PDT 24
Peak memory 248920 kb
Host smart-a5bceafd-a1df-456d-bf64-5b7ba986ba3e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31425
51255 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.3142551255
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.4216180869
Short name T523
Test name
Test status
Simulation time 257060892 ps
CPU time 20 seconds
Started Aug 13 05:45:53 PM PDT 24
Finished Aug 13 05:46:13 PM PDT 24
Peak memory 256068 kb
Host smart-bf0b096c-78e8-4f67-8407-bf4e7c6d581a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42161
80869 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.4216180869
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.2102694082
Short name T291
Test name
Test status
Simulation time 2718900662 ps
CPU time 44.77 seconds
Started Aug 13 05:45:58 PM PDT 24
Finished Aug 13 05:46:43 PM PDT 24
Peak memory 257068 kb
Host smart-f167d41b-5924-49cc-9519-d07ac93e7f61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21026
94082 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.2102694082
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.444078977
Short name T655
Test name
Test status
Simulation time 583620597 ps
CPU time 29.72 seconds
Started Aug 13 05:45:55 PM PDT 24
Finished Aug 13 05:46:25 PM PDT 24
Peak memory 256572 kb
Host smart-8700c828-702d-4bcd-98a1-82569810f53d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44407
8977 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.444078977
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all_with_rand_reset.3605915279
Short name T114
Test name
Test status
Simulation time 7948953504 ps
CPU time 135.29 seconds
Started Aug 13 05:45:57 PM PDT 24
Finished Aug 13 05:48:12 PM PDT 24
Peak memory 266388 kb
Host smart-969a5c26-ffb0-4dfb-ac7c-a3549f07ebff
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3605915279 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 13.alert_handler_stress_all_with_rand_reset.3605915279
Directory /workspace/13.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.3351748185
Short name T208
Test name
Test status
Simulation time 185631392 ps
CPU time 4.6 seconds
Started Aug 13 05:45:55 PM PDT 24
Finished Aug 13 05:46:00 PM PDT 24
Peak memory 248812 kb
Host smart-e81656fa-ec67-4923-968e-6041a39a5f4e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3351748185 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.3351748185
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.870123648
Short name T506
Test name
Test status
Simulation time 98903123541 ps
CPU time 1541.05 seconds
Started Aug 13 05:45:55 PM PDT 24
Finished Aug 13 06:11:37 PM PDT 24
Peak memory 273472 kb
Host smart-28832cec-9257-4ea4-8905-859ab101e47a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=870123648 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.870123648
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.2410037226
Short name T6
Test name
Test status
Simulation time 456950134 ps
CPU time 13.95 seconds
Started Aug 13 05:45:56 PM PDT 24
Finished Aug 13 05:46:10 PM PDT 24
Peak memory 248832 kb
Host smart-6142774b-3fe6-49b7-bdb0-269b674db04b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2410037226 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.2410037226
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.1972929763
Short name T645
Test name
Test status
Simulation time 18525894588 ps
CPU time 233 seconds
Started Aug 13 05:45:54 PM PDT 24
Finished Aug 13 05:49:47 PM PDT 24
Peak memory 257100 kb
Host smart-7d7dc9dc-6256-48a8-9618-51e28c860cc9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19729
29763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.1972929763
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.1702232565
Short name T499
Test name
Test status
Simulation time 503563784 ps
CPU time 31.38 seconds
Started Aug 13 05:45:55 PM PDT 24
Finished Aug 13 05:46:27 PM PDT 24
Peak memory 248084 kb
Host smart-8fb53838-647b-4c64-9bbf-da7ba65eb1a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17022
32565 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.1702232565
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.635557322
Short name T27
Test name
Test status
Simulation time 30839671681 ps
CPU time 1875.89 seconds
Started Aug 13 05:45:59 PM PDT 24
Finished Aug 13 06:17:15 PM PDT 24
Peak memory 289276 kb
Host smart-0d776629-44cd-4ce8-a6e6-675da70538ce
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=635557322 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.635557322
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.136452945
Short name T105
Test name
Test status
Simulation time 864384385 ps
CPU time 21.56 seconds
Started Aug 13 05:45:56 PM PDT 24
Finished Aug 13 05:46:18 PM PDT 24
Peak memory 256180 kb
Host smart-c0ba050d-a10e-4a8b-bbc5-d9b0a2014629
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13645
2945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.136452945
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.2114420902
Short name T280
Test name
Test status
Simulation time 247253578 ps
CPU time 18.41 seconds
Started Aug 13 05:45:55 PM PDT 24
Finished Aug 13 05:46:13 PM PDT 24
Peak memory 256972 kb
Host smart-009637ae-c3fd-4825-b759-afc7b6636d49
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21144
20902 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.2114420902
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.2883011686
Short name T435
Test name
Test status
Simulation time 143850257 ps
CPU time 16.7 seconds
Started Aug 13 05:45:59 PM PDT 24
Finished Aug 13 05:46:16 PM PDT 24
Peak memory 249204 kb
Host smart-a23ec2eb-82fe-4297-89e1-9ee5330e87a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28830
11686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.2883011686
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.3056491835
Short name T566
Test name
Test status
Simulation time 387616441 ps
CPU time 24.41 seconds
Started Aug 13 05:45:59 PM PDT 24
Finished Aug 13 05:46:24 PM PDT 24
Peak memory 256984 kb
Host smart-949bb4b0-f89b-42e8-af5f-0ed41ab5dcdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30564
91835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.3056491835
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.1317320622
Short name T522
Test name
Test status
Simulation time 47918745749 ps
CPU time 2690.07 seconds
Started Aug 13 05:45:54 PM PDT 24
Finished Aug 13 06:30:44 PM PDT 24
Peak memory 289160 kb
Host smart-ebd90f86-ea55-42db-ac8e-6e8dbcfb0cb0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1317320622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_ha
ndler_stress_all.1317320622
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all_with_rand_reset.1200392118
Short name T73
Test name
Test status
Simulation time 5834403418 ps
CPU time 334.88 seconds
Started Aug 13 05:46:05 PM PDT 24
Finished Aug 13 05:51:40 PM PDT 24
Peak memory 267488 kb
Host smart-d60e6404-5745-4ad7-9e79-2e2b42a106e9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1200392118 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.alert_handler_stress_all_with_rand_reset.1200392118
Directory /workspace/14.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.2043226881
Short name T43
Test name
Test status
Simulation time 115787638 ps
CPU time 3.29 seconds
Started Aug 13 05:46:05 PM PDT 24
Finished Aug 13 05:46:08 PM PDT 24
Peak memory 248940 kb
Host smart-81f072fb-3da6-4b46-acfd-82b84e48578c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2043226881 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.2043226881
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.3817485779
Short name T409
Test name
Test status
Simulation time 40976280623 ps
CPU time 1122.28 seconds
Started Aug 13 05:46:07 PM PDT 24
Finished Aug 13 06:04:49 PM PDT 24
Peak memory 273472 kb
Host smart-630ebfc6-f4a7-40c7-9c7a-4568e7c9984a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3817485779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.3817485779
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.1196743819
Short name T634
Test name
Test status
Simulation time 455404605 ps
CPU time 12.91 seconds
Started Aug 13 05:46:03 PM PDT 24
Finished Aug 13 05:46:17 PM PDT 24
Peak memory 248692 kb
Host smart-9779a7d7-4637-47cf-a612-cb630e904193
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1196743819 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.1196743819
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.4133891837
Short name T360
Test name
Test status
Simulation time 1243543766 ps
CPU time 99.95 seconds
Started Aug 13 05:46:08 PM PDT 24
Finished Aug 13 05:47:48 PM PDT 24
Peak memory 256600 kb
Host smart-b8dc0065-9a0a-450e-ba8d-511402236e9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41338
91837 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.4133891837
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.971415978
Short name T413
Test name
Test status
Simulation time 2025926956 ps
CPU time 56.79 seconds
Started Aug 13 05:46:04 PM PDT 24
Finished Aug 13 05:47:01 PM PDT 24
Peak memory 248756 kb
Host smart-a2ef6d49-7fa7-4d30-830b-d7c8e740c8a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97141
5978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.971415978
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.3220026223
Short name T293
Test name
Test status
Simulation time 70968525008 ps
CPU time 2320.71 seconds
Started Aug 13 05:46:04 PM PDT 24
Finished Aug 13 06:24:45 PM PDT 24
Peak memory 288848 kb
Host smart-6ade025b-f858-48b6-8771-34cc6c0d6861
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3220026223 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.3220026223
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.1010868247
Short name T660
Test name
Test status
Simulation time 5373010926 ps
CPU time 219.07 seconds
Started Aug 13 05:46:05 PM PDT 24
Finished Aug 13 05:49:44 PM PDT 24
Peak memory 255908 kb
Host smart-ffcced1e-04a1-48a7-9d48-a5e40ee2e82d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1010868247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.1010868247
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.4118911537
Short name T487
Test name
Test status
Simulation time 519287200 ps
CPU time 29.53 seconds
Started Aug 13 05:46:03 PM PDT 24
Finished Aug 13 05:46:33 PM PDT 24
Peak memory 256296 kb
Host smart-f9b0d2ad-fd91-4586-8e03-a002e5fe8603
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41189
11537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.4118911537
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.3036912474
Short name T666
Test name
Test status
Simulation time 724947779 ps
CPU time 43.71 seconds
Started Aug 13 05:46:03 PM PDT 24
Finished Aug 13 05:46:46 PM PDT 24
Peak memory 248256 kb
Host smart-0a8e31c6-97ef-44dc-a527-5637638bdbdb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30369
12474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.3036912474
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.2366341341
Short name T275
Test name
Test status
Simulation time 1056788358 ps
CPU time 27.05 seconds
Started Aug 13 05:46:04 PM PDT 24
Finished Aug 13 05:46:31 PM PDT 24
Peak memory 256008 kb
Host smart-1295d98b-e35a-48cc-8be5-998bbc920578
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23663
41341 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.2366341341
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.404368552
Short name T380
Test name
Test status
Simulation time 161796002 ps
CPU time 11.9 seconds
Started Aug 13 05:46:03 PM PDT 24
Finished Aug 13 05:46:15 PM PDT 24
Peak memory 254904 kb
Host smart-595e52e8-1c25-4c77-951b-0939078a6431
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40436
8552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.404368552
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.685481033
Short name T526
Test name
Test status
Simulation time 1520581659 ps
CPU time 117.13 seconds
Started Aug 13 05:46:04 PM PDT 24
Finished Aug 13 05:48:01 PM PDT 24
Peak memory 257052 kb
Host smart-3ec79402-4f81-49ba-92d8-4043c053ec98
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=685481033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_han
dler_stress_all.685481033
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.2729219712
Short name T204
Test name
Test status
Simulation time 60777768 ps
CPU time 3.49 seconds
Started Aug 13 05:46:05 PM PDT 24
Finished Aug 13 05:46:09 PM PDT 24
Peak memory 249000 kb
Host smart-2397abe1-0130-4c3c-8b66-516d9cf1a8da
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2729219712 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.2729219712
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.3386426812
Short name T402
Test name
Test status
Simulation time 450419197212 ps
CPU time 1581.48 seconds
Started Aug 13 05:46:07 PM PDT 24
Finished Aug 13 06:12:29 PM PDT 24
Peak memory 273176 kb
Host smart-95e69b1d-033f-4c3f-bd8b-0e7bb6bab7b2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3386426812 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.3386426812
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.1592419553
Short name T576
Test name
Test status
Simulation time 1017794838 ps
CPU time 14.65 seconds
Started Aug 13 05:46:07 PM PDT 24
Finished Aug 13 05:46:22 PM PDT 24
Peak memory 248808 kb
Host smart-3b199499-f952-40aa-9374-5be1f897969b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1592419553 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.1592419553
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.3237665635
Short name T543
Test name
Test status
Simulation time 224133600 ps
CPU time 17.08 seconds
Started Aug 13 05:46:05 PM PDT 24
Finished Aug 13 05:46:22 PM PDT 24
Peak memory 254584 kb
Host smart-4df5b7a4-b7b5-45a5-9afe-d5a90e68f631
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32376
65635 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.3237665635
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.3727586679
Short name T37
Test name
Test status
Simulation time 3466348539 ps
CPU time 23.41 seconds
Started Aug 13 05:46:05 PM PDT 24
Finished Aug 13 05:46:29 PM PDT 24
Peak memory 257084 kb
Host smart-3e3d76a4-6ff6-474f-b50c-eebe7502c177
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37275
86679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.3727586679
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.379596954
Short name T15
Test name
Test status
Simulation time 16924904325 ps
CPU time 1299.53 seconds
Started Aug 13 05:46:05 PM PDT 24
Finished Aug 13 06:07:45 PM PDT 24
Peak memory 289700 kb
Host smart-e349339e-f557-4500-b6f1-8fb784fe2da7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379596954 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.379596954
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.1454735617
Short name T305
Test name
Test status
Simulation time 18169699166 ps
CPU time 402.57 seconds
Started Aug 13 05:46:07 PM PDT 24
Finished Aug 13 05:52:50 PM PDT 24
Peak memory 248844 kb
Host smart-6ac2e0e3-d3e4-4be7-8815-20ae8121eeca
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1454735617 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.1454735617
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.1755237236
Short name T363
Test name
Test status
Simulation time 601397064 ps
CPU time 37.6 seconds
Started Aug 13 05:46:05 PM PDT 24
Finished Aug 13 05:46:43 PM PDT 24
Peak memory 256624 kb
Host smart-65f933a9-0a3e-4c50-a0f0-6c42f1e0bb5a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17552
37236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.1755237236
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.3064910383
Short name T505
Test name
Test status
Simulation time 1884173864 ps
CPU time 64.73 seconds
Started Aug 13 05:46:07 PM PDT 24
Finished Aug 13 05:47:12 PM PDT 24
Peak memory 248176 kb
Host smart-d6879000-6a05-47d8-bd21-118dbc0409bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30649
10383 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.3064910383
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.1689791455
Short name T81
Test name
Test status
Simulation time 979430792 ps
CPU time 27.18 seconds
Started Aug 13 05:46:05 PM PDT 24
Finished Aug 13 05:46:32 PM PDT 24
Peak memory 256820 kb
Host smart-51f3fe63-bde5-4f3a-add2-0e1c914351ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16897
91455 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.1689791455
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.1910938468
Short name T609
Test name
Test status
Simulation time 93018783 ps
CPU time 6.34 seconds
Started Aug 13 05:46:02 PM PDT 24
Finished Aug 13 05:46:08 PM PDT 24
Peak memory 251768 kb
Host smart-2a1c1f70-09f2-4a76-9e00-eadb4a7a9e24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19109
38468 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.1910938468
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.1652143936
Short name T255
Test name
Test status
Simulation time 882158802 ps
CPU time 41.13 seconds
Started Aug 13 05:46:07 PM PDT 24
Finished Aug 13 05:46:48 PM PDT 24
Peak memory 256956 kb
Host smart-148f163a-804e-45c8-9b1e-341af3dcd36e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1652143936 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_ha
ndler_stress_all.1652143936
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all_with_rand_reset.2278551625
Short name T71
Test name
Test status
Simulation time 2978095044 ps
CPU time 258.86 seconds
Started Aug 13 05:46:09 PM PDT 24
Finished Aug 13 05:50:28 PM PDT 24
Peak memory 267468 kb
Host smart-0d67580f-e3ab-40b3-b531-22b03ac208fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2278551625 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 16.alert_handler_stress_all_with_rand_reset.2278551625
Directory /workspace/16.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.1716034327
Short name T213
Test name
Test status
Simulation time 52131385 ps
CPU time 2.54 seconds
Started Aug 13 05:46:07 PM PDT 24
Finished Aug 13 05:46:10 PM PDT 24
Peak memory 248952 kb
Host smart-d440ab9d-bf89-4dec-902b-ed7f096bd135
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1716034327 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.1716034327
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.372628982
Short name T17
Test name
Test status
Simulation time 150812498518 ps
CPU time 1211.32 seconds
Started Aug 13 05:46:07 PM PDT 24
Finished Aug 13 06:06:19 PM PDT 24
Peak memory 282868 kb
Host smart-deb27c0e-d0c1-4bb7-9f07-4a4a2e756b76
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372628982 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.372628982
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.1929117380
Short name T606
Test name
Test status
Simulation time 613581919 ps
CPU time 10.78 seconds
Started Aug 13 05:46:13 PM PDT 24
Finished Aug 13 05:46:24 PM PDT 24
Peak memory 248744 kb
Host smart-2231c73b-6d90-4f71-bea5-8f3a43015178
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1929117380 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.1929117380
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.260101095
Short name T656
Test name
Test status
Simulation time 5819031864 ps
CPU time 85.14 seconds
Started Aug 13 05:46:11 PM PDT 24
Finished Aug 13 05:47:36 PM PDT 24
Peak memory 256580 kb
Host smart-a15166d7-250b-47e6-ad48-c50f50dad03c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26010
1095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.260101095
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.1214677783
Short name T436
Test name
Test status
Simulation time 1214030173 ps
CPU time 73.82 seconds
Started Aug 13 05:46:09 PM PDT 24
Finished Aug 13 05:47:24 PM PDT 24
Peak memory 248668 kb
Host smart-59cd8f28-2bd5-4b68-9596-8f8d6b41c4ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12146
77783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.1214677783
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.2216013733
Short name T662
Test name
Test status
Simulation time 55665109827 ps
CPU time 1448.49 seconds
Started Aug 13 05:46:07 PM PDT 24
Finished Aug 13 06:10:16 PM PDT 24
Peak memory 273396 kb
Host smart-7916f9ea-a496-4f88-809c-1d72c7ed9e48
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2216013733 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.2216013733
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.1914041351
Short name T617
Test name
Test status
Simulation time 16005118574 ps
CPU time 172.27 seconds
Started Aug 13 05:46:09 PM PDT 24
Finished Aug 13 05:49:02 PM PDT 24
Peak memory 255432 kb
Host smart-487b1250-e9c3-427f-8b2f-6974ddd4120c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1914041351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.1914041351
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.3031790527
Short name T496
Test name
Test status
Simulation time 287504066 ps
CPU time 27.91 seconds
Started Aug 13 05:46:09 PM PDT 24
Finished Aug 13 05:46:37 PM PDT 24
Peak memory 256128 kb
Host smart-4f0e7452-88f6-427c-8323-10148cc32bac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30317
90527 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.3031790527
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.3077612190
Short name T274
Test name
Test status
Simulation time 771914507 ps
CPU time 58.04 seconds
Started Aug 13 05:46:06 PM PDT 24
Finished Aug 13 05:47:04 PM PDT 24
Peak memory 248428 kb
Host smart-b5950e6e-cfe8-4719-b021-72bf0284035e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30776
12190 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.3077612190
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.1426390669
Short name T85
Test name
Test status
Simulation time 562901969 ps
CPU time 18.23 seconds
Started Aug 13 05:46:08 PM PDT 24
Finished Aug 13 05:46:26 PM PDT 24
Peak memory 248224 kb
Host smart-39e4faf5-378a-453d-b0d8-bded0361bbb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14263
90669 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.1426390669
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.3909394349
Short name T282
Test name
Test status
Simulation time 1711525172 ps
CPU time 22.35 seconds
Started Aug 13 05:46:10 PM PDT 24
Finished Aug 13 05:46:32 PM PDT 24
Peak memory 256976 kb
Host smart-a15a0a94-5ac2-4c12-a128-bb230f0bafe9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39093
94349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.3909394349
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all_with_rand_reset.878485783
Short name T272
Test name
Test status
Simulation time 19205357399 ps
CPU time 121.75 seconds
Started Aug 13 05:46:02 PM PDT 24
Finished Aug 13 05:48:03 PM PDT 24
Peak memory 271020 kb
Host smart-5e675b65-7122-4f33-9185-66623c52587b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=878485783 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 17.alert_handler_stress_all_with_rand_reset.878485783
Directory /workspace/17.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.1968890410
Short name T206
Test name
Test status
Simulation time 219021768 ps
CPU time 4.55 seconds
Started Aug 13 05:46:17 PM PDT 24
Finished Aug 13 05:46:22 PM PDT 24
Peak memory 248956 kb
Host smart-2a6d54b4-466e-4e6e-86d6-885a75a8b16d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1968890410 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.1968890410
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.1379220818
Short name T593
Test name
Test status
Simulation time 37804667541 ps
CPU time 849.14 seconds
Started Aug 13 05:46:12 PM PDT 24
Finished Aug 13 06:00:22 PM PDT 24
Peak memory 273464 kb
Host smart-547a347b-c233-4366-acc1-1fd4a3c1b1a9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1379220818 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.1379220818
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.1780023920
Short name T396
Test name
Test status
Simulation time 529320003 ps
CPU time 15.13 seconds
Started Aug 13 05:46:17 PM PDT 24
Finished Aug 13 05:46:32 PM PDT 24
Peak memory 248792 kb
Host smart-3548a44c-846f-4423-83c8-f31b76011610
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1780023920 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.1780023920
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.2649996356
Short name T633
Test name
Test status
Simulation time 9334497235 ps
CPU time 315.08 seconds
Started Aug 13 05:46:06 PM PDT 24
Finished Aug 13 05:51:21 PM PDT 24
Peak memory 256428 kb
Host smart-21969b9b-0119-4994-bddc-23a74f5f060e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26499
96356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.2649996356
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.508622666
Short name T582
Test name
Test status
Simulation time 494198878 ps
CPU time 9.99 seconds
Started Aug 13 05:46:04 PM PDT 24
Finished Aug 13 05:46:14 PM PDT 24
Peak memory 248796 kb
Host smart-a6784e95-6a62-4354-9ac6-84e55808845e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50862
2666 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.508622666
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.3986635676
Short name T451
Test name
Test status
Simulation time 25802803386 ps
CPU time 1614.03 seconds
Started Aug 13 05:46:16 PM PDT 24
Finished Aug 13 06:13:10 PM PDT 24
Peak memory 273492 kb
Host smart-e0d03197-7f25-41ec-b1c0-a0b7a375ddcf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3986635676 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.3986635676
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.777668272
Short name T324
Test name
Test status
Simulation time 5932770112 ps
CPU time 261.41 seconds
Started Aug 13 05:46:14 PM PDT 24
Finished Aug 13 05:50:36 PM PDT 24
Peak memory 248900 kb
Host smart-1c376682-3c45-4d55-ac84-f5dc7a1abcc3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=777668272 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.777668272
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.1538426679
Short name T517
Test name
Test status
Simulation time 531930273 ps
CPU time 25.34 seconds
Started Aug 13 05:46:08 PM PDT 24
Finished Aug 13 05:46:34 PM PDT 24
Peak memory 248708 kb
Host smart-49ac1479-7fdc-4095-836b-fc263a4f3cae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15384
26679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.1538426679
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.3403227142
Short name T116
Test name
Test status
Simulation time 3942962124 ps
CPU time 40.12 seconds
Started Aug 13 05:46:04 PM PDT 24
Finished Aug 13 05:46:44 PM PDT 24
Peak memory 256036 kb
Host smart-2b7c0029-5e33-4a8c-aab4-31a3ae971d8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34032
27142 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.3403227142
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.686152338
Short name T488
Test name
Test status
Simulation time 594556770 ps
CPU time 37.67 seconds
Started Aug 13 05:46:05 PM PDT 24
Finished Aug 13 05:46:43 PM PDT 24
Peak memory 249176 kb
Host smart-ceb2a00d-eb9e-4c1f-b2e3-ae86250d2f55
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68615
2338 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.686152338
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.1726403978
Short name T392
Test name
Test status
Simulation time 57740345 ps
CPU time 2.77 seconds
Started Aug 13 05:46:08 PM PDT 24
Finished Aug 13 05:46:11 PM PDT 24
Peak memory 250876 kb
Host smart-bf02d871-cf6a-4d4c-95da-b48eaaf6230b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17264
03978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.1726403978
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.61066254
Short name T613
Test name
Test status
Simulation time 167115429436 ps
CPU time 2601.58 seconds
Started Aug 13 05:46:12 PM PDT 24
Finished Aug 13 06:29:35 PM PDT 24
Peak memory 289124 kb
Host smart-ab84be81-985c-4d1d-b186-45680693ef1c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61066254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_hand
ler_stress_all.61066254
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.1164027450
Short name T205
Test name
Test status
Simulation time 17921998 ps
CPU time 3.07 seconds
Started Aug 13 05:46:17 PM PDT 24
Finished Aug 13 05:46:20 PM PDT 24
Peak memory 249052 kb
Host smart-1ae11ad0-9d05-4f85-a762-4944b9e191f2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1164027450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.1164027450
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.512785532
Short name T121
Test name
Test status
Simulation time 109078532424 ps
CPU time 3380.39 seconds
Started Aug 13 05:46:16 PM PDT 24
Finished Aug 13 06:42:37 PM PDT 24
Peak memory 289624 kb
Host smart-21ad795a-2c88-4700-927b-be7eb97f526d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=512785532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.512785532
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.400337683
Short name T427
Test name
Test status
Simulation time 753578974 ps
CPU time 10.48 seconds
Started Aug 13 05:46:11 PM PDT 24
Finished Aug 13 05:46:21 PM PDT 24
Peak memory 248812 kb
Host smart-a6ea8f7f-d196-4af8-b691-2c774092f68c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=400337683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.400337683
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.1308332933
Short name T652
Test name
Test status
Simulation time 6652832849 ps
CPU time 188.16 seconds
Started Aug 13 05:46:11 PM PDT 24
Finished Aug 13 05:49:19 PM PDT 24
Peak memory 257084 kb
Host smart-f92c1d74-71b5-470e-adff-84833ef4a6ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13083
32933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.1308332933
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.679228293
Short name T494
Test name
Test status
Simulation time 2409879691 ps
CPU time 26.59 seconds
Started Aug 13 05:46:09 PM PDT 24
Finished Aug 13 05:46:36 PM PDT 24
Peak memory 256212 kb
Host smart-32eecbe0-f038-44fa-8545-0384ec7785dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=67922
8293 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.679228293
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.1868332095
Short name T335
Test name
Test status
Simulation time 51214882139 ps
CPU time 1507.61 seconds
Started Aug 13 05:46:17 PM PDT 24
Finished Aug 13 06:11:25 PM PDT 24
Peak memory 272820 kb
Host smart-7d178f9d-a0f6-415a-8c9f-22ccbf1548f7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1868332095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.1868332095
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.1166511110
Short name T287
Test name
Test status
Simulation time 42488879624 ps
CPU time 1264.33 seconds
Started Aug 13 05:46:18 PM PDT 24
Finished Aug 13 06:07:22 PM PDT 24
Peak memory 272972 kb
Host smart-7ba2206b-edde-4fd8-98b5-b117a8a8eacb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1166511110 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.1166511110
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.3690087887
Short name T369
Test name
Test status
Simulation time 2395631801 ps
CPU time 26.98 seconds
Started Aug 13 05:46:10 PM PDT 24
Finished Aug 13 05:46:37 PM PDT 24
Peak memory 257004 kb
Host smart-865b0bb8-6d72-43a9-a025-2d7de3b99552
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36900
87887 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.3690087887
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.2616121498
Short name T100
Test name
Test status
Simulation time 1096713154 ps
CPU time 64.65 seconds
Started Aug 13 05:46:17 PM PDT 24
Finished Aug 13 05:47:22 PM PDT 24
Peak memory 256608 kb
Host smart-9d2a355c-df4e-478b-bcfb-ff4626d67fc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26161
21498 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.2616121498
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.2130729282
Short name T621
Test name
Test status
Simulation time 232123854 ps
CPU time 28.24 seconds
Started Aug 13 05:46:08 PM PDT 24
Finished Aug 13 05:46:36 PM PDT 24
Peak memory 248416 kb
Host smart-c2f290eb-2692-4449-94b5-3f7380431fdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21307
29282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.2130729282
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.3380011286
Short name T703
Test name
Test status
Simulation time 693043988 ps
CPU time 41.28 seconds
Started Aug 13 05:46:17 PM PDT 24
Finished Aug 13 05:46:58 PM PDT 24
Peak memory 256928 kb
Host smart-9627d399-29ce-4f83-a0ba-cfcb9a8c6384
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33800
11286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.3380011286
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.873643938
Short name T495
Test name
Test status
Simulation time 1279821574 ps
CPU time 52.3 seconds
Started Aug 13 05:46:15 PM PDT 24
Finished Aug 13 05:47:07 PM PDT 24
Peak memory 256928 kb
Host smart-5fda3964-26a9-4519-9eff-9c3f7d52d921
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=873643938 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_han
dler_stress_all.873643938
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all_with_rand_reset.3745708957
Short name T77
Test name
Test status
Simulation time 7759394832 ps
CPU time 128.96 seconds
Started Aug 13 05:46:09 PM PDT 24
Finished Aug 13 05:48:18 PM PDT 24
Peak memory 266880 kb
Host smart-7717ce14-c135-4fd8-87f7-865880e0fceb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3745708957 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.alert_handler_stress_all_with_rand_reset.3745708957
Directory /workspace/19.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.745977485
Short name T13
Test name
Test status
Simulation time 53285745 ps
CPU time 4.59 seconds
Started Aug 13 05:45:32 PM PDT 24
Finished Aug 13 05:45:37 PM PDT 24
Peak memory 249028 kb
Host smart-c89a591c-1dfd-4cb2-a07b-80b9b9287093
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=745977485 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.745977485
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.2224873899
Short name T651
Test name
Test status
Simulation time 31732625765 ps
CPU time 1835.18 seconds
Started Aug 13 05:45:30 PM PDT 24
Finished Aug 13 06:16:06 PM PDT 24
Peak memory 281696 kb
Host smart-cfc45594-5b24-4953-a8db-ddd9d4b09280
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2224873899 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.2224873899
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.1676507671
Short name T388
Test name
Test status
Simulation time 2161217113 ps
CPU time 76.92 seconds
Started Aug 13 05:45:29 PM PDT 24
Finished Aug 13 05:46:46 PM PDT 24
Peak memory 248768 kb
Host smart-d6eb95a1-df83-4605-835e-bec3b9abe5aa
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1676507671 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.1676507671
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.1224858986
Short name T424
Test name
Test status
Simulation time 518056252 ps
CPU time 43.64 seconds
Started Aug 13 05:45:30 PM PDT 24
Finished Aug 13 05:46:14 PM PDT 24
Peak memory 256596 kb
Host smart-05db5a05-b0af-4e67-bb54-378e2fe86cc1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12248
58986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.1224858986
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.4121603628
Short name T697
Test name
Test status
Simulation time 1102790681 ps
CPU time 22.46 seconds
Started Aug 13 05:45:29 PM PDT 24
Finished Aug 13 05:45:52 PM PDT 24
Peak memory 256600 kb
Host smart-2d5fc485-8bb7-4c9c-815a-64fc78542f32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41216
03628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.4121603628
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.1121653092
Short name T283
Test name
Test status
Simulation time 81138018977 ps
CPU time 2443.31 seconds
Started Aug 13 05:45:52 PM PDT 24
Finished Aug 13 06:26:35 PM PDT 24
Peak memory 289240 kb
Host smart-54a74f26-94a6-489f-91c3-b2633bf94bbb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1121653092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.1121653092
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.2598471812
Short name T631
Test name
Test status
Simulation time 14646960717 ps
CPU time 163.01 seconds
Started Aug 13 05:45:30 PM PDT 24
Finished Aug 13 05:48:13 PM PDT 24
Peak memory 248592 kb
Host smart-e4474761-5a62-41d8-9ccd-3f81b8ee188c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2598471812 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.2598471812
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.1336933073
Short name T440
Test name
Test status
Simulation time 629081618 ps
CPU time 31.84 seconds
Started Aug 13 05:45:29 PM PDT 24
Finished Aug 13 05:46:01 PM PDT 24
Peak memory 256272 kb
Host smart-bb92e640-d1bb-4db5-85e6-7f6b1f4d08d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13369
33073 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.1336933073
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.1387859531
Short name T595
Test name
Test status
Simulation time 4654686639 ps
CPU time 47.36 seconds
Started Aug 13 05:45:27 PM PDT 24
Finished Aug 13 05:46:14 PM PDT 24
Peak memory 255584 kb
Host smart-ba2456e4-4b8a-4523-b0f0-ab1e8f9e1d34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13878
59531 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.1387859531
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.3486025544
Short name T29
Test name
Test status
Simulation time 2151491564 ps
CPU time 13.94 seconds
Started Aug 13 05:45:30 PM PDT 24
Finished Aug 13 05:45:44 PM PDT 24
Peak memory 270520 kb
Host smart-a0422769-8223-4491-b830-bf2f2fd4e0b4
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3486025544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.3486025544
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.1907157903
Short name T421
Test name
Test status
Simulation time 63578117 ps
CPU time 2.96 seconds
Started Aug 13 05:45:30 PM PDT 24
Finished Aug 13 05:45:33 PM PDT 24
Peak memory 240592 kb
Host smart-b3a8f61f-f8b7-4298-8201-f3305dff9494
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19071
57903 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.1907157903
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.417115232
Short name T470
Test name
Test status
Simulation time 747985868 ps
CPU time 21.93 seconds
Started Aug 13 05:45:32 PM PDT 24
Finished Aug 13 05:45:54 PM PDT 24
Peak memory 256692 kb
Host smart-8f7228e6-79d4-4c70-861a-9889f4b4018a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41711
5232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.417115232
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.700388856
Short name T668
Test name
Test status
Simulation time 15411127120 ps
CPU time 240.72 seconds
Started Aug 13 05:45:32 PM PDT 24
Finished Aug 13 05:49:33 PM PDT 24
Peak memory 257128 kb
Host smart-b85a6f62-e50e-4c4d-a94d-ff4b8c54def2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=700388856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_hand
ler_stress_all.700388856
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.2143044966
Short name T458
Test name
Test status
Simulation time 38337312921 ps
CPU time 1422.89 seconds
Started Aug 13 05:46:16 PM PDT 24
Finished Aug 13 06:10:00 PM PDT 24
Peak memory 289064 kb
Host smart-843b6165-7aab-4e83-b438-9d6d3378aab5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2143044966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.2143044966
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.1881364564
Short name T480
Test name
Test status
Simulation time 54056066 ps
CPU time 8.07 seconds
Started Aug 13 05:46:15 PM PDT 24
Finished Aug 13 05:46:23 PM PDT 24
Peak memory 255164 kb
Host smart-57c2187a-9a9b-497f-8920-77d31b0c2022
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18813
64564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.1881364564
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.51806267
Short name T520
Test name
Test status
Simulation time 157265307 ps
CPU time 15.68 seconds
Started Aug 13 05:46:18 PM PDT 24
Finished Aug 13 05:46:34 PM PDT 24
Peak memory 248368 kb
Host smart-d2d7fac6-496a-4720-9977-ba67e2a2eba6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51806
267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.51806267
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.153276353
Short name T626
Test name
Test status
Simulation time 6190956942 ps
CPU time 750.24 seconds
Started Aug 13 05:46:17 PM PDT 24
Finished Aug 13 05:58:48 PM PDT 24
Peak memory 272816 kb
Host smart-68c9bb68-7e07-4acf-94ec-7c8f2cd45603
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=153276353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.153276353
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.42848521
Short name T604
Test name
Test status
Simulation time 30749600307 ps
CPU time 1352.97 seconds
Started Aug 13 05:46:09 PM PDT 24
Finished Aug 13 06:08:42 PM PDT 24
Peak memory 288808 kb
Host smart-96ed7b31-84a4-4118-87ef-ae35e008f86b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=42848521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.42848521
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.1025892137
Short name T639
Test name
Test status
Simulation time 4882023513 ps
CPU time 208.92 seconds
Started Aug 13 05:46:17 PM PDT 24
Finished Aug 13 05:49:46 PM PDT 24
Peak memory 255268 kb
Host smart-d198a01d-a7cd-4238-a0e4-b5294507a978
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1025892137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.1025892137
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.935007162
Short name T600
Test name
Test status
Simulation time 1087765571 ps
CPU time 30.95 seconds
Started Aug 13 05:46:18 PM PDT 24
Finished Aug 13 05:46:49 PM PDT 24
Peak memory 248800 kb
Host smart-55879484-e29b-4a67-8fed-fa52b2321390
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=93500
7162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.935007162
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.1054325909
Short name T68
Test name
Test status
Simulation time 3836092985 ps
CPU time 54.15 seconds
Started Aug 13 05:46:10 PM PDT 24
Finished Aug 13 05:47:04 PM PDT 24
Peak memory 248892 kb
Host smart-f3ad2feb-afe7-4b40-85c9-53718e3de34f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10543
25909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.1054325909
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.4265929530
Short name T252
Test name
Test status
Simulation time 967909948 ps
CPU time 61.51 seconds
Started Aug 13 05:46:17 PM PDT 24
Finished Aug 13 05:47:19 PM PDT 24
Peak memory 257028 kb
Host smart-67277fbd-7f24-44be-b7c3-881d8b408c92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42659
29530 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.4265929530
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.262476979
Short name T540
Test name
Test status
Simulation time 1559874070 ps
CPU time 26.61 seconds
Started Aug 13 05:46:15 PM PDT 24
Finished Aug 13 05:46:41 PM PDT 24
Peak memory 257016 kb
Host smart-8d0dbdb8-f8ac-4db3-8898-049d9e1a7027
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26247
6979 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.262476979
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.2525651812
Short name T110
Test name
Test status
Simulation time 22432769221 ps
CPU time 1603.84 seconds
Started Aug 13 05:46:19 PM PDT 24
Finished Aug 13 06:13:03 PM PDT 24
Peak memory 269380 kb
Host smart-a770a0e7-e9c5-48be-8297-9f05282c4b75
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2525651812 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.2525651812
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.2839609170
Short name T599
Test name
Test status
Simulation time 5679000782 ps
CPU time 146.2 seconds
Started Aug 13 05:46:18 PM PDT 24
Finished Aug 13 05:48:44 PM PDT 24
Peak memory 257004 kb
Host smart-b337c968-8c94-44a3-9026-e80cdadcb0e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28396
09170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.2839609170
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.3191575110
Short name T83
Test name
Test status
Simulation time 1786160247 ps
CPU time 35.14 seconds
Started Aug 13 05:46:15 PM PDT 24
Finished Aug 13 05:46:50 PM PDT 24
Peak memory 248344 kb
Host smart-b306be44-4622-4d89-a492-5d950d1c500a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31915
75110 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.3191575110
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.2576850893
Short name T549
Test name
Test status
Simulation time 37089064664 ps
CPU time 2509.62 seconds
Started Aug 13 05:46:18 PM PDT 24
Finished Aug 13 06:28:08 PM PDT 24
Peak memory 289228 kb
Host smart-349f81f1-a0f1-4106-89a6-315295a54a69
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2576850893 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.2576850893
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.2288308393
Short name T467
Test name
Test status
Simulation time 11764227625 ps
CPU time 245.33 seconds
Started Aug 13 05:46:14 PM PDT 24
Finished Aug 13 05:50:19 PM PDT 24
Peak memory 248892 kb
Host smart-3db298f1-37b8-4768-bc9a-51483fa944f5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2288308393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.2288308393
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.2618301766
Short name T449
Test name
Test status
Simulation time 149062165 ps
CPU time 10.08 seconds
Started Aug 13 05:46:16 PM PDT 24
Finished Aug 13 05:46:26 PM PDT 24
Peak memory 254680 kb
Host smart-73273ec2-34dd-4417-a3a5-9064d78a90b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26183
01766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.2618301766
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.2888947490
Short name T119
Test name
Test status
Simulation time 1494190606 ps
CPU time 23.89 seconds
Started Aug 13 05:46:17 PM PDT 24
Finished Aug 13 05:46:41 PM PDT 24
Peak memory 248244 kb
Host smart-8d42f9ee-3a6a-40a7-af72-6a3359ca8154
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28889
47490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.2888947490
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.1436891522
Short name T515
Test name
Test status
Simulation time 428528879 ps
CPU time 23.63 seconds
Started Aug 13 05:46:17 PM PDT 24
Finished Aug 13 05:46:41 PM PDT 24
Peak memory 248280 kb
Host smart-107f4ed7-8844-4241-8a38-df97a01f27ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14368
91522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.1436891522
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.1395477093
Short name T555
Test name
Test status
Simulation time 2612957212 ps
CPU time 46.21 seconds
Started Aug 13 05:46:28 PM PDT 24
Finished Aug 13 05:47:14 PM PDT 24
Peak memory 257072 kb
Host smart-76c4ebc1-53e3-42bc-98d6-d34b674025b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13954
77093 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.1395477093
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.3271975436
Short name T108
Test name
Test status
Simulation time 4157451116 ps
CPU time 230.78 seconds
Started Aug 13 05:46:17 PM PDT 24
Finished Aug 13 05:50:08 PM PDT 24
Peak memory 257056 kb
Host smart-957011e9-4f36-4d64-8474-03bdd9857d12
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3271975436 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_ha
ndler_stress_all.3271975436
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all_with_rand_reset.790422166
Short name T426
Test name
Test status
Simulation time 2894841979 ps
CPU time 104.76 seconds
Started Aug 13 05:46:28 PM PDT 24
Finished Aug 13 05:48:13 PM PDT 24
Peak memory 265356 kb
Host smart-bba98a2b-d257-4547-a64f-99225d1ae21d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=790422166 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 21.alert_handler_stress_all_with_rand_reset.790422166
Directory /workspace/21.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.898212725
Short name T82
Test name
Test status
Simulation time 62759810462 ps
CPU time 1543.47 seconds
Started Aug 13 05:46:23 PM PDT 24
Finished Aug 13 06:12:06 PM PDT 24
Peak memory 289624 kb
Host smart-aeb1bc76-bc06-4968-8e25-a959a4a73715
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=898212725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.898212725
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.1359458788
Short name T580
Test name
Test status
Simulation time 2824987385 ps
CPU time 157.17 seconds
Started Aug 13 05:46:28 PM PDT 24
Finished Aug 13 05:49:05 PM PDT 24
Peak memory 257096 kb
Host smart-86760b35-390f-41aa-b3ff-54969138f96c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13594
58788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.1359458788
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.3036814961
Short name T556
Test name
Test status
Simulation time 101798152 ps
CPU time 3.5 seconds
Started Aug 13 05:46:24 PM PDT 24
Finished Aug 13 05:46:28 PM PDT 24
Peak memory 240672 kb
Host smart-466ec3c4-f631-4205-94f8-0a219233c9c8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30368
14961 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.3036814961
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.1352097455
Short name T295
Test name
Test status
Simulation time 22992599427 ps
CPU time 1038.77 seconds
Started Aug 13 05:46:23 PM PDT 24
Finished Aug 13 06:03:42 PM PDT 24
Peak memory 281692 kb
Host smart-8c5ffeb0-57f7-41a3-a2e0-4b9699edf5f3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1352097455 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.1352097455
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.1527672491
Short name T558
Test name
Test status
Simulation time 64836414661 ps
CPU time 887.74 seconds
Started Aug 13 05:46:22 PM PDT 24
Finished Aug 13 06:01:10 PM PDT 24
Peak memory 272784 kb
Host smart-a5100ec8-9a7c-4939-ae86-f2d0ecf1b082
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1527672491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.1527672491
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.4040522811
Short name T364
Test name
Test status
Simulation time 1004486819 ps
CPU time 37.33 seconds
Started Aug 13 05:46:17 PM PDT 24
Finished Aug 13 05:46:55 PM PDT 24
Peak memory 256984 kb
Host smart-e7fe82c9-cab8-42a3-b871-a44edb05cb16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40405
22811 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.4040522811
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.2081696916
Short name T568
Test name
Test status
Simulation time 7253862742 ps
CPU time 50.18 seconds
Started Aug 13 05:46:27 PM PDT 24
Finished Aug 13 05:47:17 PM PDT 24
Peak memory 248904 kb
Host smart-a94ce873-6dbc-40ee-9809-b9b8af51df43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20816
96916 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.2081696916
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.2392623484
Short name T504
Test name
Test status
Simulation time 2522693835 ps
CPU time 38.04 seconds
Started Aug 13 05:46:20 PM PDT 24
Finished Aug 13 05:46:58 PM PDT 24
Peak memory 257092 kb
Host smart-0a326b04-e3e2-4372-aff7-b22f00244716
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23926
23484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.2392623484
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.1697223311
Short name T643
Test name
Test status
Simulation time 24950144350 ps
CPU time 1566.91 seconds
Started Aug 13 05:46:22 PM PDT 24
Finished Aug 13 06:12:29 PM PDT 24
Peak memory 289444 kb
Host smart-b1283f96-a7ca-464e-b256-8737803781c4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1697223311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.1697223311
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.1431324690
Short name T244
Test name
Test status
Simulation time 2666365636 ps
CPU time 110.65 seconds
Started Aug 13 05:46:21 PM PDT 24
Finished Aug 13 05:48:12 PM PDT 24
Peak memory 257020 kb
Host smart-8f63c383-cd6f-4426-9f4e-f7f807030f1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14313
24690 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.1431324690
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.1685990520
Short name T474
Test name
Test status
Simulation time 562164819 ps
CPU time 31.78 seconds
Started Aug 13 05:46:27 PM PDT 24
Finished Aug 13 05:46:59 PM PDT 24
Peak memory 256428 kb
Host smart-9c1f91f7-7abd-4a97-9504-7423d930f959
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16859
90520 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.1685990520
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.2619334591
Short name T699
Test name
Test status
Simulation time 39209285971 ps
CPU time 2392.95 seconds
Started Aug 13 05:46:23 PM PDT 24
Finished Aug 13 06:26:16 PM PDT 24
Peak memory 287580 kb
Host smart-5e076f91-fda1-4e54-b972-fdc246cf8eb2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2619334591 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.2619334591
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.1370675329
Short name T419
Test name
Test status
Simulation time 128139963293 ps
CPU time 1662.14 seconds
Started Aug 13 05:46:29 PM PDT 24
Finished Aug 13 06:14:11 PM PDT 24
Peak memory 273436 kb
Host smart-c20f6d67-1b78-4c87-891a-50ed925be7af
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1370675329 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.1370675329
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.879572022
Short name T620
Test name
Test status
Simulation time 167697097 ps
CPU time 6.42 seconds
Started Aug 13 05:46:28 PM PDT 24
Finished Aug 13 05:46:35 PM PDT 24
Peak memory 248824 kb
Host smart-3df9d885-fcea-42b7-9172-6212cedb3a39
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87957
2022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.879572022
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.1303888179
Short name T376
Test name
Test status
Simulation time 327753043 ps
CPU time 24.29 seconds
Started Aug 13 05:46:28 PM PDT 24
Finished Aug 13 05:46:52 PM PDT 24
Peak memory 248236 kb
Host smart-917db913-8fc5-4bf5-9e77-fedc8d973530
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13038
88179 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.1303888179
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.2351131277
Short name T425
Test name
Test status
Simulation time 2834257910 ps
CPU time 48.04 seconds
Started Aug 13 05:46:25 PM PDT 24
Finished Aug 13 05:47:13 PM PDT 24
Peak memory 249252 kb
Host smart-cb182ae3-5a56-4dc2-92f9-41f3694b9f27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23511
31277 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.2351131277
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.208139009
Short name T640
Test name
Test status
Simulation time 324444992 ps
CPU time 24 seconds
Started Aug 13 05:46:24 PM PDT 24
Finished Aug 13 05:46:48 PM PDT 24
Peak memory 248732 kb
Host smart-1a03571f-8f4a-427e-8025-ac58c4625348
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20813
9009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.208139009
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.2438709836
Short name T243
Test name
Test status
Simulation time 162151804427 ps
CPU time 1606.36 seconds
Started Aug 13 05:46:22 PM PDT 24
Finished Aug 13 06:13:08 PM PDT 24
Peak memory 301244 kb
Host smart-3ee08e77-74c2-4748-8241-0ab5f508b296
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2438709836 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_ha
ndler_stress_all.2438709836
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all_with_rand_reset.445173826
Short name T190
Test name
Test status
Simulation time 4643340829 ps
CPU time 140.89 seconds
Started Aug 13 05:46:23 PM PDT 24
Finished Aug 13 05:48:44 PM PDT 24
Peak memory 265384 kb
Host smart-41150145-f589-4120-8d6c-d571186bcd18
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=445173826 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 23.alert_handler_stress_all_with_rand_reset.445173826
Directory /workspace/23.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.720460617
Short name T664
Test name
Test status
Simulation time 8272473408 ps
CPU time 1187.79 seconds
Started Aug 13 05:46:31 PM PDT 24
Finished Aug 13 06:06:19 PM PDT 24
Peak memory 283596 kb
Host smart-6f2aaf50-9da2-4c49-885b-800ad8a8154e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720460617 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.720460617
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.3260668156
Short name T529
Test name
Test status
Simulation time 4160119577 ps
CPU time 254.92 seconds
Started Aug 13 05:46:31 PM PDT 24
Finished Aug 13 05:50:46 PM PDT 24
Peak memory 257132 kb
Host smart-87f415ab-209c-44f2-9974-25c2e75b6885
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32606
68156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.3260668156
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.2091721810
Short name T696
Test name
Test status
Simulation time 662876798 ps
CPU time 15.88 seconds
Started Aug 13 05:46:31 PM PDT 24
Finished Aug 13 05:46:47 PM PDT 24
Peak memory 256220 kb
Host smart-f4818316-8029-45f8-b95b-23bc1553721d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20917
21810 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.2091721810
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.4037100200
Short name T279
Test name
Test status
Simulation time 17157862474 ps
CPU time 1495.82 seconds
Started Aug 13 05:46:30 PM PDT 24
Finished Aug 13 06:11:26 PM PDT 24
Peak memory 288828 kb
Host smart-63996441-f6f2-4a85-baec-e481a4cc37d9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4037100200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.4037100200
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.4020001064
Short name T313
Test name
Test status
Simulation time 7966729650 ps
CPU time 361.6 seconds
Started Aug 13 05:46:32 PM PDT 24
Finished Aug 13 05:52:34 PM PDT 24
Peak memory 256944 kb
Host smart-94cb48ca-7a64-4843-ba49-0c43921ba69f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020001064 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.4020001064
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.2922580541
Short name T453
Test name
Test status
Simulation time 369838966 ps
CPU time 26.87 seconds
Started Aug 13 05:46:31 PM PDT 24
Finished Aug 13 05:46:58 PM PDT 24
Peak memory 248804 kb
Host smart-0d264521-524e-4db8-909f-f3133fe88cf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29225
80541 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.2922580541
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.2473643881
Short name T497
Test name
Test status
Simulation time 1685937661 ps
CPU time 30.65 seconds
Started Aug 13 05:46:29 PM PDT 24
Finished Aug 13 05:47:00 PM PDT 24
Peak memory 256524 kb
Host smart-4a7529d9-3ddf-4ab8-bd25-e7c68482728a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24736
43881 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.2473643881
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.1709304812
Short name T521
Test name
Test status
Simulation time 1268598048 ps
CPU time 23.82 seconds
Started Aug 13 05:46:27 PM PDT 24
Finished Aug 13 05:46:51 PM PDT 24
Peak memory 248772 kb
Host smart-acb1fc1a-7094-4ac8-bba5-7a56fe0c59b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17093
04812 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.1709304812
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.1642702738
Short name T109
Test name
Test status
Simulation time 120373811036 ps
CPU time 2029.49 seconds
Started Aug 13 05:46:30 PM PDT 24
Finished Aug 13 06:20:19 PM PDT 24
Peak memory 286940 kb
Host smart-1ff6df79-7a12-4f99-899b-b4b45337d884
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1642702738 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_ha
ndler_stress_all.1642702738
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all_with_rand_reset.3227398210
Short name T448
Test name
Test status
Simulation time 14283971007 ps
CPU time 282.48 seconds
Started Aug 13 05:46:30 PM PDT 24
Finished Aug 13 05:51:13 PM PDT 24
Peak memory 266552 kb
Host smart-cd280f05-6eb2-43f6-8d6d-b1ec39cbcae7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3227398210 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.alert_handler_stress_all_with_rand_reset.3227398210
Directory /workspace/24.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.3323641026
Short name T636
Test name
Test status
Simulation time 25101127195 ps
CPU time 1486.95 seconds
Started Aug 13 05:46:30 PM PDT 24
Finished Aug 13 06:11:17 PM PDT 24
Peak memory 272736 kb
Host smart-8977ce07-3853-4f7e-ba02-9858bde7ef89
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3323641026 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.3323641026
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.1299141574
Short name T537
Test name
Test status
Simulation time 4857823484 ps
CPU time 110.89 seconds
Started Aug 13 05:46:32 PM PDT 24
Finished Aug 13 05:48:23 PM PDT 24
Peak memory 256548 kb
Host smart-ac85b549-7329-4b3a-9bda-23399985c5ec
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12991
41574 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.1299141574
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.2513794683
Short name T618
Test name
Test status
Simulation time 283023211 ps
CPU time 29.35 seconds
Started Aug 13 05:46:31 PM PDT 24
Finished Aug 13 05:47:00 PM PDT 24
Peak memory 248832 kb
Host smart-c87a634b-ec6c-49be-9c88-d2e02051a324
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25137
94683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.2513794683
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.2034880595
Short name T334
Test name
Test status
Simulation time 43731283477 ps
CPU time 2300.32 seconds
Started Aug 13 05:46:37 PM PDT 24
Finished Aug 13 06:24:57 PM PDT 24
Peak memory 273568 kb
Host smart-ae3f0482-1a27-4a3e-b874-8e6aee16cd6a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2034880595 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.2034880595
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.200661075
Short name T569
Test name
Test status
Simulation time 35233989403 ps
CPU time 1604.84 seconds
Started Aug 13 05:46:37 PM PDT 24
Finished Aug 13 06:13:22 PM PDT 24
Peak memory 289628 kb
Host smart-b281efd3-ed67-4022-a226-13dbb8b234b1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=200661075 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.200661075
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.3286576427
Short name T36
Test name
Test status
Simulation time 6512278897 ps
CPU time 247.66 seconds
Started Aug 13 05:46:38 PM PDT 24
Finished Aug 13 05:50:46 PM PDT 24
Peak memory 247764 kb
Host smart-31afccdc-1de5-4320-8bc3-ba67630a427a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286576427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.3286576427
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.1502198890
Short name T677
Test name
Test status
Simulation time 707980247 ps
CPU time 31.32 seconds
Started Aug 13 05:46:30 PM PDT 24
Finished Aug 13 05:47:02 PM PDT 24
Peak memory 255944 kb
Host smart-299afbf4-99da-480d-9348-81da32367baf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15021
98890 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.1502198890
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.4189221540
Short name T128
Test name
Test status
Simulation time 169597631 ps
CPU time 19.77 seconds
Started Aug 13 05:46:34 PM PDT 24
Finished Aug 13 05:46:54 PM PDT 24
Peak memory 248488 kb
Host smart-23177ef6-1f2a-43ea-9707-a8a99cb04e0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41892
21540 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.4189221540
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.1862187611
Short name T394
Test name
Test status
Simulation time 281494947 ps
CPU time 19.98 seconds
Started Aug 13 05:46:33 PM PDT 24
Finished Aug 13 05:46:53 PM PDT 24
Peak memory 249088 kb
Host smart-d7d6b0fc-5fc8-4bd8-8847-3450553f56dc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18621
87611 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.1862187611
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.3299664691
Short name T557
Test name
Test status
Simulation time 2492258040 ps
CPU time 44.12 seconds
Started Aug 13 05:46:31 PM PDT 24
Finished Aug 13 05:47:15 PM PDT 24
Peak memory 256996 kb
Host smart-4dd36be8-a086-4c26-8f9a-75be7f2befae
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32996
64691 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.3299664691
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.3477420288
Short name T124
Test name
Test status
Simulation time 5039616742 ps
CPU time 131.27 seconds
Started Aug 13 05:46:38 PM PDT 24
Finished Aug 13 05:48:50 PM PDT 24
Peak memory 257124 kb
Host smart-ef8b46e2-c37f-4934-8783-31fd44c87d0d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477420288 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_ha
ndler_stress_all.3477420288
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.390029215
Short name T103
Test name
Test status
Simulation time 21328808240 ps
CPU time 1342.59 seconds
Started Aug 13 05:46:39 PM PDT 24
Finished Aug 13 06:09:01 PM PDT 24
Peak memory 269380 kb
Host smart-84c7f0eb-f5b6-4a64-afef-413828bb4645
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390029215 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.390029215
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.849152852
Short name T559
Test name
Test status
Simulation time 10660675316 ps
CPU time 165.62 seconds
Started Aug 13 05:46:38 PM PDT 24
Finished Aug 13 05:49:23 PM PDT 24
Peak memory 256592 kb
Host smart-39ecb259-2627-40f7-ae2d-a52138945fb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84915
2852 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.849152852
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.1482331756
Short name T12
Test name
Test status
Simulation time 465801982 ps
CPU time 28.96 seconds
Started Aug 13 05:46:34 PM PDT 24
Finished Aug 13 05:47:03 PM PDT 24
Peak memory 248384 kb
Host smart-d761beed-f2dc-435a-ae6e-ce0fe1295658
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14823
31756 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.1482331756
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.300017741
Short name T646
Test name
Test status
Simulation time 191803679265 ps
CPU time 2792.46 seconds
Started Aug 13 05:46:37 PM PDT 24
Finished Aug 13 06:33:10 PM PDT 24
Peak memory 285236 kb
Host smart-18507306-225f-4a82-b6c2-039728d6d451
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=300017741 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.300017741
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.3140009252
Short name T479
Test name
Test status
Simulation time 9520453897 ps
CPU time 912.8 seconds
Started Aug 13 05:46:37 PM PDT 24
Finished Aug 13 06:01:50 PM PDT 24
Peak memory 273372 kb
Host smart-33e67b22-9ead-48cd-b755-ef0316d60305
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140009252 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.3140009252
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.2068378045
Short name T307
Test name
Test status
Simulation time 50487973517 ps
CPU time 538.52 seconds
Started Aug 13 05:46:39 PM PDT 24
Finished Aug 13 05:55:38 PM PDT 24
Peak memory 255436 kb
Host smart-c1fc0207-0084-4bea-915b-ac3e3803f3bd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2068378045 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.2068378045
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.1543507015
Short name T647
Test name
Test status
Simulation time 664361017 ps
CPU time 26.95 seconds
Started Aug 13 05:46:38 PM PDT 24
Finished Aug 13 05:47:05 PM PDT 24
Peak memory 256396 kb
Host smart-6c66607d-ecc1-48e9-af33-c13d32bd7198
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15435
07015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.1543507015
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.2081732943
Short name T429
Test name
Test status
Simulation time 336770540 ps
CPU time 20.19 seconds
Started Aug 13 05:46:38 PM PDT 24
Finished Aug 13 05:46:58 PM PDT 24
Peak memory 247972 kb
Host smart-8749afb4-2018-4a1b-be9b-770fbca5282d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20817
32943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.2081732943
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.2979457609
Short name T642
Test name
Test status
Simulation time 688950270 ps
CPU time 39.54 seconds
Started Aug 13 05:46:38 PM PDT 24
Finished Aug 13 05:47:17 PM PDT 24
Peak memory 248068 kb
Host smart-b9612e1f-f98a-4d48-ba40-180a387ffaaa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29794
57609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.2979457609
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.2240423239
Short name T407
Test name
Test status
Simulation time 435127257 ps
CPU time 41.12 seconds
Started Aug 13 05:46:36 PM PDT 24
Finished Aug 13 05:47:17 PM PDT 24
Peak memory 256980 kb
Host smart-c652e200-b5ae-42c6-88db-de65e248d3b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22404
23239 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.2240423239
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.3127383966
Short name T290
Test name
Test status
Simulation time 49295859200 ps
CPU time 1263.73 seconds
Started Aug 13 05:46:36 PM PDT 24
Finished Aug 13 06:07:40 PM PDT 24
Peak memory 286124 kb
Host smart-cac1f5cc-10e6-42a6-9d6f-9ff142bd74ad
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3127383966 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_ha
ndler_stress_all.3127383966
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.14604828
Short name T623
Test name
Test status
Simulation time 65320231327 ps
CPU time 1888.03 seconds
Started Aug 13 05:46:43 PM PDT 24
Finished Aug 13 06:18:11 PM PDT 24
Peak memory 273376 kb
Host smart-3e4fe6c1-eac6-4fbf-8651-d6c95cd00912
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=14604828 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.14604828
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.594370045
Short name T678
Test name
Test status
Simulation time 2441513982 ps
CPU time 98.52 seconds
Started Aug 13 05:46:43 PM PDT 24
Finished Aug 13 05:48:22 PM PDT 24
Peak memory 256304 kb
Host smart-1e6ab01b-421a-4450-95d6-0fe330912d8b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59437
0045 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.594370045
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.2066641815
Short name T378
Test name
Test status
Simulation time 791463369 ps
CPU time 26.57 seconds
Started Aug 13 05:46:44 PM PDT 24
Finished Aug 13 05:47:10 PM PDT 24
Peak memory 248252 kb
Host smart-3f6ebb58-b0fd-42a2-bfdd-ce4b4ae21d32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20666
41815 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.2066641815
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.4068074766
Short name T64
Test name
Test status
Simulation time 28621852693 ps
CPU time 2040.79 seconds
Started Aug 13 05:46:44 PM PDT 24
Finished Aug 13 06:20:46 PM PDT 24
Peak memory 281604 kb
Host smart-5ac72735-d111-4fe0-ab3b-41f09c873fb7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4068074766 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.4068074766
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.658382284
Short name T412
Test name
Test status
Simulation time 41370993775 ps
CPU time 1267.36 seconds
Started Aug 13 05:46:46 PM PDT 24
Finished Aug 13 06:07:53 PM PDT 24
Peak memory 265236 kb
Host smart-270ae47f-15e4-4fc8-b539-39f729d6c351
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658382284 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.658382284
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.674809568
Short name T317
Test name
Test status
Simulation time 46990572357 ps
CPU time 203.55 seconds
Started Aug 13 05:46:46 PM PDT 24
Finished Aug 13 05:50:10 PM PDT 24
Peak memory 248732 kb
Host smart-1a24beb8-3f5a-47c6-97bb-8ac4e84052a5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=674809568 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.674809568
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.28542147
Short name T473
Test name
Test status
Simulation time 4081205112 ps
CPU time 23.06 seconds
Started Aug 13 05:46:39 PM PDT 24
Finished Aug 13 05:47:03 PM PDT 24
Peak memory 248876 kb
Host smart-6905bb3d-d7f9-48da-a64e-00e209274f04
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28542
147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.28542147
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.3106072148
Short name T401
Test name
Test status
Simulation time 150113960 ps
CPU time 5.07 seconds
Started Aug 13 05:46:44 PM PDT 24
Finished Aug 13 05:46:50 PM PDT 24
Peak memory 240500 kb
Host smart-f6687d59-53f6-4ab8-9bcc-51124b45d29d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31060
72148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.3106072148
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.3096756513
Short name T265
Test name
Test status
Simulation time 426709352 ps
CPU time 27.19 seconds
Started Aug 13 05:46:46 PM PDT 24
Finished Aug 13 05:47:14 PM PDT 24
Peak memory 248520 kb
Host smart-42a6f99d-4dd0-4036-b657-353fdcbbb59d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30967
56513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.3096756513
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.1492772973
Short name T289
Test name
Test status
Simulation time 391039028 ps
CPU time 9.53 seconds
Started Aug 13 05:46:35 PM PDT 24
Finished Aug 13 05:46:45 PM PDT 24
Peak memory 254404 kb
Host smart-148ac28d-50d1-4001-9943-d0c1f65117c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14927
72973 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.1492772973
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.3767606232
Short name T420
Test name
Test status
Simulation time 17231822651 ps
CPU time 1339.85 seconds
Started Aug 13 05:46:44 PM PDT 24
Finished Aug 13 06:09:04 PM PDT 24
Peak memory 287800 kb
Host smart-23cdb027-e3d5-46c7-b957-f481de5afc49
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3767606232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_ha
ndler_stress_all.3767606232
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.2815366216
Short name T548
Test name
Test status
Simulation time 790653790 ps
CPU time 45.27 seconds
Started Aug 13 05:46:46 PM PDT 24
Finished Aug 13 05:47:31 PM PDT 24
Peak memory 256160 kb
Host smart-9af10edd-7841-4f48-8d6b-912c724592de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28153
66216 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.2815366216
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.687001820
Short name T516
Test name
Test status
Simulation time 714603513 ps
CPU time 53.36 seconds
Started Aug 13 05:46:45 PM PDT 24
Finished Aug 13 05:47:38 PM PDT 24
Peak memory 248780 kb
Host smart-26762ac1-a900-4755-95b8-4cbe474305cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68700
1820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.687001820
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.2235569009
Short name T619
Test name
Test status
Simulation time 13399333527 ps
CPU time 1158.44 seconds
Started Aug 13 05:47:02 PM PDT 24
Finished Aug 13 06:06:21 PM PDT 24
Peak memory 283660 kb
Host smart-c8664906-715a-4cf3-8962-73ad1c9ffe40
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2235569009 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.2235569009
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.1359050923
Short name T691
Test name
Test status
Simulation time 66184492679 ps
CPU time 1807.94 seconds
Started Aug 13 05:47:02 PM PDT 24
Finished Aug 13 06:17:10 PM PDT 24
Peak memory 273176 kb
Host smart-94197d2d-5b69-4160-88bc-97ce347f2362
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359050923 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.1359050923
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.2105356309
Short name T330
Test name
Test status
Simulation time 3200449588 ps
CPU time 144.16 seconds
Started Aug 13 05:46:50 PM PDT 24
Finished Aug 13 05:49:14 PM PDT 24
Peak memory 248876 kb
Host smart-3ca23c94-18e6-4b13-82a0-10348abb4eed
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105356309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.2105356309
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.137538788
Short name T417
Test name
Test status
Simulation time 244273955 ps
CPU time 22.28 seconds
Started Aug 13 05:46:44 PM PDT 24
Finished Aug 13 05:47:06 PM PDT 24
Peak memory 256292 kb
Host smart-0e34a545-3054-4938-8aad-02bb1771e240
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13753
8788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.137538788
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.3356733048
Short name T596
Test name
Test status
Simulation time 722823710 ps
CPU time 7.91 seconds
Started Aug 13 05:46:43 PM PDT 24
Finished Aug 13 05:46:51 PM PDT 24
Peak memory 250908 kb
Host smart-3db32002-dca5-406f-9582-35264eca4814
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33567
33048 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.3356733048
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.2407098329
Short name T542
Test name
Test status
Simulation time 2204228830 ps
CPU time 49.51 seconds
Started Aug 13 05:47:00 PM PDT 24
Finished Aug 13 05:47:49 PM PDT 24
Peak memory 248820 kb
Host smart-07506568-081b-46fb-b4f0-86036de6a253
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24070
98329 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.2407098329
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.856984919
Short name T432
Test name
Test status
Simulation time 4305486195 ps
CPU time 66.82 seconds
Started Aug 13 05:46:47 PM PDT 24
Finished Aug 13 05:47:54 PM PDT 24
Peak memory 257060 kb
Host smart-0c885beb-0e9a-4dfd-9829-4821ae58bc18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85698
4919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.856984919
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.542999962
Short name T266
Test name
Test status
Simulation time 1539669740 ps
CPU time 34.76 seconds
Started Aug 13 05:47:02 PM PDT 24
Finished Aug 13 05:47:37 PM PDT 24
Peak memory 256908 kb
Host smart-787a88dd-826d-4837-b99c-371b5820222e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=542999962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_han
dler_stress_all.542999962
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.82394189
Short name T493
Test name
Test status
Simulation time 73735794370 ps
CPU time 2218.44 seconds
Started Aug 13 05:47:01 PM PDT 24
Finished Aug 13 06:24:00 PM PDT 24
Peak memory 289064 kb
Host smart-58f23213-abb5-4275-b219-db16e3d146dc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=82394189 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.82394189
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.966067936
Short name T481
Test name
Test status
Simulation time 409306723 ps
CPU time 46.45 seconds
Started Aug 13 05:47:01 PM PDT 24
Finished Aug 13 05:47:48 PM PDT 24
Peak memory 256592 kb
Host smart-b8637d1c-95fa-4324-8830-f80411de717c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96606
7936 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.966067936
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.2390647078
Short name T260
Test name
Test status
Simulation time 1056922301 ps
CPU time 32.53 seconds
Started Aug 13 05:47:02 PM PDT 24
Finished Aug 13 05:47:35 PM PDT 24
Peak memory 248508 kb
Host smart-7c7cd8d0-3e15-4e50-b6bb-4a32c5860d02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23906
47078 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.2390647078
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.4038227953
Short name T561
Test name
Test status
Simulation time 93683725624 ps
CPU time 1494.61 seconds
Started Aug 13 05:47:02 PM PDT 24
Finished Aug 13 06:11:57 PM PDT 24
Peak memory 273464 kb
Host smart-1b6ea7d0-7afa-4a49-848c-7f77cda095a1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4038227953 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.4038227953
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.320658019
Short name T492
Test name
Test status
Simulation time 97779878317 ps
CPU time 2465.27 seconds
Started Aug 13 05:46:51 PM PDT 24
Finished Aug 13 06:27:57 PM PDT 24
Peak memory 283560 kb
Host smart-57ce1916-96b8-48f4-949b-65f17d23b262
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=320658019 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.320658019
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.3652825526
Short name T685
Test name
Test status
Simulation time 373521046 ps
CPU time 20.45 seconds
Started Aug 13 05:47:02 PM PDT 24
Finished Aug 13 05:47:22 PM PDT 24
Peak memory 256320 kb
Host smart-c803c872-76de-43d6-8439-599badbd60ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36528
25526 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.3652825526
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.3191263367
Short name T384
Test name
Test status
Simulation time 482277037 ps
CPU time 32.06 seconds
Started Aug 13 05:46:58 PM PDT 24
Finished Aug 13 05:47:30 PM PDT 24
Peak memory 256684 kb
Host smart-cce022d4-b93a-4d5d-b60b-dbb440f6e7f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31912
63367 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.3191263367
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.3316392873
Short name T483
Test name
Test status
Simulation time 1374261786 ps
CPU time 8.64 seconds
Started Aug 13 05:47:02 PM PDT 24
Finished Aug 13 05:47:10 PM PDT 24
Peak memory 248828 kb
Host smart-19929737-9e6f-4c7c-afa4-112e25e57570
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33163
92873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.3316392873
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.1342886090
Short name T377
Test name
Test status
Simulation time 2738188439 ps
CPU time 57.69 seconds
Started Aug 13 05:47:04 PM PDT 24
Finished Aug 13 05:48:02 PM PDT 24
Peak memory 257056 kb
Host smart-7305b9a6-22af-4f7c-9f11-48be37001296
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13428
86090 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.1342886090
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.2287898185
Short name T209
Test name
Test status
Simulation time 36889833 ps
CPU time 2.34 seconds
Started Aug 13 05:45:40 PM PDT 24
Finished Aug 13 05:45:43 PM PDT 24
Peak memory 248808 kb
Host smart-64a01be9-c516-4f6b-9fa4-ce40729f6304
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2287898185 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.2287898185
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.256220985
Short name T31
Test name
Test status
Simulation time 32003831971 ps
CPU time 1533.16 seconds
Started Aug 13 05:45:38 PM PDT 24
Finished Aug 13 06:11:11 PM PDT 24
Peak memory 272944 kb
Host smart-7edfb65c-2cbe-4bc3-b42e-c406a7492555
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=256220985 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.256220985
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.1662214529
Short name T694
Test name
Test status
Simulation time 942384291 ps
CPU time 16.63 seconds
Started Aug 13 05:45:37 PM PDT 24
Finished Aug 13 05:45:53 PM PDT 24
Peak memory 248860 kb
Host smart-8ffaa063-c82f-44c8-9d36-07fd7905d220
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1662214529 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.1662214529
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.1229217286
Short name T1
Test name
Test status
Simulation time 809515154 ps
CPU time 75.94 seconds
Started Aug 13 05:45:39 PM PDT 24
Finished Aug 13 05:46:56 PM PDT 24
Peak memory 256184 kb
Host smart-96072885-6fb0-4362-b0d6-a53359e63dfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12292
17286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.1229217286
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.910463666
Short name T261
Test name
Test status
Simulation time 235115297 ps
CPU time 18.82 seconds
Started Aug 13 05:45:30 PM PDT 24
Finished Aug 13 05:45:49 PM PDT 24
Peak memory 248148 kb
Host smart-529c08b1-3404-4538-811f-ebfe28ca72a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91046
3666 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.910463666
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.2986908960
Short name T333
Test name
Test status
Simulation time 228498283134 ps
CPU time 2448.99 seconds
Started Aug 13 05:45:39 PM PDT 24
Finished Aug 13 06:26:29 PM PDT 24
Peak memory 281708 kb
Host smart-caf81c12-167e-4f38-982d-1e4b2f90bbfd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2986908960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.2986908960
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.2731646512
Short name T32
Test name
Test status
Simulation time 20636267367 ps
CPU time 995.46 seconds
Started Aug 13 05:45:41 PM PDT 24
Finished Aug 13 06:02:17 PM PDT 24
Peak memory 289720 kb
Host smart-e74df3e2-06e3-4934-a99c-d57dda3ad65e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2731646512 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.2731646512
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.13444797
Short name T42
Test name
Test status
Simulation time 11048353380 ps
CPU time 117.39 seconds
Started Aug 13 05:45:40 PM PDT 24
Finished Aug 13 05:47:37 PM PDT 24
Peak memory 248852 kb
Host smart-683e2e81-67b4-4b5f-a5d0-9fd44ba9b373
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13444797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.13444797
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.1814466871
Short name T403
Test name
Test status
Simulation time 30286940 ps
CPU time 2.9 seconds
Started Aug 13 05:45:27 PM PDT 24
Finished Aug 13 05:45:30 PM PDT 24
Peak memory 248812 kb
Host smart-876d4372-cd0d-432e-8cde-dd55741a5e3a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18144
66871 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.1814466871
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.2623847422
Short name T113
Test name
Test status
Simulation time 1209873386 ps
CPU time 20.45 seconds
Started Aug 13 05:45:28 PM PDT 24
Finished Aug 13 05:45:49 PM PDT 24
Peak memory 248824 kb
Host smart-75407652-8613-4e01-8196-e249c25a8e20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26238
47422 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.2623847422
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.1231504547
Short name T30
Test name
Test status
Simulation time 849935281 ps
CPU time 14.17 seconds
Started Aug 13 05:45:43 PM PDT 24
Finished Aug 13 05:45:57 PM PDT 24
Peak memory 270916 kb
Host smart-72eb811d-3448-494a-ad93-247f09beae50
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1231504547 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.1231504547
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.1128735599
Short name T627
Test name
Test status
Simulation time 853779836 ps
CPU time 58.93 seconds
Started Aug 13 05:45:30 PM PDT 24
Finished Aug 13 05:46:29 PM PDT 24
Peak memory 248752 kb
Host smart-77c1dbb9-314d-4994-b56a-06a4004e88af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11287
35599 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.1128735599
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.3413504987
Short name T393
Test name
Test status
Simulation time 293781386 ps
CPU time 25.68 seconds
Started Aug 13 05:45:41 PM PDT 24
Finished Aug 13 05:46:07 PM PDT 24
Peak memory 248816 kb
Host smart-8906755b-7c05-400e-8e34-5bec44915e1d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3413504987 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_han
dler_stress_all.3413504987
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.2395254176
Short name T622
Test name
Test status
Simulation time 38895019708 ps
CPU time 2280.51 seconds
Started Aug 13 05:47:05 PM PDT 24
Finished Aug 13 06:25:06 PM PDT 24
Peak memory 288852 kb
Host smart-05c318c5-885a-42aa-b193-a66d644acbf7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2395254176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.2395254176
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.1991524438
Short name T423
Test name
Test status
Simulation time 3790730449 ps
CPU time 179.65 seconds
Started Aug 13 05:47:02 PM PDT 24
Finished Aug 13 05:50:01 PM PDT 24
Peak memory 256440 kb
Host smart-7682ed61-cc5a-4eb7-8d88-88aae98e5d65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19915
24438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.1991524438
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.1902959278
Short name T219
Test name
Test status
Simulation time 161856351 ps
CPU time 3.02 seconds
Started Aug 13 05:46:50 PM PDT 24
Finished Aug 13 05:46:54 PM PDT 24
Peak memory 239936 kb
Host smart-934dc8bf-8413-4598-9235-f3c5ba2ddba4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19029
59278 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.1902959278
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.372130949
Short name T235
Test name
Test status
Simulation time 30202017687 ps
CPU time 704.56 seconds
Started Aug 13 05:47:05 PM PDT 24
Finished Aug 13 05:58:49 PM PDT 24
Peak memory 273288 kb
Host smart-b7255674-10d5-42e5-838d-c1cd3010e70b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372130949 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.372130949
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.26917973
Short name T500
Test name
Test status
Simulation time 151094508292 ps
CPU time 2260.66 seconds
Started Aug 13 05:47:04 PM PDT 24
Finished Aug 13 06:24:45 PM PDT 24
Peak memory 281692 kb
Host smart-11ac1a06-deb5-4535-8f5d-1042b731c54d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=26917973 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.26917973
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.2650560850
Short name T550
Test name
Test status
Simulation time 2747137767 ps
CPU time 21.21 seconds
Started Aug 13 05:46:50 PM PDT 24
Finished Aug 13 05:47:11 PM PDT 24
Peak memory 248824 kb
Host smart-296b3538-4e9f-4cab-b6fb-929b8d5ecc92
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26505
60850 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.2650560850
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.3821504486
Short name T40
Test name
Test status
Simulation time 314332997 ps
CPU time 19.83 seconds
Started Aug 13 05:46:50 PM PDT 24
Finished Aug 13 05:47:10 PM PDT 24
Peak memory 256956 kb
Host smart-1ef44524-653e-4a7a-9cb3-4e7d0267ac43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38215
04486 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.3821504486
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.458195728
Short name T246
Test name
Test status
Simulation time 740594736 ps
CPU time 22.68 seconds
Started Aug 13 05:47:03 PM PDT 24
Finished Aug 13 05:47:26 PM PDT 24
Peak memory 248888 kb
Host smart-123151cc-0b0f-43e7-be0d-29d112eb8cc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=45819
5728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.458195728
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.2595349621
Short name T390
Test name
Test status
Simulation time 147437580 ps
CPU time 5.92 seconds
Started Aug 13 05:46:53 PM PDT 24
Finished Aug 13 05:46:59 PM PDT 24
Peak memory 254988 kb
Host smart-08c4cb28-38f5-46da-a8ce-8419dfd863dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25953
49621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.2595349621
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.1789454615
Short name T263
Test name
Test status
Simulation time 545814518162 ps
CPU time 2192.14 seconds
Started Aug 13 05:47:02 PM PDT 24
Finished Aug 13 06:23:35 PM PDT 24
Peak memory 289544 kb
Host smart-9f259a7f-3611-4f66-a5a4-66c7a967a4b6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1789454615 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_ha
ndler_stress_all.1789454615
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.3470570165
Short name T468
Test name
Test status
Simulation time 163106262794 ps
CPU time 2515.39 seconds
Started Aug 13 05:47:02 PM PDT 24
Finished Aug 13 06:28:58 PM PDT 24
Peak memory 289684 kb
Host smart-bfd085c0-6c94-40f4-8f56-f66fa2c9fc5b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3470570165 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.3470570165
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.3277801165
Short name T658
Test name
Test status
Simulation time 5291826193 ps
CPU time 75.79 seconds
Started Aug 13 05:47:04 PM PDT 24
Finished Aug 13 05:48:20 PM PDT 24
Peak memory 256624 kb
Host smart-aa5c2696-3f9f-493d-b5f2-112eb1207251
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32778
01165 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.3277801165
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.1498003254
Short name T485
Test name
Test status
Simulation time 304103495 ps
CPU time 7.64 seconds
Started Aug 13 05:47:01 PM PDT 24
Finished Aug 13 05:47:09 PM PDT 24
Peak memory 248396 kb
Host smart-66b169c7-ea9c-4acc-9016-8a73b3269797
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14980
03254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.1498003254
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.2289645981
Short name T232
Test name
Test status
Simulation time 123928303223 ps
CPU time 3489.16 seconds
Started Aug 13 05:47:06 PM PDT 24
Finished Aug 13 06:45:16 PM PDT 24
Peak memory 289280 kb
Host smart-c9297266-5778-4837-ac1d-f1ff5c8be758
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2289645981 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.2289645981
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.1251552202
Short name T408
Test name
Test status
Simulation time 18271748030 ps
CPU time 1052.03 seconds
Started Aug 13 05:47:01 PM PDT 24
Finished Aug 13 06:04:33 PM PDT 24
Peak memory 266236 kb
Host smart-8c0a6de2-d91c-44aa-9c60-90526e1ac637
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1251552202 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.1251552202
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.3279220894
Short name T312
Test name
Test status
Simulation time 102028431216 ps
CPU time 279.63 seconds
Started Aug 13 05:47:01 PM PDT 24
Finished Aug 13 05:51:41 PM PDT 24
Peak memory 248688 kb
Host smart-4ab56f5f-374b-4470-856a-07a852eae404
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3279220894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.3279220894
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.3344645955
Short name T437
Test name
Test status
Simulation time 71963062 ps
CPU time 6.35 seconds
Started Aug 13 05:47:04 PM PDT 24
Finished Aug 13 05:47:11 PM PDT 24
Peak memory 248852 kb
Host smart-d5e832aa-9428-44b8-b3d5-fecfc00e3b37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33446
45955 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.3344645955
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.3965293705
Short name T457
Test name
Test status
Simulation time 750620547 ps
CPU time 40.95 seconds
Started Aug 13 05:47:03 PM PDT 24
Finished Aug 13 05:47:44 PM PDT 24
Peak memory 248888 kb
Host smart-2915a14b-dbf9-4223-9543-a3669a7c9d3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39652
93705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.3965293705
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.1999025850
Short name T552
Test name
Test status
Simulation time 235292857 ps
CPU time 22.97 seconds
Started Aug 13 05:47:03 PM PDT 24
Finished Aug 13 05:47:27 PM PDT 24
Peak memory 256852 kb
Host smart-1bfabb6a-bfce-416f-b2d1-875b150a8fa0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19990
25850 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.1999025850
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.2448069591
Short name T33
Test name
Test status
Simulation time 896883813 ps
CPU time 65.71 seconds
Started Aug 13 05:47:03 PM PDT 24
Finished Aug 13 05:48:09 PM PDT 24
Peak memory 257056 kb
Host smart-8a34c93b-6c97-4feb-a776-f6292bd66726
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2448069591 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_ha
ndler_stress_all.2448069591
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.2371350926
Short name T562
Test name
Test status
Simulation time 33469865609 ps
CPU time 2330.04 seconds
Started Aug 13 05:47:09 PM PDT 24
Finished Aug 13 06:26:00 PM PDT 24
Peak memory 289200 kb
Host smart-f5c99451-7033-4de5-af6d-149a4fcf0f8f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2371350926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.2371350926
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.520706034
Short name T502
Test name
Test status
Simulation time 3496577156 ps
CPU time 75.34 seconds
Started Aug 13 05:47:07 PM PDT 24
Finished Aug 13 05:48:23 PM PDT 24
Peak memory 257024 kb
Host smart-0200577b-51d8-4d61-a895-b1e5f39ed37b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52070
6034 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.520706034
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.1484979559
Short name T680
Test name
Test status
Simulation time 317731016 ps
CPU time 27.47 seconds
Started Aug 13 05:47:05 PM PDT 24
Finished Aug 13 05:47:32 PM PDT 24
Peak memory 248864 kb
Host smart-e62cfc7c-1a5b-4ab1-add3-9c45205c5891
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14849
79559 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.1484979559
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.173325519
Short name T318
Test name
Test status
Simulation time 38956870502 ps
CPU time 2291.57 seconds
Started Aug 13 05:47:09 PM PDT 24
Finished Aug 13 06:25:21 PM PDT 24
Peak memory 289076 kb
Host smart-cbc2d892-c665-4b7b-b3d6-3a39317e2c83
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=173325519 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.173325519
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.1814914276
Short name T383
Test name
Test status
Simulation time 16022487679 ps
CPU time 1053.25 seconds
Started Aug 13 05:47:10 PM PDT 24
Finished Aug 13 06:04:43 PM PDT 24
Peak memory 282692 kb
Host smart-a0acd014-268c-4a9b-aa8e-f41063692e62
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1814914276 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.1814914276
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.51410658
Short name T635
Test name
Test status
Simulation time 9700807257 ps
CPU time 231.98 seconds
Started Aug 13 05:47:04 PM PDT 24
Finished Aug 13 05:50:57 PM PDT 24
Peak memory 248764 kb
Host smart-afc2044d-4c06-4146-9eee-09ea0e1130e8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=51410658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.51410658
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.2041387400
Short name T359
Test name
Test status
Simulation time 373430480 ps
CPU time 8.27 seconds
Started Aug 13 05:47:07 PM PDT 24
Finished Aug 13 05:47:15 PM PDT 24
Peak memory 256880 kb
Host smart-f4e83f9e-d50f-4885-a4ae-633d570fbc8c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20413
87400 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.2041387400
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.3850451468
Short name T95
Test name
Test status
Simulation time 830453781 ps
CPU time 16.49 seconds
Started Aug 13 05:47:07 PM PDT 24
Finished Aug 13 05:47:24 PM PDT 24
Peak memory 249052 kb
Host smart-5cbfb721-b16a-4fd7-a5a6-3c0c9fbe5425
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38504
51468 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.3850451468
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.808713825
Short name T247
Test name
Test status
Simulation time 1237378348 ps
CPU time 41.11 seconds
Started Aug 13 05:47:05 PM PDT 24
Finished Aug 13 05:47:46 PM PDT 24
Peak memory 248796 kb
Host smart-522817e1-32ba-4cb1-a6f3-c91589b95301
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80871
3825 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.808713825
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.4135705845
Short name T563
Test name
Test status
Simulation time 226278604 ps
CPU time 8.14 seconds
Started Aug 13 05:47:04 PM PDT 24
Finished Aug 13 05:47:12 PM PDT 24
Peak memory 252944 kb
Host smart-a130fc35-59e6-4e4d-80bf-df381f12334a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41357
05845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.4135705845
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.2028002022
Short name T608
Test name
Test status
Simulation time 8161853430 ps
CPU time 112.92 seconds
Started Aug 13 05:47:06 PM PDT 24
Finished Aug 13 05:48:59 PM PDT 24
Peak memory 257092 kb
Host smart-ea809d49-c5c3-47f0-b41d-a548e12cacd0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2028002022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_ha
ndler_stress_all.2028002022
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.2325431420
Short name T382
Test name
Test status
Simulation time 19722055780 ps
CPU time 882.53 seconds
Started Aug 13 05:47:08 PM PDT 24
Finished Aug 13 06:01:51 PM PDT 24
Peak memory 271620 kb
Host smart-81d8d4d0-8293-4432-9f07-4b8dbbef7981
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2325431420 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.2325431420
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.2346272567
Short name T386
Test name
Test status
Simulation time 1435489790 ps
CPU time 102.56 seconds
Started Aug 13 05:47:05 PM PDT 24
Finished Aug 13 05:48:48 PM PDT 24
Peak memory 256976 kb
Host smart-706bd31c-c856-4a06-84b4-0a77cf16279b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23462
72567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.2346272567
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.1681284442
Short name T416
Test name
Test status
Simulation time 195558780 ps
CPU time 4.67 seconds
Started Aug 13 05:47:09 PM PDT 24
Finished Aug 13 05:47:14 PM PDT 24
Peak memory 239952 kb
Host smart-04f335c9-6fbe-49f7-95cf-0991490ff206
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16812
84442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.1681284442
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.191637534
Short name T438
Test name
Test status
Simulation time 16846919492 ps
CPU time 1449.24 seconds
Started Aug 13 05:47:07 PM PDT 24
Finished Aug 13 06:11:16 PM PDT 24
Peak memory 284664 kb
Host smart-dd6bf92e-6b2f-4617-9b0e-fdb5f14f100e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=191637534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.191637534
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.1325291323
Short name T501
Test name
Test status
Simulation time 14821866724 ps
CPU time 1293.93 seconds
Started Aug 13 05:47:05 PM PDT 24
Finished Aug 13 06:08:40 PM PDT 24
Peak memory 281620 kb
Host smart-4cd9f17e-4b8c-49a4-a0c7-16eac7426015
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1325291323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.1325291323
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.2636191635
Short name T316
Test name
Test status
Simulation time 147900813761 ps
CPU time 328.09 seconds
Started Aug 13 05:47:10 PM PDT 24
Finished Aug 13 05:52:38 PM PDT 24
Peak memory 248696 kb
Host smart-52f467fe-f53d-408d-973a-1370faff520f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2636191635 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.2636191635
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.2550411213
Short name T112
Test name
Test status
Simulation time 247668439 ps
CPU time 25.57 seconds
Started Aug 13 05:47:06 PM PDT 24
Finished Aug 13 05:47:31 PM PDT 24
Peak memory 248876 kb
Host smart-814a9e81-673c-4da8-8d96-2c0aa4061a3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25504
11213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.2550411213
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.1377209803
Short name T23
Test name
Test status
Simulation time 146205283 ps
CPU time 9.91 seconds
Started Aug 13 05:47:09 PM PDT 24
Finished Aug 13 05:47:19 PM PDT 24
Peak memory 248740 kb
Host smart-7674887a-9ecd-4385-ba5e-e4593dd5d455
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13772
09803 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.1377209803
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.2825414079
Short name T572
Test name
Test status
Simulation time 461089539 ps
CPU time 5.95 seconds
Started Aug 13 05:47:07 PM PDT 24
Finished Aug 13 05:47:13 PM PDT 24
Peak memory 248064 kb
Host smart-bc4f3ac8-fb29-471a-b194-f431fb0ebb53
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28254
14079 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.2825414079
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.2757433299
Short name T527
Test name
Test status
Simulation time 10223456620 ps
CPU time 49.82 seconds
Started Aug 13 05:47:08 PM PDT 24
Finished Aug 13 05:47:58 PM PDT 24
Peak memory 257052 kb
Host smart-97d38b5e-0863-47a6-97b4-9aeca0f79adf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27574
33299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.2757433299
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.212760733
Short name T681
Test name
Test status
Simulation time 354305268 ps
CPU time 13.23 seconds
Started Aug 13 05:47:08 PM PDT 24
Finished Aug 13 05:47:22 PM PDT 24
Peak memory 254940 kb
Host smart-09446d66-8e47-45f4-a0e2-47df31d55e6f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=212760733 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_han
dler_stress_all.212760733
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.2260456258
Short name T567
Test name
Test status
Simulation time 2970837027 ps
CPU time 83.48 seconds
Started Aug 13 05:47:11 PM PDT 24
Finished Aug 13 05:48:35 PM PDT 24
Peak memory 256988 kb
Host smart-84284c3f-b9fd-4c72-b850-d278c7ee8c4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22604
56258 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.2260456258
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.287766458
Short name T584
Test name
Test status
Simulation time 2193050685 ps
CPU time 36.46 seconds
Started Aug 13 05:47:13 PM PDT 24
Finished Aug 13 05:47:50 PM PDT 24
Peak memory 248952 kb
Host smart-9dc1a077-bbd2-426f-a26e-384acfbf9f5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28776
6458 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.287766458
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.3289712143
Short name T336
Test name
Test status
Simulation time 706639553514 ps
CPU time 2381.57 seconds
Started Aug 13 05:47:12 PM PDT 24
Finished Aug 13 06:26:54 PM PDT 24
Peak memory 281612 kb
Host smart-42277370-6bf9-4b7e-bba1-0b9cd28791ab
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3289712143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.3289712143
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.379477489
Short name T659
Test name
Test status
Simulation time 62188028686 ps
CPU time 1536.79 seconds
Started Aug 13 05:47:20 PM PDT 24
Finished Aug 13 06:12:57 PM PDT 24
Peak memory 288964 kb
Host smart-0e72b000-af95-42b8-a6b9-d6e2bf59371d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379477489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.379477489
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.2593850543
Short name T547
Test name
Test status
Simulation time 5613781030 ps
CPU time 239.38 seconds
Started Aug 13 05:47:10 PM PDT 24
Finished Aug 13 05:51:09 PM PDT 24
Peak memory 255580 kb
Host smart-1d4a7006-a81b-41de-bdd3-bbd00347573a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2593850543 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.2593850543
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.3856710691
Short name T464
Test name
Test status
Simulation time 5005665371 ps
CPU time 76.05 seconds
Started Aug 13 05:47:15 PM PDT 24
Finished Aug 13 05:48:31 PM PDT 24
Peak memory 248732 kb
Host smart-417c23df-f8cf-4373-919a-14b1eb79d667
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38567
10691 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.3856710691
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.4211010764
Short name T406
Test name
Test status
Simulation time 110503473 ps
CPU time 8.77 seconds
Started Aug 13 05:47:18 PM PDT 24
Finished Aug 13 05:47:27 PM PDT 24
Peak memory 248280 kb
Host smart-f5ea3f44-a5a9-41c8-9a48-9127bbe688da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42110
10764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.4211010764
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.699329579
Short name T682
Test name
Test status
Simulation time 379726756 ps
CPU time 22.73 seconds
Started Aug 13 05:47:12 PM PDT 24
Finished Aug 13 05:47:35 PM PDT 24
Peak memory 248492 kb
Host smart-819992d3-f500-4a77-9dd2-dfff47c87de6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69932
9579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.699329579
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.1292131301
Short name T106
Test name
Test status
Simulation time 1942306841 ps
CPU time 59.3 seconds
Started Aug 13 05:47:06 PM PDT 24
Finished Aug 13 05:48:06 PM PDT 24
Peak memory 256396 kb
Host smart-db01b980-2a94-4278-8bdf-602791114ace
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12921
31301 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.1292131301
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all_with_rand_reset.1956144099
Short name T589
Test name
Test status
Simulation time 7686795983 ps
CPU time 426.52 seconds
Started Aug 13 05:47:13 PM PDT 24
Finished Aug 13 05:54:19 PM PDT 24
Peak memory 270760 kb
Host smart-897d9d90-cb33-49b4-beaa-728902a78cf6
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1956144099 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.alert_handler_stress_all_with_rand_reset.1956144099
Directory /workspace/34.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.2542795804
Short name T588
Test name
Test status
Simulation time 33727562 ps
CPU time 3.61 seconds
Started Aug 13 05:47:12 PM PDT 24
Finished Aug 13 05:47:16 PM PDT 24
Peak memory 240008 kb
Host smart-712e41ac-e449-4f85-92cd-249b829a8d2f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25427
95804 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.2542795804
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.4210458898
Short name T233
Test name
Test status
Simulation time 17724466789 ps
CPU time 1203.21 seconds
Started Aug 13 05:47:14 PM PDT 24
Finished Aug 13 06:07:18 PM PDT 24
Peak memory 283824 kb
Host smart-7486e002-d1a6-4cbb-9f18-e7766aaff344
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210458898 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.4210458898
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.3261194942
Short name T663
Test name
Test status
Simulation time 17393800970 ps
CPU time 1128.21 seconds
Started Aug 13 05:47:12 PM PDT 24
Finished Aug 13 06:06:01 PM PDT 24
Peak memory 273024 kb
Host smart-2441778a-ad21-43ae-906b-61ba035de4de
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3261194942 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.3261194942
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.3523558999
Short name T592
Test name
Test status
Simulation time 6463050948 ps
CPU time 268.03 seconds
Started Aug 13 05:47:20 PM PDT 24
Finished Aug 13 05:51:48 PM PDT 24
Peak memory 247724 kb
Host smart-d7492fc9-f13d-421a-951d-65498ccc7765
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3523558999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.3523558999
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.3131083950
Short name T564
Test name
Test status
Simulation time 967215386 ps
CPU time 57.2 seconds
Started Aug 13 05:47:13 PM PDT 24
Finished Aug 13 05:48:10 PM PDT 24
Peak memory 248796 kb
Host smart-9be66412-cc12-4bc1-9e35-9d8241e60f23
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31310
83950 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.3131083950
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.695893605
Short name T276
Test name
Test status
Simulation time 1850768759 ps
CPU time 15.33 seconds
Started Aug 13 05:47:20 PM PDT 24
Finished Aug 13 05:47:35 PM PDT 24
Peak memory 248316 kb
Host smart-7491404f-91e4-4b22-8b1d-817008795774
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69589
3605 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.695893605
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.505723052
Short name T684
Test name
Test status
Simulation time 223758495 ps
CPU time 24.04 seconds
Started Aug 13 05:47:13 PM PDT 24
Finished Aug 13 05:47:37 PM PDT 24
Peak memory 257020 kb
Host smart-2f56a20b-e7aa-4cf1-aff3-c6c63c83d6d6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50572
3052 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.505723052
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.3408714412
Short name T533
Test name
Test status
Simulation time 776860050 ps
CPU time 24.79 seconds
Started Aug 13 05:47:20 PM PDT 24
Finished Aug 13 05:47:45 PM PDT 24
Peak memory 256888 kb
Host smart-0deb2312-6068-45fa-98ef-05278e25ad70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34087
14412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.3408714412
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.909549622
Short name T398
Test name
Test status
Simulation time 170225515347 ps
CPU time 2295.14 seconds
Started Aug 13 05:47:12 PM PDT 24
Finished Aug 13 06:25:27 PM PDT 24
Peak memory 284132 kb
Host smart-74cf74a0-6d15-46a6-a821-1a5822999958
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=909549622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_han
dler_stress_all.909549622
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all_with_rand_reset.424176667
Short name T702
Test name
Test status
Simulation time 1903286222 ps
CPU time 123.99 seconds
Started Aug 13 05:47:15 PM PDT 24
Finished Aug 13 05:49:19 PM PDT 24
Peak memory 270340 kb
Host smart-98943877-68b7-43bd-a1d5-450157a16a6a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=424176667 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 35.alert_handler_stress_all_with_rand_reset.424176667
Directory /workspace/35.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.2737175296
Short name T603
Test name
Test status
Simulation time 37952720170 ps
CPU time 2539.96 seconds
Started Aug 13 05:47:19 PM PDT 24
Finished Aug 13 06:29:39 PM PDT 24
Peak memory 289884 kb
Host smart-b3dfd330-607c-4626-bcff-802b2fb8a0f8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2737175296 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.2737175296
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.3187773286
Short name T648
Test name
Test status
Simulation time 11175139105 ps
CPU time 162.06 seconds
Started Aug 13 05:47:17 PM PDT 24
Finished Aug 13 05:50:00 PM PDT 24
Peak memory 257068 kb
Host smart-c456eade-0845-48cc-9231-2f6efb864c07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31877
73286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.3187773286
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.3830049725
Short name T579
Test name
Test status
Simulation time 166663336 ps
CPU time 10.3 seconds
Started Aug 13 05:47:23 PM PDT 24
Finished Aug 13 05:47:33 PM PDT 24
Peak memory 248364 kb
Host smart-f1716bf2-9096-4da4-bcee-2b5c2c69239f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38300
49725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.3830049725
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.2379787762
Short name T343
Test name
Test status
Simulation time 212427412306 ps
CPU time 1813.33 seconds
Started Aug 13 05:47:20 PM PDT 24
Finished Aug 13 06:17:33 PM PDT 24
Peak memory 273452 kb
Host smart-9b94514e-0a99-4c72-8661-fb401d3a5f54
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379787762 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.2379787762
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.282287084
Short name T601
Test name
Test status
Simulation time 568254620470 ps
CPU time 3563.38 seconds
Started Aug 13 05:47:21 PM PDT 24
Finished Aug 13 06:46:45 PM PDT 24
Peak memory 289792 kb
Host smart-07d57768-e6bd-4949-af0b-5c1ef1fa4a1d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=282287084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.282287084
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.114128201
Short name T127
Test name
Test status
Simulation time 20247552400 ps
CPU time 224.09 seconds
Started Aug 13 05:47:19 PM PDT 24
Finished Aug 13 05:51:03 PM PDT 24
Peak memory 247828 kb
Host smart-ebe7a133-df8d-4c84-ae3f-e59658f9b0f2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=114128201 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.114128201
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.523567309
Short name T65
Test name
Test status
Simulation time 112384921 ps
CPU time 11.61 seconds
Started Aug 13 05:47:18 PM PDT 24
Finished Aug 13 05:47:29 PM PDT 24
Peak memory 255192 kb
Host smart-ff2bfe8c-cc01-44a5-87cc-633e14acd398
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52356
7309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.523567309
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.2858147389
Short name T531
Test name
Test status
Simulation time 732074011 ps
CPU time 16.39 seconds
Started Aug 13 05:47:22 PM PDT 24
Finished Aug 13 05:47:38 PM PDT 24
Peak memory 255968 kb
Host smart-967c01a7-23c5-4d6c-a79a-008d54234624
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28581
47389 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.2858147389
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.3058085024
Short name T629
Test name
Test status
Simulation time 35682430 ps
CPU time 2.87 seconds
Started Aug 13 05:47:19 PM PDT 24
Finished Aug 13 05:47:22 PM PDT 24
Peak memory 249196 kb
Host smart-3babf17b-e1c3-49b3-bdaf-ec7584966dd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30580
85024 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.3058085024
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.3149428262
Short name T441
Test name
Test status
Simulation time 917343529 ps
CPU time 18.65 seconds
Started Aug 13 05:47:12 PM PDT 24
Finished Aug 13 05:47:30 PM PDT 24
Peak memory 255600 kb
Host smart-03123a1f-8a0e-46f8-8e22-352c0db98410
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31494
28262 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.3149428262
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.574213303
Short name T371
Test name
Test status
Simulation time 4185354366 ps
CPU time 111.4 seconds
Started Aug 13 05:47:21 PM PDT 24
Finished Aug 13 05:49:13 PM PDT 24
Peak memory 257052 kb
Host smart-932f27f5-f352-4586-9181-b7bf095824f0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=574213303 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_han
dler_stress_all.574213303
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.1289137749
Short name T644
Test name
Test status
Simulation time 627809574822 ps
CPU time 2531.54 seconds
Started Aug 13 05:47:26 PM PDT 24
Finished Aug 13 06:29:38 PM PDT 24
Peak memory 283548 kb
Host smart-2cd076c8-90fb-45d3-b434-2af2f8c823e4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1289137749 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.1289137749
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.157175496
Short name T536
Test name
Test status
Simulation time 11210403632 ps
CPU time 182.53 seconds
Started Aug 13 05:47:29 PM PDT 24
Finished Aug 13 05:50:31 PM PDT 24
Peak memory 257012 kb
Host smart-58020a3c-0ca1-4bae-a46d-56bd1e1445a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15717
5496 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.157175496
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.516331448
Short name T385
Test name
Test status
Simulation time 3306013498 ps
CPU time 60.57 seconds
Started Aug 13 05:47:25 PM PDT 24
Finished Aug 13 05:48:26 PM PDT 24
Peak memory 256452 kb
Host smart-03c6c27e-9cce-4cac-9656-543aca61191a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=51633
1448 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.516331448
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.3726277159
Short name T414
Test name
Test status
Simulation time 40706383887 ps
CPU time 999.8 seconds
Started Aug 13 05:47:32 PM PDT 24
Finished Aug 13 06:04:12 PM PDT 24
Peak memory 273404 kb
Host smart-aec616c5-415c-4b9f-b54e-2758d0011ff4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3726277159 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.3726277159
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.4032777096
Short name T284
Test name
Test status
Simulation time 119568794907 ps
CPU time 1586.18 seconds
Started Aug 13 05:47:27 PM PDT 24
Finished Aug 13 06:13:53 PM PDT 24
Peak memory 273208 kb
Host smart-98a2dbb8-fc9a-4064-932a-4e4fd69446db
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4032777096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.4032777096
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.759711859
Short name T597
Test name
Test status
Simulation time 341715617 ps
CPU time 31.92 seconds
Started Aug 13 05:47:28 PM PDT 24
Finished Aug 13 05:48:00 PM PDT 24
Peak memory 256312 kb
Host smart-33c3f084-6dce-4046-9b67-87dc081f6882
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75971
1859 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.759711859
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.3279362223
Short name T125
Test name
Test status
Simulation time 693066267 ps
CPU time 20.89 seconds
Started Aug 13 05:47:26 PM PDT 24
Finished Aug 13 05:47:47 PM PDT 24
Peak memory 248436 kb
Host smart-e35a3406-7c1b-4354-b8a5-2212b6645280
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32793
62223 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.3279362223
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.3610607574
Short name T616
Test name
Test status
Simulation time 840939297 ps
CPU time 49 seconds
Started Aug 13 05:47:25 PM PDT 24
Finished Aug 13 05:48:14 PM PDT 24
Peak memory 256544 kb
Host smart-0e724f23-ae7c-4fa4-8775-d6cf29f2dbbe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36106
07574 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.3610607574
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.2539806403
Short name T433
Test name
Test status
Simulation time 501096682 ps
CPU time 36.75 seconds
Started Aug 13 05:47:27 PM PDT 24
Finished Aug 13 05:48:03 PM PDT 24
Peak memory 256920 kb
Host smart-d15d293c-d4d6-45f8-b2bc-eae96796260b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25398
06403 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.2539806403
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.2073773467
Short name T611
Test name
Test status
Simulation time 35208095897 ps
CPU time 1882.83 seconds
Started Aug 13 05:47:26 PM PDT 24
Finished Aug 13 06:18:49 PM PDT 24
Peak memory 287548 kb
Host smart-72b4704a-f5de-48cc-b766-00f2ac052ad1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073773467 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_ha
ndler_stress_all.2073773467
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all_with_rand_reset.117376861
Short name T444
Test name
Test status
Simulation time 2480809043 ps
CPU time 250.64 seconds
Started Aug 13 05:47:26 PM PDT 24
Finished Aug 13 05:51:37 PM PDT 24
Peak memory 265344 kb
Host smart-819436d9-feab-4aa7-8731-c7a9d596e0fb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=117376861 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 37.alert_handler_stress_all_with_rand_reset.117376861
Directory /workspace/37.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.3155655641
Short name T98
Test name
Test status
Simulation time 108073040716 ps
CPU time 3218.59 seconds
Started Aug 13 05:47:28 PM PDT 24
Finished Aug 13 06:41:07 PM PDT 24
Peak memory 289136 kb
Host smart-622e5b2d-9280-4b92-88de-c61ea3743c50
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3155655641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.3155655641
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.1351557100
Short name T665
Test name
Test status
Simulation time 8297560858 ps
CPU time 131 seconds
Started Aug 13 05:47:24 PM PDT 24
Finished Aug 13 05:49:35 PM PDT 24
Peak memory 256520 kb
Host smart-3fcd6abf-2ea1-4638-a307-62ec113ed89d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13515
57100 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.1351557100
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.731623630
Short name T447
Test name
Test status
Simulation time 170199558 ps
CPU time 10.51 seconds
Started Aug 13 05:47:23 PM PDT 24
Finished Aug 13 05:47:34 PM PDT 24
Peak memory 255072 kb
Host smart-7928df3a-8798-413a-997d-4024b9f27681
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=73162
3630 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.731623630
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.1078633628
Short name T314
Test name
Test status
Simulation time 107249578180 ps
CPU time 3268.93 seconds
Started Aug 13 05:47:34 PM PDT 24
Finished Aug 13 06:42:03 PM PDT 24
Peak memory 288784 kb
Host smart-966e6bd9-cc91-4481-9156-0f325652d787
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1078633628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.1078633628
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.3136101274
Short name T528
Test name
Test status
Simulation time 27293531893 ps
CPU time 1679.42 seconds
Started Aug 13 05:47:35 PM PDT 24
Finished Aug 13 06:15:35 PM PDT 24
Peak memory 273384 kb
Host smart-61458c75-3d18-496d-82fa-ea22516d8314
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3136101274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.3136101274
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.4210375882
Short name T309
Test name
Test status
Simulation time 28131106554 ps
CPU time 331.21 seconds
Started Aug 13 05:47:34 PM PDT 24
Finished Aug 13 05:53:06 PM PDT 24
Peak memory 248824 kb
Host smart-ed4ebfaa-a291-4383-9603-02e581e15769
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4210375882 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.4210375882
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.3829076816
Short name T524
Test name
Test status
Simulation time 398195524 ps
CPU time 35.97 seconds
Started Aug 13 05:47:27 PM PDT 24
Finished Aug 13 05:48:03 PM PDT 24
Peak memory 256256 kb
Host smart-90b44076-b68b-447e-888b-c48cb25a02bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38290
76816 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.3829076816
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.176646604
Short name T669
Test name
Test status
Simulation time 10838683504 ps
CPU time 51.34 seconds
Started Aug 13 05:47:27 PM PDT 24
Finished Aug 13 05:48:18 PM PDT 24
Peak memory 249912 kb
Host smart-56aa53b9-70c3-400a-aed3-7fb406b56125
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17664
6604 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.176646604
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.4252932336
Short name T87
Test name
Test status
Simulation time 1058243770 ps
CPU time 35.06 seconds
Started Aug 13 05:47:26 PM PDT 24
Finished Aug 13 05:48:02 PM PDT 24
Peak memory 256064 kb
Host smart-58f030a3-5f78-489f-b861-46868b28ccb4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42529
32336 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.4252932336
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.2933573427
Short name T428
Test name
Test status
Simulation time 201234174 ps
CPU time 5.6 seconds
Started Aug 13 05:47:26 PM PDT 24
Finished Aug 13 05:47:32 PM PDT 24
Peak memory 251676 kb
Host smart-fa345341-e93e-4b80-b0e4-844fcf2febf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29335
73427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.2933573427
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.2409655888
Short name T624
Test name
Test status
Simulation time 8927535222 ps
CPU time 85.96 seconds
Started Aug 13 05:47:33 PM PDT 24
Finished Aug 13 05:48:59 PM PDT 24
Peak memory 257016 kb
Host smart-47a7a429-49fb-496c-b425-c817519985ab
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2409655888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_ha
ndler_stress_all.2409655888
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all_with_rand_reset.3660029475
Short name T86
Test name
Test status
Simulation time 35018873153 ps
CPU time 430.65 seconds
Started Aug 13 05:47:35 PM PDT 24
Finished Aug 13 05:54:45 PM PDT 24
Peak memory 272004 kb
Host smart-c2d87fa4-c461-4cdb-9172-cb138301a3dd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3660029475 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 38.alert_handler_stress_all_with_rand_reset.3660029475
Directory /workspace/38.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.158970974
Short name T379
Test name
Test status
Simulation time 33865119213 ps
CPU time 2148.95 seconds
Started Aug 13 05:47:35 PM PDT 24
Finished Aug 13 06:23:24 PM PDT 24
Peak memory 287868 kb
Host smart-07467d2a-1f87-4252-95d4-26af7e81b2be
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=158970974 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.158970974
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.3519401552
Short name T591
Test name
Test status
Simulation time 16458961466 ps
CPU time 280.44 seconds
Started Aug 13 05:47:33 PM PDT 24
Finished Aug 13 05:52:14 PM PDT 24
Peak memory 257016 kb
Host smart-98d28276-04d5-47ca-a379-31b559100288
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35194
01552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.3519401552
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.2357105027
Short name T686
Test name
Test status
Simulation time 142764574 ps
CPU time 4.03 seconds
Started Aug 13 05:47:36 PM PDT 24
Finished Aug 13 05:47:40 PM PDT 24
Peak memory 240056 kb
Host smart-6a34e516-f823-4ba5-9d66-8b0a5ecf5780
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23571
05027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.2357105027
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.3419608531
Short name T498
Test name
Test status
Simulation time 90002018888 ps
CPU time 1612.29 seconds
Started Aug 13 05:47:31 PM PDT 24
Finished Aug 13 06:14:24 PM PDT 24
Peak memory 289312 kb
Host smart-45987980-21ef-4362-acc3-52b314b01e1d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3419608531 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.3419608531
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.1849025287
Short name T689
Test name
Test status
Simulation time 107826997713 ps
CPU time 1674.07 seconds
Started Aug 13 05:47:35 PM PDT 24
Finished Aug 13 06:15:29 PM PDT 24
Peak memory 273068 kb
Host smart-08fa7121-743c-400f-a834-c385f00fa869
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1849025287 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.1849025287
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.182672073
Short name T222
Test name
Test status
Simulation time 4715621403 ps
CPU time 205.82 seconds
Started Aug 13 05:47:36 PM PDT 24
Finished Aug 13 05:51:01 PM PDT 24
Peak memory 248624 kb
Host smart-5dd8419a-a7a6-47cb-9d47-04bab81faa30
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=182672073 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.182672073
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.763427056
Short name T415
Test name
Test status
Simulation time 335188206 ps
CPU time 30.33 seconds
Started Aug 13 05:47:38 PM PDT 24
Finished Aug 13 05:48:08 PM PDT 24
Peak memory 255972 kb
Host smart-8dc1598d-b2d6-44f2-b807-abaf6234a795
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76342
7056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.763427056
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.4018142008
Short name T700
Test name
Test status
Simulation time 274962735 ps
CPU time 23.08 seconds
Started Aug 13 05:47:34 PM PDT 24
Finished Aug 13 05:47:57 PM PDT 24
Peak memory 248700 kb
Host smart-b271f3fd-2084-4322-aa05-7b3bc0a0e3f4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40181
42008 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.4018142008
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.3714262890
Short name T518
Test name
Test status
Simulation time 674989665 ps
CPU time 48.46 seconds
Started Aug 13 05:47:35 PM PDT 24
Finished Aug 13 05:48:23 PM PDT 24
Peak memory 248244 kb
Host smart-a305d44b-9a63-4f52-bf0b-e9c100f6fbd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37142
62890 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.3714262890
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.2995698715
Short name T513
Test name
Test status
Simulation time 564321657 ps
CPU time 36.19 seconds
Started Aug 13 05:47:33 PM PDT 24
Finished Aug 13 05:48:10 PM PDT 24
Peak memory 257020 kb
Host smart-79822d0d-46a6-43b3-84ef-8e96fb6341d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29956
98715 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.2995698715
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.1093728246
Short name T123
Test name
Test status
Simulation time 205129978914 ps
CPU time 3381.79 seconds
Started Aug 13 05:47:38 PM PDT 24
Finished Aug 13 06:44:00 PM PDT 24
Peak memory 289356 kb
Host smart-7a37f7b1-1404-4ee3-b04a-0a10944440a8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1093728246 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_ha
ndler_stress_all.1093728246
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.2139628822
Short name T2
Test name
Test status
Simulation time 168751391 ps
CPU time 3.75 seconds
Started Aug 13 05:45:40 PM PDT 24
Finished Aug 13 05:45:44 PM PDT 24
Peak memory 249036 kb
Host smart-6c22fdef-6542-4b4d-99ef-ef42d99ca4a4
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2139628822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.2139628822
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.2337910071
Short name T484
Test name
Test status
Simulation time 13555485627 ps
CPU time 614.45 seconds
Started Aug 13 05:45:38 PM PDT 24
Finished Aug 13 05:55:53 PM PDT 24
Peak memory 271772 kb
Host smart-3f3352c3-d748-46fe-9b62-a724dcfd0a73
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2337910071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.2337910071
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.4003416377
Short name T430
Test name
Test status
Simulation time 359153059 ps
CPU time 17.49 seconds
Started Aug 13 05:45:41 PM PDT 24
Finished Aug 13 05:45:59 PM PDT 24
Peak memory 248784 kb
Host smart-5518b2ad-4ea9-4f5d-925f-da9a11b1c293
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4003416377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.4003416377
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.1024131491
Short name T221
Test name
Test status
Simulation time 1625251751 ps
CPU time 130.9 seconds
Started Aug 13 05:45:38 PM PDT 24
Finished Aug 13 05:47:49 PM PDT 24
Peak memory 257032 kb
Host smart-f0f267b1-68a2-4c87-b303-75fa58163e5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10241
31491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.1024131491
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.3350557312
Short name T683
Test name
Test status
Simulation time 49832856422 ps
CPU time 1724.87 seconds
Started Aug 13 05:45:43 PM PDT 24
Finished Aug 13 06:14:28 PM PDT 24
Peak memory 284028 kb
Host smart-5941e305-1301-48d1-921a-dca083e271ed
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3350557312 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.3350557312
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.1562946450
Short name T512
Test name
Test status
Simulation time 11392917978 ps
CPU time 1255.87 seconds
Started Aug 13 05:45:38 PM PDT 24
Finished Aug 13 06:06:34 PM PDT 24
Peak memory 289564 kb
Host smart-cd4caa9d-f4f1-43e0-8434-9751466c764d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1562946450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.1562946450
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.240205963
Short name T590
Test name
Test status
Simulation time 8001621985 ps
CPU time 150.94 seconds
Started Aug 13 05:45:39 PM PDT 24
Finished Aug 13 05:48:10 PM PDT 24
Peak memory 248720 kb
Host smart-69447ee2-5250-4d81-80bb-38987aa3a1e8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=240205963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.240205963
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.1690239463
Short name T676
Test name
Test status
Simulation time 504683011 ps
CPU time 33.2 seconds
Started Aug 13 05:45:38 PM PDT 24
Finished Aug 13 05:46:11 PM PDT 24
Peak memory 256628 kb
Host smart-3c360c67-f978-4afe-a7e6-fcada0d53404
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16902
39463 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.1690239463
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.1250787588
Short name T538
Test name
Test status
Simulation time 296916053 ps
CPU time 11 seconds
Started Aug 13 05:45:38 PM PDT 24
Finished Aug 13 05:45:49 PM PDT 24
Peak memory 248340 kb
Host smart-7858d992-a15a-4130-bda2-87bd9e9f8329
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12507
87588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.1250787588
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.3648264069
Short name T245
Test name
Test status
Simulation time 403281619 ps
CPU time 20.89 seconds
Started Aug 13 05:45:40 PM PDT 24
Finished Aug 13 05:46:01 PM PDT 24
Peak memory 249152 kb
Host smart-d61a8491-112c-498b-990d-a31125b04a4a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36482
64069 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.3648264069
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.3771734613
Short name T525
Test name
Test status
Simulation time 2246800438 ps
CPU time 33.69 seconds
Started Aug 13 05:45:39 PM PDT 24
Finished Aug 13 05:46:12 PM PDT 24
Peak memory 257020 kb
Host smart-be672f27-3313-4345-91d6-0a525dea576f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37717
34613 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.3771734613
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.2337708744
Short name T25
Test name
Test status
Simulation time 10696756657 ps
CPU time 1103.27 seconds
Started Aug 13 05:45:38 PM PDT 24
Finished Aug 13 06:04:01 PM PDT 24
Peak memory 282664 kb
Host smart-6e07218b-e34b-446c-b2aa-ced575ce88eb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2337708744 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_han
dler_stress_all.2337708744
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.1081590345
Short name T271
Test name
Test status
Simulation time 11890038805 ps
CPU time 910.36 seconds
Started Aug 13 05:47:45 PM PDT 24
Finished Aug 13 06:02:55 PM PDT 24
Peak memory 273104 kb
Host smart-7851b149-ac8a-4e8e-b498-6935d3298245
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1081590345 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.1081590345
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.3145354908
Short name T391
Test name
Test status
Simulation time 14808838010 ps
CPU time 345.97 seconds
Started Aug 13 05:47:42 PM PDT 24
Finished Aug 13 05:53:28 PM PDT 24
Peak memory 256964 kb
Host smart-d1c2dc78-ab73-4b53-9d2b-b41aeac92563
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31453
54908 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.3145354908
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.642163729
Short name T373
Test name
Test status
Simulation time 769251909 ps
CPU time 23.12 seconds
Started Aug 13 05:47:40 PM PDT 24
Finished Aug 13 05:48:04 PM PDT 24
Peak memory 248764 kb
Host smart-20ebde0b-b3ad-48bb-a32c-795c37fd670b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64216
3729 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.642163729
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.194866274
Short name T268
Test name
Test status
Simulation time 549968446028 ps
CPU time 2061.55 seconds
Started Aug 13 05:47:42 PM PDT 24
Finished Aug 13 06:22:03 PM PDT 24
Peak memory 288972 kb
Host smart-9e8404b0-acc4-4ed8-a983-60b33e4fc544
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194866274 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.194866274
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.3356844984
Short name T326
Test name
Test status
Simulation time 19751634004 ps
CPU time 404.33 seconds
Started Aug 13 05:47:42 PM PDT 24
Finished Aug 13 05:54:27 PM PDT 24
Peak memory 248876 kb
Host smart-b3c5546c-dd33-4b9e-a805-3748126b4b5f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3356844984 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.3356844984
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.2407318199
Short name T530
Test name
Test status
Simulation time 2209587446 ps
CPU time 59.61 seconds
Started Aug 13 05:47:41 PM PDT 24
Finished Aug 13 05:48:41 PM PDT 24
Peak memory 256300 kb
Host smart-4d656ed6-f68e-424f-9306-1c538fe9e60e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24073
18199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.2407318199
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.46248080
Short name T101
Test name
Test status
Simulation time 539819938 ps
CPU time 38.67 seconds
Started Aug 13 05:47:40 PM PDT 24
Finished Aug 13 05:48:19 PM PDT 24
Peak memory 248260 kb
Host smart-acb9e630-7535-44bc-a5b8-bebc6a005670
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46248
080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.46248080
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.3778890806
Short name T72
Test name
Test status
Simulation time 438247779 ps
CPU time 46.93 seconds
Started Aug 13 05:47:42 PM PDT 24
Finished Aug 13 05:48:29 PM PDT 24
Peak memory 248892 kb
Host smart-565d9088-c79f-4992-92cb-34f5d3edb5fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37788
90806 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.3778890806
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.2845590752
Short name T410
Test name
Test status
Simulation time 487570956 ps
CPU time 35.71 seconds
Started Aug 13 05:47:40 PM PDT 24
Finished Aug 13 05:48:16 PM PDT 24
Peak memory 256980 kb
Host smart-2b6bb79f-fb2e-407b-8e23-91ba1b7ec4e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28455
90752 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.2845590752
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.264583118
Short name T285
Test name
Test status
Simulation time 77223520028 ps
CPU time 1747.71 seconds
Started Aug 13 05:47:42 PM PDT 24
Finished Aug 13 06:16:50 PM PDT 24
Peak memory 297632 kb
Host smart-12feb835-c67c-4d5f-891c-fcace158b77f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=264583118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_han
dler_stress_all.264583118
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all_with_rand_reset.3511069789
Short name T24
Test name
Test status
Simulation time 4229109680 ps
CPU time 303.74 seconds
Started Aug 13 05:47:41 PM PDT 24
Finished Aug 13 05:52:45 PM PDT 24
Peak memory 273500 kb
Host smart-63ee81bd-d554-4736-b151-29e6186d8689
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511069789 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.alert_handler_stress_all_with_rand_reset.3511069789
Directory /workspace/40.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.3989144614
Short name T347
Test name
Test status
Simulation time 158784070160 ps
CPU time 2110.85 seconds
Started Aug 13 05:47:48 PM PDT 24
Finished Aug 13 06:22:59 PM PDT 24
Peak memory 289244 kb
Host smart-835d1f9f-f3e3-4a3c-b2fa-a4e5e7bb4fa7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3989144614 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.3989144614
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.1851119768
Short name T653
Test name
Test status
Simulation time 328836581 ps
CPU time 34.82 seconds
Started Aug 13 05:47:40 PM PDT 24
Finished Aug 13 05:48:15 PM PDT 24
Peak memory 256196 kb
Host smart-0c1da0b0-4958-4d53-98f3-59549a8eb68c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18511
19768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.1851119768
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.3288007682
Short name T503
Test name
Test status
Simulation time 408978880 ps
CPU time 32.54 seconds
Started Aug 13 05:47:41 PM PDT 24
Finished Aug 13 05:48:14 PM PDT 24
Peak memory 256168 kb
Host smart-97bba01f-7038-41ed-a9c0-ad4f36401875
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32880
07682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.3288007682
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.853794435
Short name T341
Test name
Test status
Simulation time 47914807805 ps
CPU time 2635.51 seconds
Started Aug 13 05:47:49 PM PDT 24
Finished Aug 13 06:31:45 PM PDT 24
Peak memory 286624 kb
Host smart-a0d52150-50c3-4ad7-86e6-8e54b6cfaaea
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=853794435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.853794435
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.3080710307
Short name T532
Test name
Test status
Simulation time 15225700999 ps
CPU time 1241.36 seconds
Started Aug 13 05:47:50 PM PDT 24
Finished Aug 13 06:08:32 PM PDT 24
Peak memory 288960 kb
Host smart-82c2aae9-749a-403e-a4dd-0e7eb61c004f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3080710307 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.3080710307
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.2994752592
Short name T306
Test name
Test status
Simulation time 26976978810 ps
CPU time 304.53 seconds
Started Aug 13 05:47:46 PM PDT 24
Finished Aug 13 05:52:51 PM PDT 24
Peak memory 248896 kb
Host smart-3e8de9e5-eaa0-4473-a438-e6253487adf6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2994752592 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.2994752592
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.1707591152
Short name T475
Test name
Test status
Simulation time 243935776 ps
CPU time 23.73 seconds
Started Aug 13 05:47:40 PM PDT 24
Finished Aug 13 05:48:04 PM PDT 24
Peak memory 248788 kb
Host smart-b71b18a1-62a7-449e-a3a8-d1d6f4eea307
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17075
91152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.1707591152
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.259535406
Short name T583
Test name
Test status
Simulation time 8098402633 ps
CPU time 31.05 seconds
Started Aug 13 05:47:42 PM PDT 24
Finished Aug 13 05:48:14 PM PDT 24
Peak memory 256396 kb
Host smart-5dfc4658-2f2a-4761-80b9-7996aa88a0fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25953
5406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.259535406
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.434060292
Short name T57
Test name
Test status
Simulation time 802836459 ps
CPU time 52.69 seconds
Started Aug 13 05:47:43 PM PDT 24
Finished Aug 13 05:48:36 PM PDT 24
Peak memory 257060 kb
Host smart-663b295d-c249-488b-bc66-652d9c031eb7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=43406
0292 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.434060292
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.2744783533
Short name T649
Test name
Test status
Simulation time 4056321980 ps
CPU time 60.99 seconds
Started Aug 13 05:47:45 PM PDT 24
Finished Aug 13 05:48:46 PM PDT 24
Peak memory 248852 kb
Host smart-7428035a-7845-4b20-baaf-d3a78c62ea38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27447
83533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.2744783533
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.593978882
Short name T560
Test name
Test status
Simulation time 93642121774 ps
CPU time 2663.13 seconds
Started Aug 13 05:47:47 PM PDT 24
Finished Aug 13 06:32:11 PM PDT 24
Peak memory 289460 kb
Host smart-80ae1f8e-deee-41f4-b8f5-0d776d47d966
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=593978882 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_han
dler_stress_all.593978882
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.2844641933
Short name T687
Test name
Test status
Simulation time 7823648581 ps
CPU time 676.58 seconds
Started Aug 13 05:47:48 PM PDT 24
Finished Aug 13 05:59:04 PM PDT 24
Peak memory 272660 kb
Host smart-8a55321a-c804-4550-80b1-fe68213368d5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2844641933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.2844641933
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.3072403662
Short name T387
Test name
Test status
Simulation time 3707131456 ps
CPU time 58.87 seconds
Started Aug 13 05:47:49 PM PDT 24
Finished Aug 13 05:48:48 PM PDT 24
Peak memory 256592 kb
Host smart-65db71dd-89ec-4916-8668-9f8ee66db391
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30724
03662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.3072403662
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.1185574978
Short name T674
Test name
Test status
Simulation time 1587358102 ps
CPU time 53.26 seconds
Started Aug 13 05:47:46 PM PDT 24
Finished Aug 13 05:48:40 PM PDT 24
Peak memory 248756 kb
Host smart-2b5cf4e4-9d77-4a62-bd2b-032f70e8357e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11855
74978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.1185574978
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.4263267232
Short name T607
Test name
Test status
Simulation time 30531402843 ps
CPU time 2018.46 seconds
Started Aug 13 05:47:47 PM PDT 24
Finished Aug 13 06:21:26 PM PDT 24
Peak memory 282900 kb
Host smart-15800a0f-7e3f-4254-a0e9-b8a7e953901e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4263267232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.4263267232
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.2725546016
Short name T454
Test name
Test status
Simulation time 67079099239 ps
CPU time 2072.21 seconds
Started Aug 13 05:47:51 PM PDT 24
Finished Aug 13 06:22:23 PM PDT 24
Peak memory 289804 kb
Host smart-e1dfe9cd-1fd0-4313-89a4-db9019750175
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2725546016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.2725546016
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.1777296482
Short name T8
Test name
Test status
Simulation time 9392456713 ps
CPU time 67.91 seconds
Started Aug 13 05:47:49 PM PDT 24
Finished Aug 13 05:48:57 PM PDT 24
Peak memory 248604 kb
Host smart-2241b80a-ddb5-428d-aa7b-5c188c5748e1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1777296482 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.1777296482
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.2959803989
Short name T281
Test name
Test status
Simulation time 712051460 ps
CPU time 32.24 seconds
Started Aug 13 05:47:50 PM PDT 24
Finished Aug 13 05:48:22 PM PDT 24
Peak memory 257020 kb
Host smart-35e56678-1148-4a43-ae36-9e8789d28a5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29598
03989 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.2959803989
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.3427529483
Short name T462
Test name
Test status
Simulation time 878429494 ps
CPU time 52.94 seconds
Started Aug 13 05:47:48 PM PDT 24
Finished Aug 13 05:48:41 PM PDT 24
Peak memory 257020 kb
Host smart-6932b2a7-ace7-460c-866a-7c9d5dc18eed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34275
29483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.3427529483
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.1238166391
Short name T79
Test name
Test status
Simulation time 3071095369 ps
CPU time 26.72 seconds
Started Aug 13 05:47:49 PM PDT 24
Finished Aug 13 05:48:16 PM PDT 24
Peak memory 248780 kb
Host smart-5eee74e3-778a-46ee-a381-8d8db3f53d01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12381
66391 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.1238166391
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.2002144969
Short name T397
Test name
Test status
Simulation time 2196600738 ps
CPU time 42.83 seconds
Started Aug 13 05:47:49 PM PDT 24
Finished Aug 13 05:48:32 PM PDT 24
Peak memory 256964 kb
Host smart-cdb230b4-3d4d-41f1-8021-ce2969dd277e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20021
44969 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.2002144969
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.3294618237
Short name T374
Test name
Test status
Simulation time 403995096 ps
CPU time 29.92 seconds
Started Aug 13 05:47:49 PM PDT 24
Finished Aug 13 05:48:19 PM PDT 24
Peak memory 248876 kb
Host smart-f75cdfde-b737-46b0-8780-d267c195b260
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3294618237 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_ha
ndler_stress_all.3294618237
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.2098759927
Short name T226
Test name
Test status
Simulation time 7935011200 ps
CPU time 92.63 seconds
Started Aug 13 05:47:49 PM PDT 24
Finished Aug 13 05:49:22 PM PDT 24
Peak memory 256320 kb
Host smart-cb832be2-b42d-4401-b4bd-b95328f2c183
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20987
59927 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.2098759927
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.25733201
Short name T578
Test name
Test status
Simulation time 192178324 ps
CPU time 18.6 seconds
Started Aug 13 05:47:49 PM PDT 24
Finished Aug 13 05:48:08 PM PDT 24
Peak memory 248660 kb
Host smart-550db1ce-5cc1-4cf9-b294-ed034a0abcf0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25733
201 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.25733201
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.538656550
Short name T286
Test name
Test status
Simulation time 10281216046 ps
CPU time 742.35 seconds
Started Aug 13 05:47:55 PM PDT 24
Finished Aug 13 06:00:18 PM PDT 24
Peak memory 272684 kb
Host smart-10633601-becd-4675-8c7d-092c5c62c11b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=538656550 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.538656550
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.606781025
Short name T461
Test name
Test status
Simulation time 41870315747 ps
CPU time 1005.7 seconds
Started Aug 13 05:47:54 PM PDT 24
Finished Aug 13 06:04:40 PM PDT 24
Peak memory 273340 kb
Host smart-9d4e42f8-69b3-46b5-a0b0-c18d8767b4ea
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=606781025 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.606781025
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.230899121
Short name T545
Test name
Test status
Simulation time 2203533931 ps
CPU time 94.01 seconds
Started Aug 13 05:47:55 PM PDT 24
Finished Aug 13 05:49:29 PM PDT 24
Peak memory 248824 kb
Host smart-199de984-867e-496f-8552-f305460a0b2f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=230899121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.230899121
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.2120991911
Short name T509
Test name
Test status
Simulation time 996321113 ps
CPU time 56.78 seconds
Started Aug 13 05:47:49 PM PDT 24
Finished Aug 13 05:48:46 PM PDT 24
Peak memory 256392 kb
Host smart-0bcac980-115c-4190-830a-cc3fe4737f4f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21209
91911 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.2120991911
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.4147432834
Short name T443
Test name
Test status
Simulation time 1914734089 ps
CPU time 32.98 seconds
Started Aug 13 05:47:45 PM PDT 24
Finished Aug 13 05:48:19 PM PDT 24
Peak memory 256384 kb
Host smart-0f4b6c83-f659-47e8-9f2a-eda68d39d878
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41474
32834 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.4147432834
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.2629791822
Short name T442
Test name
Test status
Simulation time 28459454 ps
CPU time 5.36 seconds
Started Aug 13 05:47:54 PM PDT 24
Finished Aug 13 05:48:00 PM PDT 24
Peak memory 240136 kb
Host smart-d38852ed-19b2-499e-a293-11aadf607ab3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26297
91822 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.2629791822
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.2898127568
Short name T637
Test name
Test status
Simulation time 565665735 ps
CPU time 6.13 seconds
Started Aug 13 05:47:49 PM PDT 24
Finished Aug 13 05:47:55 PM PDT 24
Peak memory 240528 kb
Host smart-435c355f-a1e6-4fcb-901a-b172e3d84d10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28981
27568 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.2898127568
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.890708163
Short name T89
Test name
Test status
Simulation time 59215811985 ps
CPU time 3346.9 seconds
Started Aug 13 05:47:54 PM PDT 24
Finished Aug 13 06:43:41 PM PDT 24
Peak memory 289484 kb
Host smart-c390f06c-6e27-4e17-adbb-93bc4599b292
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=890708163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_han
dler_stress_all.890708163
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.876893385
Short name T254
Test name
Test status
Simulation time 435334391188 ps
CPU time 1425.78 seconds
Started Aug 13 05:47:55 PM PDT 24
Finished Aug 13 06:11:41 PM PDT 24
Peak memory 273492 kb
Host smart-d65cf9e5-47ce-4f4d-bdcc-5b64e49856e8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=876893385 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.876893385
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.1473975919
Short name T399
Test name
Test status
Simulation time 2377319006 ps
CPU time 44.42 seconds
Started Aug 13 05:47:55 PM PDT 24
Finished Aug 13 05:48:39 PM PDT 24
Peak memory 257076 kb
Host smart-f0b2df97-bb9e-4c27-ba30-769a13c9c6b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14739
75919 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.1473975919
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.3558567317
Short name T418
Test name
Test status
Simulation time 865115663 ps
CPU time 28.52 seconds
Started Aug 13 05:47:53 PM PDT 24
Finished Aug 13 05:48:22 PM PDT 24
Peak memory 248032 kb
Host smart-2c0ec3e3-91b5-4d3b-99ae-d449bc729f38
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35585
67317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.3558567317
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.2578064731
Short name T298
Test name
Test status
Simulation time 234227502622 ps
CPU time 2106.97 seconds
Started Aug 13 05:47:57 PM PDT 24
Finished Aug 13 06:23:04 PM PDT 24
Peak memory 288308 kb
Host smart-d808b104-5300-4894-a45d-603ad19aa1a9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2578064731 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.2578064731
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.314539656
Short name T614
Test name
Test status
Simulation time 21853301639 ps
CPU time 1640.02 seconds
Started Aug 13 05:47:56 PM PDT 24
Finished Aug 13 06:15:16 PM PDT 24
Peak memory 289444 kb
Host smart-a719994f-201e-4b59-931b-d7b7da898b53
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=314539656 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.314539656
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.792090210
Short name T304
Test name
Test status
Simulation time 3227623617 ps
CPU time 139.16 seconds
Started Aug 13 05:47:55 PM PDT 24
Finished Aug 13 05:50:15 PM PDT 24
Peak memory 255432 kb
Host smart-5cb31396-745e-43ac-bbeb-e76b06af55f5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=792090210 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.792090210
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.2710044091
Short name T434
Test name
Test status
Simulation time 238215808 ps
CPU time 17.81 seconds
Started Aug 13 05:47:56 PM PDT 24
Finished Aug 13 05:48:14 PM PDT 24
Peak memory 248832 kb
Host smart-94246cfe-6774-44f4-9dcc-568322e2e8a5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27100
44091 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.2710044091
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.65988040
Short name T698
Test name
Test status
Simulation time 3902475411 ps
CPU time 63.18 seconds
Started Aug 13 05:47:54 PM PDT 24
Finished Aug 13 05:48:58 PM PDT 24
Peak memory 248820 kb
Host smart-b1ed1761-b9d8-4a98-ab96-59772e6a28e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65988
040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.65988040
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.3772844840
Short name T465
Test name
Test status
Simulation time 1106420293 ps
CPU time 39.03 seconds
Started Aug 13 05:47:53 PM PDT 24
Finished Aug 13 05:48:32 PM PDT 24
Peak memory 256304 kb
Host smart-2b53c7b2-1487-492b-b57f-cce0669ffd32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37728
44840 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.3772844840
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.536545643
Short name T404
Test name
Test status
Simulation time 304482146 ps
CPU time 21.28 seconds
Started Aug 13 05:47:54 PM PDT 24
Finished Aug 13 05:48:16 PM PDT 24
Peak memory 256876 kb
Host smart-3ca0e00e-b10e-496c-a883-04bd53f6e203
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53654
5643 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.536545643
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.1981035817
Short name T41
Test name
Test status
Simulation time 50805312465 ps
CPU time 767.84 seconds
Started Aug 13 05:47:55 PM PDT 24
Finished Aug 13 06:00:43 PM PDT 24
Peak memory 265272 kb
Host smart-4f078cd5-20b6-4a9b-b754-77a63a26745a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1981035817 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_ha
ndler_stress_all.1981035817
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all_with_rand_reset.1854045371
Short name T129
Test name
Test status
Simulation time 10034646148 ps
CPU time 149.13 seconds
Started Aug 13 05:48:04 PM PDT 24
Finished Aug 13 05:50:33 PM PDT 24
Peak memory 265508 kb
Host smart-8163aca7-9dc3-4d0c-b7d8-c671a3e24b6a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1854045371 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 44.alert_handler_stress_all_with_rand_reset.1854045371
Directory /workspace/44.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.2505073969
Short name T75
Test name
Test status
Simulation time 144940063167 ps
CPU time 2134.33 seconds
Started Aug 13 05:48:01 PM PDT 24
Finished Aug 13 06:23:36 PM PDT 24
Peak memory 287852 kb
Host smart-f0e70854-87a5-402f-89f3-a70ee9ed7c35
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2505073969 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.2505073969
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.1144658514
Short name T571
Test name
Test status
Simulation time 3364201481 ps
CPU time 181.68 seconds
Started Aug 13 05:48:02 PM PDT 24
Finished Aug 13 05:51:04 PM PDT 24
Peak memory 257116 kb
Host smart-176a4fc4-1892-43fc-b44a-738547688d15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11446
58514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.1144658514
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.3430921648
Short name T570
Test name
Test status
Simulation time 211774313 ps
CPU time 19.95 seconds
Started Aug 13 05:48:02 PM PDT 24
Finished Aug 13 05:48:22 PM PDT 24
Peak memory 256556 kb
Host smart-328bd607-e445-41d3-88da-c9a68df1c3a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34309
21648 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.3430921648
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.2872381119
Short name T345
Test name
Test status
Simulation time 17551570671 ps
CPU time 1566.87 seconds
Started Aug 13 05:48:03 PM PDT 24
Finished Aug 13 06:14:10 PM PDT 24
Peak memory 289220 kb
Host smart-bbe5b5f1-ecce-4534-9a73-6a59292b8c2f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2872381119 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.2872381119
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.1463483403
Short name T120
Test name
Test status
Simulation time 73832306437 ps
CPU time 970.62 seconds
Started Aug 13 05:48:14 PM PDT 24
Finished Aug 13 06:04:24 PM PDT 24
Peak memory 265176 kb
Host smart-2dbe0acb-5bc4-4326-8379-ffd8f75d5eae
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1463483403 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.1463483403
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.2189003955
Short name T332
Test name
Test status
Simulation time 2738166691 ps
CPU time 94.51 seconds
Started Aug 13 05:48:02 PM PDT 24
Finished Aug 13 05:49:37 PM PDT 24
Peak memory 248540 kb
Host smart-1dbcea0e-c7be-46c9-b74a-60c9f1326e68
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2189003955 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.2189003955
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.1459217096
Short name T650
Test name
Test status
Simulation time 196541007 ps
CPU time 13.55 seconds
Started Aug 13 05:48:01 PM PDT 24
Finished Aug 13 05:48:15 PM PDT 24
Peak memory 248880 kb
Host smart-47a0c813-ce71-48a4-b3b9-fd2230abf732
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14592
17096 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.1459217096
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.4262025090
Short name T59
Test name
Test status
Simulation time 1036268256 ps
CPU time 40.74 seconds
Started Aug 13 05:48:03 PM PDT 24
Finished Aug 13 05:48:43 PM PDT 24
Peak memory 248576 kb
Host smart-caebaccb-38dc-4d9f-8abb-aeebfece007e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42620
25090 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.4262025090
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.121475577
Short name T372
Test name
Test status
Simulation time 1182339681 ps
CPU time 22.5 seconds
Started Aug 13 05:48:01 PM PDT 24
Finished Aug 13 05:48:24 PM PDT 24
Peak memory 257048 kb
Host smart-aa46e145-9659-4866-b779-f429104acf9e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12147
5577 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.121475577
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.4013054080
Short name T615
Test name
Test status
Simulation time 191429787 ps
CPU time 24.51 seconds
Started Aug 13 05:48:02 PM PDT 24
Finished Aug 13 05:48:27 PM PDT 24
Peak memory 256668 kb
Host smart-c5421a01-a3ec-465e-8f6f-20178f68241f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40130
54080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.4013054080
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.110533319
Short name T704
Test name
Test status
Simulation time 19409388815 ps
CPU time 1833.55 seconds
Started Aug 13 05:48:03 PM PDT 24
Finished Aug 13 06:18:37 PM PDT 24
Peak memory 289848 kb
Host smart-ad18073d-1f5e-483e-b700-f883ce551d06
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=110533319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_han
dler_stress_all.110533319
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all_with_rand_reset.2069931220
Short name T482
Test name
Test status
Simulation time 1025604737 ps
CPU time 79.99 seconds
Started Aug 13 05:48:01 PM PDT 24
Finished Aug 13 05:49:21 PM PDT 24
Peak memory 265396 kb
Host smart-75eebd80-49bd-4266-a17a-7ed483d1d62b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2069931220 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.alert_handler_stress_all_with_rand_reset.2069931220
Directory /workspace/45.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.116766316
Short name T288
Test name
Test status
Simulation time 7458520229 ps
CPU time 891.22 seconds
Started Aug 13 05:48:11 PM PDT 24
Finished Aug 13 06:03:02 PM PDT 24
Peak memory 273492 kb
Host smart-d62a9145-92a1-4810-be6f-87748252d8b4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116766316 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.116766316
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.2944720281
Short name T192
Test name
Test status
Simulation time 8836825706 ps
CPU time 280.85 seconds
Started Aug 13 05:48:10 PM PDT 24
Finished Aug 13 05:52:51 PM PDT 24
Peak memory 256968 kb
Host smart-b96bc082-00ae-4537-a055-17f2c1dc2d7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29447
20281 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.2944720281
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.1847806030
Short name T581
Test name
Test status
Simulation time 358282209 ps
CPU time 17.16 seconds
Started Aug 13 05:48:12 PM PDT 24
Finished Aug 13 05:48:29 PM PDT 24
Peak memory 256928 kb
Host smart-01cb751d-0175-40be-828b-bad236abbc65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18478
06030 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.1847806030
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.767557575
Short name T344
Test name
Test status
Simulation time 20909066621 ps
CPU time 1294.18 seconds
Started Aug 13 05:48:13 PM PDT 24
Finished Aug 13 06:09:47 PM PDT 24
Peak memory 273340 kb
Host smart-10df992a-9afe-4ff0-840a-b7760976ebca
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=767557575 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.767557575
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.2818786036
Short name T69
Test name
Test status
Simulation time 37160947725 ps
CPU time 1332.43 seconds
Started Aug 13 05:48:12 PM PDT 24
Finished Aug 13 06:10:25 PM PDT 24
Peak memory 265272 kb
Host smart-67d82b91-4272-46df-9b3a-c867002c0324
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2818786036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.2818786036
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.172550741
Short name T301
Test name
Test status
Simulation time 63947875604 ps
CPU time 413.59 seconds
Started Aug 13 05:48:09 PM PDT 24
Finished Aug 13 05:55:03 PM PDT 24
Peak memory 248872 kb
Host smart-a016d5f0-c7a1-41e9-ad3b-5e2414a44eaa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=172550741 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.172550741
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.3754183888
Short name T667
Test name
Test status
Simulation time 3394171349 ps
CPU time 44.42 seconds
Started Aug 13 05:48:12 PM PDT 24
Finished Aug 13 05:48:57 PM PDT 24
Peak memory 256900 kb
Host smart-f23f09c0-3732-49eb-bbed-b0d530c24fb5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37541
83888 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.3754183888
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.2002739429
Short name T445
Test name
Test status
Simulation time 160032176 ps
CPU time 13.19 seconds
Started Aug 13 05:48:10 PM PDT 24
Finished Aug 13 05:48:23 PM PDT 24
Peak memory 248036 kb
Host smart-492a1206-6946-41c8-b413-07ff0395c7e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20027
39429 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.2002739429
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.2947885594
Short name T126
Test name
Test status
Simulation time 2369908624 ps
CPU time 15.17 seconds
Started Aug 13 05:48:14 PM PDT 24
Finished Aug 13 05:48:29 PM PDT 24
Peak memory 255584 kb
Host smart-f267d1dc-760d-476f-a820-5d8df36ab831
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29478
85594 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.2947885594
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.1980707281
Short name T688
Test name
Test status
Simulation time 932322408 ps
CPU time 54.83 seconds
Started Aug 13 05:48:13 PM PDT 24
Finished Aug 13 05:49:08 PM PDT 24
Peak memory 256980 kb
Host smart-167437ba-352c-415c-ba4c-8fe823cdf4fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19807
07281 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.1980707281
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.4144523427
Short name T78
Test name
Test status
Simulation time 71965643826 ps
CPU time 2683.45 seconds
Started Aug 13 05:48:13 PM PDT 24
Finished Aug 13 06:32:57 PM PDT 24
Peak memory 299216 kb
Host smart-a0a6b6a9-fef7-4f3d-b7c1-0af349b04ef8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4144523427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_ha
ndler_stress_all.4144523427
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all_with_rand_reset.1444213608
Short name T490
Test name
Test status
Simulation time 18846869763 ps
CPU time 305.73 seconds
Started Aug 13 05:48:09 PM PDT 24
Finished Aug 13 05:53:15 PM PDT 24
Peak memory 268672 kb
Host smart-4a32644a-a830-4853-9cb9-bb5a46c41b71
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1444213608 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.alert_handler_stress_all_with_rand_reset.1444213608
Directory /workspace/46.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.3816778197
Short name T539
Test name
Test status
Simulation time 117739179499 ps
CPU time 1096.52 seconds
Started Aug 13 05:48:11 PM PDT 24
Finished Aug 13 06:06:28 PM PDT 24
Peak memory 265260 kb
Host smart-ecc9c36f-a35e-488b-8279-b8a6fd3212ab
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3816778197 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.3816778197
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.1360092659
Short name T411
Test name
Test status
Simulation time 682376282 ps
CPU time 17.53 seconds
Started Aug 13 05:48:13 PM PDT 24
Finished Aug 13 05:48:31 PM PDT 24
Peak memory 256156 kb
Host smart-93489903-fc61-48d7-b27c-47ad83212797
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13600
92659 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.1360092659
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.3458938169
Short name T546
Test name
Test status
Simulation time 2810400564 ps
CPU time 40.26 seconds
Started Aug 13 05:48:12 PM PDT 24
Finished Aug 13 05:48:52 PM PDT 24
Peak memory 248848 kb
Host smart-9e08dd73-7ea0-4255-88df-59b1db771dce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34589
38169 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.3458938169
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.2148911983
Short name T339
Test name
Test status
Simulation time 26368061870 ps
CPU time 1467.48 seconds
Started Aug 13 05:48:20 PM PDT 24
Finished Aug 13 06:12:48 PM PDT 24
Peak memory 272732 kb
Host smart-abbd4623-bd10-4fcb-9b5d-7177afa3dd95
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2148911983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.2148911983
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.3094888848
Short name T439
Test name
Test status
Simulation time 6671513863 ps
CPU time 900.4 seconds
Started Aug 13 05:48:18 PM PDT 24
Finished Aug 13 06:03:19 PM PDT 24
Peak memory 273488 kb
Host smart-aabc1e6f-9a94-46a9-98b3-626f63699f8d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3094888848 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.3094888848
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.3781200476
Short name T303
Test name
Test status
Simulation time 29460818110 ps
CPU time 64.5 seconds
Started Aug 13 05:48:26 PM PDT 24
Finished Aug 13 05:49:31 PM PDT 24
Peak memory 253496 kb
Host smart-2274b2c4-75df-43aa-aaa6-a2801ff414d6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3781200476 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.3781200476
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.3120471083
Short name T478
Test name
Test status
Simulation time 119530382 ps
CPU time 7.28 seconds
Started Aug 13 05:48:11 PM PDT 24
Finished Aug 13 05:48:18 PM PDT 24
Peak memory 248848 kb
Host smart-f578a1ab-e4a3-4410-9294-b98c80341af7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31204
71083 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.3120471083
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.2755088238
Short name T641
Test name
Test status
Simulation time 781930879 ps
CPU time 49.45 seconds
Started Aug 13 05:48:14 PM PDT 24
Finished Aug 13 05:49:03 PM PDT 24
Peak memory 256096 kb
Host smart-708c2400-d0a7-4d90-8350-014a36f76c76
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27550
88238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.2755088238
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.4037137571
Short name T507
Test name
Test status
Simulation time 333977081 ps
CPU time 23.25 seconds
Started Aug 13 05:48:10 PM PDT 24
Finished Aug 13 05:48:34 PM PDT 24
Peak memory 256528 kb
Host smart-fea48a8c-06a5-429b-ac02-85b880e3f020
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40371
37571 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.4037137571
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.3402341741
Short name T191
Test name
Test status
Simulation time 1053978288 ps
CPU time 23.35 seconds
Started Aug 13 05:48:12 PM PDT 24
Finished Aug 13 05:48:35 PM PDT 24
Peak memory 248752 kb
Host smart-bf87556e-ba04-41ed-a259-e9c812f18eb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34023
41741 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.3402341741
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.88635276
Short name T48
Test name
Test status
Simulation time 13156780819 ps
CPU time 1206.02 seconds
Started Aug 13 05:48:17 PM PDT 24
Finished Aug 13 06:08:23 PM PDT 24
Peak memory 289868 kb
Host smart-f6f12b08-05d0-4e69-8336-1d0905f634eb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88635276 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.88635276
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.700145449
Short name T431
Test name
Test status
Simulation time 7689334193 ps
CPU time 113.68 seconds
Started Aug 13 05:48:23 PM PDT 24
Finished Aug 13 05:50:17 PM PDT 24
Peak memory 256336 kb
Host smart-39c77a2f-5cf6-4ac4-bcab-cb7d558dc2cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70014
5449 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.700145449
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.1389766333
Short name T612
Test name
Test status
Simulation time 1209169719 ps
CPU time 22.14 seconds
Started Aug 13 05:48:18 PM PDT 24
Finished Aug 13 05:48:40 PM PDT 24
Peak memory 248100 kb
Host smart-a1b660bb-32d0-486d-bfb1-337f9bbfda07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13897
66333 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.1389766333
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.1545934763
Short name T695
Test name
Test status
Simulation time 22155299391 ps
CPU time 1086.59 seconds
Started Aug 13 05:48:16 PM PDT 24
Finished Aug 13 06:06:23 PM PDT 24
Peak memory 273056 kb
Host smart-89523cbc-0fd1-431b-af97-cb7797cb4459
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1545934763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.1545934763
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.4049046680
Short name T315
Test name
Test status
Simulation time 6743233439 ps
CPU time 139.55 seconds
Started Aug 13 05:48:18 PM PDT 24
Finished Aug 13 05:50:38 PM PDT 24
Peak memory 248868 kb
Host smart-43d4bffd-3d81-4637-a413-67112e49081d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4049046680 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.4049046680
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.4283428488
Short name T362
Test name
Test status
Simulation time 270773947 ps
CPU time 6.54 seconds
Started Aug 13 05:48:18 PM PDT 24
Finished Aug 13 05:48:25 PM PDT 24
Peak memory 251420 kb
Host smart-f88166e5-7e41-43f6-9708-872f4eac106e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42834
28488 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.4283428488
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.3135807462
Short name T460
Test name
Test status
Simulation time 109807740 ps
CPU time 6.44 seconds
Started Aug 13 05:48:26 PM PDT 24
Finished Aug 13 05:48:33 PM PDT 24
Peak memory 254228 kb
Host smart-40fb9f03-9306-40b0-a98f-7b85d8fd343f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31358
07462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.3135807462
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.2986639773
Short name T690
Test name
Test status
Simulation time 1901516389 ps
CPU time 28.43 seconds
Started Aug 13 05:48:26 PM PDT 24
Finished Aug 13 05:48:55 PM PDT 24
Peak memory 255964 kb
Host smart-a7b6c498-8e40-469c-93e1-3dcaeec9e96d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29866
39773 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.2986639773
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.2920131812
Short name T477
Test name
Test status
Simulation time 203945831 ps
CPU time 14.21 seconds
Started Aug 13 05:48:18 PM PDT 24
Finished Aug 13 05:48:32 PM PDT 24
Peak memory 248808 kb
Host smart-9c1c11ba-1b4d-489f-8b1c-8dc03452cff3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29201
31812 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.2920131812
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.673855641
Short name T630
Test name
Test status
Simulation time 1065514790 ps
CPU time 95.65 seconds
Started Aug 13 05:48:15 PM PDT 24
Finished Aug 13 05:49:51 PM PDT 24
Peak memory 257032 kb
Host smart-aaaaab4a-e045-40ca-83b6-994e8bf93a03
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=673855641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_han
dler_stress_all.673855641
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.720363937
Short name T605
Test name
Test status
Simulation time 36312675579 ps
CPU time 2106.57 seconds
Started Aug 13 05:48:25 PM PDT 24
Finished Aug 13 06:23:32 PM PDT 24
Peak memory 273360 kb
Host smart-52e9db2c-852f-46f5-aa0d-12ee166dc5eb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=720363937 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.720363937
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.2503450133
Short name T469
Test name
Test status
Simulation time 2846440807 ps
CPU time 148.89 seconds
Started Aug 13 05:48:25 PM PDT 24
Finished Aug 13 05:50:54 PM PDT 24
Peak memory 256504 kb
Host smart-126fafa4-574f-4855-b507-244c18c2357c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25034
50133 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.2503450133
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.3401657771
Short name T693
Test name
Test status
Simulation time 1819754314 ps
CPU time 30.94 seconds
Started Aug 13 05:48:26 PM PDT 24
Finished Aug 13 05:48:57 PM PDT 24
Peak memory 256532 kb
Host smart-3bd04b44-6916-4389-a616-b0603d1e7653
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34016
57771 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.3401657771
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.1310741157
Short name T329
Test name
Test status
Simulation time 47080943207 ps
CPU time 1534.07 seconds
Started Aug 13 05:48:25 PM PDT 24
Finished Aug 13 06:13:59 PM PDT 24
Peak memory 272688 kb
Host smart-b1968044-8548-4491-9e10-2c4bdc55bee4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1310741157 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.1310741157
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.532497515
Short name T452
Test name
Test status
Simulation time 98940110185 ps
CPU time 1321.89 seconds
Started Aug 13 05:48:25 PM PDT 24
Finished Aug 13 06:10:27 PM PDT 24
Peak memory 272372 kb
Host smart-1f091215-1554-415b-8316-be4b0372a4a3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=532497515 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.532497515
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.760997144
Short name T389
Test name
Test status
Simulation time 1592005650 ps
CPU time 38.09 seconds
Started Aug 13 05:48:24 PM PDT 24
Finished Aug 13 05:49:03 PM PDT 24
Peak memory 256328 kb
Host smart-d2bde1ed-af38-4a78-9b36-38ea5176ea6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76099
7144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.760997144
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.4206925039
Short name T99
Test name
Test status
Simulation time 1069508439 ps
CPU time 20.29 seconds
Started Aug 13 05:48:24 PM PDT 24
Finished Aug 13 05:48:45 PM PDT 24
Peak memory 248808 kb
Host smart-ece347db-78df-4d0d-a82b-94f8d835363f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42069
25039 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.4206925039
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.2243863094
Short name T28
Test name
Test status
Simulation time 2113887423 ps
CPU time 18.9 seconds
Started Aug 13 05:48:25 PM PDT 24
Finished Aug 13 05:48:44 PM PDT 24
Peak memory 248832 kb
Host smart-f2ec875a-aea2-48b2-843f-c7779d39b4ac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22438
63094 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.2243863094
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.1418929292
Short name T654
Test name
Test status
Simulation time 2963808132 ps
CPU time 45.31 seconds
Started Aug 13 05:48:28 PM PDT 24
Finished Aug 13 05:49:13 PM PDT 24
Peak memory 256436 kb
Host smart-85f2dee5-f79e-47bd-a6e9-8fa5b8c78f9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14189
29292 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.1418929292
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.274786041
Short name T211
Test name
Test status
Simulation time 29107477 ps
CPU time 3.11 seconds
Started Aug 13 05:45:38 PM PDT 24
Finished Aug 13 05:45:41 PM PDT 24
Peak memory 248892 kb
Host smart-484c7c39-a85d-4dac-a8bb-dbd464872119
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=274786041 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.274786041
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.1328042629
Short name T228
Test name
Test status
Simulation time 35976780589 ps
CPU time 2232.16 seconds
Started Aug 13 05:45:39 PM PDT 24
Finished Aug 13 06:22:52 PM PDT 24
Peak memory 289448 kb
Host smart-c8f6b5b5-a5a8-4f62-995c-dcc454dd260d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1328042629 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.1328042629
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.1964798625
Short name T541
Test name
Test status
Simulation time 529578751 ps
CPU time 16.73 seconds
Started Aug 13 05:45:38 PM PDT 24
Finished Aug 13 05:45:55 PM PDT 24
Peak memory 248736 kb
Host smart-f2bfa654-8c86-470e-81e2-623945abb8ae
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1964798625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.1964798625
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.3616599576
Short name T657
Test name
Test status
Simulation time 824541360 ps
CPU time 48.84 seconds
Started Aug 13 05:45:40 PM PDT 24
Finished Aug 13 05:46:29 PM PDT 24
Peak memory 257012 kb
Host smart-de8d7659-714b-4ec3-90f5-aa967fee6cc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36165
99576 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.3616599576
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.2241405286
Short name T459
Test name
Test status
Simulation time 1371169356 ps
CPU time 45.58 seconds
Started Aug 13 05:45:39 PM PDT 24
Finished Aug 13 05:46:25 PM PDT 24
Peak memory 248840 kb
Host smart-b6ab0c64-f524-4ee3-ae38-2fb87adf5da9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22414
05286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.2241405286
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.3436683774
Short name T348
Test name
Test status
Simulation time 252613036908 ps
CPU time 1782.59 seconds
Started Aug 13 05:45:39 PM PDT 24
Finished Aug 13 06:15:21 PM PDT 24
Peak memory 273428 kb
Host smart-0946c943-99fa-4538-8961-d8e4afbed43c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3436683774 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.3436683774
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.2088918002
Short name T638
Test name
Test status
Simulation time 57267485780 ps
CPU time 1895.93 seconds
Started Aug 13 05:45:42 PM PDT 24
Finished Aug 13 06:17:18 PM PDT 24
Peak memory 273372 kb
Host smart-1c8c4a6d-fd13-48c0-a3a5-49df7dbe82ec
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2088918002 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.2088918002
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.983522166
Short name T671
Test name
Test status
Simulation time 78755890254 ps
CPU time 520.87 seconds
Started Aug 13 05:45:40 PM PDT 24
Finished Aug 13 05:54:21 PM PDT 24
Peak memory 255600 kb
Host smart-4988895b-5103-4f17-8587-2b2abe551bb4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=983522166 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.983522166
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.3279290444
Short name T446
Test name
Test status
Simulation time 3303432136 ps
CPU time 48.53 seconds
Started Aug 13 05:45:39 PM PDT 24
Finished Aug 13 05:46:28 PM PDT 24
Peak memory 256344 kb
Host smart-823aab96-a474-4aec-9e2e-d9216c76df29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32792
90444 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.3279290444
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.4112246071
Short name T610
Test name
Test status
Simulation time 268714357 ps
CPU time 22.96 seconds
Started Aug 13 05:45:38 PM PDT 24
Finished Aug 13 05:46:01 PM PDT 24
Peak memory 248336 kb
Host smart-2f5b2ada-c09e-4fdf-87a7-0ab352502e4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41122
46071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.4112246071
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.315091125
Short name T367
Test name
Test status
Simulation time 28083346 ps
CPU time 2.75 seconds
Started Aug 13 05:45:38 PM PDT 24
Finished Aug 13 05:45:41 PM PDT 24
Peak memory 256864 kb
Host smart-f3ec6730-a272-470d-9653-6e2b622dc996
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31509
1125 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.315091125
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.5909450
Short name T210
Test name
Test status
Simulation time 45525282 ps
CPU time 2.06 seconds
Started Aug 13 05:45:39 PM PDT 24
Finished Aug 13 05:45:41 PM PDT 24
Peak memory 248996 kb
Host smart-3279316e-89d4-4ba8-983e-0251983af889
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=5909450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.5909450
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.2040476319
Short name T708
Test name
Test status
Simulation time 63627703874 ps
CPU time 1138.27 seconds
Started Aug 13 05:45:40 PM PDT 24
Finished Aug 13 06:04:39 PM PDT 24
Peak memory 288976 kb
Host smart-3019cf9f-8f92-4411-bf35-ec9abfeb5aa2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2040476319 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.2040476319
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.4074546884
Short name T61
Test name
Test status
Simulation time 673790708 ps
CPU time 30.32 seconds
Started Aug 13 05:45:43 PM PDT 24
Finished Aug 13 05:46:14 PM PDT 24
Peak memory 248748 kb
Host smart-b7426bdc-5c50-4963-a41b-14710cfe2420
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4074546884 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.4074546884
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.1009120200
Short name T489
Test name
Test status
Simulation time 15445682832 ps
CPU time 235.34 seconds
Started Aug 13 05:45:39 PM PDT 24
Finished Aug 13 05:49:35 PM PDT 24
Peak memory 256964 kb
Host smart-0a65c27b-d24a-465e-8350-c2f78db467f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10091
20200 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.1009120200
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.2871227349
Short name T231
Test name
Test status
Simulation time 2261075402 ps
CPU time 63.01 seconds
Started Aug 13 05:45:39 PM PDT 24
Finished Aug 13 05:46:43 PM PDT 24
Peak memory 248868 kb
Host smart-4f73b131-efd3-4ee3-a570-f8b5953076b5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28712
27349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.2871227349
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.3067374806
Short name T321
Test name
Test status
Simulation time 43030785745 ps
CPU time 2432.86 seconds
Started Aug 13 05:45:40 PM PDT 24
Finished Aug 13 06:26:13 PM PDT 24
Peak memory 281628 kb
Host smart-10471d5e-d53e-4bb0-aa71-b7f0ce94e719
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3067374806 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.3067374806
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.3384351985
Short name T97
Test name
Test status
Simulation time 111430570418 ps
CPU time 3295.89 seconds
Started Aug 13 05:45:40 PM PDT 24
Finished Aug 13 06:40:36 PM PDT 24
Peak memory 289516 kb
Host smart-2de9f9a1-6b63-467a-806a-2617f120a5dc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3384351985 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.3384351985
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.332818322
Short name T327
Test name
Test status
Simulation time 10432745874 ps
CPU time 429.1 seconds
Started Aug 13 05:45:41 PM PDT 24
Finished Aug 13 05:52:51 PM PDT 24
Peak memory 248884 kb
Host smart-804b8059-381c-45ad-9ec6-b94273c32962
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=332818322 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.332818322
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.3755918302
Short name T476
Test name
Test status
Simulation time 762450249 ps
CPU time 57.63 seconds
Started Aug 13 05:45:38 PM PDT 24
Finished Aug 13 05:46:36 PM PDT 24
Peak memory 256112 kb
Host smart-487f3049-4b6e-4864-9f60-bce3785ed97f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37559
18302 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.3755918302
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.4257527349
Short name T551
Test name
Test status
Simulation time 1196719471 ps
CPU time 25.71 seconds
Started Aug 13 05:45:38 PM PDT 24
Finished Aug 13 05:46:04 PM PDT 24
Peak memory 248872 kb
Host smart-ae97626f-66b0-4231-ac6d-09ecc8c43577
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42575
27349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.4257527349
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.2385058142
Short name T278
Test name
Test status
Simulation time 744965379 ps
CPU time 56.29 seconds
Started Aug 13 05:45:37 PM PDT 24
Finished Aug 13 05:46:33 PM PDT 24
Peak memory 256324 kb
Host smart-243ef813-a7c3-40ea-a2d1-0697a77f2470
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23850
58142 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.2385058142
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.3840440392
Short name T361
Test name
Test status
Simulation time 2543364956 ps
CPU time 44.81 seconds
Started Aug 13 05:45:38 PM PDT 24
Finished Aug 13 05:46:23 PM PDT 24
Peak memory 257060 kb
Host smart-13315ab5-49d3-4e6c-b625-6950bc2550d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38404
40392 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.3840440392
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.3706963728
Short name T218
Test name
Test status
Simulation time 50463734 ps
CPU time 2.98 seconds
Started Aug 13 05:45:42 PM PDT 24
Finished Aug 13 05:45:45 PM PDT 24
Peak memory 248932 kb
Host smart-98d38ee3-f444-4c36-b41f-d91636a1378d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3706963728 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.3706963728
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.2221619502
Short name T223
Test name
Test status
Simulation time 773029200 ps
CPU time 31.96 seconds
Started Aug 13 05:45:41 PM PDT 24
Finished Aug 13 05:46:13 PM PDT 24
Peak memory 248856 kb
Host smart-e8ccc993-73aa-4b2c-a993-370946906c73
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2221619502 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.2221619502
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.1363255691
Short name T575
Test name
Test status
Simulation time 3517280189 ps
CPU time 61.64 seconds
Started Aug 13 05:45:40 PM PDT 24
Finished Aug 13 05:46:42 PM PDT 24
Peak memory 256508 kb
Host smart-c75d2ea8-3e83-45b2-a5a5-3f9bc8051a2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13632
55691 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.1363255691
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.2584012114
Short name T511
Test name
Test status
Simulation time 184951936 ps
CPU time 8.73 seconds
Started Aug 13 05:45:43 PM PDT 24
Finished Aug 13 05:45:51 PM PDT 24
Peak memory 248804 kb
Host smart-ed5015a1-f9ad-44d8-924b-dddffa062430
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25840
12114 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.2584012114
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.1421239831
Short name T18
Test name
Test status
Simulation time 101690922461 ps
CPU time 1518.03 seconds
Started Aug 13 05:45:42 PM PDT 24
Finished Aug 13 06:11:00 PM PDT 24
Peak memory 272364 kb
Host smart-5409279f-ff9d-4454-8f07-0ffb416f347c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1421239831 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.1421239831
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.638332635
Short name T70
Test name
Test status
Simulation time 26725553929 ps
CPU time 1276.14 seconds
Started Aug 13 05:45:40 PM PDT 24
Finished Aug 13 06:06:56 PM PDT 24
Peak memory 289008 kb
Host smart-2516ca24-f928-47de-8011-c089c0cb9ea6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=638332635 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.638332635
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.778323341
Short name T16
Test name
Test status
Simulation time 7885890196 ps
CPU time 171.84 seconds
Started Aug 13 05:45:43 PM PDT 24
Finished Aug 13 05:48:35 PM PDT 24
Peak memory 248888 kb
Host smart-39d0f161-b0b5-4aa0-88d2-0f1217fd6539
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=778323341 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.778323341
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.1810413192
Short name T53
Test name
Test status
Simulation time 239682817 ps
CPU time 17.04 seconds
Started Aug 13 05:45:37 PM PDT 24
Finished Aug 13 05:45:54 PM PDT 24
Peak memory 248860 kb
Host smart-3c79c970-72eb-4c2a-b1ae-878ad04e7c90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18104
13192 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.1810413192
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.2211774806
Short name T587
Test name
Test status
Simulation time 905391285 ps
CPU time 65.4 seconds
Started Aug 13 05:45:41 PM PDT 24
Finished Aug 13 05:46:46 PM PDT 24
Peak memory 248856 kb
Host smart-a7e0eb26-ba49-4800-aa90-56e9b9f08fa1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22117
74806 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.2211774806
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.576348770
Short name T544
Test name
Test status
Simulation time 44122082 ps
CPU time 6.62 seconds
Started Aug 13 05:45:40 PM PDT 24
Finished Aug 13 05:45:47 PM PDT 24
Peak memory 253392 kb
Host smart-74470cef-9bb8-411c-af6a-9ed35953d6f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57634
8770 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.576348770
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.3199200569
Short name T365
Test name
Test status
Simulation time 2181199631 ps
CPU time 29.91 seconds
Started Aug 13 05:45:42 PM PDT 24
Finished Aug 13 05:46:12 PM PDT 24
Peak memory 256960 kb
Host smart-d097e75d-ebb4-45d6-a166-e3873746e19f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31992
00569 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.3199200569
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.803101613
Short name T670
Test name
Test status
Simulation time 133523929212 ps
CPU time 1699.44 seconds
Started Aug 13 05:45:45 PM PDT 24
Finished Aug 13 06:14:04 PM PDT 24
Peak memory 273504 kb
Host smart-95396055-2197-4b4f-8080-ff7c62b79514
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=803101613 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_hand
ler_stress_all.803101613
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all_with_rand_reset.2353842962
Short name T115
Test name
Test status
Simulation time 1988673195 ps
CPU time 201.89 seconds
Started Aug 13 05:45:45 PM PDT 24
Finished Aug 13 05:49:07 PM PDT 24
Peak memory 273568 kb
Host smart-8a869677-12f2-4514-8a10-a0f0e9318497
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2353842962 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.alert_handler_stress_all_with_rand_reset.2353842962
Directory /workspace/7.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.2812102133
Short name T217
Test name
Test status
Simulation time 13812024 ps
CPU time 2.72 seconds
Started Aug 13 05:45:55 PM PDT 24
Finished Aug 13 05:45:58 PM PDT 24
Peak memory 248928 kb
Host smart-8fa0aee0-5162-4835-ac16-9e92b187a6d0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2812102133 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.2812102133
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.2886722491
Short name T577
Test name
Test status
Simulation time 38385769684 ps
CPU time 950.83 seconds
Started Aug 13 05:45:44 PM PDT 24
Finished Aug 13 06:01:35 PM PDT 24
Peak memory 273208 kb
Host smart-3e86213f-4f48-4910-8ebd-3994d9648cb7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2886722491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.2886722491
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.4235282491
Short name T38
Test name
Test status
Simulation time 1009545589 ps
CPU time 42.04 seconds
Started Aug 13 05:45:46 PM PDT 24
Finished Aug 13 05:46:28 PM PDT 24
Peak memory 248832 kb
Host smart-5a6cbe90-4ed5-40c4-9481-f55e9b20f418
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4235282491 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.4235282491
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.70255221
Short name T553
Test name
Test status
Simulation time 1820909810 ps
CPU time 107.97 seconds
Started Aug 13 05:45:44 PM PDT 24
Finished Aug 13 05:47:32 PM PDT 24
Peak memory 257008 kb
Host smart-400790a3-edc4-4808-bff6-8f55d6457ec0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=70255
221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.70255221
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.725813606
Short name T692
Test name
Test status
Simulation time 1828996765 ps
CPU time 53.69 seconds
Started Aug 13 05:45:38 PM PDT 24
Finished Aug 13 05:46:32 PM PDT 24
Peak memory 248740 kb
Host smart-38ddc8d8-aa85-45d4-a085-0689242f3e59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72581
3606 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.725813606
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.2441012360
Short name T342
Test name
Test status
Simulation time 189371323262 ps
CPU time 1089.65 seconds
Started Aug 13 05:45:40 PM PDT 24
Finished Aug 13 06:03:49 PM PDT 24
Peak memory 289108 kb
Host smart-2cac3b94-9792-4ad8-a473-5cbb7b8aeab8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2441012360 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.2441012360
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.2554224191
Short name T14
Test name
Test status
Simulation time 32133375412 ps
CPU time 1239.38 seconds
Started Aug 13 05:45:40 PM PDT 24
Finished Aug 13 06:06:20 PM PDT 24
Peak memory 289784 kb
Host smart-64f560b0-84f9-4eae-84c1-84cf07132fde
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2554224191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.2554224191
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.801174335
Short name T463
Test name
Test status
Simulation time 417426169 ps
CPU time 40.37 seconds
Started Aug 13 05:45:41 PM PDT 24
Finished Aug 13 05:46:22 PM PDT 24
Peak memory 248676 kb
Host smart-2aa19e5b-cf15-4761-9c28-c89f434be9ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80117
4335 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.801174335
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.180784407
Short name T491
Test name
Test status
Simulation time 420149208 ps
CPU time 33.92 seconds
Started Aug 13 05:45:44 PM PDT 24
Finished Aug 13 05:46:18 PM PDT 24
Peak memory 248296 kb
Host smart-a1fdd04f-ad17-45d2-9d41-4cb9a849a20c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18078
4407 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.180784407
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.4066526749
Short name T375
Test name
Test status
Simulation time 452441448 ps
CPU time 28.54 seconds
Started Aug 13 05:45:44 PM PDT 24
Finished Aug 13 05:46:13 PM PDT 24
Peak memory 248060 kb
Host smart-f7e8bee5-47d2-46ca-88bc-8dd7ea78344f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40665
26749 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.4066526749
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.260501783
Short name T368
Test name
Test status
Simulation time 67595511 ps
CPU time 8.12 seconds
Started Aug 13 05:45:42 PM PDT 24
Finished Aug 13 05:45:50 PM PDT 24
Peak memory 255120 kb
Host smart-d96aeeb3-7909-481c-a27a-6ba144237738
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26050
1783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.260501783
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.3175157199
Short name T26
Test name
Test status
Simulation time 8691791857 ps
CPU time 1123.96 seconds
Started Aug 13 05:45:45 PM PDT 24
Finished Aug 13 06:04:29 PM PDT 24
Peak memory 287476 kb
Host smart-2a571d9f-dc45-4b0f-b380-9f190d17f316
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3175157199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_han
dler_stress_all.3175157199
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.3608422481
Short name T214
Test name
Test status
Simulation time 239488969 ps
CPU time 4.4 seconds
Started Aug 13 05:45:55 PM PDT 24
Finished Aug 13 05:45:59 PM PDT 24
Peak memory 249024 kb
Host smart-1dd8802c-48c2-434b-b45b-c7354be1ed17
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3608422481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.3608422481
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.1570289905
Short name T117
Test name
Test status
Simulation time 47916089585 ps
CPU time 1252.86 seconds
Started Aug 13 05:45:47 PM PDT 24
Finished Aug 13 06:06:40 PM PDT 24
Peak memory 288040 kb
Host smart-e9a30a4f-19a6-46ad-ac46-5e64fb2e7828
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1570289905 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.1570289905
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.1594489808
Short name T628
Test name
Test status
Simulation time 1599588044 ps
CPU time 68.9 seconds
Started Aug 13 05:45:53 PM PDT 24
Finished Aug 13 05:47:02 PM PDT 24
Peak memory 248788 kb
Host smart-81a17c81-b8cd-4173-b89f-4dca85f4d7a6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1594489808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.1594489808
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.4207267869
Short name T242
Test name
Test status
Simulation time 3803835654 ps
CPU time 116.08 seconds
Started Aug 13 05:45:53 PM PDT 24
Finished Aug 13 05:47:50 PM PDT 24
Peak memory 256504 kb
Host smart-af992a13-4f47-4e68-a7a8-ce021825f000
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42072
67869 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.4207267869
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.2627781783
Short name T300
Test name
Test status
Simulation time 92573572 ps
CPU time 6.39 seconds
Started Aug 13 05:45:46 PM PDT 24
Finished Aug 13 05:45:53 PM PDT 24
Peak memory 240184 kb
Host smart-f831a710-5924-4a91-8aa1-b010fa9aac54
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26277
81783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.2627781783
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.194853366
Short name T554
Test name
Test status
Simulation time 39612505531 ps
CPU time 2220.02 seconds
Started Aug 13 05:45:55 PM PDT 24
Finished Aug 13 06:22:55 PM PDT 24
Peak memory 272964 kb
Host smart-5d619331-b7ba-4b8c-9a54-8c29f971e2bf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=194853366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.194853366
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.3695216933
Short name T395
Test name
Test status
Simulation time 36399237830 ps
CPU time 2189.71 seconds
Started Aug 13 05:45:48 PM PDT 24
Finished Aug 13 06:22:18 PM PDT 24
Peak memory 289160 kb
Host smart-8f6f2913-8b21-4437-b74b-e2e63a0083e8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3695216933 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.3695216933
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.1647882743
Short name T672
Test name
Test status
Simulation time 7802127722 ps
CPU time 347.27 seconds
Started Aug 13 05:45:55 PM PDT 24
Finished Aug 13 05:51:42 PM PDT 24
Peak memory 248712 kb
Host smart-b515e77f-6200-4499-b78d-fea0fa3012c6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1647882743 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.1647882743
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.3761592527
Short name T273
Test name
Test status
Simulation time 33629255 ps
CPU time 5.43 seconds
Started Aug 13 05:45:46 PM PDT 24
Finished Aug 13 05:45:52 PM PDT 24
Peak memory 248848 kb
Host smart-f5d84ff3-65db-4644-b415-e9d0c90e703a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37615
92527 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.3761592527
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.3623117425
Short name T472
Test name
Test status
Simulation time 1723689671 ps
CPU time 29.69 seconds
Started Aug 13 05:45:46 PM PDT 24
Finished Aug 13 05:46:16 PM PDT 24
Peak memory 248844 kb
Host smart-5ddd7296-f120-4442-a74a-e5b5d4a1edb0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36231
17425 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.3623117425
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.1971972713
Short name T661
Test name
Test status
Simulation time 119102033 ps
CPU time 11.51 seconds
Started Aug 13 05:45:47 PM PDT 24
Finished Aug 13 05:45:59 PM PDT 24
Peak memory 256348 kb
Host smart-51b456e7-1b19-4a6f-a7d1-230a9c72b867
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19719
72713 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.1971972713
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.3179767515
Short name T574
Test name
Test status
Simulation time 667645266 ps
CPU time 22.03 seconds
Started Aug 13 05:45:53 PM PDT 24
Finished Aug 13 05:46:15 PM PDT 24
Peak memory 248696 kb
Host smart-c6c0bbd5-cec7-4390-b35a-5231fac225bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31797
67515 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.3179767515
Directory /workspace/9.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.3005045370
Short name T258
Test name
Test status
Simulation time 50158920823 ps
CPU time 1135.58 seconds
Started Aug 13 05:45:53 PM PDT 24
Finished Aug 13 06:04:48 PM PDT 24
Peak memory 288736 kb
Host smart-58e4894e-0eef-41a0-a58c-fff6ee5b12a1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3005045370 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_han
dler_stress_all.3005045370
Directory /workspace/9.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all_with_rand_reset.2047456844
Short name T58
Test name
Test status
Simulation time 2104181732 ps
CPU time 162.13 seconds
Started Aug 13 05:45:46 PM PDT 24
Finished Aug 13 05:48:28 PM PDT 24
Peak memory 265392 kb
Host smart-e29b80d0-8f28-478e-b4dd-69333b549914
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2047456844 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.alert_handler_stress_all_with_rand_reset.2047456844
Directory /workspace/9.alert_handler_stress_all_with_rand_reset/latest
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