Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	49302	1			T5	21		T17	1		T35	3025
class_i[0x1]	72206	1			T5	5		T23	23		T13	6
class_i[0x2]	45467	1			T5	6		T6	23		T17	5
class_i[0x3]	48079	1			T49	1394		T18	12		T20	4938

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	53666	1			T5	7		T6	3		T17	1
alert[0x1]	57647	1			T5	6		T6	3		T17	2
alert[0x2]	53556	1			T5	13		T6	17		T17	2
alert[0x3]	50185	1			T5	6		T17	1		T49	3

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

214795

1

T5

32

T6

23

T17

6

esc_ping_fail

259

1

T13

6

T14

4

T15

2

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	53590	1			T5	7		T6	3		T17	1
esc_integrity_fail	alert[0x1]	57586	1			T5	6		T6	3		T17	2
esc_integrity_fail	alert[0x2]	53494	1			T5	13		T6	17		T17	2
esc_integrity_fail	alert[0x3]	50125	1			T5	6		T17	1		T49	3
esc_ping_fail	alert[0x0]	76	1			T13	3		T14	2		T302	2
esc_ping_fail	alert[0x1]	61	1			T13	1		T14	1		T302	1
esc_ping_fail	alert[0x2]	62	1			T13	1		T14	1		T15	1
esc_ping_fail	alert[0x3]	60	1			T13	1		T15	1		T302	1

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	49247	1			T5	21		T17	1		T35	3025
esc_integrity_fail	class_i[0x1]	72121	1			T5	5		T23	23		T74	11
esc_integrity_fail	class_i[0x2]	45407	1			T5	6		T6	23		T17	5
esc_integrity_fail	class_i[0x3]	48020	1			T49	1394		T18	12		T20	4938
esc_ping_fail	class_i[0x0]	55	1			T14	2		T302	6		T227	1
esc_ping_fail	class_i[0x1]	85	1			T13	6		T227	9		T102	1
esc_ping_fail	class_i[0x2]	60	1			T14	1		T15	2		T40	4
esc_ping_fail	class_i[0x3]	59	1			T14	1		T227	1		T309	1