Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	530889237	0	0	627
tb.dut.u_edn_req.u_prim_packer_fifo.ValidOPairedWithReadyI_A	0	0	530889237	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AckPKnownO_A	0	0	530889237	530716672	0	0
tb.dut.CheckAccuCntDw	0	0	627	627	0	0
tb.dut.CheckEscCntDw	0	0	627	627	0	0
tb.dut.CheckNAlerts	0	0	627	627	0	0
tb.dut.CheckNClasses	0	0	627	627	0	0
tb.dut.CheckNEscSev	0	0	627	627	0	0
tb.dut.CrashdumpKnownO_A	0	0	530889237	530716672	0	0
tb.dut.EdnKnownO_A	0	0	530889237	530716672	0	0
tb.dut.EscPKnownO_A	0	0	530889237	530716672	0	0
tb.dut.FpvSecCmPingTimerCnterCheck_A	0	0	530889237	80	0	0
tb.dut.FpvSecCmPingTimerDoubleLfsrCheck_A	0	0	530889237	80	0	0
tb.dut.FpvSecCmPingTimerEscCnterCheck_A	0	0	530889237	80	0	0
tb.dut.FpvSecCmPingTimerFsmCheck_A	0	0	530889237	80	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	530889237	80	0	0
tb.dut.IrqAKnownO_A	0	0	530889237	530716672	0	0
tb.dut.IrqBKnownO_A	0	0	530889237	530716672	0	0
tb.dut.IrqCKnownO_A	0	0	530889237	530716672	0	0
tb.dut.IrqDKnownO_A	0	0	530889237	530716672	0	0
tb.dut.TlAReadyKnownO_A	0	0	530889237	530716672	0	0
tb.dut.TlDValidKnownO_A	0	0	530889237	530716672	0	0
tb.dut.alert_handler_csr_assert.TlulOOBAddrErr_A	0	0	559313181	218897	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_0_rd_A	0	0	559313181	14806	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_10_rd_A	0	0	559313181	13873	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_11_rd_A	0	0	559313181	13786	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_12_rd_A	0	0	559313181	14369	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_13_rd_A	0	0	559313181	13910	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_14_rd_A	0	0	559313181	14244	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_15_rd_A	0	0	559313181	13905	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_16_rd_A	0	0	559313181	13931	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_17_rd_A	0	0	559313181	14349	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_18_rd_A	0	0	559313181	14342	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_19_rd_A	0	0	559313181	14312	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_1_rd_A	0	0	559313181	14070	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_20_rd_A	0	0	559313181	14269	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_21_rd_A	0	0	559313181	14139	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_22_rd_A	0	0	559313181	14436	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_23_rd_A	0	0	559313181	14324	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_24_rd_A	0	0	559313181	14335	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_25_rd_A	0	0	559313181	14223	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_26_rd_A	0	0	559313181	14062	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_27_rd_A	0	0	559313181	14178	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_28_rd_A	0	0	559313181	14199	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_29_rd_A	0	0	559313181	14395	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_2_rd_A	0	0	559313181	14024	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_30_rd_A	0	0	559313181	14510	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_31_rd_A	0	0	559313181	13990	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_32_rd_A	0	0	559313181	14236	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_33_rd_A	0	0	559313181	13798	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_34_rd_A	0	0	559313181	14236	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_35_rd_A	0	0	559313181	14635	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_36_rd_A	0	0	559313181	14171	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_37_rd_A	0	0	559313181	14338	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_38_rd_A	0	0	559313181	14451	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_39_rd_A	0	0	559313181	14315	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_3_rd_A	0	0	559313181	13927	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_40_rd_A	0	0	559313181	14122	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_41_rd_A	0	0	559313181	14313	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_42_rd_A	0	0	559313181	14641	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_43_rd_A	0	0	559313181	14282	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_44_rd_A	0	0	559313181	13985	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_45_rd_A	0	0	559313181	14005	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_46_rd_A	0	0	559313181	14397	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_47_rd_A	0	0	559313181	14248	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_48_rd_A	0	0	559313181	14220	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_49_rd_A	0	0	559313181	14296	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_4_rd_A	0	0	559313181	14121	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_50_rd_A	0	0	559313181	13870	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_51_rd_A	0	0	559313181	14310	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_52_rd_A	0	0	559313181	14594	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_53_rd_A	0	0	559313181	14256	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_54_rd_A	0	0	559313181	14362	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_55_rd_A	0	0	559313181	14065	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_56_rd_A	0	0	559313181	13979	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_57_rd_A	0	0	559313181	14142	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_58_rd_A	0	0	559313181	14004	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_59_rd_A	0	0	559313181	14227	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_5_rd_A	0	0	559313181	13956	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_60_rd_A	0	0	559313181	14291	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_61_rd_A	0	0	559313181	14100	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_62_rd_A	0	0	559313181	14384	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_63_rd_A	0	0	559313181	14431	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_64_rd_A	0	0	559313181	14307	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_6_rd_A	0	0	559313181	14132	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_7_rd_A	0	0	559313181	14403	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_8_rd_A	0	0	559313181	14161	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_9_rd_A	0	0	559313181	14302	0	0
tb.dut.alert_handler_csr_assert.classa_regwen_rd_A	0	0	559313181	14270	0	0
tb.dut.alert_handler_csr_assert.classb_regwen_rd_A	0	0	559313181	14134	0	0
tb.dut.alert_handler_csr_assert.classc_regwen_rd_A	0	0	559313181	14269	0	0
tb.dut.alert_handler_csr_assert.classd_regwen_rd_A	0	0	559313181	14225	0	0
tb.dut.alert_handler_csr_assert.intr_enable_rd_A	0	0	559313181	26864	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_0_rd_A	0	0	559313181	14219	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_1_rd_A	0	0	559313181	14286	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_2_rd_A	0	0	559313181	14314	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_3_rd_A	0	0	559313181	13868	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_4_rd_A	0	0	559313181	14475	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_5_rd_A	0	0	559313181	14532	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_6_rd_A	0	0	559313181	14144	0	0
tb.dut.alert_handler_csr_assert.ping_timer_regwen_rd_A	0	0	559313181	14211	0	0
tb.dut.gen_classes[0].FpvSecCmAccuCnterCheck_A	0	0	530889237	80	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerCnterCheck_A	0	0	530889237	80	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerFsmCheck_A	0	0	530889237	80	0	0
tb.dut.gen_classes[0].u_accu.CountSaturateStable_A	0	0	530889237	2170	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigBkwd_A	0	0	530889237	161341	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigFwd_A	0	0	530889237	269214049	0	0
tb.dut.gen_classes[0].u_esc_timer.AccuFailToFsmError_A	0	0	530889237	249	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig0_A	0	0	530889237	797	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig1_A	0	0	530889237	47	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckClr_A	0	0	530889237	412	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckEn_A	0	0	530510716	212884941	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase0_A	0	0	530889237	879	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase1_A	0	0	530889237	849	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase2_A	0	0	530889237	825	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase3_A	0	0	530889237	806	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeout0_A	0	0	530889237	1035	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt1_A	0	0	530889237	127035	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt2_A	0	0	530889237	925	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutStTrig_A	0	0	530889237	62	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStAllEscAsserted_A	0	0	530889237	1260	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStIsTerminal_A	0	0	530889237	1020	0	0
tb.dut.gen_classes[0].u_esc_timer.EscStateOut_A	0	0	530508707	530437852	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs.AssertConnected_A	0	0	627	627	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs_A	0	0	530889237	530716672	0	0
tb.dut.gen_classes[1].FpvSecCmAccuCnterCheck_A	0	0	530889237	80	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerCnterCheck_A	0	0	530889237	80	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerFsmCheck_A	0	0	530889237	80	0	0
tb.dut.gen_classes[1].u_accu.CountSaturateStable_A	0	0	530889237	2565	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigBkwd_A	0	0	530889237	130862	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigFwd_A	0	0	530889237	300863845	0	0
tb.dut.gen_classes[1].u_esc_timer.AccuFailToFsmError_A	0	0	530889237	250	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig0_A	0	0	530889237	470	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig1_A	0	0	530889237	16	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckClr_A	0	0	530889237	195	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckEn_A	0	0	530510716	237898104	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase0_A	0	0	530889237	516	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase1_A	0	0	530889237	502	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase2_A	0	0	530889237	493	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase3_A	0	0	530889237	483	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeout0_A	0	0	530889237	1377	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt1_A	0	0	530889237	171616	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt2_A	0	0	530889237	1313	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutStTrig_A	0	0	530889237	45	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStAllEscAsserted_A	0	0	530889237	1314	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStIsTerminal_A	0	0	530889237	1074	0	0
tb.dut.gen_classes[1].u_esc_timer.EscStateOut_A	0	0	530508707	530437852	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs.AssertConnected_A	0	0	627	627	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs_A	0	0	530889237	530716672	0	0
tb.dut.gen_classes[2].FpvSecCmAccuCnterCheck_A	0	0	530889237	80	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerCnterCheck_A	0	0	530889237	80	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerFsmCheck_A	0	0	530889237	80	0	0
tb.dut.gen_classes[2].u_accu.CountSaturateStable_A	0	0	530889237	6911	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigBkwd_A	0	0	530889237	217983	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigFwd_A	0	0	530889237	271793995	0	0
tb.dut.gen_classes[2].u_esc_timer.AccuFailToFsmError_A	0	0	530889237	229	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig0_A	0	0	530889237	511	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig1_A	0	0	530889237	21	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckClr_A	0	0	530889237	240	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckEn_A	0	0	530510716	219162738	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase0_A	0	0	530889237	573	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase1_A	0	0	530889237	556	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase2_A	0	0	530889237	542	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase3_A	0	0	530889237	537	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeout0_A	0	0	530889237	1245	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt1_A	0	0	530889237	140407	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt2_A	0	0	530889237	1162	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutStTrig_A	0	0	530889237	59	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStAllEscAsserted_A	0	0	530889237	1268	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStIsTerminal_A	0	0	530889237	1028	0	0
tb.dut.gen_classes[2].u_esc_timer.EscStateOut_A	0	0	530508707	530437852	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs.AssertConnected_A	0	0	627	627	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs_A	0	0	530889237	530716672	0	0
tb.dut.gen_classes[3].FpvSecCmAccuCnterCheck_A	0	0	530889237	80	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerCnterCheck_A	0	0	530889237	80	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerFsmCheck_A	0	0	530889237	80	0	0
tb.dut.gen_classes[3].u_accu.CountSaturateStable_A	0	0	530889237	2151	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigBkwd_A	0	0	530889237	155215	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigFwd_A	0	0	530889237	295144736	0	0
tb.dut.gen_classes[3].u_esc_timer.AccuFailToFsmError_A	0	0	530889237	242	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig0_A	0	0	530889237	517	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig1_A	0	0	530889237	20	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckClr_A	0	0	530889237	235	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckEn_A	0	0	530510716	215936444	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase0_A	0	0	530889237	562	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase1_A	0	0	530889237	553	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase2_A	0	0	530889237	540	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase3_A	0	0	530889237	531	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeout0_A	0	0	530889237	432	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt1_A	0	0	530889237	54862	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt2_A	0	0	530889237	363	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutStTrig_A	0	0	530889237	45	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStAllEscAsserted_A	0	0	530889237	1308	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStIsTerminal_A	0	0	530889237	1068	0	0
tb.dut.gen_classes[3].u_esc_timer.EscStateOut_A	0	0	530508707	530437852	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs.AssertConnected_A	0	0	627	627	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs_A	0	0	530889237	530716672	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	559313181	80697464	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	559313181	558631359	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	559313181	558631359	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	559313181	140312286	0	0
tb.dut.tlul_assert_device.dKnown_AKnownEnable	0	0	559313181	558631359	0	0
tb.dut.tlul_assert_device.dReadyKnown_A	0	0	559313181	558631359	0	0
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tb.dut.tlul_assert_device.gen_assert_final[178].noOutstandingReqsAtEndOfSim_A	0	0	832	832	0	0
tb.dut.tlul_assert_device.gen_assert_final[179].noOutstandingReqsAtEndOfSim_A	0	0	832	832	0	0
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tb.dut.tlul_assert_device.gen_assert_final[191].noOutstandingReqsAtEndOfSim_A	0	0	832	832	0	0
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tb.dut.tlul_assert_device.gen_assert_final[193].noOutstandingReqsAtEndOfSim_A	0	0	832	832	0	0
tb.dut.tlul_assert_device.gen_assert_final[194].noOutstandingReqsAtEndOfSim_A	0	0	832	832	0	0
tb.dut.tlul_assert_device.gen_assert_final[195].noOutstandingReqsAtEndOfSim_A	0	0	832	832	0	0
tb.dut.tlul_assert_device.gen_assert_final[196].noOutstandingReqsAtEndOfSim_A	0	0	832	832	0	0
tb.dut.tlul_assert_device.gen_assert_final[197].noOutstandingReqsAtEndOfSim_A	0	0	832	832	0	0
tb.dut.tlul_assert_device.gen_assert_final[198].noOutstandingReqsAtEndOfSim_A	0	0	832	832	0	0

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