Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.61	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	44	2	42	95.45

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_sig_index_cp	4	0	4	100.00	100	1	1	0
esc_sig_len_cp	11	0	11	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
len_per_esc_sig	44	2	42	95.45	100	1	1	0

Summary for Variable esc_sig_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_sig_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	176	1			T10	1		T5	1		T22	1
index[0x1]	163	1			T5	1		T11	1		T17	1
index[0x2]	176	1			T1	4		T48	1		T33	1
index[0x3]	194	1			T1	2		T10	1		T6	3

---

Summary for Variable esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for esc_sig_len_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
lens_less_than_1000[0]	244	1			T1	6		T6	2		T245	1
lens_less_than_1000[1]	142	1			T10	2		T11	1		T12	1
lens_less_than_1000[2]	89	1			T21	1		T22	1		T48	1
lens_less_than_1000[3]	72	1			T5	1		T48	1		T32	1
lens_less_than_1000[4]	50	1			T5	1		T11	1		T32	1
lens_less_than_1000[5]	49	1			T17	2		T30	1		T25	3
lens_less_than_1000[6]	18	1			T41	1		T26	1		T53	1
lens_less_than_1000[7]	18	1			T33	1		T71	1		T53	1
lens_less_than_1000[8]	13	1			T24	1		T72	1		T103	1
lens_less_than_1000[9]	4	1			T32	1		T24	1		T117	1
len_2	10	1			T6	1		T266	1		T272	1

---

Summary for Cross len_per_esc_sig

Samples crossed: esc_sig_index_cp esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	44	2	42	95.45	2

Automatically Generated Cross Bins for len_per_esc_sig

Uncovered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	NUMBER	STATUS
[index[0x0] , index[0x1]]	[lens_less_than_1000[9]]	--	--	2

Covered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	lens_less_than_1000[0]	62	1			T245	1		T69	1		T24	1
index[0x0]	lens_less_than_1000[1]	28	1			T10	1		T31	1		T71	1
index[0x0]	lens_less_than_1000[2]	29	1			T22	1		T48	1		T94	1
index[0x0]	lens_less_than_1000[3]	22	1			T5	1		T67	1		T41	1
index[0x0]	lens_less_than_1000[4]	10	1			T29	1		T273	1		T274	1
index[0x0]	lens_less_than_1000[5]	11	1			T53	1		T275	1		T106	1
index[0x0]	lens_less_than_1000[6]	4	1			T41	1		T276	1		T277	1
index[0x0]	lens_less_than_1000[7]	3	1			T278	1		T279	2		-	-
index[0x0]	lens_less_than_1000[8]	5	1			T24	1		T72	1		T59	2
index[0x0]	len_2	2	1			T266	1		T280	1		-	-
index[0x1]	lens_less_than_1000[0]	47	1			T31	1		T69	1		T40	1
index[0x1]	lens_less_than_1000[1]	40	1			T11	1		T35	1		T32	1
index[0x1]	lens_less_than_1000[2]	23	1			T44	1		T281	1		T62	1
index[0x1]	lens_less_than_1000[3]	17	1			T32	1		T78	1		T36	1
index[0x1]	lens_less_than_1000[4]	13	1			T5	1		T32	1		T114	1
index[0x1]	lens_less_than_1000[5]	8	1			T17	1		T54	1		T282	1
index[0x1]	lens_less_than_1000[6]	5	1			T26	1		T283	1		T257	1
index[0x1]	lens_less_than_1000[7]	4	1			T57	1		T284	1		T285	2
index[0x1]	lens_less_than_1000[8]	5	1			T103	1		T286	1		T287	1
index[0x1]	len_2	1	1			T272	1		-	-		-	-
index[0x2]	lens_less_than_1000[0]	71	1			T1	4		T31	1		T67	4
index[0x2]	lens_less_than_1000[1]	29	1			T41	1		T37	1		T46	1
index[0x2]	lens_less_than_1000[2]	15	1			T29	2		T288	1		T110	1
index[0x2]	lens_less_than_1000[3]	15	1			T48	1		T83	1		T59	1
index[0x2]	lens_less_than_1000[4]	11	1			T51	1		T26	1		T61	1
index[0x2]	lens_less_than_1000[5]	16	1			T25	3		T75	1		T52	1
index[0x2]	lens_less_than_1000[6]	3	1			T53	1		T289	2		-	-
index[0x2]	lens_less_than_1000[7]	6	1			T33	1		T71	1		T290	1
index[0x2]	lens_less_than_1000[8]	2	1			T291	1		T292	1		-	-
index[0x2]	lens_less_than_1000[9]	3	1			T32	1		T117	1		T293	1
index[0x2]	len_2	5	1			T294	1		T269	3		T295	1
index[0x3]	lens_less_than_1000[0]	64	1			T1	2		T6	2		T23	1
index[0x3]	lens_less_than_1000[1]	45	1			T10	1		T12	1		T31	1
index[0x3]	lens_less_than_1000[2]	22	1			T21	1		T74	1		T44	1
index[0x3]	lens_less_than_1000[3]	18	1			T50	1		T258	1		T122	3
index[0x3]	lens_less_than_1000[4]	16	1			T11	1		T79	1		T81	1
index[0x3]	lens_less_than_1000[5]	14	1			T17	1		T30	1		T112	1
index[0x3]	lens_less_than_1000[6]	6	1			T117	3		T293	1		T296	1
index[0x3]	lens_less_than_1000[7]	5	1			T53	1		T62	1		T297	1
index[0x3]	lens_less_than_1000[8]	1	1			T286	1		-	-		-	-
index[0x3]	lens_less_than_1000[9]	1	1			T24	1		-	-		-	-
index[0x3]	len_2	2	1			T6	1		T298	1		-	-