Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
90.74	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	5	35	87.50

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	5	35	87.50	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	62	1			T6	1		T23	1		T79	2
class_index[0x1]	45	1			T72	1		T29	2		T79	1
class_index[0x2]	59	1			T24	1		T71	2		T78	1
class_index[0x3]	45	1			T98	1		T36	1		T41	3

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	93	1			T6	1		T78	1		T98	1
intr_timeout_cnt[1]	39	1			T72	1		T79	1		T86	1
intr_timeout_cnt[2]	18	1			T79	1		T41	2		T88	1
intr_timeout_cnt[3]	6	1			T24	1		T80	1		T37	1
intr_timeout_cnt[4]	12	1			T29	1		T80	2		T52	2
intr_timeout_cnt[5]	15	1			T36	1		T108	6		T254	1
intr_timeout_cnt[6]	7	1			T23	1		T108	1		T255	1
intr_timeout_cnt[7]	9	1			T71	2		T36	1		T41	1
intr_timeout_cnt[8]	10	1			T41	2		T110	1		T63	1
intr_timeout_cnt[9]	2	1			T256	1		T257	1		-	-

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	5	35	87.50	5

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x0]]	[intr_timeout_cnt[7] , intr_timeout_cnt[8]]	--	--	2
[class_index[0x2]]	[intr_timeout_cnt[9]]	0	1	1
[class_index[0x3]]	[intr_timeout_cnt[7]]	0	1	1
[class_index[0x3]]	[intr_timeout_cnt[9]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	31	1			T6	1		T79	1		T41	1
class_index[0x0]	intr_timeout_cnt[1]	13	1			T79	1		T41	2		T56	1
class_index[0x0]	intr_timeout_cnt[2]	5	1			T88	1		T103	2		T258	1
class_index[0x0]	intr_timeout_cnt[3]	2	1			T80	1		T257	1		-	-
class_index[0x0]	intr_timeout_cnt[4]	4	1			T258	1		T122	1		T259	1
class_index[0x0]	intr_timeout_cnt[5]	3	1			T36	1		T260	1		T261	1
class_index[0x0]	intr_timeout_cnt[6]	3	1			T23	1		T108	1		T262	1
class_index[0x0]	intr_timeout_cnt[9]	1	1			T257	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[0]	13	1			T29	1		T93	1		T258	1
class_index[0x1]	intr_timeout_cnt[1]	8	1			T72	1		T86	1		T89	1
class_index[0x1]	intr_timeout_cnt[2]	4	1			T79	1		T56	1		T124	1
class_index[0x1]	intr_timeout_cnt[3]	2	1			T37	1		T63	1		-	-
class_index[0x1]	intr_timeout_cnt[4]	3	1			T29	1		T80	1		T261	1
class_index[0x1]	intr_timeout_cnt[5]	6	1			T108	3		T254	1		T247	1
class_index[0x1]	intr_timeout_cnt[6]	1	1			T263	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[7]	5	1			T36	1		T41	1		T252	2
class_index[0x1]	intr_timeout_cnt[8]	2	1			T41	1		T110	1		-	-
class_index[0x1]	intr_timeout_cnt[9]	1	1			T256	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[0]	27	1			T78	1		T36	1		T41	1
class_index[0x2]	intr_timeout_cnt[1]	11	1			T91	1		T56	1		T99	1
class_index[0x2]	intr_timeout_cnt[2]	4	1			T110	1		T254	1		T264	1
class_index[0x2]	intr_timeout_cnt[3]	1	1			T24	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[4]	4	1			T80	1		T52	2		T260	1
class_index[0x2]	intr_timeout_cnt[5]	3	1			T108	1		T251	2		-	-
class_index[0x2]	intr_timeout_cnt[6]	2	1			T255	1		T265	1		-	-
class_index[0x2]	intr_timeout_cnt[7]	4	1			T71	2		T109	1		T266	1
class_index[0x2]	intr_timeout_cnt[8]	3	1			T41	1		T63	1		T267	1
class_index[0x3]	intr_timeout_cnt[0]	22	1			T98	1		T36	1		T41	1
class_index[0x3]	intr_timeout_cnt[1]	7	1			T110	1		T122	1		T123	1
class_index[0x3]	intr_timeout_cnt[2]	5	1			T41	2		T259	1		T268	1
class_index[0x3]	intr_timeout_cnt[3]	1	1			T269	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[4]	1	1			T256	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[5]	3	1			T108	2		T260	1		-	-
class_index[0x3]	intr_timeout_cnt[6]	1	1			T262	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[8]	5	1			T266	4		T259	1		-	-