Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	286901	1			T1	13		T2	39		T3	1913
all_values[1]	286901	1			T1	13		T2	39		T3	1913
all_values[2]	286901	1			T1	13		T2	39		T3	1913
all_values[3]	286901	1			T1	13		T2	39		T3	1913

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

571185

1

T1

32

T2

85

T3

3871

auto[1]

576419

1

T1

20

T2

71

T3

3781

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

677568

1

T1

28

T2

142

T3

6671

auto[1]

470036

1

T1

24

T2

14

T3

981

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	83393	1			T1	3		T2	15		T3	719
all_values[0]	auto[0]	auto[1]	59774	1			T1	2		T2	7		T3	247
all_values[0]	auto[1]	auto[0]	84402	1			T1	4		T2	10		T3	713
all_values[0]	auto[1]	auto[1]	59332	1			T1	4		T2	7		T3	234
all_values[1]	auto[0]	auto[0]	84300	1			T1	6		T2	19		T3	949
all_values[1]	auto[0]	auto[1]	57476	1			T1	5		T10	23		T5	411
all_values[1]	auto[1]	auto[0]	86898	1			T1	1		T2	20		T3	962
all_values[1]	auto[1]	auto[1]	58227	1			T1	1		T3	2		T10	18
all_values[2]	auto[0]	auto[0]	83784	1			T1	5		T2	20		T3	760
all_values[2]	auto[0]	auto[1]	59121	1			T1	4		T3	270		T10	17
all_values[2]	auto[1]	auto[0]	84837	1			T1	2		T2	19		T3	657
all_values[2]	auto[1]	auto[1]	59159	1			T1	2		T3	226		T10	24
all_values[3]	auto[0]	auto[0]	84662	1			T1	4		T2	24		T3	926
all_values[3]	auto[0]	auto[1]	58675	1			T1	3		T10	25		T5	402
all_values[3]	auto[1]	auto[0]	85292	1			T1	3		T2	15		T3	985
all_values[3]	auto[1]	auto[1]	58272	1			T1	3		T3	2		T10	16