Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

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Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	286901	1			T1	13		T2	39		T3	1913
all_pins[1]	286901	1			T1	13		T2	39		T3	1913
all_pins[2]	286901	1			T1	13		T2	39		T3	1913
all_pins[3]	286901	1			T1	13		T2	39		T3	1913

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Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	912614	1			T1	42		T2	149		T3	7188
values[0x1]	234990	1			T1	10		T2	7		T3	464
transitions[0x0=>0x1]	155130	1			T1	7		T2	6		T3	463
transitions[0x1=>0x0]	155378	1			T1	8		T2	7		T3	464

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Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	227569	1			T1	9		T2	32		T3	1679
all_pins[0]	values[0x1]	59332	1			T1	4		T2	7		T3	234
all_pins[0]	transitions[0x0=>0x1]	58744	1			T1	3		T2	6		T3	233
all_pins[0]	transitions[0x1=>0x0]	57932	1			T1	3		T3	2		T10	16
all_pins[1]	values[0x0]	228674	1			T1	12		T2	39		T3	1911
all_pins[1]	values[0x1]	58227	1			T1	1		T3	2		T10	18
all_pins[1]	transitions[0x0=>0x1]	31901	1			T1	1		T3	2		T10	8
all_pins[1]	transitions[0x1=>0x0]	33006	1			T1	4		T2	7		T3	234
all_pins[2]	values[0x0]	227742	1			T1	11		T2	39		T3	1687
all_pins[2]	values[0x1]	59159	1			T1	2		T3	226		T10	24
all_pins[2]	transitions[0x0=>0x1]	32518	1			T1	2		T3	226		T10	13
all_pins[2]	transitions[0x1=>0x0]	31586	1			T1	1		T3	2		T10	7
all_pins[3]	values[0x0]	228629	1			T1	10		T2	39		T3	1911
all_pins[3]	values[0x1]	58272	1			T1	3		T3	2		T10	16
all_pins[3]	transitions[0x0=>0x1]	31967	1			T1	1		T3	2		T10	4
all_pins[3]	transitions[0x1=>0x0]	32854	1			T3	226		T10	12		T5	190