Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	74287	1			T5	805		T16	868		T17	252
accum_cnt_1000	181594	1			T3	1106		T5	1099		T11	1578
accum_cnt_100	23523	1			T3	142		T10	29		T5	227
accum_cnt_50	52174	1			T1	6		T2	7		T3	142
accum_cnt_10	139190	1			T1	20		T2	22		T3	1438
accum_cnt_0	343769	1			T1	10		T2	91		T3	2844

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	212710	1			T1	9		T2	30		T3	1418
class_index[0x1]	212710	1			T1	9		T2	30		T3	1418
class_index[0x2]	212710	1			T1	9		T2	30		T3	1418
class_index[0x3]	212710	1			T1	9		T2	30		T3	1418

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	17384	1			T5	373		T17	116		T31	132
class_index[0x0]	accum_cnt_1000	47017	1			T3	1106		T5	449		T17	671
class_index[0x0]	accum_cnt_100	7078	1			T3	142		T5	55		T21	2
class_index[0x0]	accum_cnt_50	11243	1			T2	7		T3	142		T5	55
class_index[0x0]	accum_cnt_10	36719	1			T1	8		T2	22		T3	25
class_index[0x0]	accum_cnt_0	84671	1			T1	1		T2	1		T3	3
class_index[0x1]	accum_cnt_2000	18381	1			T17	136		T31	164		T35	199
class_index[0x1]	accum_cnt_1000	40820	1			T5	6		T17	659		T48	21
class_index[0x1]	accum_cnt_100	5211	1			T10	14		T5	42		T17	36
class_index[0x1]	accum_cnt_50	11575	1			T10	19		T5	18		T6	11
class_index[0x1]	accum_cnt_10	35784	1			T1	5		T3	1413		T10	7
class_index[0x1]	accum_cnt_0	95405	1			T1	4		T2	30		T3	5
class_index[0x2]	accum_cnt_2000	20656	1			T5	118		T16	487		T31	129
class_index[0x2]	accum_cnt_1000	47946	1			T5	112		T11	791		T16	479
class_index[0x2]	accum_cnt_100	5239	1			T10	15		T5	58		T11	75
class_index[0x2]	accum_cnt_50	12846	1			T1	6		T10	13		T5	32
class_index[0x2]	accum_cnt_10	29543	1			T1	3		T10	6		T5	93
class_index[0x2]	accum_cnt_0	82430	1			T2	30		T3	1418		T10	7
class_index[0x3]	accum_cnt_2000	17866	1			T5	314		T16	381		T20	238
class_index[0x3]	accum_cnt_1000	45811	1			T5	532		T11	787		T16	579
class_index[0x3]	accum_cnt_100	5995	1			T5	72		T11	77		T16	33
class_index[0x3]	accum_cnt_50	16510	1			T5	58		T6	16		T11	58
class_index[0x3]	accum_cnt_10	37144	1			T1	4		T10	36		T5	20
class_index[0x3]	accum_cnt_0	81263	1			T1	5		T2	30		T3	1418