Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	6055	1			T5	1464		T23	13		T24	79
alert[0x1]	2338	1			T5	41		T70	80		T72	2
alert[0x2]	3035	1			T17	53		T24	4		T71	22
alert[0x3]	2670	1			T71	592		T29	1		T15	1
alert[0x4]	11781	1			T70	1698		T71	246		T94	159
alert[0x5]	5665	1			T17	533		T75	4		T24	833
alert[0x6]	5667	1			T13	1		T246	3		T24	225
alert[0x7]	4099	1			T5	215		T17	32		T24	51
alert[0x8]	2604	1			T5	15		T17	5		T23	5
alert[0x9]	8646	1			T13	1		T24	5344		T70	1080
alert[0xa]	3010	1			T5	562		T6	9		T11	1
alert[0xb]	7687	1			T5	330		T17	20		T71	2
alert[0xc]	4129	1			T5	424		T17	756		T246	10
alert[0xd]	3894	1			T5	875		T24	7		T71	168
alert[0xe]	3775	1			T5	50		T17	2		T13	2
alert[0xf]	4611	1			T17	2032		T74	26		T24	26
alert[0x10]	2783	1			T5	414		T70	19		T71	94
alert[0x11]	9154	1			T5	56		T17	3318		T70	109
alert[0x12]	4425	1			T13	1		T50	34		T36	38
alert[0x13]	7769	1			T5	12		T11	1		T24	206
alert[0x14]	3789	1			T5	61		T49	1		T24	10
alert[0x15]	5453	1			T17	53		T24	43		T71	583
alert[0x16]	10772	1			T11	1		T74	2		T302	1
alert[0x17]	3534	1			T23	14		T24	32		T70	804
alert[0x18]	7043	1			T17	197		T23	9		T24	581
alert[0x19]	3854	1			T5	19		T17	10		T24	518
alert[0x1a]	7277	1			T5	2130		T17	8		T49	3
alert[0x1b]	2306	1			T5	1		T12	1		T13	1
alert[0x1c]	3386	1			T5	29		T17	7		T23	19
alert[0x1d]	8181	1			T17	1		T13	1		T24	265
alert[0x1e]	3839	1			T49	22		T246	18		T74	10
alert[0x1f]	10828	1			T17	10		T49	1		T18	8
alert[0x20]	5771	1			T5	15		T17	116		T23	5
alert[0x21]	9711	1			T17	2718		T18	1		T12	1
alert[0x22]	8222	1			T6	2		T17	18		T49	1
alert[0x23]	5859	1			T5	31		T17	84		T246	5
alert[0x24]	5316	1			T17	43		T70	9		T71	74
alert[0x25]	1650	1			T5	126		T17	25		T24	6
alert[0x26]	2216	1			T17	165		T71	33		T72	2
alert[0x27]	2532	1			T24	471		T37	10		T53	9
alert[0x28]	6341	1			T17	84		T94	2		T50	507
alert[0x29]	5384	1			T5	1793		T17	21		T70	252
alert[0x2a]	6323	1			T5	462		T23	4		T13	1
alert[0x2b]	9790	1			T5	50		T24	188		T45	1
alert[0x2c]	15558	1			T11	1		T23	20		T70	4
alert[0x2d]	3032	1			T13	1		T70	12		T71	406
alert[0x2e]	2288	1			T5	128		T12	1		T246	12
alert[0x2f]	4038	1			T23	1		T74	1		T75	1
alert[0x30]	5250	1			T17	10		T24	27		T94	58
alert[0x31]	4933	1			T5	468		T17	9		T246	25
alert[0x32]	4732	1			T17	25		T94	18		T50	5
alert[0x33]	7774	1			T18	1		T24	169		T70	39
alert[0x34]	5307	1			T17	140		T13	1		T74	24
alert[0x35]	3470	1			T5	209		T17	298		T23	8
alert[0x36]	5411	1			T17	43		T13	1		T24	56
alert[0x37]	4133	1			T17	54		T24	408		T70	41
alert[0x38]	5798	1			T5	156		T75	1		T70	317
alert[0x39]	3684	1			T23	1		T246	3		T70	408
alert[0x3a]	3374	1			T5	1		T246	4		T24	1534
alert[0x3b]	5615	1			T49	4		T74	4		T50	22
alert[0x3c]	4808	1			T13	1		T246	7		T24	91
alert[0x3d]	4493	1			T24	111		T94	49		T42	12
alert[0x3e]	3284	1			T5	15		T246	1		T24	14
alert[0x3f]	5917	1			T74	2		T24	145		T94	194
alert[0x40]	4388	1			T5	171		T17	473		T23	2

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	72393	1			T17	20		T49	32		T13	1
class_i[0x1]	57093	1			T12	3		T23	2		T13	2
class_i[0x2]	110592	1			T5	10323		T17	9		T13	3
class_i[0x3]	110383	1			T6	11		T11	4		T17	11339

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

349823

1

T5

10323

T6

11

T17

11368

alert_ping_fail

638

1

T11

4

T12

3

T13

14

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	6051	1			T5	1464		T23	13		T24	79
alert_integrity_fail	alert[0x1]	2327	1			T5	41		T70	80		T72	2
alert_integrity_fail	alert[0x2]	3016	1			T17	53		T24	4		T71	22
alert_integrity_fail	alert[0x3]	2663	1			T71	592		T29	1		T36	64
alert_integrity_fail	alert[0x4]	11775	1			T70	1698		T71	246		T94	159
alert_integrity_fail	alert[0x5]	5652	1			T17	533		T75	4		T24	833
alert_integrity_fail	alert[0x6]	5658	1			T246	3		T24	225		T94	64
alert_integrity_fail	alert[0x7]	4082	1			T5	215		T17	32		T24	51
alert_integrity_fail	alert[0x8]	2591	1			T5	15		T17	5		T23	5
alert_integrity_fail	alert[0x9]	8639	1			T24	5344		T70	1080		T94	23
alert_integrity_fail	alert[0xa]	3001	1			T5	562		T6	9		T17	5
alert_integrity_fail	alert[0xb]	7678	1			T5	330		T17	20		T71	2
alert_integrity_fail	alert[0xc]	4121	1			T5	424		T17	756		T246	10
alert_integrity_fail	alert[0xd]	3890	1			T5	875		T24	7		T71	168
alert_integrity_fail	alert[0xe]	3763	1			T5	50		T17	2		T24	169
alert_integrity_fail	alert[0xf]	4598	1			T17	2032		T74	26		T24	26
alert_integrity_fail	alert[0x10]	2772	1			T5	414		T70	19		T71	94
alert_integrity_fail	alert[0x11]	9144	1			T5	56		T17	3318		T70	109
alert_integrity_fail	alert[0x12]	4415	1			T50	34		T36	38		T37	34
alert_integrity_fail	alert[0x13]	7755	1			T5	12		T24	206		T94	152
alert_integrity_fail	alert[0x14]	3768	1			T5	61		T49	1		T24	10
alert_integrity_fail	alert[0x15]	5438	1			T17	53		T24	43		T71	583
alert_integrity_fail	alert[0x16]	10763	1			T74	2		T41	35		T37	16
alert_integrity_fail	alert[0x17]	3529	1			T23	14		T24	32		T70	804
alert_integrity_fail	alert[0x18]	7030	1			T17	197		T23	9		T24	581
alert_integrity_fail	alert[0x19]	3848	1			T5	19		T17	10		T24	518
alert_integrity_fail	alert[0x1a]	7267	1			T5	2130		T17	8		T49	3
alert_integrity_fail	alert[0x1b]	2300	1			T5	1		T89	27		T117	52
alert_integrity_fail	alert[0x1c]	3381	1			T5	29		T17	7		T23	19
alert_integrity_fail	alert[0x1d]	8172	1			T17	1		T24	265		T70	2010
alert_integrity_fail	alert[0x1e]	3832	1			T49	22		T246	18		T74	10
alert_integrity_fail	alert[0x1f]	10819	1			T17	10		T49	1		T18	8
alert_integrity_fail	alert[0x20]	5762	1			T5	15		T17	116		T23	5
alert_integrity_fail	alert[0x21]	9699	1			T17	2718		T18	1		T71	432
alert_integrity_fail	alert[0x22]	8205	1			T6	2		T17	18		T49	1
alert_integrity_fail	alert[0x23]	5846	1			T5	31		T17	84		T246	5
alert_integrity_fail	alert[0x24]	5311	1			T17	43		T70	9		T71	74
alert_integrity_fail	alert[0x25]	1636	1			T5	126		T17	25		T24	6
alert_integrity_fail	alert[0x26]	2205	1			T17	165		T71	33		T72	2
alert_integrity_fail	alert[0x27]	2525	1			T24	471		T37	10		T53	9
alert_integrity_fail	alert[0x28]	6324	1			T17	84		T94	2		T50	507
alert_integrity_fail	alert[0x29]	5372	1			T5	1793		T17	21		T70	252
alert_integrity_fail	alert[0x2a]	6309	1			T5	462		T23	4		T71	2
alert_integrity_fail	alert[0x2b]	9782	1			T5	50		T24	188		T53	8
alert_integrity_fail	alert[0x2c]	15550	1			T23	20		T70	4		T71	1370
alert_integrity_fail	alert[0x2d]	3020	1			T70	12		T71	406		T29	1
alert_integrity_fail	alert[0x2e]	2279	1			T5	128		T246	12		T70	21
alert_integrity_fail	alert[0x2f]	4028	1			T23	1		T74	1		T75	1
alert_integrity_fail	alert[0x30]	5240	1			T17	10		T24	27		T94	58
alert_integrity_fail	alert[0x31]	4928	1			T5	468		T17	9		T246	25
alert_integrity_fail	alert[0x32]	4728	1			T17	25		T94	18		T50	5
alert_integrity_fail	alert[0x33]	7766	1			T18	1		T24	169		T70	39
alert_integrity_fail	alert[0x34]	5296	1			T17	140		T74	24		T24	2
alert_integrity_fail	alert[0x35]	3463	1			T5	209		T17	298		T23	8
alert_integrity_fail	alert[0x36]	5404	1			T17	43		T24	56		T71	160
alert_integrity_fail	alert[0x37]	4127	1			T17	54		T24	408		T70	41
alert_integrity_fail	alert[0x38]	5791	1			T5	156		T75	1		T70	317
alert_integrity_fail	alert[0x39]	3675	1			T23	1		T246	3		T70	408
alert_integrity_fail	alert[0x3a]	3366	1			T5	1		T246	4		T24	1534
alert_integrity_fail	alert[0x3b]	5599	1			T49	4		T74	4		T50	22
alert_integrity_fail	alert[0x3c]	4796	1			T246	7		T24	91		T70	148
alert_integrity_fail	alert[0x3d]	4483	1			T24	111		T94	49		T42	12
alert_integrity_fail	alert[0x3e]	3276	1			T5	15		T246	1		T24	14
alert_integrity_fail	alert[0x3f]	5912	1			T74	2		T24	145		T94	194
alert_integrity_fail	alert[0x40]	4382	1			T5	171		T17	473		T23	2
alert_ping_fail	alert[0x0]	4	1			T303	1		T304	1		T305	1
alert_ping_fail	alert[0x1]	11	1			T227	1		T306	1		T307	1
alert_ping_fail	alert[0x2]	19	1			T302	1		T288	1		T308	2
alert_ping_fail	alert[0x3]	7	1			T15	1		T227	1		T303	1
alert_ping_fail	alert[0x4]	6	1			T40	1		T309	2		T310	1
alert_ping_fail	alert[0x5]	13	1			T240	1		T311	1		T312	3
alert_ping_fail	alert[0x6]	9	1			T13	1		T313	1		T314	1
alert_ping_fail	alert[0x7]	17	1			T15	1		T302	2		T40	1
alert_ping_fail	alert[0x8]	13	1			T14	2		T40	2		T308	1
alert_ping_fail	alert[0x9]	7	1			T13	1		T227	1		T306	1
alert_ping_fail	alert[0xa]	9	1			T11	1		T308	1		T315	1
alert_ping_fail	alert[0xb]	9	1			T227	1		T309	1		T306	1
alert_ping_fail	alert[0xc]	8	1			T308	1		T316	1		T303	1
alert_ping_fail	alert[0xd]	4	1			T311	1		T307	1		T303	1
alert_ping_fail	alert[0xe]	12	1			T13	2		T302	1		T102	1
alert_ping_fail	alert[0xf]	13	1			T14	1		T302	1		T317	1
alert_ping_fail	alert[0x10]	11	1			T306	1		T318	1		T319	1
alert_ping_fail	alert[0x11]	10	1			T302	1		T40	1		T274	1
alert_ping_fail	alert[0x12]	10	1			T13	1		T288	1		T307	1
alert_ping_fail	alert[0x13]	14	1			T11	1		T15	1		T302	1
alert_ping_fail	alert[0x14]	21	1			T308	2		T238	1		T320	1
alert_ping_fail	alert[0x15]	15	1			T95	1		T299	1		T288	1
alert_ping_fail	alert[0x16]	9	1			T11	1		T302	1		T300	1
alert_ping_fail	alert[0x17]	5	1			T308	1		T303	1		T321	1
alert_ping_fail	alert[0x18]	13	1			T308	1		T309	1		T274	1
alert_ping_fail	alert[0x19]	6	1			T227	1		T306	1		T322	1
alert_ping_fail	alert[0x1a]	10	1			T316	1		T323	1		T324	1
alert_ping_fail	alert[0x1b]	6	1			T12	1		T13	1		T325	1
alert_ping_fail	alert[0x1c]	5	1			T227	1		T326	1		T323	1
alert_ping_fail	alert[0x1d]	9	1			T13	1		T95	1		T301	1
alert_ping_fail	alert[0x1e]	7	1			T240	1		T309	1		T327	1
alert_ping_fail	alert[0x1f]	9	1			T14	1		T226	1		T102	1
alert_ping_fail	alert[0x20]	9	1			T13	1		T233	1		T306	1
alert_ping_fail	alert[0x21]	12	1			T12	1		T15	1		T40	1
alert_ping_fail	alert[0x22]	17	1			T302	1		T40	1		T227	1
alert_ping_fail	alert[0x23]	13	1			T227	1		T308	1		T230	1
alert_ping_fail	alert[0x24]	5	1			T307	2		T318	1		T328	1
alert_ping_fail	alert[0x25]	14	1			T227	1		T308	2		T306	1
alert_ping_fail	alert[0x26]	11	1			T308	1		T306	2		T303	1
alert_ping_fail	alert[0x27]	7	1			T309	1		T319	1		T310	1
alert_ping_fail	alert[0x28]	17	1			T299	1		T300	2		T311	1
alert_ping_fail	alert[0x29]	12	1			T15	1		T227	2		T240	1
alert_ping_fail	alert[0x2a]	14	1			T13	1		T14	1		T302	1
alert_ping_fail	alert[0x2b]	8	1			T45	1		T233	1		T313	1
alert_ping_fail	alert[0x2c]	8	1			T11	1		T308	1		T325	1
alert_ping_fail	alert[0x2d]	12	1			T13	1		T102	1		T274	1
alert_ping_fail	alert[0x2e]	9	1			T12	1		T233	1		T322	2
alert_ping_fail	alert[0x2f]	10	1			T95	1		T302	1		T308	1
alert_ping_fail	alert[0x30]	10	1			T95	1		T102	2		T308	1
alert_ping_fail	alert[0x31]	5	1			T240	1		T311	1		T303	1
alert_ping_fail	alert[0x32]	4	1			T306	1		T329	1		T330	1
alert_ping_fail	alert[0x33]	8	1			T308	1		T317	1		T318	1
alert_ping_fail	alert[0x34]	11	1			T13	1		T308	1		T274	1
alert_ping_fail	alert[0x35]	7	1			T13	1		T308	1		T327	2
alert_ping_fail	alert[0x36]	7	1			T13	1		T15	1		T102	1
alert_ping_fail	alert[0x37]	6	1			T14	1		T306	1		T322	1
alert_ping_fail	alert[0x38]	7	1			T233	1		T327	1		T322	1
alert_ping_fail	alert[0x39]	9	1			T227	2		T309	1		T331	1
alert_ping_fail	alert[0x3a]	8	1			T15	1		T302	1		T308	1
alert_ping_fail	alert[0x3b]	16	1			T15	1		T308	1		T233	1
alert_ping_fail	alert[0x3c]	12	1			T13	1		T317	1		T306	1
alert_ping_fail	alert[0x3d]	10	1			T307	1		T318	2		T331	1
alert_ping_fail	alert[0x3e]	8	1			T240	1		T274	1		T326	1
alert_ping_fail	alert[0x3f]	5	1			T302	1		T311	1		T331	1
alert_ping_fail	alert[0x40]	6	1			T317	1		T313	1		T310	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	72211	1			T17	20		T49	32		T24	12314
alert_integrity_fail	class_i[0x1]	56990	1			T23	2		T246	89		T24	6
alert_integrity_fail	class_i[0x2]	110411	1			T5	10323		T17	9		T246	8
alert_integrity_fail	class_i[0x3]	110211	1			T6	11		T17	11339		T18	10
alert_ping_fail	class_i[0x0]	182	1			T13	1		T302	13		T40	1
alert_ping_fail	class_i[0x1]	103	1			T12	3		T13	2		T95	4
alert_ping_fail	class_i[0x2]	181	1			T13	3		T14	5		T15	8
alert_ping_fail	class_i[0x3]	172	1			T11	4		T13	8		T14	1