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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.24 99.99 98.73 97.09 100.00 100.00 99.38 99.52


Total test records in report: 832
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T144 /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.2688155477 Aug 14 04:58:31 PM PDT 24 Aug 14 05:04:00 PM PDT 24 8301355779 ps
T778 /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.3302299570 Aug 14 04:57:49 PM PDT 24 Aug 14 04:57:54 PM PDT 24 258140935 ps
T779 /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.2521377007 Aug 14 04:57:59 PM PDT 24 Aug 14 04:58:06 PM PDT 24 151393579 ps
T780 /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.1631153851 Aug 14 04:57:50 PM PDT 24 Aug 14 04:59:15 PM PDT 24 525750884 ps
T781 /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.3121701705 Aug 14 04:58:29 PM PDT 24 Aug 14 04:58:33 PM PDT 24 54556598 ps
T150 /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.3203364202 Aug 14 04:58:31 PM PDT 24 Aug 14 05:03:57 PM PDT 24 17298331595 ps
T782 /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.710022033 Aug 14 04:58:00 PM PDT 24 Aug 14 04:58:05 PM PDT 24 196700639 ps
T162 /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.1455279146 Aug 14 04:57:56 PM PDT 24 Aug 14 05:14:42 PM PDT 24 64565376623 ps
T783 /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.4268394803 Aug 14 04:57:49 PM PDT 24 Aug 14 04:57:56 PM PDT 24 96680514 ps
T784 /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.294922418 Aug 14 04:57:56 PM PDT 24 Aug 14 04:59:54 PM PDT 24 15350942264 ps
T156 /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.2074580589 Aug 14 04:58:43 PM PDT 24 Aug 14 05:18:43 PM PDT 24 33978843893 ps
T785 /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.729343205 Aug 14 04:58:37 PM PDT 24 Aug 14 04:58:39 PM PDT 24 9043291 ps
T164 /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.654165713 Aug 14 04:58:21 PM PDT 24 Aug 14 05:18:25 PM PDT 24 65841748944 ps
T148 /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.448272514 Aug 14 04:58:30 PM PDT 24 Aug 14 05:01:09 PM PDT 24 4808423487 ps
T786 /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.704524269 Aug 14 04:57:59 PM PDT 24 Aug 14 04:58:05 PM PDT 24 127583543 ps
T787 /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.481204189 Aug 14 04:58:07 PM PDT 24 Aug 14 04:58:09 PM PDT 24 15921907 ps
T788 /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.4287492876 Aug 14 04:58:08 PM PDT 24 Aug 14 04:58:14 PM PDT 24 129089540 ps
T789 /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.3398948526 Aug 14 04:58:45 PM PDT 24 Aug 14 04:58:47 PM PDT 24 31012509 ps
T790 /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.1866807878 Aug 14 04:58:19 PM PDT 24 Aug 14 04:58:21 PM PDT 24 29166137 ps
T160 /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.3621718778 Aug 14 04:58:31 PM PDT 24 Aug 14 05:02:40 PM PDT 24 14622443541 ps
T159 /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.1024560678 Aug 14 04:58:19 PM PDT 24 Aug 14 05:01:38 PM PDT 24 25643440539 ps
T791 /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.3527725885 Aug 14 04:57:57 PM PDT 24 Aug 14 04:58:01 PM PDT 24 74916218 ps
T792 /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.2049647811 Aug 14 04:57:42 PM PDT 24 Aug 14 04:57:49 PM PDT 24 229716822 ps
T793 /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.814246975 Aug 14 04:58:06 PM PDT 24 Aug 14 04:58:19 PM PDT 24 1209799847 ps
T794 /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.638204701 Aug 14 04:58:06 PM PDT 24 Aug 14 04:58:08 PM PDT 24 10906484 ps
T795 /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.2070957061 Aug 14 04:58:05 PM PDT 24 Aug 14 04:58:08 PM PDT 24 116601885 ps
T271 /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.3264472308 Aug 14 04:58:19 PM PDT 24 Aug 14 04:58:22 PM PDT 24 52655528 ps
T796 /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.3783612649 Aug 14 04:58:39 PM PDT 24 Aug 14 04:58:40 PM PDT 24 14585082 ps
T158 /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.3188922778 Aug 14 04:58:17 PM PDT 24 Aug 14 05:03:17 PM PDT 24 14463672424 ps
T797 /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.3938518350 Aug 14 04:58:21 PM PDT 24 Aug 14 04:58:43 PM PDT 24 1206593101 ps
T798 /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.1046492038 Aug 14 04:58:21 PM PDT 24 Aug 14 04:58:24 PM PDT 24 34418237 ps
T178 /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.3291202492 Aug 14 04:57:55 PM PDT 24 Aug 14 04:58:18 PM PDT 24 170277312 ps
T799 /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.589167406 Aug 14 04:58:06 PM PDT 24 Aug 14 04:58:10 PM PDT 24 188433808 ps
T800 /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.1721503047 Aug 14 04:57:55 PM PDT 24 Aug 14 04:58:00 PM PDT 24 22170860 ps
T801 /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.2889332979 Aug 14 04:57:41 PM PDT 24 Aug 14 04:58:19 PM PDT 24 1059119268 ps
T167 /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.3124567978 Aug 14 04:57:41 PM PDT 24 Aug 14 05:02:28 PM PDT 24 10949310989 ps
T802 /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.3035853056 Aug 14 04:58:29 PM PDT 24 Aug 14 04:58:31 PM PDT 24 6827661 ps
T803 /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.3964027371 Aug 14 04:58:31 PM PDT 24 Aug 14 04:58:48 PM PDT 24 205908643 ps
T804 /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.413708533 Aug 14 04:57:59 PM PDT 24 Aug 14 04:58:41 PM PDT 24 2147917426 ps
T166 /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.420521646 Aug 14 04:57:57 PM PDT 24 Aug 14 05:14:05 PM PDT 24 49778236895 ps
T805 /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.2560058779 Aug 14 04:58:19 PM PDT 24 Aug 14 04:58:27 PM PDT 24 106454755 ps
T806 /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.3072340541 Aug 14 04:57:47 PM PDT 24 Aug 14 05:01:55 PM PDT 24 3453629691 ps
T807 /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.2139509003 Aug 14 04:58:38 PM PDT 24 Aug 14 04:58:40 PM PDT 24 10687965 ps
T187 /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.2334277562 Aug 14 04:57:49 PM PDT 24 Aug 14 04:57:51 PM PDT 24 21884452 ps
T808 /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.1432841145 Aug 14 04:58:43 PM PDT 24 Aug 14 04:58:52 PM PDT 24 500936847 ps
T809 /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.4233889640 Aug 14 04:58:07 PM PDT 24 Aug 14 04:58:08 PM PDT 24 61515083 ps
T810 /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.2160557437 Aug 14 04:57:49 PM PDT 24 Aug 14 04:57:54 PM PDT 24 64198488 ps
T811 /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.4190892845 Aug 14 04:58:47 PM PDT 24 Aug 14 04:58:49 PM PDT 24 7890992 ps
T142 /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.3418843874 Aug 14 04:58:05 PM PDT 24 Aug 14 05:02:39 PM PDT 24 18056015636 ps
T812 /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.2707061599 Aug 14 04:58:36 PM PDT 24 Aug 14 04:58:37 PM PDT 24 10381158 ps
T813 /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.826877741 Aug 14 04:57:43 PM PDT 24 Aug 14 04:57:44 PM PDT 24 18733012 ps
T163 /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.3741476174 Aug 14 04:57:58 PM PDT 24 Aug 14 04:59:47 PM PDT 24 3047541060 ps
T191 /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.3197190727 Aug 14 04:58:07 PM PDT 24 Aug 14 04:58:12 PM PDT 24 63145301 ps
T168 /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.2081511936 Aug 14 04:58:30 PM PDT 24 Aug 14 05:00:09 PM PDT 24 1653821284 ps
T814 /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.331024087 Aug 14 04:58:39 PM PDT 24 Aug 14 04:58:40 PM PDT 24 32442811 ps
T815 /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.1989543757 Aug 14 04:58:37 PM PDT 24 Aug 14 04:58:39 PM PDT 24 7678710 ps
T816 /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.4072710349 Aug 14 04:57:56 PM PDT 24 Aug 14 04:58:01 PM PDT 24 53248015 ps
T184 /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.4242490776 Aug 14 04:57:43 PM PDT 24 Aug 14 04:57:47 PM PDT 24 213493321 ps
T363 /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.3471252209 Aug 14 04:58:31 PM PDT 24 Aug 14 05:07:54 PM PDT 24 124773164117 ps
T817 /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.2093690696 Aug 14 04:57:50 PM PDT 24 Aug 14 04:58:10 PM PDT 24 1130727502 ps
T161 /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.2207407436 Aug 14 04:57:48 PM PDT 24 Aug 14 05:02:22 PM PDT 24 4045054955 ps
T818 /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.1834825688 Aug 14 04:58:38 PM PDT 24 Aug 14 04:58:40 PM PDT 24 19694824 ps
T169 /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.873965505 Aug 14 04:58:05 PM PDT 24 Aug 14 05:01:02 PM PDT 24 18531894161 ps
T819 /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.3373921087 Aug 14 04:57:55 PM PDT 24 Aug 14 04:58:06 PM PDT 24 324461824 ps
T192 /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.1264874006 Aug 14 04:57:57 PM PDT 24 Aug 14 04:58:01 PM PDT 24 157392452 ps
T820 /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.387942727 Aug 14 04:58:20 PM PDT 24 Aug 14 04:58:46 PM PDT 24 707853220 ps
T821 /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.2161109188 Aug 14 04:58:31 PM PDT 24 Aug 14 04:58:54 PM PDT 24 338460103 ps
T822 /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.234269134 Aug 14 04:58:31 PM PDT 24 Aug 14 04:58:32 PM PDT 24 10527281 ps
T823 /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.2329679948 Aug 14 04:58:39 PM PDT 24 Aug 14 04:58:40 PM PDT 24 8328770 ps
T824 /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.2415711806 Aug 14 04:58:28 PM PDT 24 Aug 14 04:58:49 PM PDT 24 288507362 ps
T825 /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.2465202309 Aug 14 04:58:07 PM PDT 24 Aug 14 04:58:16 PM PDT 24 176023123 ps
T826 /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.12847567 Aug 14 04:58:30 PM PDT 24 Aug 14 04:59:10 PM PDT 24 2007497871 ps
T180 /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.1966125099 Aug 14 04:58:07 PM PDT 24 Aug 14 04:58:10 PM PDT 24 54043663 ps
T827 /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.4255458395 Aug 14 04:58:29 PM PDT 24 Aug 14 04:58:55 PM PDT 24 343853478 ps
T828 /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.2647327234 Aug 14 04:58:37 PM PDT 24 Aug 14 04:58:39 PM PDT 24 14170104 ps
T177 /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.2753557330 Aug 14 04:58:30 PM PDT 24 Aug 14 04:58:35 PM PDT 24 148019102 ps
T829 /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.3697241975 Aug 14 04:58:29 PM PDT 24 Aug 14 04:58:39 PM PDT 24 128905767 ps
T165 /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.2692506184 Aug 14 04:58:06 PM PDT 24 Aug 14 05:04:07 PM PDT 24 5283695715 ps
T830 /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.838320059 Aug 14 04:57:51 PM PDT 24 Aug 14 04:58:05 PM PDT 24 186587109 ps
T181 /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.4192315129 Aug 14 04:58:19 PM PDT 24 Aug 14 04:58:22 PM PDT 24 25264954 ps
T831 /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.3920005614 Aug 14 04:58:32 PM PDT 24 Aug 14 04:58:45 PM PDT 24 87857188 ps
T832 /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.2563779841 Aug 14 04:57:59 PM PDT 24 Aug 14 04:58:11 PM PDT 24 149941043 ps

Test location /workspace/coverage/default/17.alert_handler_stress_all.2144986395
Short name T5
Test name
Test status
Simulation time 65068590492 ps
CPU time 1297.44 seconds
Started Aug 14 04:47:40 PM PDT 24
Finished Aug 14 05:09:17 PM PDT 24
Peak memory 289860 kb
Host smart-9e545f37-0127-4720-8791-4b17036763b6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2144986395 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_ha
ndler_stress_all.2144986395
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all_with_rand_reset.3041158437
Short name T72
Test name
Test status
Simulation time 1531572439 ps
CPU time 97.99 seconds
Started Aug 14 04:48:11 PM PDT 24
Finished Aug 14 04:49:50 PM PDT 24
Peak memory 266316 kb
Host smart-92f85b8a-3781-4e6f-9277-696366c7a918
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3041158437 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 40.alert_handler_stress_all_with_rand_reset.3041158437
Directory /workspace/40.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.2728519821
Short name T38
Test name
Test status
Simulation time 1059011769 ps
CPU time 48.17 seconds
Started Aug 14 04:46:57 PM PDT 24
Finished Aug 14 04:47:45 PM PDT 24
Peak memory 273664 kb
Host smart-22e82e1c-fd57-4915-b030-f2bf8887a13d
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2728519821 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.2728519821
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.3716999639
Short name T71
Test name
Test status
Simulation time 50937606122 ps
CPU time 3143.93 seconds
Started Aug 14 04:47:02 PM PDT 24
Finished Aug 14 05:39:26 PM PDT 24
Peak memory 297752 kb
Host smart-9b67ab14-87cd-4a42-87c9-80aa06a272c7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3716999639 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_han
dler_stress_all.3716999639
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.2829426793
Short name T170
Test name
Test status
Simulation time 973096187 ps
CPU time 70.09 seconds
Started Aug 14 04:58:33 PM PDT 24
Finished Aug 14 04:59:43 PM PDT 24
Peak memory 240700 kb
Host smart-b9dc1e25-c8e9-4110-be51-88bb25e17f9f
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2829426793 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.2829426793
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all_with_rand_reset.558771923
Short name T52
Test name
Test status
Simulation time 4924745028 ps
CPU time 599.9 seconds
Started Aug 14 04:48:05 PM PDT 24
Finished Aug 14 04:58:05 PM PDT 24
Peak memory 273560 kb
Host smart-89af6e5e-f528-40c1-98d7-f6b443a70a23
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=558771923 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 42.alert_handler_stress_all_with_rand_reset.558771923
Directory /workspace/42.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.702682751
Short name T105
Test name
Test status
Simulation time 15118616429 ps
CPU time 638.22 seconds
Started Aug 14 04:47:22 PM PDT 24
Finished Aug 14 04:58:00 PM PDT 24
Peak memory 273488 kb
Host smart-d98c4572-0c5a-4bb2-86c1-44a80c8b5af3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=702682751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.702682751
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.691959226
Short name T53
Test name
Test status
Simulation time 105176735646 ps
CPU time 1591.58 seconds
Started Aug 14 04:48:03 PM PDT 24
Finished Aug 14 05:14:35 PM PDT 24
Peak memory 289676 kb
Host smart-e2d0dbe3-de09-486a-bc9b-86e747c614ab
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=691959226 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_han
dler_stress_all.691959226
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.3476225241
Short name T20
Test name
Test status
Simulation time 42490247048 ps
CPU time 2464.22 seconds
Started Aug 14 04:48:03 PM PDT 24
Finished Aug 14 05:29:07 PM PDT 24
Peak memory 289720 kb
Host smart-35e3372a-fb54-494d-8d16-1e8b1c472894
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3476225241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.3476225241
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.3203364202
Short name T150
Test name
Test status
Simulation time 17298331595 ps
CPU time 325.86 seconds
Started Aug 14 04:58:31 PM PDT 24
Finished Aug 14 05:03:57 PM PDT 24
Peak memory 265704 kb
Host smart-192d641f-12ee-49b0-9dc4-50fa7bfda857
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3203364202 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_err
ors.3203364202
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.8502054
Short name T32
Test name
Test status
Simulation time 16965780289 ps
CPU time 220.59 seconds
Started Aug 14 04:48:22 PM PDT 24
Finished Aug 14 04:52:03 PM PDT 24
Peak memory 256160 kb
Host smart-3a44c5a5-31fc-4885-bad3-8fc06000cb34
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=8502054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handl
er_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handl
er_stress_all.8502054
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.2677755944
Short name T132
Test name
Test status
Simulation time 13979325681 ps
CPU time 958.99 seconds
Started Aug 14 04:58:45 PM PDT 24
Finished Aug 14 05:14:45 PM PDT 24
Peak memory 265832 kb
Host smart-9f81482a-68f0-4769-a616-67770109ee5f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2677755944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.2677755944
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.2256195571
Short name T24
Test name
Test status
Simulation time 80930321523 ps
CPU time 2660.79 seconds
Started Aug 14 04:48:21 PM PDT 24
Finished Aug 14 05:32:42 PM PDT 24
Peak memory 289160 kb
Host smart-3d2e691c-65c3-4414-a131-2a6e360022a6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2256195571 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_ha
ndler_stress_all.2256195571
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.1855068562
Short name T299
Test name
Test status
Simulation time 52322028463 ps
CPU time 3103.57 seconds
Started Aug 14 04:46:55 PM PDT 24
Finished Aug 14 05:38:39 PM PDT 24
Peak memory 289264 kb
Host smart-fd317863-5679-4ca8-8b91-0814f3b4e99d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1855068562 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.1855068562
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.2694720712
Short name T136
Test name
Test status
Simulation time 50140999151 ps
CPU time 1045.26 seconds
Started Aug 14 04:57:52 PM PDT 24
Finished Aug 14 05:15:17 PM PDT 24
Peak memory 273224 kb
Host smart-031a188c-8d7a-4247-8608-44b50f0e6998
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2694720712 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.2694720712
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all_with_rand_reset.2509984824
Short name T29
Test name
Test status
Simulation time 22900810634 ps
CPU time 516.31 seconds
Started Aug 14 04:46:56 PM PDT 24
Finished Aug 14 04:55:33 PM PDT 24
Peak memory 272796 kb
Host smart-a7a22c84-38c2-4a16-b087-4ad0d98f01af
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2509984824 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 3.alert_handler_stress_all_with_rand_reset.2509984824
Directory /workspace/3.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.3418843874
Short name T142
Test name
Test status
Simulation time 18056015636 ps
CPU time 274.49 seconds
Started Aug 14 04:58:05 PM PDT 24
Finished Aug 14 05:02:39 PM PDT 24
Peak memory 272888 kb
Host smart-47b47cb3-ff46-48be-bb79-ea91ab581457
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3418843874 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_erro
rs.3418843874
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.1853881588
Short name T13
Test name
Test status
Simulation time 10518622652 ps
CPU time 427.31 seconds
Started Aug 14 04:47:44 PM PDT 24
Finished Aug 14 04:54:52 PM PDT 24
Peak memory 255084 kb
Host smart-114d1c44-a4f7-48b5-8d5c-e2be00db787f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1853881588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.1853881588
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.3645683636
Short name T353
Test name
Test status
Simulation time 13190332 ps
CPU time 1.64 seconds
Started Aug 14 04:57:50 PM PDT 24
Finished Aug 14 04:57:52 PM PDT 24
Peak memory 236788 kb
Host smart-24f8a149-864c-415a-a097-5d6b9d161031
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3645683636 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.3645683636
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.3254225290
Short name T138
Test name
Test status
Simulation time 44760300401 ps
CPU time 1092.55 seconds
Started Aug 14 04:58:06 PM PDT 24
Finished Aug 14 05:16:19 PM PDT 24
Peak memory 265688 kb
Host smart-b2c4cd26-9670-487b-835b-174f3c1c9c66
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3254225290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.3254225290
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.3006990203
Short name T11
Test name
Test status
Simulation time 161749765780 ps
CPU time 2326.23 seconds
Started Aug 14 04:47:49 PM PDT 24
Finished Aug 14 05:26:35 PM PDT 24
Peak memory 273476 kb
Host smart-0cd78a50-4eed-439f-9122-41e1bd6db205
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3006990203 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.3006990203
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.1480968034
Short name T65
Test name
Test status
Simulation time 24996415645 ps
CPU time 71.9 seconds
Started Aug 14 04:47:14 PM PDT 24
Finished Aug 14 04:48:26 PM PDT 24
Peak memory 248816 kb
Host smart-b26c3b43-aecd-41ac-a218-99989288c558
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1480968034 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.1480968034
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.1114759269
Short name T146
Test name
Test status
Simulation time 2980531529 ps
CPU time 216.82 seconds
Started Aug 14 04:57:50 PM PDT 24
Finished Aug 14 05:01:27 PM PDT 24
Peak memory 268752 kb
Host smart-d7ecc61b-371a-47b1-86a0-7ca906eabf54
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1114759269 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_erro
rs.1114759269
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.359205617
Short name T308
Test name
Test status
Simulation time 129887465819 ps
CPU time 591.23 seconds
Started Aug 14 04:46:57 PM PDT 24
Finished Aug 14 04:56:48 PM PDT 24
Peak memory 248620 kb
Host smart-0820265f-353e-4418-beaf-6bc388b4888f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=359205617 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.359205617
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.1778730847
Short name T41
Test name
Test status
Simulation time 101068015827 ps
CPU time 2610.84 seconds
Started Aug 14 04:47:52 PM PDT 24
Finished Aug 14 05:31:24 PM PDT 24
Peak memory 289880 kb
Host smart-7945f5ca-8e8d-4751-abb3-d5b9a23d3403
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1778730847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_ha
ndler_stress_all.1778730847
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.250756671
Short name T323
Test name
Test status
Simulation time 21704559143 ps
CPU time 463.25 seconds
Started Aug 14 04:48:03 PM PDT 24
Finished Aug 14 04:55:47 PM PDT 24
Peak memory 247732 kb
Host smart-b1efa5f2-a327-44de-9842-74c09a92f7ed
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=250756671 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.250756671
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.363489191
Short name T139
Test name
Test status
Simulation time 18150214277 ps
CPU time 697 seconds
Started Aug 14 04:58:19 PM PDT 24
Finished Aug 14 05:09:56 PM PDT 24
Peak memory 273328 kb
Host smart-2b375523-e0c5-4462-8abc-7b44f2208291
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=363489191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.363489191
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.75295140
Short name T3
Test name
Test status
Simulation time 53308956657 ps
CPU time 1843.14 seconds
Started Aug 14 04:47:43 PM PDT 24
Finished Aug 14 05:18:26 PM PDT 24
Peak memory 289764 kb
Host smart-91ed76b7-18a6-40d9-a0e7-2f22b071968f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=75295140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.75295140
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.1028304266
Short name T153
Test name
Test status
Simulation time 16968787916 ps
CPU time 970.67 seconds
Started Aug 14 04:58:18 PM PDT 24
Finished Aug 14 05:14:29 PM PDT 24
Peak memory 273432 kb
Host smart-2a92bb92-0261-4990-82df-8f25d9f1ac2b
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1028304266 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.1028304266
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.1581902244
Short name T155
Test name
Test status
Simulation time 1138470012 ps
CPU time 97.44 seconds
Started Aug 14 04:57:45 PM PDT 24
Finished Aug 14 04:59:22 PM PDT 24
Peak memory 265396 kb
Host smart-280a534b-cb63-42a5-ae92-32a0dc611064
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1581902244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_erro
rs.1581902244
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.2182367735
Short name T656
Test name
Test status
Simulation time 14403296415 ps
CPU time 582.72 seconds
Started Aug 14 04:47:38 PM PDT 24
Finished Aug 14 04:57:21 PM PDT 24
Peak memory 257064 kb
Host smart-fb69ce31-4a3f-4c56-b63c-c90037eab471
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2182367735 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.2182367735
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.1283970175
Short name T108
Test name
Test status
Simulation time 176317650729 ps
CPU time 2660.07 seconds
Started Aug 14 04:47:51 PM PDT 24
Finished Aug 14 05:32:12 PM PDT 24
Peak memory 289156 kb
Host smart-6cc033c9-4b4b-41ed-b0e8-3f65e46344b9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1283970175 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_ha
ndler_stress_all.1283970175
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.2560047962
Short name T340
Test name
Test status
Simulation time 52574986305 ps
CPU time 2600.34 seconds
Started Aug 14 04:48:23 PM PDT 24
Finished Aug 14 05:31:44 PM PDT 24
Peak memory 284000 kb
Host smart-3d9e7930-8e67-44e6-97d2-738ccab93d3f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2560047962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.2560047962
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.4004294597
Short name T133
Test name
Test status
Simulation time 5542311450 ps
CPU time 358.88 seconds
Started Aug 14 04:57:50 PM PDT 24
Finished Aug 14 05:03:49 PM PDT 24
Peak memory 273740 kb
Host smart-1dacae3b-4a1e-4fa6-b8dd-c202b9733779
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4004294597 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_erro
rs.4004294597
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.4115454586
Short name T147
Test name
Test status
Simulation time 29318957572 ps
CPU time 437.24 seconds
Started Aug 14 04:58:08 PM PDT 24
Finished Aug 14 05:05:26 PM PDT 24
Peak memory 273872 kb
Host smart-eb35f344-0c93-4b27-9e06-aa35491bcb60
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=4115454586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_erro
rs.4115454586
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.3514595467
Short name T174
Test name
Test status
Simulation time 6689853 ps
CPU time 1.49 seconds
Started Aug 14 04:58:30 PM PDT 24
Finished Aug 14 04:58:33 PM PDT 24
Peak memory 237676 kb
Host smart-dccf9fff-5b9a-49b9-9e2a-5e2ae66beb04
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3514595467 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.3514595467
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.956777067
Short name T303
Test name
Test status
Simulation time 12248748650 ps
CPU time 522.45 seconds
Started Aug 14 04:46:52 PM PDT 24
Finished Aug 14 04:55:35 PM PDT 24
Peak memory 248896 kb
Host smart-f58cc77e-c078-4f6f-ad6b-104cc219d364
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=956777067 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.956777067
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.2678331732
Short name T334
Test name
Test status
Simulation time 89602481460 ps
CPU time 2654.09 seconds
Started Aug 14 04:48:17 PM PDT 24
Finished Aug 14 05:32:31 PM PDT 24
Peak memory 284940 kb
Host smart-40db8d12-a185-4866-bd4a-204553977a67
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2678331732 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.2678331732
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all_with_rand_reset.3391760489
Short name T6
Test name
Test status
Simulation time 8856812659 ps
CPU time 343.59 seconds
Started Aug 14 04:48:01 PM PDT 24
Finished Aug 14 04:53:45 PM PDT 24
Peak memory 267472 kb
Host smart-4f7b55a9-31bb-498a-87eb-c2cb5bf34c7e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3391760489 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.alert_handler_stress_all_with_rand_reset.3391760489
Directory /workspace/39.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.3458671364
Short name T257
Test name
Test status
Simulation time 307511143 ps
CPU time 16.67 seconds
Started Aug 14 04:47:48 PM PDT 24
Finished Aug 14 04:48:05 PM PDT 24
Peak memory 248204 kb
Host smart-3a975540-84d1-4b87-8159-0538ae799af0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34586
71364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.3458671364
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.2692506184
Short name T165
Test name
Test status
Simulation time 5283695715 ps
CPU time 360.21 seconds
Started Aug 14 04:58:06 PM PDT 24
Finished Aug 14 05:04:07 PM PDT 24
Peak memory 265520 kb
Host smart-f9ac7160-ace4-435b-ae35-f338a4203fd6
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2692506184 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_err
ors.2692506184
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.848683279
Short name T329
Test name
Test status
Simulation time 30692476656 ps
CPU time 243.48 seconds
Started Aug 14 04:47:02 PM PDT 24
Finished Aug 14 04:51:05 PM PDT 24
Peak memory 248884 kb
Host smart-df928bc9-f3ae-452c-9899-16ec658b30d4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=848683279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.848683279
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all_with_rand_reset.3889890784
Short name T266
Test name
Test status
Simulation time 3099448015 ps
CPU time 208.49 seconds
Started Aug 14 04:47:40 PM PDT 24
Finished Aug 14 04:51:09 PM PDT 24
Peak memory 265424 kb
Host smart-e0fc9fb3-5161-4a7d-9f1a-73dceaf8dd79
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3889890784 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.alert_handler_stress_all_with_rand_reset.3889890784
Directory /workspace/28.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.2081511936
Short name T168
Test name
Test status
Simulation time 1653821284 ps
CPU time 98.96 seconds
Started Aug 14 04:58:30 PM PDT 24
Finished Aug 14 05:00:09 PM PDT 24
Peak memory 265372 kb
Host smart-ff8d17bb-1abf-421f-a68a-8c5deb82c9e0
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2081511936 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_err
ors.2081511936
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.3264472308
Short name T271
Test name
Test status
Simulation time 52655528 ps
CPU time 2.73 seconds
Started Aug 14 04:58:19 PM PDT 24
Finished Aug 14 04:58:22 PM PDT 24
Peak memory 237596 kb
Host smart-99981da6-b798-455c-91d9-af9ff9943326
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3264472308 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.3264472308
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.1829634526
Short name T263
Test name
Test status
Simulation time 248253946411 ps
CPU time 3074.81 seconds
Started Aug 14 04:47:45 PM PDT 24
Finished Aug 14 05:39:01 PM PDT 24
Peak memory 289052 kb
Host smart-75f54872-4f85-4d19-bb04-cf0efddf8e32
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1829634526 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_ha
ndler_stress_all.1829634526
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.644261103
Short name T717
Test name
Test status
Simulation time 47172781552 ps
CPU time 2831.41 seconds
Started Aug 14 04:47:39 PM PDT 24
Finished Aug 14 05:34:51 PM PDT 24
Peak memory 287624 kb
Host smart-0b1599df-2b80-4cf5-9a85-f71f66c9182e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644261103 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.644261103
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.1243279549
Short name T188
Test name
Test status
Simulation time 343518329 ps
CPU time 7.78 seconds
Started Aug 14 04:58:07 PM PDT 24
Finished Aug 14 04:58:14 PM PDT 24
Peak memory 237788 kb
Host smart-80566ebc-95bd-4422-b785-962c37cb0288
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1243279549 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.1243279549
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.1557230789
Short name T37
Test name
Test status
Simulation time 16936704624 ps
CPU time 1561.1 seconds
Started Aug 14 04:47:34 PM PDT 24
Finished Aug 14 05:13:35 PM PDT 24
Peak memory 289880 kb
Host smart-a1057b04-8815-46ad-aa19-215d37ec3950
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1557230789 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_ha
ndler_stress_all.1557230789
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.2170490387
Short name T211
Test name
Test status
Simulation time 30924990 ps
CPU time 3.45 seconds
Started Aug 14 04:46:53 PM PDT 24
Finished Aug 14 04:46:57 PM PDT 24
Peak memory 248864 kb
Host smart-ed5c9c4d-0395-4c91-be5e-98207117d26a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2170490387 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.2170490387
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.3082326240
Short name T208
Test name
Test status
Simulation time 211138387 ps
CPU time 3.44 seconds
Started Aug 14 04:46:52 PM PDT 24
Finished Aug 14 04:46:55 PM PDT 24
Peak memory 249000 kb
Host smart-9eb5fea2-c4dc-40b2-ba87-470855dba64b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3082326240 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.3082326240
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.3100895479
Short name T218
Test name
Test status
Simulation time 63164552 ps
CPU time 3.64 seconds
Started Aug 14 04:47:35 PM PDT 24
Finished Aug 14 04:47:39 PM PDT 24
Peak memory 248948 kb
Host smart-0699ee56-8999-4059-bdba-957487424fb6
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3100895479 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.3100895479
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.2010914870
Short name T207
Test name
Test status
Simulation time 129471542 ps
CPU time 3.24 seconds
Started Aug 14 04:47:31 PM PDT 24
Finished Aug 14 04:47:34 PM PDT 24
Peak memory 249032 kb
Host smart-ee71423e-fd2f-484e-980b-d35a02804c2e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2010914870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.2010914870
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.3124567978
Short name T167
Test name
Test status
Simulation time 10949310989 ps
CPU time 286.98 seconds
Started Aug 14 04:57:41 PM PDT 24
Finished Aug 14 05:02:28 PM PDT 24
Peak memory 265684 kb
Host smart-e2a7d986-f687-4c29-adb5-3b4970f0bf60
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124567978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.3124567978
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.1284930725
Short name T350
Test name
Test status
Simulation time 22033510 ps
CPU time 1.33 seconds
Started Aug 14 04:58:19 PM PDT 24
Finished Aug 14 04:58:21 PM PDT 24
Peak memory 237700 kb
Host smart-d2cb7505-571e-425e-bd4f-a76e4f364b95
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1284930725 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.1284930725
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.1455279146
Short name T162
Test name
Test status
Simulation time 64565376623 ps
CPU time 1005.94 seconds
Started Aug 14 04:57:56 PM PDT 24
Finished Aug 14 05:14:42 PM PDT 24
Peak memory 265656 kb
Host smart-11c2f65d-3b16-41eb-befe-a4c0c048a419
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1455279146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.1455279146
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.4004927479
Short name T279
Test name
Test status
Simulation time 24967394338 ps
CPU time 1523.45 seconds
Started Aug 14 04:47:15 PM PDT 24
Finished Aug 14 05:12:39 PM PDT 24
Peak memory 289788 kb
Host smart-8c2c9964-4d20-4243-8522-4c12da7e4ca2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4004927479 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.4004927479
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.3225753190
Short name T269
Test name
Test status
Simulation time 57879663458 ps
CPU time 3046.52 seconds
Started Aug 14 04:47:00 PM PDT 24
Finished Aug 14 05:37:47 PM PDT 24
Peak memory 289876 kb
Host smart-addffb65-5204-4ad5-bf44-3b409395536f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3225753190 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_han
dler_stress_all.3225753190
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.2826349681
Short name T317
Test name
Test status
Simulation time 18774661166 ps
CPU time 194.13 seconds
Started Aug 14 04:47:27 PM PDT 24
Finished Aug 14 04:50:41 PM PDT 24
Peak memory 248752 kb
Host smart-c462a468-a00c-4e0a-8379-871eaccd3190
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2826349681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.2826349681
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all_with_rand_reset.1199186779
Short name T103
Test name
Test status
Simulation time 16744763078 ps
CPU time 555.79 seconds
Started Aug 14 04:47:48 PM PDT 24
Finished Aug 14 04:57:04 PM PDT 24
Peak memory 281792 kb
Host smart-b223b241-fe9e-46a5-9f91-ec789ea2bccd
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1199186779 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 18.alert_handler_stress_all_with_rand_reset.1199186779
Directory /workspace/18.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.469670496
Short name T600
Test name
Test status
Simulation time 54725588623 ps
CPU time 561.91 seconds
Started Aug 14 04:46:56 PM PDT 24
Finished Aug 14 04:56:18 PM PDT 24
Peak memory 248804 kb
Host smart-e49efd6e-de2f-4ab3-abdc-8c8a4e1716d3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=469670496 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.469670496
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.585332109
Short name T256
Test name
Test status
Simulation time 1265652823 ps
CPU time 35.21 seconds
Started Aug 14 04:47:55 PM PDT 24
Finished Aug 14 04:48:31 PM PDT 24
Peak memory 249320 kb
Host smart-3d4fcda9-806f-41e6-ab01-9774b62c5c32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58533
2109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.585332109
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.2560005294
Short name T117
Test name
Test status
Simulation time 50217409431 ps
CPU time 1293.42 seconds
Started Aug 14 04:48:10 PM PDT 24
Finished Aug 14 05:09:44 PM PDT 24
Peak memory 289828 kb
Host smart-70105cd5-e881-490b-9cfe-9924338b60a6
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2560005294 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_ha
ndler_stress_all.2560005294
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all_with_rand_reset.875678876
Short name T56
Test name
Test status
Simulation time 16187782652 ps
CPU time 187.47 seconds
Started Aug 14 04:48:23 PM PDT 24
Finished Aug 14 04:51:30 PM PDT 24
Peak memory 265444 kb
Host smart-16fb7c3f-19ff-4c88-beca-c536be8b5920
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=875678876 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 46.alert_handler_stress_all_with_rand_reset.875678876
Directory /workspace/46.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.1952101462
Short name T36
Test name
Test status
Simulation time 48204939594 ps
CPU time 2394.4 seconds
Started Aug 14 04:47:08 PM PDT 24
Finished Aug 14 05:27:03 PM PDT 24
Peak memory 289712 kb
Host smart-987c42be-7076-43e5-808b-d7fb85a8a63b
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1952101462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_han
dler_stress_all.1952101462
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.688012824
Short name T28
Test name
Test status
Simulation time 30963099303 ps
CPU time 1261.71 seconds
Started Aug 14 04:48:03 PM PDT 24
Finished Aug 14 05:09:05 PM PDT 24
Peak memory 289736 kb
Host smart-b6b993c9-8f00-43cd-9174-4f5db938876e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=688012824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.688012824
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.3471252209
Short name T363
Test name
Test status
Simulation time 124773164117 ps
CPU time 562.59 seconds
Started Aug 14 04:58:31 PM PDT 24
Finished Aug 14 05:07:54 PM PDT 24
Peak memory 265640 kb
Host smart-f7a04cbf-55fc-4cdf-9dfa-6e603f7f5f40
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3471252209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.3471252209
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.2983224146
Short name T291
Test name
Test status
Simulation time 160615613 ps
CPU time 10.63 seconds
Started Aug 14 04:47:37 PM PDT 24
Finished Aug 14 04:47:48 PM PDT 24
Peak memory 253608 kb
Host smart-33001638-b789-4b3c-a9cb-613af9adc813
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29832
24146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.2983224146
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.674158059
Short name T716
Test name
Test status
Simulation time 19617755048 ps
CPU time 530.68 seconds
Started Aug 14 04:47:31 PM PDT 24
Finished Aug 14 04:56:22 PM PDT 24
Peak memory 255280 kb
Host smart-b3d04ccd-7073-4c6d-8bd7-7ae2192f7cb1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=674158059 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_han
dler_stress_all.674158059
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.1823481245
Short name T284
Test name
Test status
Simulation time 1395675818 ps
CPU time 47.77 seconds
Started Aug 14 04:47:32 PM PDT 24
Finished Aug 14 04:48:20 PM PDT 24
Peak memory 256280 kb
Host smart-2e64acbc-3a08-4d00-a662-80bfa6c43a20
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18234
81245 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.1823481245
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.1089357226
Short name T265
Test name
Test status
Simulation time 2044582826 ps
CPU time 11.27 seconds
Started Aug 14 04:47:41 PM PDT 24
Finished Aug 14 04:47:52 PM PDT 24
Peak memory 254420 kb
Host smart-d3d496c9-190f-440c-88e3-3a72070a0464
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10893
57226 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.1089357226
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all_with_rand_reset.1390760599
Short name T693
Test name
Test status
Simulation time 3407479164 ps
CPU time 437.77 seconds
Started Aug 14 04:47:39 PM PDT 24
Finished Aug 14 04:54:57 PM PDT 24
Peak memory 267984 kb
Host smart-b22b87da-8e7e-4ef3-9201-649126547274
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1390760599 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 24.alert_handler_stress_all_with_rand_reset.1390760599
Directory /workspace/24.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.1565699648
Short name T325
Test name
Test status
Simulation time 286462687038 ps
CPU time 2375.29 seconds
Started Aug 14 04:47:53 PM PDT 24
Finished Aug 14 05:27:28 PM PDT 24
Peak memory 271320 kb
Host smart-1cf46845-0e47-496c-8e13-3ecfdde4edcb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1565699648 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.1565699648
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.4233460117
Short name T341
Test name
Test status
Simulation time 63385953215 ps
CPU time 1358.11 seconds
Started Aug 14 04:46:57 PM PDT 24
Finished Aug 14 05:09:36 PM PDT 24
Peak memory 285916 kb
Host smart-e93fe548-16d8-403e-a188-a2eb2b040bb9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4233460117 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.4233460117
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.77696703
Short name T318
Test name
Test status
Simulation time 14595818199 ps
CPU time 356.56 seconds
Started Aug 14 04:48:09 PM PDT 24
Finished Aug 14 04:54:06 PM PDT 24
Peak memory 248716 kb
Host smart-20af57af-aa51-41f0-8ea0-9c59c1e2b150
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=77696703 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.77696703
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.1610390641
Short name T262
Test name
Test status
Simulation time 58893032480 ps
CPU time 3271.91 seconds
Started Aug 14 04:47:51 PM PDT 24
Finished Aug 14 05:42:24 PM PDT 24
Peak memory 289872 kb
Host smart-2992f281-65a5-42d0-a2a4-ddc0e8203063
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1610390641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_ha
ndler_stress_all.1610390641
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.4110851263
Short name T272
Test name
Test status
Simulation time 126256319401 ps
CPU time 645.38 seconds
Started Aug 14 04:48:12 PM PDT 24
Finished Aug 14 04:58:57 PM PDT 24
Peak memory 265296 kb
Host smart-3b3b19d3-cd1b-4150-8551-a840fc1d3bd3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4110851263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.4110851263
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all_with_rand_reset.2683466251
Short name T286
Test name
Test status
Simulation time 29893396779 ps
CPU time 505.89 seconds
Started Aug 14 04:46:58 PM PDT 24
Finished Aug 14 04:55:25 PM PDT 24
Peak memory 273560 kb
Host smart-2272251f-e035-4008-9f31-d22382018cf0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683466251 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.alert_handler_stress_all_with_rand_reset.2683466251
Directory /workspace/7.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.394759102
Short name T171
Test name
Test status
Simulation time 3861111862 ps
CPU time 76.3 seconds
Started Aug 14 04:57:51 PM PDT 24
Finished Aug 14 04:59:07 PM PDT 24
Peak memory 240884 kb
Host smart-cb8081b1-23c3-4b17-a858-2e189917699e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=394759102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.394759102
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.3545594671
Short name T179
Test name
Test status
Simulation time 3708277770 ps
CPU time 65.4 seconds
Started Aug 14 04:58:19 PM PDT 24
Finished Aug 14 04:59:24 PM PDT 24
Peak memory 240744 kb
Host smart-49e1cbdd-6b31-4979-b521-da14e6051cee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3545594671 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.3545594671
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.2327389418
Short name T134
Test name
Test status
Simulation time 8500801842 ps
CPU time 314.06 seconds
Started Aug 14 04:57:57 PM PDT 24
Finished Aug 14 05:03:11 PM PDT 24
Peak memory 265664 kb
Host smart-fde58fad-9e81-4701-96e3-7c7335699913
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2327389418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.2327389418
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.4242490776
Short name T184
Test name
Test status
Simulation time 213493321 ps
CPU time 4.02 seconds
Started Aug 14 04:57:43 PM PDT 24
Finished Aug 14 04:57:47 PM PDT 24
Peak memory 237788 kb
Host smart-8a355e23-a1b7-4ac4-8578-f79115b5cada
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4242490776 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.4242490776
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.3746963556
Short name T185
Test name
Test status
Simulation time 108637715 ps
CPU time 2.71 seconds
Started Aug 14 04:58:20 PM PDT 24
Finished Aug 14 04:58:22 PM PDT 24
Peak memory 236716 kb
Host smart-bd849cca-697a-46a9-aa29-00834e9eef16
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3746963556 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.3746963556
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.55280160
Short name T183
Test name
Test status
Simulation time 292347837 ps
CPU time 4.06 seconds
Started Aug 14 04:58:30 PM PDT 24
Finished Aug 14 04:58:34 PM PDT 24
Peak memory 237772 kb
Host smart-4057009a-48f1-4e97-a491-85616939eda2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=55280160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.55280160
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.2753557330
Short name T177
Test name
Test status
Simulation time 148019102 ps
CPU time 4.52 seconds
Started Aug 14 04:58:30 PM PDT 24
Finished Aug 14 04:58:35 PM PDT 24
Peak memory 237772 kb
Host smart-5ed76bcb-8cf7-47b9-a4dd-3eec15cfa22d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2753557330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.2753557330
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.471779170
Short name T176
Test name
Test status
Simulation time 99267931 ps
CPU time 2.8 seconds
Started Aug 14 04:58:00 PM PDT 24
Finished Aug 14 04:58:03 PM PDT 24
Peak memory 237768 kb
Host smart-078d3409-5bba-4666-90d0-96fcfd99cdeb
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=471779170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.471779170
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.3197190727
Short name T191
Test name
Test status
Simulation time 63145301 ps
CPU time 4.91 seconds
Started Aug 14 04:58:07 PM PDT 24
Finished Aug 14 04:58:12 PM PDT 24
Peak memory 237772 kb
Host smart-1950808b-19a3-4ba5-86f4-412a1f3156ee
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3197190727 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.3197190727
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.4192315129
Short name T181
Test name
Test status
Simulation time 25264954 ps
CPU time 2.67 seconds
Started Aug 14 04:58:19 PM PDT 24
Finished Aug 14 04:58:22 PM PDT 24
Peak memory 237644 kb
Host smart-cb1aeebf-7d4b-47a9-bbae-8da024d487d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4192315129 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.4192315129
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.1420187148
Short name T172
Test name
Test status
Simulation time 9864781918 ps
CPU time 82.84 seconds
Started Aug 14 04:58:30 PM PDT 24
Finished Aug 14 04:59:53 PM PDT 24
Peak memory 240664 kb
Host smart-7bc5730e-b274-4159-8206-e95fc11b138b
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1420187148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.1420187148
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.3291202492
Short name T178
Test name
Test status
Simulation time 170277312 ps
CPU time 22.52 seconds
Started Aug 14 04:57:55 PM PDT 24
Finished Aug 14 04:58:18 PM PDT 24
Peak memory 237876 kb
Host smart-bf56d897-072d-40e2-b9aa-35a3e203d9f6
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3291202492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.3291202492
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.1966125099
Short name T180
Test name
Test status
Simulation time 54043663 ps
CPU time 2.32 seconds
Started Aug 14 04:58:07 PM PDT 24
Finished Aug 14 04:58:10 PM PDT 24
Peak memory 238144 kb
Host smart-ef13cbd5-cf5d-481a-8f0f-99bce10b4bf1
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1966125099 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.1966125099
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.1264874006
Short name T192
Test name
Test status
Simulation time 157392452 ps
CPU time 3.22 seconds
Started Aug 14 04:57:57 PM PDT 24
Finished Aug 14 04:58:01 PM PDT 24
Peak memory 236872 kb
Host smart-91e22a93-9de8-437c-bd9e-24666e797a19
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1264874006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.1264874006
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.159257137
Short name T182
Test name
Test status
Simulation time 67587127 ps
CPU time 3.18 seconds
Started Aug 14 04:58:30 PM PDT 24
Finished Aug 14 04:58:34 PM PDT 24
Peak memory 237632 kb
Host smart-78616cc9-b04d-425f-8c95-d63bfed4897c
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=159257137 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.159257137
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.3073269514
Short name T186
Test name
Test status
Simulation time 63239505 ps
CPU time 3.05 seconds
Started Aug 14 04:58:00 PM PDT 24
Finished Aug 14 04:58:03 PM PDT 24
Peak memory 236632 kb
Host smart-d6fe00fd-7c37-452c-90b4-6d6efee18744
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3073269514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.3073269514
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.538881683
Short name T27
Test name
Test status
Simulation time 30579702296 ps
CPU time 918.98 seconds
Started Aug 14 04:47:34 PM PDT 24
Finished Aug 14 05:02:53 PM PDT 24
Peak memory 272000 kb
Host smart-beb65173-cd5a-4dea-9540-adb9efc4cf77
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=538881683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_han
dler_stress_all.538881683
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.3749516353
Short name T26
Test name
Test status
Simulation time 939001945 ps
CPU time 29.57 seconds
Started Aug 14 04:48:09 PM PDT 24
Finished Aug 14 04:48:38 PM PDT 24
Peak memory 248180 kb
Host smart-65aaf9d7-3eba-4c33-8cb1-20ed34fad0d5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37495
16353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.3749516353
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.3072340541
Short name T806
Test name
Test status
Simulation time 3453629691 ps
CPU time 248.53 seconds
Started Aug 14 04:57:47 PM PDT 24
Finished Aug 14 05:01:55 PM PDT 24
Peak memory 240776 kb
Host smart-7bb91a3b-8e51-40f1-842a-4311ee977d33
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3072340541 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.3072340541
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.540868101
Short name T361
Test name
Test status
Simulation time 11415669670 ps
CPU time 212.23 seconds
Started Aug 14 04:57:41 PM PDT 24
Finished Aug 14 05:01:14 PM PDT 24
Peak memory 237772 kb
Host smart-3b10badd-502b-4a20-b11e-e4e996bc5f68
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=540868101 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.540868101
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.2049647811
Short name T792
Test name
Test status
Simulation time 229716822 ps
CPU time 6.61 seconds
Started Aug 14 04:57:42 PM PDT 24
Finished Aug 14 04:57:49 PM PDT 24
Peak memory 240724 kb
Host smart-d12af92e-2066-4c55-aebf-7427adc5f67b
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2049647811 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.2049647811
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.838320059
Short name T830
Test name
Test status
Simulation time 186587109 ps
CPU time 13.52 seconds
Started Aug 14 04:57:51 PM PDT 24
Finished Aug 14 04:58:05 PM PDT 24
Peak memory 251928 kb
Host smart-d420edf3-7bca-42ff-89fd-4dcceb3e082c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=838320059 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 0.alert_handler_csr_mem_rw_with_rand_reset.838320059
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.2014091213
Short name T199
Test name
Test status
Simulation time 59897740 ps
CPU time 5.96 seconds
Started Aug 14 04:57:41 PM PDT 24
Finished Aug 14 04:57:48 PM PDT 24
Peak memory 236816 kb
Host smart-42131739-d7dc-4bc6-b817-c963ec1cf104
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2014091213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.2014091213
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.826877741
Short name T813
Test name
Test status
Simulation time 18733012 ps
CPU time 1.33 seconds
Started Aug 14 04:57:43 PM PDT 24
Finished Aug 14 04:57:44 PM PDT 24
Peak memory 237788 kb
Host smart-c4e277bd-797c-464b-966a-a9527ef9964a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=826877741 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.826877741
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.2889332979
Short name T801
Test name
Test status
Simulation time 1059119268 ps
CPU time 37.53 seconds
Started Aug 14 04:57:41 PM PDT 24
Finished Aug 14 04:58:19 PM PDT 24
Peak memory 245096 kb
Host smart-943cde28-0e67-4048-b219-35d92fd61640
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2889332979 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_out
standing.2889332979
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.2382945987
Short name T733
Test name
Test status
Simulation time 118402545 ps
CPU time 5.59 seconds
Started Aug 14 04:57:42 PM PDT 24
Finished Aug 14 04:57:47 PM PDT 24
Peak memory 253944 kb
Host smart-481d4da8-512f-4fb4-b86d-6854ed93b256
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2382945987 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.2382945987
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.1631153851
Short name T780
Test name
Test status
Simulation time 525750884 ps
CPU time 85 seconds
Started Aug 14 04:57:50 PM PDT 24
Finished Aug 14 04:59:15 PM PDT 24
Peak memory 237780 kb
Host smart-9f2034f7-c0ca-4ff4-8204-3240e2db5273
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1631153851 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.1631153851
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.1906162487
Short name T364
Test name
Test status
Simulation time 23729517432 ps
CPU time 419.32 seconds
Started Aug 14 04:57:49 PM PDT 24
Finished Aug 14 05:04:49 PM PDT 24
Peak memory 237836 kb
Host smart-926c711b-2064-4bf9-bfa3-62c846e7c8e4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1906162487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.1906162487
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.1721503047
Short name T800
Test name
Test status
Simulation time 22170860 ps
CPU time 4.61 seconds
Started Aug 14 04:57:55 PM PDT 24
Finished Aug 14 04:58:00 PM PDT 24
Peak memory 248808 kb
Host smart-96db8aeb-ad6c-4697-9cff-6cb88e1434e6
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1721503047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.1721503047
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.1409378506
Short name T770
Test name
Test status
Simulation time 940448665 ps
CPU time 16.37 seconds
Started Aug 14 04:57:51 PM PDT 24
Finished Aug 14 04:58:08 PM PDT 24
Peak memory 252388 kb
Host smart-95f7cd5f-0a14-4fc9-a1ab-ea1f737a0071
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1409378506 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 1.alert_handler_csr_mem_rw_with_rand_reset.1409378506
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.4268394803
Short name T783
Test name
Test status
Simulation time 96680514 ps
CPU time 6.63 seconds
Started Aug 14 04:57:49 PM PDT 24
Finished Aug 14 04:57:56 PM PDT 24
Peak memory 237740 kb
Host smart-cd12f2c6-481f-41d6-92f7-9304acddcdaa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4268394803 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.4268394803
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.3968143669
Short name T774
Test name
Test status
Simulation time 21497210 ps
CPU time 1.44 seconds
Started Aug 14 04:57:49 PM PDT 24
Finished Aug 14 04:57:51 PM PDT 24
Peak memory 236716 kb
Host smart-adf43567-b97b-422b-a2ab-bb128f1add64
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3968143669 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.3968143669
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.1431085034
Short name T771
Test name
Test status
Simulation time 176498093 ps
CPU time 19.92 seconds
Started Aug 14 04:57:50 PM PDT 24
Finished Aug 14 04:58:11 PM PDT 24
Peak memory 248952 kb
Host smart-b27001f8-6a9e-4e5a-bd1a-ce9ff64f9d2e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1431085034 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_out
standing.1431085034
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.1846161405
Short name T131
Test name
Test status
Simulation time 1628689075 ps
CPU time 87.8 seconds
Started Aug 14 04:57:49 PM PDT 24
Finished Aug 14 04:59:17 PM PDT 24
Peak memory 267980 kb
Host smart-872badbe-5936-46c0-a8e8-8b9398241c41
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1846161405 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_erro
rs.1846161405
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.540216494
Short name T137
Test name
Test status
Simulation time 25044323945 ps
CPU time 491.08 seconds
Started Aug 14 04:57:55 PM PDT 24
Finished Aug 14 05:06:07 PM PDT 24
Peak memory 265612 kb
Host smart-565b21ed-10c7-495d-b955-d7175330fc55
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=540216494 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.540216494
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.396524720
Short name T726
Test name
Test status
Simulation time 61553320 ps
CPU time 8.25 seconds
Started Aug 14 04:57:56 PM PDT 24
Finished Aug 14 04:58:05 PM PDT 24
Peak memory 248376 kb
Host smart-82b057c5-5d1f-4dde-bbbf-4f4011c6c1bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=396524720 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.396524720
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.289800598
Short name T360
Test name
Test status
Simulation time 217955322 ps
CPU time 9.2 seconds
Started Aug 14 04:58:07 PM PDT 24
Finished Aug 14 04:58:16 PM PDT 24
Peak memory 256840 kb
Host smart-d8ae9b41-34b9-42e4-8cf2-11dd30031b08
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=289800598 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 10.alert_handler_csr_mem_rw_with_rand_reset.289800598
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.1356246826
Short name T745
Test name
Test status
Simulation time 25997566 ps
CPU time 1.51 seconds
Started Aug 14 04:58:08 PM PDT 24
Finished Aug 14 04:58:09 PM PDT 24
Peak memory 237796 kb
Host smart-9a13d1dc-ea31-42af-81c5-92fae7e6cd61
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1356246826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.1356246826
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.1654918943
Short name T197
Test name
Test status
Simulation time 1026229477 ps
CPU time 34.73 seconds
Started Aug 14 04:58:07 PM PDT 24
Finished Aug 14 04:58:42 PM PDT 24
Peak memory 245892 kb
Host smart-dcf35668-8a9b-4670-b85a-e79b4c6fddae
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1654918943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_ou
tstanding.1654918943
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.1701194350
Short name T151
Test name
Test status
Simulation time 3228569698 ps
CPU time 114.06 seconds
Started Aug 14 04:58:06 PM PDT 24
Finished Aug 14 05:00:00 PM PDT 24
Peak memory 265688 kb
Host smart-6a623784-fdbf-48ed-bedf-f6ca35d19928
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1701194350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_err
ors.1701194350
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.2335486717
Short name T734
Test name
Test status
Simulation time 448456092 ps
CPU time 10.8 seconds
Started Aug 14 04:58:07 PM PDT 24
Finished Aug 14 04:58:18 PM PDT 24
Peak memory 254612 kb
Host smart-8bf6de22-3982-4acc-b5b0-276f2ce4e991
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2335486717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.2335486717
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.4169965332
Short name T204
Test name
Test status
Simulation time 40142291 ps
CPU time 3.7 seconds
Started Aug 14 04:58:06 PM PDT 24
Finished Aug 14 04:58:10 PM PDT 24
Peak memory 237780 kb
Host smart-67936ff9-8514-4ad7-ba22-0387869fcf2e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4169965332 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.4169965332
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.2107214839
Short name T365
Test name
Test status
Simulation time 98187235 ps
CPU time 8.91 seconds
Started Aug 14 04:58:24 PM PDT 24
Finished Aug 14 04:58:33 PM PDT 24
Peak memory 240792 kb
Host smart-21a9aae1-4c22-4c75-9aa2-820c12ab68e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2107214839 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.alert_handler_csr_mem_rw_with_rand_reset.2107214839
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.1046492038
Short name T798
Test name
Test status
Simulation time 34418237 ps
CPU time 3.37 seconds
Started Aug 14 04:58:21 PM PDT 24
Finished Aug 14 04:58:24 PM PDT 24
Peak memory 237664 kb
Host smart-f85524b2-6d68-4eca-8199-510dec590e03
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1046492038 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.1046492038
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.3172739144
Short name T752
Test name
Test status
Simulation time 13901308 ps
CPU time 1.29 seconds
Started Aug 14 04:58:20 PM PDT 24
Finished Aug 14 04:58:21 PM PDT 24
Peak memory 237788 kb
Host smart-6b1b7aca-8dab-49a8-b538-8ee3df2adecb
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3172739144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.3172739144
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.2605171968
Short name T767
Test name
Test status
Simulation time 94693343 ps
CPU time 15.19 seconds
Started Aug 14 04:58:20 PM PDT 24
Finished Aug 14 04:58:35 PM PDT 24
Peak memory 245836 kb
Host smart-42356cc8-a785-4048-bcce-31e526371980
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2605171968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_ou
tstanding.2605171968
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.2447602285
Short name T145
Test name
Test status
Simulation time 26858622095 ps
CPU time 515.32 seconds
Started Aug 14 04:58:06 PM PDT 24
Finished Aug 14 05:06:41 PM PDT 24
Peak memory 265856 kb
Host smart-baedff16-a507-4214-91a4-95ef6ccb52e0
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2447602285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.2447602285
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.2560058779
Short name T805
Test name
Test status
Simulation time 106454755 ps
CPU time 7.92 seconds
Started Aug 14 04:58:19 PM PDT 24
Finished Aug 14 04:58:27 PM PDT 24
Peak memory 248972 kb
Host smart-faf7cc05-ab27-4a67-a2b1-88ee74832a08
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2560058779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.2560058779
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.2972299970
Short name T765
Test name
Test status
Simulation time 78711812 ps
CPU time 7.4 seconds
Started Aug 14 04:58:20 PM PDT 24
Finished Aug 14 04:58:27 PM PDT 24
Peak memory 240604 kb
Host smart-2db5b59f-89ce-43a8-bc06-eab506f94e8d
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972299970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 12.alert_handler_csr_mem_rw_with_rand_reset.2972299970
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.1715833145
Short name T189
Test name
Test status
Simulation time 89905501 ps
CPU time 5.26 seconds
Started Aug 14 04:58:19 PM PDT 24
Finished Aug 14 04:58:25 PM PDT 24
Peak memory 237780 kb
Host smart-f2b3926c-b33f-48b7-87db-b5196f32c26f
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1715833145 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.1715833145
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.387942727
Short name T820
Test name
Test status
Simulation time 707853220 ps
CPU time 25.85 seconds
Started Aug 14 04:58:20 PM PDT 24
Finished Aug 14 04:58:46 PM PDT 24
Peak memory 245972 kb
Host smart-4c79dddc-7ece-41d7-8f54-10d5c0daee3d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=387942727 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_out
standing.387942727
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.3188922778
Short name T158
Test name
Test status
Simulation time 14463672424 ps
CPU time 299.07 seconds
Started Aug 14 04:58:17 PM PDT 24
Finished Aug 14 05:03:17 PM PDT 24
Peak memory 265652 kb
Host smart-423e0d19-366c-46b1-b660-625b04422d65
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3188922778 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_err
ors.3188922778
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.2551651526
Short name T725
Test name
Test status
Simulation time 94370880 ps
CPU time 13.84 seconds
Started Aug 14 04:58:23 PM PDT 24
Finished Aug 14 04:58:37 PM PDT 24
Peak memory 256808 kb
Host smart-e76727d0-611f-4ae5-8d04-e99c9289f64f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2551651526 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.2551651526
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.1781766709
Short name T729
Test name
Test status
Simulation time 111260893 ps
CPU time 10.03 seconds
Started Aug 14 04:58:20 PM PDT 24
Finished Aug 14 04:58:30 PM PDT 24
Peak memory 252892 kb
Host smart-7822b50f-ac66-465b-97ed-7fb75132437b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1781766709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 13.alert_handler_csr_mem_rw_with_rand_reset.1781766709
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.3930116918
Short name T200
Test name
Test status
Simulation time 324868460 ps
CPU time 4.95 seconds
Started Aug 14 04:58:19 PM PDT 24
Finished Aug 14 04:58:24 PM PDT 24
Peak memory 236796 kb
Host smart-ca55ce52-f803-41ed-83fe-b2db5c26c6aa
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3930116918 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.3930116918
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.3721055825
Short name T747
Test name
Test status
Simulation time 17148173 ps
CPU time 1.51 seconds
Started Aug 14 04:58:20 PM PDT 24
Finished Aug 14 04:58:21 PM PDT 24
Peak memory 236808 kb
Host smart-4dff1386-6539-4d25-b9a6-b265954b309e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3721055825 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.3721055825
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.1564944676
Short name T739
Test name
Test status
Simulation time 967909625 ps
CPU time 39.45 seconds
Started Aug 14 04:58:19 PM PDT 24
Finished Aug 14 04:58:59 PM PDT 24
Peak memory 245896 kb
Host smart-43c0d523-d0cd-4fbe-86f3-dc7c9302593c
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1564944676 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_ou
tstanding.1564944676
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.425524472
Short name T141
Test name
Test status
Simulation time 3310495863 ps
CPU time 211.4 seconds
Started Aug 14 04:58:20 PM PDT 24
Finished Aug 14 05:01:52 PM PDT 24
Peak memory 265688 kb
Host smart-76e1b3de-3151-4390-a869-b9a1ca8c917e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=425524472 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_erro
rs.425524472
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.741943815
Short name T724
Test name
Test status
Simulation time 32052572 ps
CPU time 4.1 seconds
Started Aug 14 04:58:21 PM PDT 24
Finished Aug 14 04:58:25 PM PDT 24
Peak memory 248888 kb
Host smart-3d89a862-dadc-458e-82a8-e2bb239d6310
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=741943815 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.741943815
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.197445082
Short name T749
Test name
Test status
Simulation time 1388380027 ps
CPU time 16.49 seconds
Started Aug 14 04:58:30 PM PDT 24
Finished Aug 14 04:58:47 PM PDT 24
Peak memory 244004 kb
Host smart-97f87fbd-a6f6-4b04-a142-2935bada629a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=197445082 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 14.alert_handler_csr_mem_rw_with_rand_reset.197445082
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.2492266813
Short name T195
Test name
Test status
Simulation time 37392798 ps
CPU time 6.24 seconds
Started Aug 14 04:58:21 PM PDT 24
Finished Aug 14 04:58:27 PM PDT 24
Peak memory 237772 kb
Host smart-9487324b-2d20-40c8-be00-aae79ef5fcb0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2492266813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.2492266813
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.1866807878
Short name T790
Test name
Test status
Simulation time 29166137 ps
CPU time 1.47 seconds
Started Aug 14 04:58:19 PM PDT 24
Finished Aug 14 04:58:21 PM PDT 24
Peak memory 237660 kb
Host smart-059d8e1b-51a6-423e-8683-11c94716842d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1866807878 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.1866807878
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.3938518350
Short name T797
Test name
Test status
Simulation time 1206593101 ps
CPU time 22.13 seconds
Started Aug 14 04:58:21 PM PDT 24
Finished Aug 14 04:58:43 PM PDT 24
Peak memory 245016 kb
Host smart-26cecafc-8761-4f2d-9307-a2508d4e6c58
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3938518350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_ou
tstanding.3938518350
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.1024560678
Short name T159
Test name
Test status
Simulation time 25643440539 ps
CPU time 198.32 seconds
Started Aug 14 04:58:19 PM PDT 24
Finished Aug 14 05:01:38 PM PDT 24
Peak memory 265612 kb
Host smart-d2fd1c6a-db40-4061-b2d8-d739da404ba9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1024560678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_err
ors.1024560678
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.654165713
Short name T164
Test name
Test status
Simulation time 65841748944 ps
CPU time 1203.93 seconds
Started Aug 14 04:58:21 PM PDT 24
Finished Aug 14 05:18:25 PM PDT 24
Peak memory 265636 kb
Host smart-c111e979-66fb-4183-8e7f-6e7a9c021192
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=654165713 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.654165713
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.81028751
Short name T763
Test name
Test status
Simulation time 38302156 ps
CPU time 3.09 seconds
Started Aug 14 04:58:21 PM PDT 24
Finished Aug 14 04:58:24 PM PDT 24
Peak memory 247772 kb
Host smart-16faf2cf-95c2-44dc-a591-5ac15c410279
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=81028751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.81028751
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.2531606055
Short name T742
Test name
Test status
Simulation time 78671065 ps
CPU time 6.64 seconds
Started Aug 14 04:58:44 PM PDT 24
Finished Aug 14 04:58:51 PM PDT 24
Peak memory 241176 kb
Host smart-e4cf53b4-a370-475e-b515-e88306407263
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2531606055 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 15.alert_handler_csr_mem_rw_with_rand_reset.2531606055
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.955423395
Short name T362
Test name
Test status
Simulation time 204946931 ps
CPU time 4.9 seconds
Started Aug 14 04:58:31 PM PDT 24
Finished Aug 14 04:58:36 PM PDT 24
Peak memory 237804 kb
Host smart-7b4b32de-2f82-4784-be35-5471b32f9965
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=955423395 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.955423395
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.3385424960
Short name T756
Test name
Test status
Simulation time 8609469 ps
CPU time 1.39 seconds
Started Aug 14 04:58:44 PM PDT 24
Finished Aug 14 04:58:45 PM PDT 24
Peak memory 236900 kb
Host smart-3bd880cd-2340-4f75-8c04-ddd79c2a7649
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3385424960 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.3385424960
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.4276952901
Short name T194
Test name
Test status
Simulation time 169824846 ps
CPU time 27.38 seconds
Started Aug 14 04:58:32 PM PDT 24
Finished Aug 14 04:59:00 PM PDT 24
Peak memory 245956 kb
Host smart-5bec2e2f-0e93-493c-b5a6-c00f8b09635f
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4276952901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_ou
tstanding.4276952901
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.448272514
Short name T148
Test name
Test status
Simulation time 4808423487 ps
CPU time 158.41 seconds
Started Aug 14 04:58:30 PM PDT 24
Finished Aug 14 05:01:09 PM PDT 24
Peak memory 265700 kb
Host smart-71e9c4f2-2923-4e78-936e-a0ef230d1b8f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=448272514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_erro
rs.448272514
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.2688155477
Short name T144
Test name
Test status
Simulation time 8301355779 ps
CPU time 328.07 seconds
Started Aug 14 04:58:31 PM PDT 24
Finished Aug 14 05:04:00 PM PDT 24
Peak memory 265664 kb
Host smart-27facd49-65f5-43d5-a915-83d658084c0f
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2688155477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.2688155477
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.451195431
Short name T248
Test name
Test status
Simulation time 1042000643 ps
CPU time 22.83 seconds
Started Aug 14 04:58:30 PM PDT 24
Finished Aug 14 04:58:54 PM PDT 24
Peak memory 255608 kb
Host smart-e09c317d-1038-40b8-9dbc-433c6670e15d
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=451195431 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.451195431
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.1558169839
Short name T773
Test name
Test status
Simulation time 37859879 ps
CPU time 5.51 seconds
Started Aug 14 04:58:31 PM PDT 24
Finished Aug 14 04:58:36 PM PDT 24
Peak memory 251976 kb
Host smart-ccda5fb5-aa89-45e1-9881-e8fa263f133a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1558169839 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 16.alert_handler_csr_mem_rw_with_rand_reset.1558169839
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.1432841145
Short name T808
Test name
Test status
Simulation time 500936847 ps
CPU time 8.87 seconds
Started Aug 14 04:58:43 PM PDT 24
Finished Aug 14 04:58:52 PM PDT 24
Peak memory 237764 kb
Host smart-83d4ea7b-e878-4601-8ff1-bf7d17a873d2
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1432841145 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.1432841145
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.234269134
Short name T822
Test name
Test status
Simulation time 10527281 ps
CPU time 1.65 seconds
Started Aug 14 04:58:31 PM PDT 24
Finished Aug 14 04:58:32 PM PDT 24
Peak memory 236840 kb
Host smart-64041523-a91f-43b8-bf13-b0711810ddf2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=234269134 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.234269134
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.2415711806
Short name T824
Test name
Test status
Simulation time 288507362 ps
CPU time 20.57 seconds
Started Aug 14 04:58:28 PM PDT 24
Finished Aug 14 04:58:49 PM PDT 24
Peak memory 245040 kb
Host smart-fde967b4-44ac-4865-8a75-6196c5d74987
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2415711806 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_ou
tstanding.2415711806
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.794213050
Short name T140
Test name
Test status
Simulation time 18190053894 ps
CPU time 147.46 seconds
Started Aug 14 04:58:44 PM PDT 24
Finished Aug 14 05:01:11 PM PDT 24
Peak memory 266580 kb
Host smart-c0bf2f56-8887-4eae-93e5-2c1b2ca1ee6d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=794213050 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_erro
rs.794213050
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.343599349
Short name T154
Test name
Test status
Simulation time 26754181447 ps
CPU time 1058.06 seconds
Started Aug 14 04:58:29 PM PDT 24
Finished Aug 14 05:16:08 PM PDT 24
Peak memory 265672 kb
Host smart-ddf35047-a79c-49f1-8af0-1296c4da14ea
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=343599349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.343599349
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.1477507982
Short name T731
Test name
Test status
Simulation time 74815758 ps
CPU time 10.7 seconds
Started Aug 14 04:58:31 PM PDT 24
Finished Aug 14 04:58:42 PM PDT 24
Peak memory 256316 kb
Host smart-cf031827-88fa-46de-a3c6-9f5640197db3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1477507982 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.1477507982
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.1469464894
Short name T761
Test name
Test status
Simulation time 578336574 ps
CPU time 6.12 seconds
Started Aug 14 04:58:29 PM PDT 24
Finished Aug 14 04:58:35 PM PDT 24
Peak memory 240680 kb
Host smart-f3ffe3e3-3a1d-450f-a361-3ddb74361c4f
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1469464894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 17.alert_handler_csr_mem_rw_with_rand_reset.1469464894
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.1966085251
Short name T776
Test name
Test status
Simulation time 312656795 ps
CPU time 5.15 seconds
Started Aug 14 04:58:30 PM PDT 24
Finished Aug 14 04:58:35 PM PDT 24
Peak memory 240656 kb
Host smart-ebc2359c-d1c5-4eab-8ad7-d057edacaa57
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1966085251 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.1966085251
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.4255458395
Short name T827
Test name
Test status
Simulation time 343853478 ps
CPU time 25.36 seconds
Started Aug 14 04:58:29 PM PDT 24
Finished Aug 14 04:58:55 PM PDT 24
Peak memory 245080 kb
Host smart-8b1c55fa-2dcd-4401-b3c2-4d514abe2d07
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4255458395 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_ou
tstanding.4255458395
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.828990318
Short name T723
Test name
Test status
Simulation time 92184298 ps
CPU time 9.6 seconds
Started Aug 14 04:58:30 PM PDT 24
Finished Aug 14 04:58:39 PM PDT 24
Peak memory 249996 kb
Host smart-e7d7216d-272d-48a9-b07b-678aaef63715
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=828990318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.828990318
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.3006334514
Short name T190
Test name
Test status
Simulation time 109212610 ps
CPU time 9.25 seconds
Started Aug 14 04:58:30 PM PDT 24
Finished Aug 14 04:58:39 PM PDT 24
Peak memory 241072 kb
Host smart-7e6d19cc-b029-4bf5-8ad7-e144697ffc3c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3006334514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 18.alert_handler_csr_mem_rw_with_rand_reset.3006334514
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.3697241975
Short name T829
Test name
Test status
Simulation time 128905767 ps
CPU time 10.3 seconds
Started Aug 14 04:58:29 PM PDT 24
Finished Aug 14 04:58:39 PM PDT 24
Peak memory 237676 kb
Host smart-fee8f6bf-5ca9-48ad-b8fb-681eceb16215
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3697241975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.3697241975
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.1722013968
Short name T175
Test name
Test status
Simulation time 6811578 ps
CPU time 1.55 seconds
Started Aug 14 04:58:31 PM PDT 24
Finished Aug 14 04:58:33 PM PDT 24
Peak memory 236932 kb
Host smart-1788994e-cb14-4e51-8d01-108839e26b62
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1722013968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.1722013968
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.2161109188
Short name T821
Test name
Test status
Simulation time 338460103 ps
CPU time 23.4 seconds
Started Aug 14 04:58:31 PM PDT 24
Finished Aug 14 04:58:54 PM PDT 24
Peak memory 240692 kb
Host smart-3e23d87e-24d4-4b04-a328-ff5c7e0a3de0
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2161109188 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_ou
tstanding.2161109188
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.3621718778
Short name T160
Test name
Test status
Simulation time 14622443541 ps
CPU time 249.16 seconds
Started Aug 14 04:58:31 PM PDT 24
Finished Aug 14 05:02:40 PM PDT 24
Peak memory 265608 kb
Host smart-c654e43f-570f-41aa-91f3-f5565e638f2c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3621718778 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_err
ors.3621718778
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.2074580589
Short name T156
Test name
Test status
Simulation time 33978843893 ps
CPU time 1199.81 seconds
Started Aug 14 04:58:43 PM PDT 24
Finished Aug 14 05:18:43 PM PDT 24
Peak memory 273652 kb
Host smart-723045bd-836f-4369-a2aa-94cb630f2ff0
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2074580589 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.2074580589
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.3964027371
Short name T803
Test name
Test status
Simulation time 205908643 ps
CPU time 17.09 seconds
Started Aug 14 04:58:31 PM PDT 24
Finished Aug 14 04:58:48 PM PDT 24
Peak memory 248916 kb
Host smart-8617b73b-a1d2-4672-a8b4-a8801180d73a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3964027371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.3964027371
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.3686905658
Short name T755
Test name
Test status
Simulation time 118590851 ps
CPU time 4.83 seconds
Started Aug 14 04:58:31 PM PDT 24
Finished Aug 14 04:58:36 PM PDT 24
Peak memory 257068 kb
Host smart-d960f259-08f0-4bba-ae23-65b76eb7cda4
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3686905658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 19.alert_handler_csr_mem_rw_with_rand_reset.3686905658
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.3121701705
Short name T781
Test name
Test status
Simulation time 54556598 ps
CPU time 3.19 seconds
Started Aug 14 04:58:29 PM PDT 24
Finished Aug 14 04:58:33 PM PDT 24
Peak memory 236740 kb
Host smart-08f706dc-5bdc-44f7-8547-3c0fa6e39d30
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3121701705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.3121701705
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.3035853056
Short name T802
Test name
Test status
Simulation time 6827661 ps
CPU time 1.44 seconds
Started Aug 14 04:58:29 PM PDT 24
Finished Aug 14 04:58:31 PM PDT 24
Peak memory 236876 kb
Host smart-d3ffabe0-8c59-4e9f-af25-15c60e90723a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3035853056 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.3035853056
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.12847567
Short name T826
Test name
Test status
Simulation time 2007497871 ps
CPU time 39.93 seconds
Started Aug 14 04:58:30 PM PDT 24
Finished Aug 14 04:59:10 PM PDT 24
Peak memory 248836 kb
Host smart-97b3015b-11f5-45ab-a6b6-22e2e5b78936
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=12847567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_outs
tanding.12847567
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.3920005614
Short name T831
Test name
Test status
Simulation time 87857188 ps
CPU time 12.88 seconds
Started Aug 14 04:58:32 PM PDT 24
Finished Aug 14 04:58:45 PM PDT 24
Peak memory 254604 kb
Host smart-67b9c25d-f1a0-4164-a3eb-fff0246924c3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3920005614 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.3920005614
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.438807246
Short name T203
Test name
Test status
Simulation time 2227439189 ps
CPU time 73.1 seconds
Started Aug 14 04:57:57 PM PDT 24
Finished Aug 14 04:59:10 PM PDT 24
Peak memory 237832 kb
Host smart-f09ee9ea-78a2-47d2-83a6-d2a05b55cdcb
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=438807246 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.438807246
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.4023971410
Short name T196
Test name
Test status
Simulation time 4559106248 ps
CPU time 267.35 seconds
Started Aug 14 04:57:56 PM PDT 24
Finished Aug 14 05:02:23 PM PDT 24
Peak memory 237848 kb
Host smart-67ecc35d-125d-4a79-9237-f39764e65357
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4023971410 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.4023971410
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.2160557437
Short name T810
Test name
Test status
Simulation time 64198488 ps
CPU time 5.65 seconds
Started Aug 14 04:57:49 PM PDT 24
Finished Aug 14 04:57:54 PM PDT 24
Peak memory 248924 kb
Host smart-d09c349c-b889-46c4-9c86-e85f593a9345
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2160557437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.2160557437
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.1607798696
Short name T757
Test name
Test status
Simulation time 87108003 ps
CPU time 8.24 seconds
Started Aug 14 04:57:50 PM PDT 24
Finished Aug 14 04:57:58 PM PDT 24
Peak memory 241324 kb
Host smart-d7de2beb-b4da-47ae-80c0-b5ad5ab82b89
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1607798696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.alert_handler_csr_mem_rw_with_rand_reset.1607798696
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.2615362622
Short name T193
Test name
Test status
Simulation time 114091769 ps
CPU time 5.07 seconds
Started Aug 14 04:57:55 PM PDT 24
Finished Aug 14 04:58:01 PM PDT 24
Peak memory 239580 kb
Host smart-bd1213d1-3ac1-4ccf-909e-69012561c8dd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2615362622 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.2615362622
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.282509261
Short name T740
Test name
Test status
Simulation time 267539708 ps
CPU time 22.4 seconds
Started Aug 14 04:57:49 PM PDT 24
Finished Aug 14 04:58:12 PM PDT 24
Peak memory 245972 kb
Host smart-8cd290a0-bb7d-4872-a390-d8b73b82f220
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=282509261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_outs
tanding.282509261
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.2455017001
Short name T152
Test name
Test status
Simulation time 32953462135 ps
CPU time 636.62 seconds
Started Aug 14 04:57:57 PM PDT 24
Finished Aug 14 05:08:34 PM PDT 24
Peak memory 265636 kb
Host smart-666f9cd1-dfe5-4f51-8c49-0e2989279569
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2455017001 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.2455017001
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.372234719
Short name T753
Test name
Test status
Simulation time 269278725 ps
CPU time 12.33 seconds
Started Aug 14 04:57:52 PM PDT 24
Finished Aug 14 04:58:04 PM PDT 24
Peak memory 255924 kb
Host smart-43f93656-f023-47a4-a2eb-eb21c34ca9a3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=372234719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.372234719
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.4276880997
Short name T352
Test name
Test status
Simulation time 17956327 ps
CPU time 1.39 seconds
Started Aug 14 04:58:29 PM PDT 24
Finished Aug 14 04:58:31 PM PDT 24
Peak memory 237720 kb
Host smart-cd3a4e5f-73cd-4c53-80ec-ad5133ba6a8f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4276880997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.4276880997
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.3190943671
Short name T750
Test name
Test status
Simulation time 8822543 ps
CPU time 1.35 seconds
Started Aug 14 04:58:37 PM PDT 24
Finished Aug 14 04:58:38 PM PDT 24
Peak memory 237752 kb
Host smart-3050b9e8-4ca8-427c-b057-f3b2929dd289
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3190943671 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.3190943671
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.331024087
Short name T814
Test name
Test status
Simulation time 32442811 ps
CPU time 1.41 seconds
Started Aug 14 04:58:39 PM PDT 24
Finished Aug 14 04:58:40 PM PDT 24
Peak memory 236908 kb
Host smart-fe321597-69a1-449d-8013-fb0914635794
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=331024087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.331024087
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.2329679948
Short name T823
Test name
Test status
Simulation time 8328770 ps
CPU time 1.54 seconds
Started Aug 14 04:58:39 PM PDT 24
Finished Aug 14 04:58:40 PM PDT 24
Peak memory 235756 kb
Host smart-189cf7c4-26a8-4917-a208-7f8f1744332c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2329679948 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.2329679948
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.2139509003
Short name T807
Test name
Test status
Simulation time 10687965 ps
CPU time 1.35 seconds
Started Aug 14 04:58:38 PM PDT 24
Finished Aug 14 04:58:40 PM PDT 24
Peak memory 236792 kb
Host smart-b8e93a8a-815a-4c73-8637-dc3853880b84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2139509003 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.2139509003
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.3398948526
Short name T789
Test name
Test status
Simulation time 31012509 ps
CPU time 2.26 seconds
Started Aug 14 04:58:45 PM PDT 24
Finished Aug 14 04:58:47 PM PDT 24
Peak memory 236896 kb
Host smart-91d69750-d317-4800-9b67-20f05607a711
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3398948526 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.3398948526
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.2707061599
Short name T812
Test name
Test status
Simulation time 10381158 ps
CPU time 1.18 seconds
Started Aug 14 04:58:36 PM PDT 24
Finished Aug 14 04:58:37 PM PDT 24
Peak memory 237672 kb
Host smart-8ecf20fb-0c9f-4271-9d72-6f91d0862eab
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2707061599 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.2707061599
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.1956773086
Short name T766
Test name
Test status
Simulation time 18530259 ps
CPU time 1.26 seconds
Started Aug 14 04:58:37 PM PDT 24
Finished Aug 14 04:58:38 PM PDT 24
Peak memory 236800 kb
Host smart-8e5bd27b-083c-4f7a-bc2b-25ad624dadd0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1956773086 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.1956773086
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.3286374574
Short name T744
Test name
Test status
Simulation time 8256800 ps
CPU time 1.47 seconds
Started Aug 14 04:58:39 PM PDT 24
Finished Aug 14 04:58:40 PM PDT 24
Peak memory 237804 kb
Host smart-c19a75ff-b3de-49ca-b817-34e055ed8a10
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3286374574 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.3286374574
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.2641186832
Short name T762
Test name
Test status
Simulation time 11993726 ps
CPU time 1.35 seconds
Started Aug 14 04:58:41 PM PDT 24
Finished Aug 14 04:58:42 PM PDT 24
Peak memory 236892 kb
Host smart-db7eea36-767d-4b64-8f74-d5aa8d24318c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2641186832 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.2641186832
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.294922418
Short name T784
Test name
Test status
Simulation time 15350942264 ps
CPU time 117.8 seconds
Started Aug 14 04:57:56 PM PDT 24
Finished Aug 14 04:59:54 PM PDT 24
Peak memory 240712 kb
Host smart-b9ef3087-d6f0-4ec1-90b4-0c623d4897c5
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=294922418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.294922418
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.1415597636
Short name T768
Test name
Test status
Simulation time 22840610381 ps
CPU time 406.18 seconds
Started Aug 14 04:57:52 PM PDT 24
Finished Aug 14 05:04:38 PM PDT 24
Peak memory 240788 kb
Host smart-0ebb12b2-d46f-46db-964d-f8b2181759b7
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1415597636 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.1415597636
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.3050493293
Short name T727
Test name
Test status
Simulation time 89172983 ps
CPU time 3.73 seconds
Started Aug 14 04:57:48 PM PDT 24
Finished Aug 14 04:57:52 PM PDT 24
Peak memory 248808 kb
Host smart-2271bd73-caaf-41b1-b276-3db4f76bcc95
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3050493293 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.3050493293
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.3434402600
Short name T730
Test name
Test status
Simulation time 120031265 ps
CPU time 8.84 seconds
Started Aug 14 04:57:50 PM PDT 24
Finished Aug 14 04:57:59 PM PDT 24
Peak memory 253264 kb
Host smart-a0dcc52d-38a4-4ded-bde5-63a3387d88e3
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3434402600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.alert_handler_csr_mem_rw_with_rand_reset.3434402600
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.514383848
Short name T728
Test name
Test status
Simulation time 91838064 ps
CPU time 4.44 seconds
Started Aug 14 04:57:48 PM PDT 24
Finished Aug 14 04:57:53 PM PDT 24
Peak memory 236872 kb
Host smart-2bfa1a95-d2cf-438b-9be5-67a2f5d58a60
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=514383848 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.514383848
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.1576023418
Short name T735
Test name
Test status
Simulation time 9900238 ps
CPU time 1.55 seconds
Started Aug 14 04:57:56 PM PDT 24
Finished Aug 14 04:57:58 PM PDT 24
Peak memory 236864 kb
Host smart-f5313157-1b17-4621-b330-ad6fda98c779
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1576023418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.1576023418
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.3373921087
Short name T819
Test name
Test status
Simulation time 324461824 ps
CPU time 11.17 seconds
Started Aug 14 04:57:55 PM PDT 24
Finished Aug 14 04:58:06 PM PDT 24
Peak memory 248956 kb
Host smart-4e7518e3-7c86-4a49-b731-affed6c1854a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3373921087 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_out
standing.3373921087
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.2207407436
Short name T161
Test name
Test status
Simulation time 4045054955 ps
CPU time 274.38 seconds
Started Aug 14 04:57:48 PM PDT 24
Finished Aug 14 05:02:22 PM PDT 24
Peak memory 271476 kb
Host smart-65ca9670-a619-4e2c-8feb-eadbc016ee8d
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2207407436 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_erro
rs.2207407436
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.2093690696
Short name T817
Test name
Test status
Simulation time 1130727502 ps
CPU time 19.99 seconds
Started Aug 14 04:57:50 PM PDT 24
Finished Aug 14 04:58:10 PM PDT 24
Peak memory 255460 kb
Host smart-b26aa8ad-1dc1-42de-aa96-cfbf1b083801
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2093690696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.2093690696
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.2334277562
Short name T187
Test name
Test status
Simulation time 21884452 ps
CPU time 2.29 seconds
Started Aug 14 04:57:49 PM PDT 24
Finished Aug 14 04:57:51 PM PDT 24
Peak memory 237672 kb
Host smart-4a3b309b-d216-4e71-81d6-56e1d8626826
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2334277562 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.2334277562
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.729343205
Short name T785
Test name
Test status
Simulation time 9043291 ps
CPU time 1.51 seconds
Started Aug 14 04:58:37 PM PDT 24
Finished Aug 14 04:58:39 PM PDT 24
Peak memory 237652 kb
Host smart-9f36d28c-9f3a-4fc7-b50c-75f5a771684e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=729343205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.729343205
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.903252484
Short name T355
Test name
Test status
Simulation time 7312641 ps
CPU time 1.44 seconds
Started Aug 14 04:58:37 PM PDT 24
Finished Aug 14 04:58:39 PM PDT 24
Peak memory 235724 kb
Host smart-0301e752-cfeb-4068-959d-d6699209a638
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=903252484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.903252484
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.857917479
Short name T758
Test name
Test status
Simulation time 25815714 ps
CPU time 1.71 seconds
Started Aug 14 04:58:38 PM PDT 24
Finished Aug 14 04:58:39 PM PDT 24
Peak memory 236844 kb
Host smart-ae805811-31a2-4ee8-9f7f-18a9e29c5ce1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=857917479 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.857917479
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.291374722
Short name T732
Test name
Test status
Simulation time 10278414 ps
CPU time 1.26 seconds
Started Aug 14 04:58:44 PM PDT 24
Finished Aug 14 04:58:46 PM PDT 24
Peak memory 236896 kb
Host smart-23440c5a-bce9-4160-ab6a-5735028f2f24
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=291374722 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.291374722
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.1834825688
Short name T818
Test name
Test status
Simulation time 19694824 ps
CPU time 1.33 seconds
Started Aug 14 04:58:38 PM PDT 24
Finished Aug 14 04:58:40 PM PDT 24
Peak memory 235816 kb
Host smart-7b8674c5-72dc-41f9-9681-56dbdfc353ca
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1834825688 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.1834825688
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.4126008003
Short name T760
Test name
Test status
Simulation time 6530787 ps
CPU time 1.41 seconds
Started Aug 14 04:58:38 PM PDT 24
Finished Aug 14 04:58:40 PM PDT 24
Peak memory 237816 kb
Host smart-e3faffc6-b68a-4a04-8ef4-01c66b6c9b0c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4126008003 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.4126008003
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.212695496
Short name T359
Test name
Test status
Simulation time 8074545 ps
CPU time 1.66 seconds
Started Aug 14 04:58:40 PM PDT 24
Finished Aug 14 04:58:42 PM PDT 24
Peak memory 237796 kb
Host smart-2e1d91d6-e09f-4d1f-8ad4-d6441b788b23
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=212695496 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.212695496
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.3107261423
Short name T759
Test name
Test status
Simulation time 32396146 ps
CPU time 1.38 seconds
Started Aug 14 04:58:45 PM PDT 24
Finished Aug 14 04:58:46 PM PDT 24
Peak memory 235880 kb
Host smart-ff1c401b-b388-471f-9a45-d7930d24920a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3107261423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.3107261423
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.2647327234
Short name T828
Test name
Test status
Simulation time 14170104 ps
CPU time 1.56 seconds
Started Aug 14 04:58:37 PM PDT 24
Finished Aug 14 04:58:39 PM PDT 24
Peak memory 236932 kb
Host smart-e0cb55c3-a7ea-4419-b0a2-7eb31c577908
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2647327234 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.2647327234
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.3783612649
Short name T796
Test name
Test status
Simulation time 14585082 ps
CPU time 1.38 seconds
Started Aug 14 04:58:39 PM PDT 24
Finished Aug 14 04:58:40 PM PDT 24
Peak memory 237796 kb
Host smart-a87d25cf-45c1-4d4d-8c00-60023a7174c5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3783612649 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.3783612649
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.1174003108
Short name T751
Test name
Test status
Simulation time 4391426400 ps
CPU time 146.47 seconds
Started Aug 14 04:58:07 PM PDT 24
Finished Aug 14 05:00:34 PM PDT 24
Peak memory 240728 kb
Host smart-062af30f-1f49-4468-9f3f-d629dbaf7b42
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1174003108 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.1174003108
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.3417522604
Short name T738
Test name
Test status
Simulation time 1640899123 ps
CPU time 195.13 seconds
Started Aug 14 04:58:00 PM PDT 24
Finished Aug 14 05:01:15 PM PDT 24
Peak memory 237784 kb
Host smart-43e627fa-9359-46a7-9258-d74a39914d54
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3417522604 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.3417522604
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.3527725885
Short name T791
Test name
Test status
Simulation time 74916218 ps
CPU time 3.4 seconds
Started Aug 14 04:57:57 PM PDT 24
Finished Aug 14 04:58:01 PM PDT 24
Peak memory 240716 kb
Host smart-dc7b5934-691d-4c49-b63a-27d3fcb1c826
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3527725885 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.3527725885
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.2521377007
Short name T779
Test name
Test status
Simulation time 151393579 ps
CPU time 6.21 seconds
Started Aug 14 04:57:59 PM PDT 24
Finished Aug 14 04:58:06 PM PDT 24
Peak memory 241408 kb
Host smart-672cf345-56ef-4902-b503-45712c5be95b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2521377007 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 4.alert_handler_csr_mem_rw_with_rand_reset.2521377007
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.4072710349
Short name T816
Test name
Test status
Simulation time 53248015 ps
CPU time 4.44 seconds
Started Aug 14 04:57:56 PM PDT 24
Finished Aug 14 04:58:01 PM PDT 24
Peak memory 239484 kb
Host smart-c5472b0e-0c3e-449e-b6f9-3506d3c9fc33
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4072710349 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.4072710349
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.3436961814
Short name T354
Test name
Test status
Simulation time 11545378 ps
CPU time 1.33 seconds
Started Aug 14 04:57:57 PM PDT 24
Finished Aug 14 04:57:59 PM PDT 24
Peak memory 237796 kb
Host smart-5793db04-d0c2-4d81-bf9c-5e6b3d482069
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3436961814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.3436961814
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.413708533
Short name T804
Test name
Test status
Simulation time 2147917426 ps
CPU time 41.74 seconds
Started Aug 14 04:57:59 PM PDT 24
Finished Aug 14 04:58:41 PM PDT 24
Peak memory 246032 kb
Host smart-91f4be3d-145c-4772-a0b3-b2c6b07b83c4
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=413708533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_outs
tanding.413708533
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.3302299570
Short name T778
Test name
Test status
Simulation time 258140935 ps
CPU time 4.94 seconds
Started Aug 14 04:57:49 PM PDT 24
Finished Aug 14 04:57:54 PM PDT 24
Peak memory 248424 kb
Host smart-2feb6547-58e1-4c85-9c86-b70df9414556
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3302299570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.3302299570
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.2288265326
Short name T270
Test name
Test status
Simulation time 60800840 ps
CPU time 2.26 seconds
Started Aug 14 04:57:50 PM PDT 24
Finished Aug 14 04:57:53 PM PDT 24
Peak memory 236884 kb
Host smart-d142956a-9715-4625-88ab-4fc0098399d2
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2288265326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.2288265326
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.3975336624
Short name T358
Test name
Test status
Simulation time 8751023 ps
CPU time 1.53 seconds
Started Aug 14 04:58:45 PM PDT 24
Finished Aug 14 04:58:47 PM PDT 24
Peak memory 236832 kb
Host smart-5db8ced4-af94-4c8a-a29d-7ba5856b1926
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3975336624 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.3975336624
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.1989543757
Short name T815
Test name
Test status
Simulation time 7678710 ps
CPU time 1.34 seconds
Started Aug 14 04:58:37 PM PDT 24
Finished Aug 14 04:58:39 PM PDT 24
Peak memory 237888 kb
Host smart-d51f4a43-d8db-4cf9-b609-553c621b046a
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1989543757 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.1989543757
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.2998202519
Short name T357
Test name
Test status
Simulation time 11111344 ps
CPU time 1.29 seconds
Started Aug 14 04:58:47 PM PDT 24
Finished Aug 14 04:58:48 PM PDT 24
Peak memory 235768 kb
Host smart-1afde121-9c79-4cd1-99f5-71278da43894
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2998202519 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.2998202519
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.1113674433
Short name T351
Test name
Test status
Simulation time 10175354 ps
CPU time 1.71 seconds
Started Aug 14 04:58:49 PM PDT 24
Finished Aug 14 04:58:51 PM PDT 24
Peak memory 237796 kb
Host smart-54902671-92ba-48db-8096-c315de4d870e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1113674433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.1113674433
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.2275547853
Short name T754
Test name
Test status
Simulation time 24046255 ps
CPU time 1.47 seconds
Started Aug 14 04:58:47 PM PDT 24
Finished Aug 14 04:58:49 PM PDT 24
Peak memory 237000 kb
Host smart-4c87d4c3-ece6-48a8-b720-5d4e25738d29
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2275547853 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.2275547853
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.3706012285
Short name T743
Test name
Test status
Simulation time 11112031 ps
CPU time 1.47 seconds
Started Aug 14 04:58:48 PM PDT 24
Finished Aug 14 04:58:50 PM PDT 24
Peak memory 237692 kb
Host smart-9f8eaa51-094a-4324-bd0a-b378272d9e67
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3706012285 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.3706012285
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.350013176
Short name T356
Test name
Test status
Simulation time 14713853 ps
CPU time 1.33 seconds
Started Aug 14 04:58:48 PM PDT 24
Finished Aug 14 04:58:49 PM PDT 24
Peak memory 235780 kb
Host smart-87cdf610-a747-4c09-81af-6cf9538721d9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=350013176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.350013176
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.922178213
Short name T173
Test name
Test status
Simulation time 25677268 ps
CPU time 1.5 seconds
Started Aug 14 04:58:48 PM PDT 24
Finished Aug 14 04:58:49 PM PDT 24
Peak memory 237784 kb
Host smart-38b1ff55-e720-4c42-9f49-7b6075142de2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=922178213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.922178213
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.4190892845
Short name T811
Test name
Test status
Simulation time 7890992 ps
CPU time 1.32 seconds
Started Aug 14 04:58:47 PM PDT 24
Finished Aug 14 04:58:49 PM PDT 24
Peak memory 237804 kb
Host smart-6fe50dd8-e733-4680-ba9a-682d95bf1c0f
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4190892845 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.4190892845
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.3335201517
Short name T777
Test name
Test status
Simulation time 8472887 ps
CPU time 1.52 seconds
Started Aug 14 04:58:46 PM PDT 24
Finished Aug 14 04:58:48 PM PDT 24
Peak memory 237808 kb
Host smart-4493733b-75d3-4ac5-afe6-44e1709194c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3335201517 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.3335201517
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.2563779841
Short name T832
Test name
Test status
Simulation time 149941043 ps
CPU time 11.4 seconds
Started Aug 14 04:57:59 PM PDT 24
Finished Aug 14 04:58:11 PM PDT 24
Peak memory 252012 kb
Host smart-3a034d24-8e5f-4d48-85ba-6734940b4e39
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2563779841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 5.alert_handler_csr_mem_rw_with_rand_reset.2563779841
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.2070957061
Short name T795
Test name
Test status
Simulation time 116601885 ps
CPU time 3.16 seconds
Started Aug 14 04:58:05 PM PDT 24
Finished Aug 14 04:58:08 PM PDT 24
Peak memory 240724 kb
Host smart-2a53df4f-9758-42a6-abd9-fbfcd3be9ae1
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2070957061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.2070957061
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.638204701
Short name T794
Test name
Test status
Simulation time 10906484 ps
CPU time 1.23 seconds
Started Aug 14 04:58:06 PM PDT 24
Finished Aug 14 04:58:08 PM PDT 24
Peak memory 235812 kb
Host smart-feefee49-0389-42f6-9478-8278c8cb8111
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=638204701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.638204701
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.2404032341
Short name T249
Test name
Test status
Simulation time 11386254654 ps
CPU time 41.02 seconds
Started Aug 14 04:57:57 PM PDT 24
Finished Aug 14 04:58:38 PM PDT 24
Peak memory 245012 kb
Host smart-4cd633a3-0cee-44d3-9155-2fd57488cc15
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2404032341 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_out
standing.2404032341
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.2556022680
Short name T748
Test name
Test status
Simulation time 45657928 ps
CPU time 6.66 seconds
Started Aug 14 04:58:05 PM PDT 24
Finished Aug 14 04:58:12 PM PDT 24
Peak memory 248904 kb
Host smart-aaa46607-1be5-4636-baa3-8c4bfab08033
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2556022680 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.2556022680
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.2306652997
Short name T746
Test name
Test status
Simulation time 130883755 ps
CPU time 5.89 seconds
Started Aug 14 04:58:00 PM PDT 24
Finished Aug 14 04:58:06 PM PDT 24
Peak memory 240144 kb
Host smart-1c1d828c-f7de-4c9c-ba1b-bc2b35827adf
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2306652997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.alert_handler_csr_mem_rw_with_rand_reset.2306652997
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.3274776533
Short name T775
Test name
Test status
Simulation time 216325656 ps
CPU time 4.85 seconds
Started Aug 14 04:58:06 PM PDT 24
Finished Aug 14 04:58:11 PM PDT 24
Peak memory 236880 kb
Host smart-0c6fb9e6-921c-4aee-bcdc-7f79d81c6fe5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3274776533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.3274776533
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.1161273225
Short name T741
Test name
Test status
Simulation time 44348704 ps
CPU time 1.47 seconds
Started Aug 14 04:57:58 PM PDT 24
Finished Aug 14 04:58:00 PM PDT 24
Peak memory 235760 kb
Host smart-b1ce652c-6282-47ee-a4f9-8996353e0489
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1161273225 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.1161273225
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.2365873023
Short name T198
Test name
Test status
Simulation time 625130869 ps
CPU time 22.24 seconds
Started Aug 14 04:57:57 PM PDT 24
Finished Aug 14 04:58:19 PM PDT 24
Peak memory 245032 kb
Host smart-b56ab089-5059-40c9-b674-0918d6c76e0b
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2365873023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_out
standing.2365873023
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.3741476174
Short name T163
Test name
Test status
Simulation time 3047541060 ps
CPU time 109.85 seconds
Started Aug 14 04:57:58 PM PDT 24
Finished Aug 14 04:59:47 PM PDT 24
Peak memory 265688 kb
Host smart-75194a90-4c86-45a6-9f3e-05c2b279c3c3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3741476174 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_erro
rs.3741476174
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.3255823895
Short name T149
Test name
Test status
Simulation time 95614628758 ps
CPU time 460.81 seconds
Started Aug 14 04:58:08 PM PDT 24
Finished Aug 14 05:05:49 PM PDT 24
Peak memory 269688 kb
Host smart-188586bc-c365-4d4b-9bd7-87fbe7694550
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3255823895 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.3255823895
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.3942465289
Short name T769
Test name
Test status
Simulation time 327291730 ps
CPU time 15.21 seconds
Started Aug 14 04:57:56 PM PDT 24
Finished Aug 14 04:58:12 PM PDT 24
Peak memory 248888 kb
Host smart-8cf8d74d-3ea9-4417-aa61-07c4187931b7
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3942465289 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.3942465289
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.710022033
Short name T782
Test name
Test status
Simulation time 196700639 ps
CPU time 5.18 seconds
Started Aug 14 04:58:00 PM PDT 24
Finished Aug 14 04:58:05 PM PDT 24
Peak memory 240792 kb
Host smart-b69b6f55-15f1-4312-8444-338a698c1e8b
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=710022033 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 7.alert_handler_csr_mem_rw_with_rand_reset.710022033
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.704524269
Short name T786
Test name
Test status
Simulation time 127583543 ps
CPU time 5.56 seconds
Started Aug 14 04:57:59 PM PDT 24
Finished Aug 14 04:58:05 PM PDT 24
Peak memory 236628 kb
Host smart-68d84fa3-677e-49b5-849d-a12fb549f7da
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=704524269 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.704524269
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.481204189
Short name T787
Test name
Test status
Simulation time 15921907 ps
CPU time 1.35 seconds
Started Aug 14 04:58:07 PM PDT 24
Finished Aug 14 04:58:09 PM PDT 24
Peak memory 235844 kb
Host smart-d46ba867-8fcb-4d0c-9242-d7c10f60e5ce
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=481204189 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.481204189
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.3113109655
Short name T202
Test name
Test status
Simulation time 86222800 ps
CPU time 11.83 seconds
Started Aug 14 04:58:00 PM PDT 24
Finished Aug 14 04:58:12 PM PDT 24
Peak memory 239564 kb
Host smart-8e3a4fd8-1c64-4adf-bbdd-7c3d30b156d3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3113109655 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_out
standing.3113109655
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.873965505
Short name T169
Test name
Test status
Simulation time 18531894161 ps
CPU time 177.17 seconds
Started Aug 14 04:58:05 PM PDT 24
Finished Aug 14 05:01:02 PM PDT 24
Peak memory 268952 kb
Host smart-ef8735a3-23cb-420f-a5aa-a0271c0c7de3
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=873965505 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_error
s.873965505
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.468542954
Short name T143
Test name
Test status
Simulation time 118557021549 ps
CPU time 962.79 seconds
Started Aug 14 04:57:58 PM PDT 24
Finished Aug 14 05:14:01 PM PDT 24
Peak memory 265604 kb
Host smart-21e77885-1447-4695-b1b5-c615d5f7af08
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=468542954 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.468542954
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.2748220124
Short name T764
Test name
Test status
Simulation time 663761512 ps
CPU time 13.95 seconds
Started Aug 14 04:58:05 PM PDT 24
Finished Aug 14 04:58:20 PM PDT 24
Peak memory 248512 kb
Host smart-0b7a5783-b719-4a3f-8f90-188de8f610a3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2748220124 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.2748220124
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.589167406
Short name T799
Test name
Test status
Simulation time 188433808 ps
CPU time 4.51 seconds
Started Aug 14 04:58:06 PM PDT 24
Finished Aug 14 04:58:10 PM PDT 24
Peak memory 237836 kb
Host smart-21c237cc-be18-40f6-8c97-b63549456303
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=589167406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 8.alert_handler_csr_mem_rw_with_rand_reset.589167406
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.2465202309
Short name T825
Test name
Test status
Simulation time 176023123 ps
CPU time 8.41 seconds
Started Aug 14 04:58:07 PM PDT 24
Finished Aug 14 04:58:16 PM PDT 24
Peak memory 236852 kb
Host smart-fcc3f11e-f584-45de-9031-e48d10ea2409
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2465202309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.2465202309
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.4233889640
Short name T809
Test name
Test status
Simulation time 61515083 ps
CPU time 1.46 seconds
Started Aug 14 04:58:07 PM PDT 24
Finished Aug 14 04:58:08 PM PDT 24
Peak memory 237552 kb
Host smart-ac8ac5d9-0a7f-4709-920e-fec59e2cf97c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4233889640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.4233889640
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.814246975
Short name T793
Test name
Test status
Simulation time 1209799847 ps
CPU time 13.07 seconds
Started Aug 14 04:58:06 PM PDT 24
Finished Aug 14 04:58:19 PM PDT 24
Peak memory 240908 kb
Host smart-b8015381-d9cd-48e7-8344-3bd8153479e6
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=814246975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_outs
tanding.814246975
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.3703762824
Short name T135
Test name
Test status
Simulation time 5514609631 ps
CPU time 347.11 seconds
Started Aug 14 04:57:57 PM PDT 24
Finished Aug 14 05:03:44 PM PDT 24
Peak memory 265508 kb
Host smart-2f07b856-04ed-4cad-9925-1295ffaae8f8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3703762824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_erro
rs.3703762824
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.420521646
Short name T166
Test name
Test status
Simulation time 49778236895 ps
CPU time 967.42 seconds
Started Aug 14 04:57:57 PM PDT 24
Finished Aug 14 05:14:05 PM PDT 24
Peak memory 265620 kb
Host smart-5130bdb8-abc9-44fd-a2e0-d0400277674b
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=420521646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.420521646
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.3605378283
Short name T772
Test name
Test status
Simulation time 185237951 ps
CPU time 6.53 seconds
Started Aug 14 04:58:08 PM PDT 24
Finished Aug 14 04:58:14 PM PDT 24
Peak memory 250008 kb
Host smart-b7214989-b2d5-4112-ac16-b4c28e1c3612
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3605378283 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.3605378283
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.3297960897
Short name T205
Test name
Test status
Simulation time 148514146 ps
CPU time 11.84 seconds
Started Aug 14 04:58:08 PM PDT 24
Finished Aug 14 04:58:20 PM PDT 24
Peak memory 255468 kb
Host smart-f26f6321-2e13-4071-8999-3f5744d20b59
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3297960897 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.alert_handler_csr_mem_rw_with_rand_reset.3297960897
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.4287492876
Short name T788
Test name
Test status
Simulation time 129089540 ps
CPU time 5.89 seconds
Started Aug 14 04:58:08 PM PDT 24
Finished Aug 14 04:58:14 PM PDT 24
Peak memory 237780 kb
Host smart-c8d93237-068d-4ff4-8971-ec71094b4ea3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4287492876 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.4287492876
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.2253809447
Short name T736
Test name
Test status
Simulation time 7712033 ps
CPU time 1.52 seconds
Started Aug 14 04:58:08 PM PDT 24
Finished Aug 14 04:58:10 PM PDT 24
Peak memory 236904 kb
Host smart-7d3bbf13-df1a-4cef-91d6-2bf3262a1a0d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2253809447 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.2253809447
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.1177581692
Short name T201
Test name
Test status
Simulation time 317549074 ps
CPU time 26.51 seconds
Started Aug 14 04:58:07 PM PDT 24
Finished Aug 14 04:58:34 PM PDT 24
Peak memory 248796 kb
Host smart-5ab4033e-9287-4749-b6e1-acd79ac85747
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1177581692 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_out
standing.1177581692
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.4135961693
Short name T157
Test name
Test status
Simulation time 50505826008 ps
CPU time 509.92 seconds
Started Aug 14 04:58:07 PM PDT 24
Finished Aug 14 05:06:37 PM PDT 24
Peak memory 265528 kb
Host smart-2ab99ba2-fb94-4462-935a-09d4596968f5
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4135961693 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.4135961693
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.3305163751
Short name T737
Test name
Test status
Simulation time 467212192 ps
CPU time 16.7 seconds
Started Aug 14 04:58:05 PM PDT 24
Finished Aug 14 04:58:22 PM PDT 24
Peak memory 248936 kb
Host smart-1529a899-0274-46fa-8d7c-3b95d7c2f270
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3305163751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.3305163751
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.658145936
Short name T551
Test name
Test status
Simulation time 76193978969 ps
CPU time 1649.9 seconds
Started Aug 14 04:46:48 PM PDT 24
Finished Aug 14 05:14:18 PM PDT 24
Peak memory 273316 kb
Host smart-02783bee-aa0e-4c48-bd05-9305b3c92da3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=658145936 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.658145936
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.2867460599
Short name T392
Test name
Test status
Simulation time 353284339 ps
CPU time 17.7 seconds
Started Aug 14 04:46:59 PM PDT 24
Finished Aug 14 04:47:17 PM PDT 24
Peak memory 248504 kb
Host smart-a95da14e-952c-4c6d-9c8e-9fcc8c6fb7f8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2867460599 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.2867460599
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.771403398
Short name T645
Test name
Test status
Simulation time 4471648542 ps
CPU time 88.48 seconds
Started Aug 14 04:46:47 PM PDT 24
Finished Aug 14 04:48:15 PM PDT 24
Peak memory 250908 kb
Host smart-9792e062-9ce3-49e1-a553-3b22f7236da7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77140
3398 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.771403398
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.924506756
Short name T530
Test name
Test status
Simulation time 208794173 ps
CPU time 19.77 seconds
Started Aug 14 04:46:58 PM PDT 24
Finished Aug 14 04:47:18 PM PDT 24
Peak memory 248264 kb
Host smart-09c40133-f779-48bd-add0-f7f8f280f3de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92450
6756 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.924506756
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.2121841723
Short name T421
Test name
Test status
Simulation time 19010571483 ps
CPU time 1385.3 seconds
Started Aug 14 04:46:58 PM PDT 24
Finished Aug 14 05:10:04 PM PDT 24
Peak memory 273404 kb
Host smart-d41e001b-c96f-4cbb-9ea2-b145be844612
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2121841723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.2121841723
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.96131789
Short name T416
Test name
Test status
Simulation time 230932623 ps
CPU time 19.98 seconds
Started Aug 14 04:46:53 PM PDT 24
Finished Aug 14 04:47:13 PM PDT 24
Peak memory 256248 kb
Host smart-0bd194eb-01ce-4822-90e0-642c4fa8d4b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96131
789 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.96131789
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.4226523422
Short name T622
Test name
Test status
Simulation time 1428529807 ps
CPU time 44.39 seconds
Started Aug 14 04:46:58 PM PDT 24
Finished Aug 14 04:47:42 PM PDT 24
Peak memory 256508 kb
Host smart-53701a90-6f40-4014-9984-e00fdb61265c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42265
23422 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.4226523422
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.4205821100
Short name T39
Test name
Test status
Simulation time 181798497 ps
CPU time 11.64 seconds
Started Aug 14 04:46:58 PM PDT 24
Finished Aug 14 04:47:10 PM PDT 24
Peak memory 274324 kb
Host smart-550d74a1-c668-4b60-bc6a-99847265f0aa
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=4205821100 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.4205821100
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.573569983
Short name T371
Test name
Test status
Simulation time 36639732 ps
CPU time 3.22 seconds
Started Aug 14 04:46:51 PM PDT 24
Finished Aug 14 04:46:54 PM PDT 24
Peak memory 240132 kb
Host smart-91e25171-53b6-4280-b3d0-325ef815298f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57356
9983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.573569983
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.3637612932
Short name T55
Test name
Test status
Simulation time 166429315 ps
CPU time 16.56 seconds
Started Aug 14 04:46:50 PM PDT 24
Finished Aug 14 04:47:06 PM PDT 24
Peak memory 256972 kb
Host smart-46b9d19b-91c6-4466-852f-2090068dd941
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36376
12932 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.3637612932
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.1123810903
Short name T236
Test name
Test status
Simulation time 10204288084 ps
CPU time 1318.59 seconds
Started Aug 14 04:46:57 PM PDT 24
Finished Aug 14 05:08:56 PM PDT 24
Peak memory 289544 kb
Host smart-f3f01e4d-b49d-4037-89e3-6a9ec6212475
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1123810903 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.1123810903
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.1283555823
Short name T47
Test name
Test status
Simulation time 378575187 ps
CPU time 18.74 seconds
Started Aug 14 04:47:01 PM PDT 24
Finished Aug 14 04:47:20 PM PDT 24
Peak memory 248852 kb
Host smart-2b20d8e6-7b64-49a4-aa86-0ed106cef11c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1283555823 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.1283555823
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.3506951856
Short name T520
Test name
Test status
Simulation time 880475535 ps
CPU time 55.51 seconds
Started Aug 14 04:46:58 PM PDT 24
Finished Aug 14 04:47:58 PM PDT 24
Peak memory 256544 kb
Host smart-0b183a2f-45b2-41b7-99f2-54a99b7f7a9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35069
51856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.3506951856
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.416037761
Short name T552
Test name
Test status
Simulation time 3330867773 ps
CPU time 21.39 seconds
Started Aug 14 04:47:08 PM PDT 24
Finished Aug 14 04:47:29 PM PDT 24
Peak memory 257108 kb
Host smart-6284ee27-0b36-43ec-b4c0-c9f5bffbefa6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41603
7761 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.416037761
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.2424916084
Short name T452
Test name
Test status
Simulation time 65748615737 ps
CPU time 1796.77 seconds
Started Aug 14 04:47:09 PM PDT 24
Finished Aug 14 05:17:07 PM PDT 24
Peak memory 273360 kb
Host smart-5f464005-cec8-4fa3-867d-2cb59006d053
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2424916084 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.2424916084
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.979631843
Short name T237
Test name
Test status
Simulation time 1710046200 ps
CPU time 25.7 seconds
Started Aug 14 04:46:58 PM PDT 24
Finished Aug 14 04:47:24 PM PDT 24
Peak memory 248868 kb
Host smart-f2d7200f-cc3b-47fb-86bd-2debdeaa5ad9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97963
1843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.979631843
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.2939372618
Short name T516
Test name
Test status
Simulation time 303195571 ps
CPU time 8.91 seconds
Started Aug 14 04:46:59 PM PDT 24
Finished Aug 14 04:47:08 PM PDT 24
Peak memory 248208 kb
Host smart-1991c57a-4659-40cf-bf00-0162be057f18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29393
72618 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.2939372618
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.1271139027
Short name T524
Test name
Test status
Simulation time 1403371722 ps
CPU time 25.49 seconds
Started Aug 14 04:46:57 PM PDT 24
Finished Aug 14 04:47:23 PM PDT 24
Peak memory 255996 kb
Host smart-9cf7f600-aa60-4646-accb-700702de6c94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12711
39027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.1271139027
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.3634070561
Short name T378
Test name
Test status
Simulation time 1877606581 ps
CPU time 28.13 seconds
Started Aug 14 04:46:49 PM PDT 24
Finished Aug 14 04:47:17 PM PDT 24
Peak memory 248788 kb
Host smart-d40f9b1c-b5a1-45b3-b6b0-00fcc86e5f6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36340
70561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.3634070561
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.1957341297
Short name T210
Test name
Test status
Simulation time 98822302 ps
CPU time 4.18 seconds
Started Aug 14 04:47:04 PM PDT 24
Finished Aug 14 04:47:08 PM PDT 24
Peak memory 249040 kb
Host smart-6b89ba3b-b946-43b7-9cc3-63977e72b4cb
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1957341297 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.1957341297
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.516621
Short name T705
Test name
Test status
Simulation time 48679704413 ps
CPU time 2716.55 seconds
Started Aug 14 04:47:26 PM PDT 24
Finished Aug 14 05:32:43 PM PDT 24
Peak memory 288796 kb
Host smart-845e2c95-daa5-4e68-a044-176f42112f2c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=516621 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.516621
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.3225939712
Short name T532
Test name
Test status
Simulation time 211173878 ps
CPU time 11.58 seconds
Started Aug 14 04:47:17 PM PDT 24
Finished Aug 14 04:47:28 PM PDT 24
Peak memory 248692 kb
Host smart-1636339d-ba85-4418-a550-bbf20755b127
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3225939712 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.3225939712
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.3405833493
Short name T116
Test name
Test status
Simulation time 3169445430 ps
CPU time 90.74 seconds
Started Aug 14 04:47:00 PM PDT 24
Finished Aug 14 04:48:31 PM PDT 24
Peak memory 256572 kb
Host smart-519cb5af-7e1a-4c4a-9415-01524b5bc6c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34058
33493 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.3405833493
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.850250139
Short name T606
Test name
Test status
Simulation time 719535148 ps
CPU time 12.77 seconds
Started Aug 14 04:47:17 PM PDT 24
Finished Aug 14 04:47:30 PM PDT 24
Peak memory 248668 kb
Host smart-6cd3c8aa-ac2f-476a-822c-fe7864b935a1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85025
0139 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.850250139
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.1273579312
Short name T502
Test name
Test status
Simulation time 36957305671 ps
CPU time 803.24 seconds
Started Aug 14 04:47:15 PM PDT 24
Finished Aug 14 05:00:38 PM PDT 24
Peak memory 271832 kb
Host smart-3932aa18-b1e5-420c-bda7-a0d4a1f73030
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273579312 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.1273579312
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.4276788086
Short name T437
Test name
Test status
Simulation time 207532262022 ps
CPU time 2860.45 seconds
Started Aug 14 04:47:14 PM PDT 24
Finished Aug 14 05:34:55 PM PDT 24
Peak memory 281544 kb
Host smart-7c020a32-e89f-4da7-a6ae-b3f62023cf0a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4276788086 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.4276788086
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.3286089465
Short name T708
Test name
Test status
Simulation time 6454849834 ps
CPU time 267.58 seconds
Started Aug 14 04:47:04 PM PDT 24
Finished Aug 14 04:51:32 PM PDT 24
Peak memory 248760 kb
Host smart-89e9ae8a-9710-4ce9-b21b-b13352be0b03
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286089465 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.3286089465
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.1853154815
Short name T563
Test name
Test status
Simulation time 211814875 ps
CPU time 14.27 seconds
Started Aug 14 04:47:04 PM PDT 24
Finished Aug 14 04:47:18 PM PDT 24
Peak memory 248856 kb
Host smart-9cdf927b-858a-41d0-beba-edb8476e655e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18531
54815 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.1853154815
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.4219582751
Short name T471
Test name
Test status
Simulation time 493116013 ps
CPU time 20.95 seconds
Started Aug 14 04:47:20 PM PDT 24
Finished Aug 14 04:47:46 PM PDT 24
Peak memory 248676 kb
Host smart-cef7302f-98af-4dea-90d2-b0c7c080e50e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42195
82751 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.4219582751
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.2794490508
Short name T90
Test name
Test status
Simulation time 125989938 ps
CPU time 14.85 seconds
Started Aug 14 04:47:07 PM PDT 24
Finished Aug 14 04:47:22 PM PDT 24
Peak memory 248840 kb
Host smart-d9ee96f4-ff0b-42c6-a012-4df5bee17761
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27944
90508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.2794490508
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.2141875513
Short name T614
Test name
Test status
Simulation time 1793628193 ps
CPU time 55.86 seconds
Started Aug 14 04:47:01 PM PDT 24
Finished Aug 14 04:47:57 PM PDT 24
Peak memory 256924 kb
Host smart-1204d3e6-2cf1-4095-935a-3b9c2c3b4f27
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21418
75513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.2141875513
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.3124733542
Short name T79
Test name
Test status
Simulation time 100905370135 ps
CPU time 1390.74 seconds
Started Aug 14 04:47:01 PM PDT 24
Finished Aug 14 05:10:12 PM PDT 24
Peak memory 289800 kb
Host smart-c83e590e-5c1c-4b0e-9aa2-094b3ea9b434
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3124733542 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_ha
ndler_stress_all.3124733542
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all_with_rand_reset.2025449668
Short name T63
Test name
Test status
Simulation time 9749487991 ps
CPU time 327.17 seconds
Started Aug 14 04:47:05 PM PDT 24
Finished Aug 14 04:52:32 PM PDT 24
Peak memory 266724 kb
Host smart-b45b7064-8624-458b-9bdb-a6cd780a1af2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2025449668 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 10.alert_handler_stress_all_with_rand_reset.2025449668
Directory /workspace/10.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.3695882360
Short name T216
Test name
Test status
Simulation time 16669171 ps
CPU time 2.61 seconds
Started Aug 14 04:47:48 PM PDT 24
Finished Aug 14 04:47:51 PM PDT 24
Peak memory 248928 kb
Host smart-387e076f-8d2a-4754-b452-d0dd9f274f6f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3695882360 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.3695882360
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.2607018631
Short name T280
Test name
Test status
Simulation time 24315177339 ps
CPU time 1445.03 seconds
Started Aug 14 04:47:29 PM PDT 24
Finished Aug 14 05:11:35 PM PDT 24
Peak memory 265292 kb
Host smart-f1dcd81b-f6cd-43f9-ac4c-d32878f2897e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2607018631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.2607018631
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.3099642422
Short name T232
Test name
Test status
Simulation time 1276223887 ps
CPU time 6.21 seconds
Started Aug 14 04:47:28 PM PDT 24
Finished Aug 14 04:47:34 PM PDT 24
Peak memory 248760 kb
Host smart-a45baf5d-ccfd-48af-9675-ebb10f71f366
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3099642422 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.3099642422
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.364545837
Short name T711
Test name
Test status
Simulation time 3995183798 ps
CPU time 237.53 seconds
Started Aug 14 04:47:18 PM PDT 24
Finished Aug 14 04:51:16 PM PDT 24
Peak memory 256964 kb
Host smart-256512be-58d3-41b6-972d-bee601716aa1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36454
5837 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.364545837
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.2634232898
Short name T394
Test name
Test status
Simulation time 83276594 ps
CPU time 3.74 seconds
Started Aug 14 04:47:30 PM PDT 24
Finished Aug 14 04:47:34 PM PDT 24
Peak memory 240068 kb
Host smart-b59a5c98-3c14-485e-8641-7d1f803141b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26342
32898 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.2634232898
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.356708055
Short name T107
Test name
Test status
Simulation time 92087943128 ps
CPU time 1561.14 seconds
Started Aug 14 04:47:14 PM PDT 24
Finished Aug 14 05:13:20 PM PDT 24
Peak memory 272796 kb
Host smart-7d61387f-76d6-4f42-8d29-79b0c977f620
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=356708055 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.356708055
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.216725199
Short name T368
Test name
Test status
Simulation time 141083874692 ps
CPU time 1938.79 seconds
Started Aug 14 04:47:32 PM PDT 24
Finished Aug 14 05:19:52 PM PDT 24
Peak memory 285308 kb
Host smart-8dda91da-9715-4d71-828b-388693b4a3f3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=216725199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.216725199
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.3449616477
Short name T321
Test name
Test status
Simulation time 10184240348 ps
CPU time 412.08 seconds
Started Aug 14 04:47:24 PM PDT 24
Finished Aug 14 04:54:17 PM PDT 24
Peak memory 248876 kb
Host smart-443a74a1-f70d-41c3-adc8-aa4d19332a90
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3449616477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.3449616477
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.141653956
Short name T454
Test name
Test status
Simulation time 688616201 ps
CPU time 14.1 seconds
Started Aug 14 04:46:59 PM PDT 24
Finished Aug 14 04:47:14 PM PDT 24
Peak memory 256232 kb
Host smart-528a3404-fa44-4e07-9bb8-f0afc7a9e5cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14165
3956 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.141653956
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.3213444286
Short name T587
Test name
Test status
Simulation time 669109608 ps
CPU time 29.59 seconds
Started Aug 14 04:47:13 PM PDT 24
Finished Aug 14 04:47:43 PM PDT 24
Peak memory 248592 kb
Host smart-75896804-9747-465e-a495-6b960ab224fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32134
44286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.3213444286
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.2117241181
Short name T678
Test name
Test status
Simulation time 568971203 ps
CPU time 27.91 seconds
Started Aug 14 04:47:33 PM PDT 24
Finished Aug 14 04:48:01 PM PDT 24
Peak memory 256080 kb
Host smart-7bb431e5-8761-48d9-8309-9e0515adf93a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21172
41181 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.2117241181
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.1817851875
Short name T572
Test name
Test status
Simulation time 271384458 ps
CPU time 18.71 seconds
Started Aug 14 04:47:00 PM PDT 24
Finished Aug 14 04:47:19 PM PDT 24
Peak memory 248852 kb
Host smart-b35dc718-c943-4f04-bc6b-2f1813e9d532
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18178
51875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.1817851875
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.551044012
Short name T561
Test name
Test status
Simulation time 9184035061 ps
CPU time 926.67 seconds
Started Aug 14 04:47:36 PM PDT 24
Finished Aug 14 05:03:03 PM PDT 24
Peak memory 273404 kb
Host smart-85766789-f4c2-4ec8-9da4-417642de8918
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=551044012 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.551044012
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.3374017427
Short name T646
Test name
Test status
Simulation time 729122977 ps
CPU time 11.61 seconds
Started Aug 14 04:47:20 PM PDT 24
Finished Aug 14 04:47:31 PM PDT 24
Peak memory 248824 kb
Host smart-1c7e2e58-20d3-4f76-a2cd-3b52a8ee8776
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3374017427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.3374017427
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.3489307824
Short name T664
Test name
Test status
Simulation time 2266852071 ps
CPU time 40.02 seconds
Started Aug 14 04:47:15 PM PDT 24
Finished Aug 14 04:47:55 PM PDT 24
Peak memory 256556 kb
Host smart-6c1d637e-72d0-4023-996c-430ab31caa61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34893
07824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.3489307824
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.1429023379
Short name T76
Test name
Test status
Simulation time 270536426 ps
CPU time 28.38 seconds
Started Aug 14 04:47:28 PM PDT 24
Finished Aug 14 04:47:57 PM PDT 24
Peak memory 248296 kb
Host smart-bab395fd-04d3-47d5-b2f9-371086ee9a94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14290
23379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.1429023379
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.1727531583
Short name T447
Test name
Test status
Simulation time 84070211734 ps
CPU time 1342.62 seconds
Started Aug 14 04:47:17 PM PDT 24
Finished Aug 14 05:09:40 PM PDT 24
Peak memory 285724 kb
Host smart-fd179f9f-c96c-4287-84db-196a16d8453a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1727531583 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.1727531583
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.522528378
Short name T495
Test name
Test status
Simulation time 84354825638 ps
CPU time 1453.52 seconds
Started Aug 14 04:47:30 PM PDT 24
Finished Aug 14 05:11:44 PM PDT 24
Peak memory 270340 kb
Host smart-11fa6d04-9269-4726-a6b0-5c0c99a61fa7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=522528378 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.522528378
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.2159748866
Short name T294
Test name
Test status
Simulation time 643536167 ps
CPU time 18.14 seconds
Started Aug 14 04:47:33 PM PDT 24
Finished Aug 14 04:47:51 PM PDT 24
Peak memory 248864 kb
Host smart-e3d99a42-e881-4d83-94b2-7591a8b9b7a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21597
48866 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.2159748866
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.1879614833
Short name T616
Test name
Test status
Simulation time 809560464 ps
CPU time 10.47 seconds
Started Aug 14 04:47:24 PM PDT 24
Finished Aug 14 04:47:34 PM PDT 24
Peak memory 248124 kb
Host smart-2a484bbc-80e9-4260-89c9-40ef78c78031
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18796
14833 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.1879614833
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.390387019
Short name T432
Test name
Test status
Simulation time 145143259 ps
CPU time 5.63 seconds
Started Aug 14 04:47:44 PM PDT 24
Finished Aug 14 04:47:50 PM PDT 24
Peak memory 251136 kb
Host smart-9fec020f-d58f-418a-9112-f47a678f9c4b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39038
7019 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.390387019
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.2517694005
Short name T214
Test name
Test status
Simulation time 145361547 ps
CPU time 3.02 seconds
Started Aug 14 04:47:31 PM PDT 24
Finished Aug 14 04:47:34 PM PDT 24
Peak memory 248868 kb
Host smart-6ba14fad-5615-4bd8-9945-47c327345384
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2517694005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.2517694005
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.963757882
Short name T282
Test name
Test status
Simulation time 31642545981 ps
CPU time 1480.96 seconds
Started Aug 14 04:47:13 PM PDT 24
Finished Aug 14 05:11:54 PM PDT 24
Peak memory 287100 kb
Host smart-2bc465cf-cd02-4a3d-9be3-952c5d8c0f0d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=963757882 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.963757882
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.1662730758
Short name T698
Test name
Test status
Simulation time 3634065514 ps
CPU time 71.54 seconds
Started Aug 14 04:47:12 PM PDT 24
Finished Aug 14 04:48:23 PM PDT 24
Peak memory 257108 kb
Host smart-a877e3fe-27dc-4500-8d35-6d6d54a23f15
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16627
30758 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.1662730758
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.652183236
Short name T391
Test name
Test status
Simulation time 3803762010 ps
CPU time 52.64 seconds
Started Aug 14 04:47:32 PM PDT 24
Finished Aug 14 04:48:24 PM PDT 24
Peak memory 248952 kb
Host smart-441d578a-35b6-48f1-a392-f573bb7e21bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65218
3236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.652183236
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.3110147129
Short name T675
Test name
Test status
Simulation time 49704390248 ps
CPU time 1246.52 seconds
Started Aug 14 04:47:28 PM PDT 24
Finished Aug 14 05:08:15 PM PDT 24
Peak memory 288176 kb
Host smart-330516b7-df50-40e3-b07d-d559d3c0fa89
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3110147129 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.3110147129
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.1236831287
Short name T68
Test name
Test status
Simulation time 9392907590 ps
CPU time 973.68 seconds
Started Aug 14 04:47:39 PM PDT 24
Finished Aug 14 05:03:52 PM PDT 24
Peak memory 281576 kb
Host smart-2feb9466-d971-4cc9-bda6-63fdab64d85b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1236831287 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.1236831287
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.2312986461
Short name T311
Test name
Test status
Simulation time 3875417283 ps
CPU time 167.22 seconds
Started Aug 14 04:47:35 PM PDT 24
Finished Aug 14 04:50:22 PM PDT 24
Peak memory 248900 kb
Host smart-ededa0bf-f6aa-4326-a6b9-e9cffab5ecfb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2312986461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.2312986461
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.1206098191
Short name T689
Test name
Test status
Simulation time 1487601548 ps
CPU time 11.22 seconds
Started Aug 14 04:47:11 PM PDT 24
Finished Aug 14 04:47:23 PM PDT 24
Peak memory 248744 kb
Host smart-8aa1cb5b-503a-42c8-9ba5-f6527b222d11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12060
98191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.1206098191
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.1854945231
Short name T562
Test name
Test status
Simulation time 954007537 ps
CPU time 46.74 seconds
Started Aug 14 04:47:13 PM PDT 24
Finished Aug 14 04:47:59 PM PDT 24
Peak memory 256416 kb
Host smart-aafdc615-e4bf-49c7-adae-5d5718897bbf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18549
45231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.1854945231
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.2962816986
Short name T74
Test name
Test status
Simulation time 416950929 ps
CPU time 26.36 seconds
Started Aug 14 04:47:14 PM PDT 24
Finished Aug 14 04:47:41 PM PDT 24
Peak memory 256240 kb
Host smart-af3a62ec-1065-4bff-b62a-361356bc1bf8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29628
16986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.2962816986
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.3385206437
Short name T243
Test name
Test status
Simulation time 350946116 ps
CPU time 28.69 seconds
Started Aug 14 04:47:46 PM PDT 24
Finished Aug 14 04:48:15 PM PDT 24
Peak memory 257044 kb
Host smart-8b476f1d-402e-4b13-a8ea-46e04292e9d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33852
06437 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.3385206437
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.3220860400
Short name T624
Test name
Test status
Simulation time 55970772673 ps
CPU time 1908.59 seconds
Started Aug 14 04:47:35 PM PDT 24
Finished Aug 14 05:19:24 PM PDT 24
Peak memory 285200 kb
Host smart-92a6610f-d4ab-46fb-988d-1dd4166024cf
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3220860400 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_ha
ndler_stress_all.3220860400
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all_with_rand_reset.207187089
Short name T247
Test name
Test status
Simulation time 21124375869 ps
CPU time 294.59 seconds
Started Aug 14 04:47:18 PM PDT 24
Finished Aug 14 04:52:12 PM PDT 24
Peak memory 267472 kb
Host smart-6c73541a-8c4a-456f-9a1f-7efb0632d5b8
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207187089 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 13.alert_handler_stress_all_with_rand_reset.207187089
Directory /workspace/13.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.2231676036
Short name T224
Test name
Test status
Simulation time 34137446 ps
CPU time 3.41 seconds
Started Aug 14 04:47:11 PM PDT 24
Finished Aug 14 04:47:15 PM PDT 24
Peak memory 249020 kb
Host smart-45952b49-9d6a-416a-8eb5-2453081c32ea
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2231676036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.2231676036
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.1075303562
Short name T560
Test name
Test status
Simulation time 26681972093 ps
CPU time 1484.89 seconds
Started Aug 14 04:47:27 PM PDT 24
Finished Aug 14 05:12:12 PM PDT 24
Peak memory 273400 kb
Host smart-13cc6d30-315b-4dd2-9b89-c9bfcaba8e17
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1075303562 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.1075303562
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.2431552647
Short name T714
Test name
Test status
Simulation time 9218696923 ps
CPU time 30.55 seconds
Started Aug 14 04:47:33 PM PDT 24
Finished Aug 14 04:48:04 PM PDT 24
Peak memory 248804 kb
Host smart-5ec2cbd2-14f4-440d-8818-bc823a4ed022
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2431552647 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.2431552647
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.1721707681
Short name T253
Test name
Test status
Simulation time 2314276150 ps
CPU time 132.15 seconds
Started Aug 14 04:47:31 PM PDT 24
Finished Aug 14 04:49:43 PM PDT 24
Peak memory 256608 kb
Host smart-b6dd3d28-7268-44fd-af0d-64f96f253490
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17217
07681 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.1721707681
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.3559158453
Short name T463
Test name
Test status
Simulation time 1992292048 ps
CPU time 29.33 seconds
Started Aug 14 04:47:28 PM PDT 24
Finished Aug 14 04:47:58 PM PDT 24
Peak memory 248184 kb
Host smart-49a4e81c-5107-4292-ab5d-e144e3172716
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35591
58453 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.3559158453
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.2715390817
Short name T503
Test name
Test status
Simulation time 25398662642 ps
CPU time 1520.84 seconds
Started Aug 14 04:47:24 PM PDT 24
Finished Aug 14 05:12:45 PM PDT 24
Peak memory 273404 kb
Host smart-1649eb60-7f08-4fdc-918b-fe7edf01c546
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2715390817 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.2715390817
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.3843879625
Short name T281
Test name
Test status
Simulation time 21057378970 ps
CPU time 916.24 seconds
Started Aug 14 04:47:30 PM PDT 24
Finished Aug 14 05:02:47 PM PDT 24
Peak memory 270416 kb
Host smart-9fc2020a-b48f-46d3-8e6c-ec6127dbe7a6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3843879625 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.3843879625
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.127523292
Short name T14
Test name
Test status
Simulation time 17981461191 ps
CPU time 163.66 seconds
Started Aug 14 04:47:29 PM PDT 24
Finished Aug 14 04:50:13 PM PDT 24
Peak memory 248752 kb
Host smart-c5f6736e-de63-40fa-838c-e5465284272d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127523292 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.127523292
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.1358751627
Short name T487
Test name
Test status
Simulation time 236930388 ps
CPU time 20.83 seconds
Started Aug 14 04:47:27 PM PDT 24
Finished Aug 14 04:47:48 PM PDT 24
Peak memory 256224 kb
Host smart-dcd7a58a-a92c-4e6e-aa0a-1459339bebe5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13587
51627 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.1358751627
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.753284042
Short name T518
Test name
Test status
Simulation time 9318670851 ps
CPU time 35.45 seconds
Started Aug 14 04:47:25 PM PDT 24
Finished Aug 14 04:48:01 PM PDT 24
Peak memory 257064 kb
Host smart-0a408839-2733-4f90-85b9-e201bf2f8476
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75328
4042 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.753284042
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.364167391
Short name T23
Test name
Test status
Simulation time 903177140 ps
CPU time 30.92 seconds
Started Aug 14 04:47:23 PM PDT 24
Finished Aug 14 04:47:54 PM PDT 24
Peak memory 249168 kb
Host smart-7b1a671e-0488-4b6b-b5ee-8668429372ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36416
7391 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.364167391
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.3930242580
Short name T387
Test name
Test status
Simulation time 4433973476 ps
CPU time 33.08 seconds
Started Aug 14 04:47:23 PM PDT 24
Finished Aug 14 04:47:56 PM PDT 24
Peak memory 256756 kb
Host smart-afc1f69d-8318-46c1-9e52-5cea09593573
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39302
42580 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.3930242580
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all_with_rand_reset.4008916767
Short name T543
Test name
Test status
Simulation time 771593968 ps
CPU time 63.04 seconds
Started Aug 14 04:47:35 PM PDT 24
Finished Aug 14 04:48:38 PM PDT 24
Peak memory 265360 kb
Host smart-7f1830b8-46c7-4e47-adfa-6fa7997e0d75
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4008916767 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.alert_handler_stress_all_with_rand_reset.4008916767
Directory /workspace/14.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.2630093271
Short name T69
Test name
Test status
Simulation time 136822242896 ps
CPU time 1910.95 seconds
Started Aug 14 04:47:36 PM PDT 24
Finished Aug 14 05:19:27 PM PDT 24
Peak memory 273252 kb
Host smart-3ddfaff2-7d76-428f-9f65-eca745ff5e9f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2630093271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.2630093271
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.1306479128
Short name T521
Test name
Test status
Simulation time 600593236 ps
CPU time 9.54 seconds
Started Aug 14 04:47:31 PM PDT 24
Finished Aug 14 04:47:40 PM PDT 24
Peak memory 248752 kb
Host smart-3767a22e-27c6-4862-9175-eaf8d07d54ff
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1306479128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.1306479128
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.3787924617
Short name T478
Test name
Test status
Simulation time 3024613779 ps
CPU time 50.23 seconds
Started Aug 14 04:47:32 PM PDT 24
Finished Aug 14 04:48:23 PM PDT 24
Peak memory 256068 kb
Host smart-58fd1719-01a7-4ce2-9772-d54c2aba52c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37879
24617 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.3787924617
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.2973474163
Short name T710
Test name
Test status
Simulation time 942096499 ps
CPU time 9.56 seconds
Started Aug 14 04:47:29 PM PDT 24
Finished Aug 14 04:47:39 PM PDT 24
Peak memory 248444 kb
Host smart-b151fc30-f7a7-4adb-b1ae-87329262cd67
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29734
74163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.2973474163
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.3820681787
Short name T342
Test name
Test status
Simulation time 46220463789 ps
CPU time 1031.36 seconds
Started Aug 14 04:47:20 PM PDT 24
Finished Aug 14 05:04:31 PM PDT 24
Peak memory 273300 kb
Host smart-2b47b131-de12-4911-b8c5-ed61d2996b4f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3820681787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.3820681787
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.2020970736
Short name T469
Test name
Test status
Simulation time 29063631125 ps
CPU time 1665.61 seconds
Started Aug 14 04:47:34 PM PDT 24
Finished Aug 14 05:15:20 PM PDT 24
Peak memory 284344 kb
Host smart-430fac45-ee69-4181-b053-a3e5a18eb61e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020970736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.2020970736
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.3423884402
Short name T302
Test name
Test status
Simulation time 17198095486 ps
CPU time 334.88 seconds
Started Aug 14 04:47:34 PM PDT 24
Finished Aug 14 04:53:09 PM PDT 24
Peak memory 248880 kb
Host smart-808ba34e-45f4-4c61-91ee-a821f5b87cec
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3423884402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.3423884402
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.3803903244
Short name T627
Test name
Test status
Simulation time 831316929 ps
CPU time 57.16 seconds
Started Aug 14 04:47:32 PM PDT 24
Finished Aug 14 04:48:30 PM PDT 24
Peak memory 248436 kb
Host smart-21e198b7-1af5-4ec2-9ccb-b3bf0a545e81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38039
03244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.3803903244
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.1244942026
Short name T106
Test name
Test status
Simulation time 2034635513 ps
CPU time 26.09 seconds
Started Aug 14 04:47:35 PM PDT 24
Finished Aug 14 04:48:01 PM PDT 24
Peak memory 248348 kb
Host smart-02bc5430-f0e9-4dd2-a55f-c4cacc0a98c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12449
42026 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.1244942026
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.2040478926
Short name T118
Test name
Test status
Simulation time 1450136220 ps
CPU time 28.98 seconds
Started Aug 14 04:47:39 PM PDT 24
Finished Aug 14 04:48:08 PM PDT 24
Peak memory 247840 kb
Host smart-e63dcd6f-a705-498b-9aa1-3fe3ec532114
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20404
78926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.2040478926
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.3813703896
Short name T592
Test name
Test status
Simulation time 1963301499 ps
CPU time 56.65 seconds
Started Aug 14 04:47:31 PM PDT 24
Finished Aug 14 04:48:28 PM PDT 24
Peak memory 257012 kb
Host smart-093fd092-c845-4167-a996-5fd23a4694c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38137
03896 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.3813703896
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.729135829
Short name T460
Test name
Test status
Simulation time 199640940 ps
CPU time 4.78 seconds
Started Aug 14 04:47:26 PM PDT 24
Finished Aug 14 04:47:31 PM PDT 24
Peak memory 240520 kb
Host smart-96c61dd2-bded-4aa7-a445-330230f44ffb
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=729135829 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_han
dler_stress_all.729135829
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all_with_rand_reset.3843210886
Short name T648
Test name
Test status
Simulation time 2897392898 ps
CPU time 319.03 seconds
Started Aug 14 04:47:38 PM PDT 24
Finished Aug 14 04:52:58 PM PDT 24
Peak memory 272920 kb
Host smart-f7e20b36-2908-4794-95fa-f46b0968c945
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3843210886 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.alert_handler_stress_all_with_rand_reset.3843210886
Directory /workspace/15.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.4170807292
Short name T209
Test name
Test status
Simulation time 106727372 ps
CPU time 3.13 seconds
Started Aug 14 04:47:29 PM PDT 24
Finished Aug 14 04:47:32 PM PDT 24
Peak memory 249024 kb
Host smart-56ad5974-9d22-4f2b-a038-36a907b23115
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4170807292 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.4170807292
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.4160214321
Short name T423
Test name
Test status
Simulation time 30057633437 ps
CPU time 1471.37 seconds
Started Aug 14 04:47:44 PM PDT 24
Finished Aug 14 05:12:15 PM PDT 24
Peak memory 289232 kb
Host smart-dba6144a-9fb4-47fe-92d8-2d688efa740a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4160214321 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.4160214321
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.857904018
Short name T375
Test name
Test status
Simulation time 864306729 ps
CPU time 11.21 seconds
Started Aug 14 04:47:29 PM PDT 24
Finished Aug 14 04:47:40 PM PDT 24
Peak memory 248832 kb
Host smart-eed3189b-8dc2-42d4-a173-167e1c7342f8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=857904018 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.857904018
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.1932302335
Short name T602
Test name
Test status
Simulation time 8475458900 ps
CPU time 125.12 seconds
Started Aug 14 04:47:32 PM PDT 24
Finished Aug 14 04:49:38 PM PDT 24
Peak memory 256536 kb
Host smart-5de374c2-5410-48ce-99d0-f0388f31c27f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19323
02335 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.1932302335
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.4185798696
Short name T604
Test name
Test status
Simulation time 933561733 ps
CPU time 16.48 seconds
Started Aug 14 04:47:47 PM PDT 24
Finished Aug 14 04:48:03 PM PDT 24
Peak memory 256448 kb
Host smart-fec3c483-961e-46ac-b150-18b220ea2776
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41857
98696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.4185798696
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.3698984393
Short name T333
Test name
Test status
Simulation time 202087538505 ps
CPU time 1410.49 seconds
Started Aug 14 04:47:28 PM PDT 24
Finished Aug 14 05:10:59 PM PDT 24
Peak memory 272656 kb
Host smart-b1601be5-dd60-4ae1-ab17-3c1108dd03f1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3698984393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.3698984393
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.3252030415
Short name T546
Test name
Test status
Simulation time 35262370925 ps
CPU time 1058.56 seconds
Started Aug 14 04:47:39 PM PDT 24
Finished Aug 14 05:05:18 PM PDT 24
Peak memory 285752 kb
Host smart-af63b4d1-4b3d-44e0-894a-6520483dc820
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3252030415 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.3252030415
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.2983527583
Short name T15
Test name
Test status
Simulation time 10105135058 ps
CPU time 191.23 seconds
Started Aug 14 04:47:44 PM PDT 24
Finished Aug 14 04:50:55 PM PDT 24
Peak memory 248760 kb
Host smart-8ffde825-6e83-4630-a9b6-c2b3670eb047
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2983527583 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.2983527583
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.2012499515
Short name T244
Test name
Test status
Simulation time 4319878142 ps
CPU time 30.41 seconds
Started Aug 14 04:47:40 PM PDT 24
Finished Aug 14 04:48:10 PM PDT 24
Peak memory 256312 kb
Host smart-59b65028-8035-48e7-aaba-1a7a0076574b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20124
99515 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.2012499515
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.536150592
Short name T1
Test name
Test status
Simulation time 3205476813 ps
CPU time 17.15 seconds
Started Aug 14 04:47:36 PM PDT 24
Finished Aug 14 04:47:53 PM PDT 24
Peak memory 248660 kb
Host smart-6fea1969-b897-4a40-bf51-da6f8a5c1ddd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53615
0592 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.536150592
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.919300573
Short name T540
Test name
Test status
Simulation time 1145461011 ps
CPU time 71.22 seconds
Started Aug 14 04:47:23 PM PDT 24
Finished Aug 14 04:48:35 PM PDT 24
Peak memory 256400 kb
Host smart-c03cd178-9bd0-49ef-b8a0-445d991f0a24
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91930
0573 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.919300573
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.1002535307
Short name T411
Test name
Test status
Simulation time 435315116 ps
CPU time 28.64 seconds
Started Aug 14 04:47:38 PM PDT 24
Finished Aug 14 04:48:07 PM PDT 24
Peak memory 257060 kb
Host smart-492254de-45e2-4ece-aad6-0267d4352038
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10025
35307 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.1002535307
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.2813403942
Short name T634
Test name
Test status
Simulation time 52564883309 ps
CPU time 1444.73 seconds
Started Aug 14 04:47:42 PM PDT 24
Finished Aug 14 05:11:47 PM PDT 24
Peak memory 289876 kb
Host smart-c3450cd5-5162-42e5-a6e2-75ee9fd1c440
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2813403942 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_ha
ndler_stress_all.2813403942
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.3477761891
Short name T212
Test name
Test status
Simulation time 50080511 ps
CPU time 4.31 seconds
Started Aug 14 04:47:32 PM PDT 24
Finished Aug 14 04:47:37 PM PDT 24
Peak memory 249000 kb
Host smart-d8812ebe-9dd5-4eee-81d5-4769c8076c5b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3477761891 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.3477761891
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.2479503838
Short name T98
Test name
Test status
Simulation time 21429268816 ps
CPU time 637.86 seconds
Started Aug 14 04:47:33 PM PDT 24
Finished Aug 14 04:58:11 PM PDT 24
Peak memory 272932 kb
Host smart-fd63026f-3c33-4ed4-876f-f6ed7d91e496
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2479503838 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.2479503838
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.4585439
Short name T393
Test name
Test status
Simulation time 13155344025 ps
CPU time 53.45 seconds
Started Aug 14 04:47:34 PM PDT 24
Finished Aug 14 04:48:28 PM PDT 24
Peak memory 248888 kb
Host smart-d2ec4b88-c408-4dba-a00e-a9a1e23005b7
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4585439 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fsm+
tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.4585439
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.475936212
Short name T662
Test name
Test status
Simulation time 254512787 ps
CPU time 15.81 seconds
Started Aug 14 04:47:34 PM PDT 24
Finished Aug 14 04:47:50 PM PDT 24
Peak memory 255020 kb
Host smart-0e137cdd-d251-4634-9f49-41e5706e2077
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47593
6212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.475936212
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.2937327986
Short name T593
Test name
Test status
Simulation time 1998756522 ps
CPU time 35.37 seconds
Started Aug 14 04:47:35 PM PDT 24
Finished Aug 14 04:48:10 PM PDT 24
Peak memory 248848 kb
Host smart-fafb77b0-ac69-4c7d-a043-c8bb0d8c7bce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29373
27986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.2937327986
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.741117303
Short name T332
Test name
Test status
Simulation time 27158154022 ps
CPU time 1687 seconds
Started Aug 14 04:47:30 PM PDT 24
Finished Aug 14 05:15:37 PM PDT 24
Peak memory 273304 kb
Host smart-cd62f8cd-da26-4917-80dd-2f158a2b060c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741117303 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.741117303
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.1948726837
Short name T405
Test name
Test status
Simulation time 96110142351 ps
CPU time 1503.75 seconds
Started Aug 14 04:47:36 PM PDT 24
Finished Aug 14 05:12:40 PM PDT 24
Peak memory 273200 kb
Host smart-c2a4792a-6299-428f-923a-ccf0152bc7bd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1948726837 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.1948726837
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.390520790
Short name T633
Test name
Test status
Simulation time 29862065068 ps
CPU time 324.38 seconds
Started Aug 14 04:47:39 PM PDT 24
Finished Aug 14 04:53:04 PM PDT 24
Peak memory 248800 kb
Host smart-1621eb59-1d6a-464e-b0f5-0450aea39c19
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=390520790 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.390520790
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.824732291
Short name T513
Test name
Test status
Simulation time 4358898788 ps
CPU time 59.72 seconds
Started Aug 14 04:47:50 PM PDT 24
Finished Aug 14 04:48:50 PM PDT 24
Peak memory 256452 kb
Host smart-54d5306f-64f7-4d29-958f-5c170219edd9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82473
2291 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.824732291
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.4021807210
Short name T684
Test name
Test status
Simulation time 139365795 ps
CPU time 13.14 seconds
Started Aug 14 04:47:30 PM PDT 24
Finished Aug 14 04:47:43 PM PDT 24
Peak memory 248080 kb
Host smart-fe7be289-22ae-4cd9-b926-b8238100a60f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40218
07210 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.4021807210
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.1750439492
Short name T507
Test name
Test status
Simulation time 454772853 ps
CPU time 27.25 seconds
Started Aug 14 04:47:34 PM PDT 24
Finished Aug 14 04:48:02 PM PDT 24
Peak memory 248380 kb
Host smart-55f6c37e-7495-4954-979c-d204d1259371
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17504
39492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.1750439492
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.656120213
Short name T430
Test name
Test status
Simulation time 974111345 ps
CPU time 17.27 seconds
Started Aug 14 04:47:31 PM PDT 24
Finished Aug 14 04:47:48 PM PDT 24
Peak memory 255448 kb
Host smart-77f5ca2c-e252-4d71-8fdf-8c62ed719e78
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65612
0213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.656120213
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all_with_rand_reset.1605999462
Short name T443
Test name
Test status
Simulation time 19373917021 ps
CPU time 677.45 seconds
Started Aug 14 04:47:45 PM PDT 24
Finished Aug 14 04:59:03 PM PDT 24
Peak memory 281620 kb
Host smart-c4c93813-482c-469c-82c4-a6fd55959f2f
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1605999462 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.alert_handler_stress_all_with_rand_reset.1605999462
Directory /workspace/17.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.4270256664
Short name T206
Test name
Test status
Simulation time 37223682 ps
CPU time 2.26 seconds
Started Aug 14 04:47:37 PM PDT 24
Finished Aug 14 04:47:40 PM PDT 24
Peak memory 249048 kb
Host smart-6c4dac69-3411-48fe-932f-157c620d55b9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4270256664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.4270256664
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.3932915170
Short name T557
Test name
Test status
Simulation time 29610543083 ps
CPU time 1956.57 seconds
Started Aug 14 04:47:31 PM PDT 24
Finished Aug 14 05:20:08 PM PDT 24
Peak memory 283528 kb
Host smart-f9574f43-8fc4-4ee4-a7bc-fb49bda35f23
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932915170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.3932915170
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.1683377118
Short name T19
Test name
Test status
Simulation time 844369000 ps
CPU time 12.84 seconds
Started Aug 14 04:47:36 PM PDT 24
Finished Aug 14 04:47:49 PM PDT 24
Peak memory 248820 kb
Host smart-b144a9e1-f661-4da6-b4e1-faa38e694877
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1683377118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.1683377118
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.3848313853
Short name T48
Test name
Test status
Simulation time 5756428580 ps
CPU time 158.6 seconds
Started Aug 14 04:47:42 PM PDT 24
Finished Aug 14 04:50:20 PM PDT 24
Peak memory 257056 kb
Host smart-5121d807-5d87-450a-8614-dce7216afb63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38483
13853 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.3848313853
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.4165078737
Short name T591
Test name
Test status
Simulation time 873527407 ps
CPU time 54.49 seconds
Started Aug 14 04:47:31 PM PDT 24
Finished Aug 14 04:48:26 PM PDT 24
Peak memory 248876 kb
Host smart-e7773006-081c-4de2-9b6e-0026ba318724
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41650
78737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.4165078737
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.276183836
Short name T315
Test name
Test status
Simulation time 41989345513 ps
CPU time 2328.86 seconds
Started Aug 14 04:47:24 PM PDT 24
Finished Aug 14 05:26:13 PM PDT 24
Peak memory 289720 kb
Host smart-29e0c44c-1ad7-4933-8bc2-fe8cccde40f1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=276183836 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.276183836
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.3787929958
Short name T100
Test name
Test status
Simulation time 22430937056 ps
CPU time 1300.45 seconds
Started Aug 14 04:47:39 PM PDT 24
Finished Aug 14 05:09:20 PM PDT 24
Peak memory 289676 kb
Host smart-51b6a22b-d4e8-4a8c-824c-c05c6f834acf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3787929958 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.3787929958
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.13814390
Short name T461
Test name
Test status
Simulation time 3277331662 ps
CPU time 147.29 seconds
Started Aug 14 04:47:43 PM PDT 24
Finished Aug 14 04:50:10 PM PDT 24
Peak memory 248688 kb
Host smart-8ee882dd-37c6-46d8-ae88-f226e3ca98bd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=13814390 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.13814390
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.626069996
Short name T589
Test name
Test status
Simulation time 2637240828 ps
CPU time 27.22 seconds
Started Aug 14 04:47:31 PM PDT 24
Finished Aug 14 04:47:59 PM PDT 24
Peak memory 248892 kb
Host smart-afddb6c5-1818-4a98-b3dd-427fc91561ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62606
9996 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.626069996
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.12749395
Short name T519
Test name
Test status
Simulation time 237645023 ps
CPU time 8.61 seconds
Started Aug 14 04:47:38 PM PDT 24
Finished Aug 14 04:47:47 PM PDT 24
Peak memory 251180 kb
Host smart-4c3274b0-51a2-441f-9315-8ee61aedab3f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12749
395 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.12749395
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.4030276282
Short name T492
Test name
Test status
Simulation time 2013603397 ps
CPU time 35.19 seconds
Started Aug 14 04:47:32 PM PDT 24
Finished Aug 14 04:48:07 PM PDT 24
Peak memory 248772 kb
Host smart-29554b7a-5e18-4c17-a9d1-083fb17da295
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40302
76282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.4030276282
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.2953218120
Short name T482
Test name
Test status
Simulation time 2418238618 ps
CPU time 63.83 seconds
Started Aug 14 04:47:40 PM PDT 24
Finished Aug 14 04:48:44 PM PDT 24
Peak memory 257104 kb
Host smart-2c3584a0-55a9-45eb-b09a-813ac7f8c67a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29532
18120 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.2953218120
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.1499822922
Short name T293
Test name
Test status
Simulation time 115780312988 ps
CPU time 3149.42 seconds
Started Aug 14 04:47:34 PM PDT 24
Finished Aug 14 05:40:04 PM PDT 24
Peak memory 305144 kb
Host smart-01c906bf-24d2-48d6-80b0-73860e1e84b1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1499822922 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_ha
ndler_stress_all.1499822922
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.1170774040
Short name T223
Test name
Test status
Simulation time 31458325 ps
CPU time 3.13 seconds
Started Aug 14 04:47:31 PM PDT 24
Finished Aug 14 04:47:34 PM PDT 24
Peak memory 249044 kb
Host smart-d68b975c-2a72-4dd4-8a57-6ffb25ed0bb8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1170774040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.1170774040
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.3266455306
Short name T635
Test name
Test status
Simulation time 89827199874 ps
CPU time 2649.76 seconds
Started Aug 14 04:47:38 PM PDT 24
Finished Aug 14 05:31:48 PM PDT 24
Peak memory 286224 kb
Host smart-2c439d39-2974-4eb0-a69e-3376e9df9f8e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3266455306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.3266455306
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.3330981366
Short name T638
Test name
Test status
Simulation time 149208004 ps
CPU time 5.4 seconds
Started Aug 14 04:47:36 PM PDT 24
Finished Aug 14 04:47:42 PM PDT 24
Peak memory 248700 kb
Host smart-ac76ce46-f2b8-4974-82f6-56e6e065ab20
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3330981366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.3330981366
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.3214733864
Short name T680
Test name
Test status
Simulation time 2128705687 ps
CPU time 44.79 seconds
Started Aug 14 04:47:32 PM PDT 24
Finished Aug 14 04:48:17 PM PDT 24
Peak memory 248428 kb
Host smart-45b7c358-df66-4cfc-9ebc-ce153d61b76c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32147
33864 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.3214733864
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.3518621916
Short name T652
Test name
Test status
Simulation time 155262132810 ps
CPU time 1896.73 seconds
Started Aug 14 04:47:42 PM PDT 24
Finished Aug 14 05:19:19 PM PDT 24
Peak memory 273288 kb
Host smart-6280d6e3-e58f-4411-bcc3-38bcc84ba134
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3518621916 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.3518621916
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.3853258772
Short name T485
Test name
Test status
Simulation time 194366465910 ps
CPU time 2629.49 seconds
Started Aug 14 04:47:34 PM PDT 24
Finished Aug 14 05:31:24 PM PDT 24
Peak memory 287708 kb
Host smart-9ce40361-b6a8-44c8-9052-318c541d7844
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3853258772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.3853258772
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.4103128558
Short name T605
Test name
Test status
Simulation time 3196927372 ps
CPU time 48.96 seconds
Started Aug 14 04:47:33 PM PDT 24
Finished Aug 14 04:48:22 PM PDT 24
Peak memory 257084 kb
Host smart-b5ca8621-785e-4c99-81e8-93c83aa18d06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41031
28558 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.4103128558
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.3237518088
Short name T672
Test name
Test status
Simulation time 293426103 ps
CPU time 26.53 seconds
Started Aug 14 04:47:22 PM PDT 24
Finished Aug 14 04:47:49 PM PDT 24
Peak memory 256188 kb
Host smart-e9e26bab-9dcb-41d9-bf15-03f888247b41
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32375
18088 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.3237518088
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.1785931393
Short name T82
Test name
Test status
Simulation time 973024824 ps
CPU time 16.56 seconds
Started Aug 14 04:47:35 PM PDT 24
Finished Aug 14 04:47:51 PM PDT 24
Peak memory 248368 kb
Host smart-735e585b-7f09-4935-8c42-955616d6b431
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17859
31393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.1785931393
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.3372173341
Short name T395
Test name
Test status
Simulation time 932881821 ps
CPU time 60.96 seconds
Started Aug 14 04:47:53 PM PDT 24
Finished Aug 14 04:48:54 PM PDT 24
Peak memory 256508 kb
Host smart-ae6c620a-c2dc-4611-848f-fe3f0e4b8aaf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33721
73341 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.3372173341
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.2940506292
Short name T287
Test name
Test status
Simulation time 134136763612 ps
CPU time 2148.05 seconds
Started Aug 14 04:47:32 PM PDT 24
Finished Aug 14 05:23:21 PM PDT 24
Peak memory 305660 kb
Host smart-f220129b-d59f-4b2d-8a9c-74e08717d86f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2940506292 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_ha
ndler_stress_all.2940506292
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.3334670971
Short name T220
Test name
Test status
Simulation time 46916776 ps
CPU time 2.43 seconds
Started Aug 14 04:46:58 PM PDT 24
Finished Aug 14 04:47:00 PM PDT 24
Peak memory 248956 kb
Host smart-6e87a779-58e9-43df-a1aa-0f48714f5ebb
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3334670971 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.3334670971
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.2680630514
Short name T486
Test name
Test status
Simulation time 28167237615 ps
CPU time 1564.93 seconds
Started Aug 14 04:46:47 PM PDT 24
Finished Aug 14 05:12:53 PM PDT 24
Peak memory 273356 kb
Host smart-84f5aae7-5b15-469f-b712-ca452c169b93
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680630514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.2680630514
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.2092371298
Short name T380
Test name
Test status
Simulation time 524860212 ps
CPU time 9.41 seconds
Started Aug 14 04:47:01 PM PDT 24
Finished Aug 14 04:47:10 PM PDT 24
Peak memory 248668 kb
Host smart-e39509a1-e7c3-4327-9566-9fcd428fd5e2
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2092371298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.2092371298
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.1859272330
Short name T481
Test name
Test status
Simulation time 4006306118 ps
CPU time 97.97 seconds
Started Aug 14 04:47:01 PM PDT 24
Finished Aug 14 04:48:39 PM PDT 24
Peak memory 256212 kb
Host smart-f71380e5-5d1b-4d89-a18a-24ec506caeeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18592
72330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.1859272330
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.1644630170
Short name T239
Test name
Test status
Simulation time 194256175 ps
CPU time 17.17 seconds
Started Aug 14 04:46:54 PM PDT 24
Finished Aug 14 04:47:11 PM PDT 24
Peak memory 248584 kb
Host smart-03d512af-4916-4493-883c-d599ab9c7af3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16446
30170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.1644630170
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.1617893699
Short name T347
Test name
Test status
Simulation time 27478407750 ps
CPU time 1527.04 seconds
Started Aug 14 04:46:55 PM PDT 24
Finished Aug 14 05:12:22 PM PDT 24
Peak memory 272600 kb
Host smart-9938407a-d6fb-4ca5-97b6-8a6f19fecd99
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1617893699 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.1617893699
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.509244221
Short name T577
Test name
Test status
Simulation time 47327736373 ps
CPU time 1218.81 seconds
Started Aug 14 04:47:01 PM PDT 24
Finished Aug 14 05:07:20 PM PDT 24
Peak memory 289220 kb
Host smart-d8de928f-8a02-48af-929a-dee0ab07afd8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=509244221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.509244221
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.844125329
Short name T677
Test name
Test status
Simulation time 495723990 ps
CPU time 8.75 seconds
Started Aug 14 04:46:55 PM PDT 24
Finished Aug 14 04:47:04 PM PDT 24
Peak memory 248760 kb
Host smart-5132d2c2-b12b-4632-835a-89039d58ce75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=84412
5329 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.844125329
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.2968027134
Short name T268
Test name
Test status
Simulation time 2679788129 ps
CPU time 55.34 seconds
Started Aug 14 04:47:05 PM PDT 24
Finished Aug 14 04:48:00 PM PDT 24
Peak memory 248892 kb
Host smart-a68368cb-6b3b-4462-be53-619f303f782c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29680
27134 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.2968027134
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.150676536
Short name T8
Test name
Test status
Simulation time 1867453165 ps
CPU time 66.34 seconds
Started Aug 14 04:46:58 PM PDT 24
Finished Aug 14 04:48:04 PM PDT 24
Peak memory 271588 kb
Host smart-0394c99e-9e7e-445b-9361-cbdd2d7299dd
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=150676536 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.150676536
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.385855432
Short name T258
Test name
Test status
Simulation time 654105720 ps
CPU time 29.46 seconds
Started Aug 14 04:46:58 PM PDT 24
Finished Aug 14 04:47:28 PM PDT 24
Peak memory 257016 kb
Host smart-40f1cfbd-05c7-4ea6-a0e4-c04f758108b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38585
5432 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.385855432
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.3694891142
Short name T473
Test name
Test status
Simulation time 1080230081 ps
CPU time 50.91 seconds
Started Aug 14 04:47:07 PM PDT 24
Finished Aug 14 04:47:58 PM PDT 24
Peak memory 256952 kb
Host smart-0c91ead5-76d7-4afc-8b4b-be5e87a46f88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36948
91142 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.3694891142
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.2117081483
Short name T124
Test name
Test status
Simulation time 31141980436 ps
CPU time 2150.71 seconds
Started Aug 14 04:47:11 PM PDT 24
Finished Aug 14 05:23:02 PM PDT 24
Peak memory 281716 kb
Host smart-7581ef85-4524-43e8-8d50-319e0aa4ffc2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2117081483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_han
dler_stress_all.2117081483
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all_with_rand_reset.1494527013
Short name T420
Test name
Test status
Simulation time 2501035619 ps
CPU time 56.33 seconds
Started Aug 14 04:46:59 PM PDT 24
Finished Aug 14 04:47:55 PM PDT 24
Peak memory 265364 kb
Host smart-06d9a52b-d845-4732-986f-6b9b8078a846
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1494527013 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 2.alert_handler_stress_all_with_rand_reset.1494527013
Directory /workspace/2.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.1506695377
Short name T57
Test name
Test status
Simulation time 48307665833 ps
CPU time 2973.8 seconds
Started Aug 14 04:47:41 PM PDT 24
Finished Aug 14 05:37:16 PM PDT 24
Peak memory 289868 kb
Host smart-0a21ea06-b9a3-4375-90ff-2377dd5f084e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1506695377 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.1506695377
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.2668749602
Short name T369
Test name
Test status
Simulation time 1992825567 ps
CPU time 161.91 seconds
Started Aug 14 04:47:41 PM PDT 24
Finished Aug 14 04:50:23 PM PDT 24
Peak memory 256492 kb
Host smart-1cb5884f-0a36-43b0-a93d-bec73d24b31f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26687
49602 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.2668749602
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.3103937262
Short name T402
Test name
Test status
Simulation time 1191024897 ps
CPU time 73.95 seconds
Started Aug 14 04:48:00 PM PDT 24
Finished Aug 14 04:49:14 PM PDT 24
Peak memory 248520 kb
Host smart-2faec7c7-faca-48b2-8fe4-83eff3d1ed3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31039
37262 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.3103937262
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.2048220412
Short name T517
Test name
Test status
Simulation time 36935369436 ps
CPU time 1836.91 seconds
Started Aug 14 04:47:50 PM PDT 24
Finished Aug 14 05:18:28 PM PDT 24
Peak memory 273364 kb
Host smart-5fa007b8-4768-4911-805e-eda3b2a7af80
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2048220412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.2048220412
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.2144270763
Short name T497
Test name
Test status
Simulation time 26592928002 ps
CPU time 1267.17 seconds
Started Aug 14 04:47:30 PM PDT 24
Finished Aug 14 05:08:37 PM PDT 24
Peak memory 288928 kb
Host smart-34d866c5-409b-45c9-9c48-b1610c596c6b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2144270763 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.2144270763
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.1409148944
Short name T566
Test name
Test status
Simulation time 65009386946 ps
CPU time 300.93 seconds
Started Aug 14 04:47:41 PM PDT 24
Finished Aug 14 04:52:42 PM PDT 24
Peak memory 255300 kb
Host smart-e2b3dbef-c4e4-43ba-8a96-67aef71812cd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409148944 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.1409148944
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.2572091482
Short name T586
Test name
Test status
Simulation time 295748726 ps
CPU time 28.5 seconds
Started Aug 14 04:47:40 PM PDT 24
Finished Aug 14 04:48:08 PM PDT 24
Peak memory 255980 kb
Host smart-9bbed351-c1b3-4ae8-814f-5c16198daf94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25720
91482 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.2572091482
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.310765809
Short name T34
Test name
Test status
Simulation time 224230364 ps
CPU time 7.12 seconds
Started Aug 14 04:47:48 PM PDT 24
Finished Aug 14 04:47:55 PM PDT 24
Peak memory 254852 kb
Host smart-195d532a-9ac6-421a-9f9c-b163f45e4dd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31076
5809 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.310765809
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.962718229
Short name T594
Test name
Test status
Simulation time 1060628357 ps
CPU time 65.07 seconds
Started Aug 14 04:47:28 PM PDT 24
Finished Aug 14 04:48:33 PM PDT 24
Peak memory 248824 kb
Host smart-bb85ab46-c493-4b0f-8491-7d245fb5f7af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96271
8229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.962718229
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.3891842847
Short name T465
Test name
Test status
Simulation time 53083340 ps
CPU time 4.57 seconds
Started Aug 14 04:47:33 PM PDT 24
Finished Aug 14 04:47:38 PM PDT 24
Peak memory 251076 kb
Host smart-dde263f3-5a28-4adf-9c61-1ca692ca98da
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38918
42847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.3891842847
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.3394490984
Short name T275
Test name
Test status
Simulation time 6000197317 ps
CPU time 81.73 seconds
Started Aug 14 04:47:35 PM PDT 24
Finished Aug 14 04:48:57 PM PDT 24
Peak memory 257108 kb
Host smart-2413a3fa-af88-4218-8464-70296952f537
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3394490984 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_ha
ndler_stress_all.3394490984
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.2170969486
Short name T438
Test name
Test status
Simulation time 39629725107 ps
CPU time 855.43 seconds
Started Aug 14 04:47:39 PM PDT 24
Finished Aug 14 05:01:55 PM PDT 24
Peak memory 273044 kb
Host smart-9773aa43-7cfc-492c-827e-8ad43992b98c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2170969486 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.2170969486
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.3274579183
Short name T475
Test name
Test status
Simulation time 836467182 ps
CPU time 34.28 seconds
Started Aug 14 04:47:33 PM PDT 24
Finished Aug 14 04:48:07 PM PDT 24
Peak memory 256124 kb
Host smart-1998692b-62a0-4cb3-8044-8e19b27e8454
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32745
79183 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.3274579183
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.2381281543
Short name T525
Test name
Test status
Simulation time 281983210 ps
CPU time 21.33 seconds
Started Aug 14 04:47:38 PM PDT 24
Finished Aug 14 04:47:59 PM PDT 24
Peak memory 256884 kb
Host smart-84164d03-a8cc-44fe-9ef1-89bc2af2b3ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23812
81543 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.2381281543
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.3459971997
Short name T345
Test name
Test status
Simulation time 146521173298 ps
CPU time 2128.06 seconds
Started Aug 14 04:47:37 PM PDT 24
Finished Aug 14 05:23:05 PM PDT 24
Peak memory 272804 kb
Host smart-ad32f959-9161-48bd-87c7-5252ba289f73
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459971997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.3459971997
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.4228875962
Short name T571
Test name
Test status
Simulation time 23078130918 ps
CPU time 1279.81 seconds
Started Aug 14 04:47:39 PM PDT 24
Finished Aug 14 05:08:59 PM PDT 24
Peak memory 267340 kb
Host smart-e83b92b6-4b92-4636-9008-bb02f50f592d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4228875962 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.4228875962
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.2369484717
Short name T415
Test name
Test status
Simulation time 66951892 ps
CPU time 7.38 seconds
Started Aug 14 04:47:21 PM PDT 24
Finished Aug 14 04:47:29 PM PDT 24
Peak memory 248760 kb
Host smart-85305902-06a1-469e-9e41-582e9717cb61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23694
84717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.2369484717
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.4183368716
Short name T119
Test name
Test status
Simulation time 4432900672 ps
CPU time 62.34 seconds
Started Aug 14 04:47:35 PM PDT 24
Finished Aug 14 04:48:37 PM PDT 24
Peak memory 248848 kb
Host smart-bf5029f4-c5c4-4452-b454-36bfe1206a32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41833
68716 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.4183368716
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.593908771
Short name T655
Test name
Test status
Simulation time 548333522 ps
CPU time 31.94 seconds
Started Aug 14 04:47:53 PM PDT 24
Finished Aug 14 04:48:25 PM PDT 24
Peak memory 248848 kb
Host smart-268d65c5-55e6-4334-968d-eaa35a336e3d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59390
8771 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.593908771
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.4030862477
Short name T80
Test name
Test status
Simulation time 82300079579 ps
CPU time 1667.85 seconds
Started Aug 14 04:47:39 PM PDT 24
Finished Aug 14 05:15:27 PM PDT 24
Peak memory 281688 kb
Host smart-9d42e499-373d-4070-9583-6f206b4b5961
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4030862477 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_ha
ndler_stress_all.4030862477
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all_with_rand_reset.1742875324
Short name T292
Test name
Test status
Simulation time 448988547 ps
CPU time 56.25 seconds
Started Aug 14 04:47:37 PM PDT 24
Finished Aug 14 04:48:33 PM PDT 24
Peak memory 265364 kb
Host smart-302a1dc3-bee5-4ad5-b9dd-7b6cfba41f2d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1742875324 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.alert_handler_stress_all_with_rand_reset.1742875324
Directory /workspace/21.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.2134103742
Short name T556
Test name
Test status
Simulation time 42323103402 ps
CPU time 2363.05 seconds
Started Aug 14 04:47:35 PM PDT 24
Finished Aug 14 05:26:58 PM PDT 24
Peak memory 289064 kb
Host smart-b3b4b7f8-8ff3-42ef-8f32-0b9a295796c7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2134103742 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.2134103742
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.3639026263
Short name T403
Test name
Test status
Simulation time 551707634 ps
CPU time 22.86 seconds
Started Aug 14 04:47:31 PM PDT 24
Finished Aug 14 04:47:54 PM PDT 24
Peak memory 248816 kb
Host smart-5565fb91-3285-4b9c-a353-e944cc469858
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36390
26263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.3639026263
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.2347565208
Short name T575
Test name
Test status
Simulation time 393251808 ps
CPU time 36.98 seconds
Started Aug 14 04:47:43 PM PDT 24
Finished Aug 14 04:48:20 PM PDT 24
Peak memory 248760 kb
Host smart-b4b118ca-40f6-464b-9df1-1b6f8d37c89c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23475
65208 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.2347565208
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.3993036702
Short name T615
Test name
Test status
Simulation time 5714636703 ps
CPU time 515.95 seconds
Started Aug 14 04:47:31 PM PDT 24
Finished Aug 14 04:56:07 PM PDT 24
Peak memory 271620 kb
Host smart-8f8b94c1-243c-40cd-a3b1-db84b2e24e90
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3993036702 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.3993036702
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.3516020109
Short name T374
Test name
Test status
Simulation time 75470826801 ps
CPU time 2136.72 seconds
Started Aug 14 04:47:35 PM PDT 24
Finished Aug 14 05:23:12 PM PDT 24
Peak memory 288748 kb
Host smart-86ba2b9b-2a58-4bf9-9cf3-57f016482a83
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516020109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.3516020109
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.1731999124
Short name T289
Test name
Test status
Simulation time 93701344472 ps
CPU time 483.32 seconds
Started Aug 14 04:47:46 PM PDT 24
Finished Aug 14 04:55:49 PM PDT 24
Peak memory 255268 kb
Host smart-7d004b48-99e7-4232-94e5-f33c647dcb81
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1731999124 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.1731999124
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.2221884109
Short name T456
Test name
Test status
Simulation time 401191456 ps
CPU time 8.82 seconds
Started Aug 14 04:47:35 PM PDT 24
Finished Aug 14 04:47:44 PM PDT 24
Peak memory 248796 kb
Host smart-81a0fe84-f3b0-4d48-a9bd-1c6c3b17cc1a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22218
84109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.2221884109
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.3380546708
Short name T51
Test name
Test status
Simulation time 594246979 ps
CPU time 11.81 seconds
Started Aug 14 04:47:47 PM PDT 24
Finished Aug 14 04:47:59 PM PDT 24
Peak memory 256132 kb
Host smart-9b9e3448-dc83-4fa8-a472-5f62ee70b9d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33805
46708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.3380546708
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.2823868540
Short name T250
Test name
Test status
Simulation time 1574658625 ps
CPU time 51.53 seconds
Started Aug 14 04:47:42 PM PDT 24
Finished Aug 14 04:48:34 PM PDT 24
Peak memory 248184 kb
Host smart-0f929e15-ce42-4dc8-89ef-7cfce185f895
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28238
68540 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.2823868540
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.3971549366
Short name T407
Test name
Test status
Simulation time 238146264 ps
CPU time 21.81 seconds
Started Aug 14 04:47:47 PM PDT 24
Finished Aug 14 04:48:09 PM PDT 24
Peak memory 257004 kb
Host smart-7656db44-1c8c-44b9-af7f-603d6dad1f6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39715
49366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.3971549366
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.3570114545
Short name T62
Test name
Test status
Simulation time 40138949030 ps
CPU time 1448.58 seconds
Started Aug 14 04:47:47 PM PDT 24
Finished Aug 14 05:11:56 PM PDT 24
Peak memory 289784 kb
Host smart-ff3f0400-f62e-4efe-ae0f-ee8098d65fb8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3570114545 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_ha
ndler_stress_all.3570114545
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all_with_rand_reset.1898858434
Short name T276
Test name
Test status
Simulation time 12004375137 ps
CPU time 462.9 seconds
Started Aug 14 04:47:43 PM PDT 24
Finished Aug 14 04:55:26 PM PDT 24
Peak memory 283756 kb
Host smart-07df50c4-ea73-4cb7-a54d-0c4ac7cf1d10
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1898858434 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 22.alert_handler_stress_all_with_rand_reset.1898858434
Directory /workspace/22.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.372318407
Short name T640
Test name
Test status
Simulation time 83146592644 ps
CPU time 1476.34 seconds
Started Aug 14 04:47:54 PM PDT 24
Finished Aug 14 05:12:31 PM PDT 24
Peak memory 273372 kb
Host smart-4b1253da-880f-4c37-a660-d93a02d23c0b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=372318407 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.372318407
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.2286317247
Short name T508
Test name
Test status
Simulation time 220693868 ps
CPU time 7.25 seconds
Started Aug 14 04:47:45 PM PDT 24
Finished Aug 14 04:47:53 PM PDT 24
Peak memory 247944 kb
Host smart-3e1e56ca-f589-4aa7-9045-4a4d02344240
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22863
17247 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.2286317247
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.4240693191
Short name T620
Test name
Test status
Simulation time 4530473249 ps
CPU time 63.5 seconds
Started Aug 14 04:47:43 PM PDT 24
Finished Aug 14 04:48:47 PM PDT 24
Peak memory 256052 kb
Host smart-1578011d-756a-42b6-94da-49f664944f77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42406
93191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.4240693191
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.1168027742
Short name T12
Test name
Test status
Simulation time 28663314274 ps
CPU time 1674.63 seconds
Started Aug 14 04:47:50 PM PDT 24
Finished Aug 14 05:15:45 PM PDT 24
Peak memory 273476 kb
Host smart-e6b759be-2006-4e07-be04-e1413b8de9c0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1168027742 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.1168027742
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.2091056291
Short name T104
Test name
Test status
Simulation time 123034215838 ps
CPU time 1818.47 seconds
Started Aug 14 04:47:48 PM PDT 24
Finished Aug 14 05:18:07 PM PDT 24
Peak memory 273480 kb
Host smart-e25482bb-b42e-4c88-9293-198fc018ebe7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2091056291 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.2091056291
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.1358299642
Short name T306
Test name
Test status
Simulation time 17854536531 ps
CPU time 694.54 seconds
Started Aug 14 04:47:49 PM PDT 24
Finished Aug 14 04:59:24 PM PDT 24
Peak memory 248816 kb
Host smart-9d0b9e1b-1413-4c21-ae18-533000d9a881
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1358299642 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.1358299642
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.3691234078
Short name T285
Test name
Test status
Simulation time 1291389315 ps
CPU time 18.44 seconds
Started Aug 14 04:47:53 PM PDT 24
Finished Aug 14 04:48:12 PM PDT 24
Peak memory 248800 kb
Host smart-0861f789-5332-4055-b3d0-122c3633d992
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36912
34078 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.3691234078
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.588372983
Short name T459
Test name
Test status
Simulation time 955288285 ps
CPU time 33.23 seconds
Started Aug 14 04:47:48 PM PDT 24
Finished Aug 14 04:48:21 PM PDT 24
Peak memory 248152 kb
Host smart-d79073db-0698-417c-8d1f-0495e8e8ced5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58837
2983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.588372983
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.4189495003
Short name T719
Test name
Test status
Simulation time 1726750106 ps
CPU time 24.8 seconds
Started Aug 14 04:47:44 PM PDT 24
Finished Aug 14 04:48:09 PM PDT 24
Peak memory 248872 kb
Host smart-5fb5e054-0c37-410a-862f-233c37200597
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41894
95003 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.4189495003
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.3571392918
Short name T295
Test name
Test status
Simulation time 13208722854 ps
CPU time 406.78 seconds
Started Aug 14 04:47:51 PM PDT 24
Finished Aug 14 04:54:38 PM PDT 24
Peak memory 257108 kb
Host smart-e62e6491-cbbf-49a3-b1b0-788dd6f8fb6c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3571392918 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_ha
ndler_stress_all.3571392918
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all_with_rand_reset.2724013201
Short name T528
Test name
Test status
Simulation time 5985287958 ps
CPU time 199.89 seconds
Started Aug 14 04:47:49 PM PDT 24
Finished Aug 14 04:51:09 PM PDT 24
Peak memory 265432 kb
Host smart-8abea673-c7bc-4ec1-9e74-e8f5ea55f915
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2724013201 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.alert_handler_stress_all_with_rand_reset.2724013201
Directory /workspace/23.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.1808290981
Short name T457
Test name
Test status
Simulation time 60723225053 ps
CPU time 1833.99 seconds
Started Aug 14 04:47:48 PM PDT 24
Finished Aug 14 05:18:22 PM PDT 24
Peak memory 289512 kb
Host smart-b9100aaf-61d4-48d1-9ce8-1d7be0502e5b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1808290981 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.1808290981
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.649603940
Short name T676
Test name
Test status
Simulation time 948121290 ps
CPU time 65.14 seconds
Started Aug 14 04:47:44 PM PDT 24
Finished Aug 14 04:48:49 PM PDT 24
Peak memory 249812 kb
Host smart-f43cb24a-9a25-4721-83d1-4eef2fafa158
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64960
3940 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.649603940
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.1553800545
Short name T77
Test name
Test status
Simulation time 3154364904 ps
CPU time 52.49 seconds
Started Aug 14 04:48:08 PM PDT 24
Finished Aug 14 04:49:00 PM PDT 24
Peak memory 248856 kb
Host smart-92f232d2-e744-4d62-80b1-69c5566984cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15538
00545 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.1553800545
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.3622346661
Short name T343
Test name
Test status
Simulation time 64491647600 ps
CPU time 1544.94 seconds
Started Aug 14 04:47:43 PM PDT 24
Finished Aug 14 05:13:28 PM PDT 24
Peak memory 284948 kb
Host smart-4a61f68e-037e-4079-baf5-6abfe39333cd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622346661 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.3622346661
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.4046662867
Short name T412
Test name
Test status
Simulation time 82861428312 ps
CPU time 1427.86 seconds
Started Aug 14 04:47:49 PM PDT 24
Finished Aug 14 05:11:37 PM PDT 24
Peak memory 273416 kb
Host smart-9ec2f8ac-58d7-4255-b597-525025719f00
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4046662867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.4046662867
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.2446826369
Short name T319
Test name
Test status
Simulation time 5147746569 ps
CPU time 206.38 seconds
Started Aug 14 04:47:41 PM PDT 24
Finished Aug 14 04:51:08 PM PDT 24
Peak memory 248876 kb
Host smart-7bf6461c-b3e0-4e08-bed5-f85438da1c38
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2446826369 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.2446826369
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.104392492
Short name T228
Test name
Test status
Simulation time 431378234 ps
CPU time 28.04 seconds
Started Aug 14 04:47:50 PM PDT 24
Finished Aug 14 04:48:18 PM PDT 24
Peak memory 255544 kb
Host smart-0862d631-d13c-400f-832b-b939b378eacc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10439
2492 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.104392492
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.1142256581
Short name T603
Test name
Test status
Simulation time 402239800 ps
CPU time 17.81 seconds
Started Aug 14 04:47:35 PM PDT 24
Finished Aug 14 04:47:53 PM PDT 24
Peak memory 248512 kb
Host smart-73601fab-8658-4380-b9ad-d8c4689e670c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11422
56581 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.1142256581
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.3448873441
Short name T418
Test name
Test status
Simulation time 718909511 ps
CPU time 12.71 seconds
Started Aug 14 04:47:43 PM PDT 24
Finished Aug 14 04:47:56 PM PDT 24
Peak memory 253112 kb
Host smart-05b6e02d-d0ad-4246-a2d2-6c02edce4ac6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34488
73441 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.3448873441
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.1461718886
Short name T112
Test name
Test status
Simulation time 545214065 ps
CPU time 25.75 seconds
Started Aug 14 04:47:49 PM PDT 24
Finished Aug 14 04:48:15 PM PDT 24
Peak memory 248848 kb
Host smart-bc9b5bdc-c7be-42ec-bd48-375f196ea71a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14617
18886 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.1461718886
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.86090282
Short name T534
Test name
Test status
Simulation time 48781020914 ps
CPU time 1586.68 seconds
Started Aug 14 04:47:50 PM PDT 24
Finished Aug 14 05:14:17 PM PDT 24
Peak memory 273132 kb
Host smart-4aeb51d4-07b0-4ff5-b8e5-2e63ed28739f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=86090282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.86090282
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.1783624941
Short name T515
Test name
Test status
Simulation time 7057405024 ps
CPU time 153.27 seconds
Started Aug 14 04:47:59 PM PDT 24
Finished Aug 14 04:50:33 PM PDT 24
Peak memory 257060 kb
Host smart-c4cee0aa-9ed1-409f-a640-addab43dde85
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17836
24941 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.1783624941
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.382287236
Short name T584
Test name
Test status
Simulation time 27900028 ps
CPU time 2.8 seconds
Started Aug 14 04:47:50 PM PDT 24
Finished Aug 14 04:47:52 PM PDT 24
Peak memory 240568 kb
Host smart-d7c4b8aa-9f93-431d-b06f-ce04c0a223b1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38228
7236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.382287236
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.3180538563
Short name T483
Test name
Test status
Simulation time 7278736052 ps
CPU time 874.81 seconds
Started Aug 14 04:48:04 PM PDT 24
Finished Aug 14 05:02:39 PM PDT 24
Peak memory 273424 kb
Host smart-f705fa9b-271b-45b3-9018-0b604abb50bd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3180538563 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.3180538563
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.1427618540
Short name T233
Test name
Test status
Simulation time 7659041683 ps
CPU time 239.81 seconds
Started Aug 14 04:48:19 PM PDT 24
Finished Aug 14 04:52:19 PM PDT 24
Peak memory 247376 kb
Host smart-7d29fb6f-e17f-4f04-8d4e-0136d6304b47
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1427618540 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.1427618540
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.3900834569
Short name T667
Test name
Test status
Simulation time 2101975505 ps
CPU time 39.06 seconds
Started Aug 14 04:47:46 PM PDT 24
Finished Aug 14 04:48:25 PM PDT 24
Peak memory 248732 kb
Host smart-f2d3268d-4245-4c04-a18c-93512fbd198e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39008
34569 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.3900834569
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.2943409885
Short name T570
Test name
Test status
Simulation time 1137376769 ps
CPU time 38.36 seconds
Started Aug 14 04:47:46 PM PDT 24
Finished Aug 14 04:48:25 PM PDT 24
Peak memory 256432 kb
Host smart-3e6c6f7c-6bf0-4580-b34b-bbdedc3c7619
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29434
09885 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.2943409885
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.1842201558
Short name T688
Test name
Test status
Simulation time 920681017 ps
CPU time 23.87 seconds
Started Aug 14 04:47:50 PM PDT 24
Finished Aug 14 04:48:15 PM PDT 24
Peak memory 256328 kb
Host smart-5d8b3f83-be4a-40f1-8c69-5bb6370bdbe3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18422
01558 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.1842201558
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.3490823954
Short name T715
Test name
Test status
Simulation time 506764536 ps
CPU time 28.41 seconds
Started Aug 14 04:47:46 PM PDT 24
Finished Aug 14 04:48:15 PM PDT 24
Peak memory 255064 kb
Host smart-e035d20a-c88e-44f4-8127-1cc0a410f46e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34908
23954 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.3490823954
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.2065178938
Short name T125
Test name
Test status
Simulation time 65474005304 ps
CPU time 1039.03 seconds
Started Aug 14 04:47:39 PM PDT 24
Finished Aug 14 05:04:58 PM PDT 24
Peak memory 269668 kb
Host smart-91bb4ade-e8e0-4ca2-bf5f-029b5137ce1f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2065178938 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_ha
ndler_stress_all.2065178938
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all_with_rand_reset.1929395434
Short name T122
Test name
Test status
Simulation time 3434834806 ps
CPU time 217.99 seconds
Started Aug 14 04:47:44 PM PDT 24
Finished Aug 14 04:51:22 PM PDT 24
Peak memory 265396 kb
Host smart-52eb5589-35a7-4042-ad77-129b6b67c4d7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1929395434 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 25.alert_handler_stress_all_with_rand_reset.1929395434
Directory /workspace/25.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.644404963
Short name T476
Test name
Test status
Simulation time 58579249786 ps
CPU time 1033.19 seconds
Started Aug 14 04:47:50 PM PDT 24
Finished Aug 14 05:05:03 PM PDT 24
Peak memory 286244 kb
Host smart-edc0e7e1-073e-41b8-9844-19dfc8c285f9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=644404963 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.644404963
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.1503363606
Short name T10
Test name
Test status
Simulation time 8459684487 ps
CPU time 65.56 seconds
Started Aug 14 04:47:46 PM PDT 24
Finished Aug 14 04:48:51 PM PDT 24
Peak memory 256492 kb
Host smart-29e8526a-a047-4bd1-a981-73009488d020
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15033
63606 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.1503363606
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.3854933281
Short name T598
Test name
Test status
Simulation time 522820370 ps
CPU time 12.75 seconds
Started Aug 14 04:47:39 PM PDT 24
Finished Aug 14 04:47:52 PM PDT 24
Peak memory 255228 kb
Host smart-aa785084-c018-4ee2-88fb-87f0c680dfa7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38549
33281 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.3854933281
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.805938880
Short name T30
Test name
Test status
Simulation time 15888750556 ps
CPU time 1314.66 seconds
Started Aug 14 04:47:49 PM PDT 24
Finished Aug 14 05:09:44 PM PDT 24
Peak memory 289032 kb
Host smart-7bef3a34-6402-400e-b8e2-7e55f94d8862
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=805938880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.805938880
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.11214599
Short name T657
Test name
Test status
Simulation time 17793319292 ps
CPU time 193.08 seconds
Started Aug 14 04:47:53 PM PDT 24
Finished Aug 14 04:51:06 PM PDT 24
Peak memory 248976 kb
Host smart-301982e3-c038-47b1-a78e-1a104fcedeb1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=11214599 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.11214599
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.652881724
Short name T25
Test name
Test status
Simulation time 2009339715 ps
CPU time 61.73 seconds
Started Aug 14 04:47:43 PM PDT 24
Finished Aug 14 04:48:45 PM PDT 24
Peak memory 256936 kb
Host smart-740c092c-94db-4fbe-807e-6e809d330cb8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65288
1724 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.652881724
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.3711486639
Short name T549
Test name
Test status
Simulation time 3928381425 ps
CPU time 56.78 seconds
Started Aug 14 04:47:49 PM PDT 24
Finished Aug 14 04:48:46 PM PDT 24
Peak memory 248900 kb
Host smart-5853eaf4-6154-4bd8-b38b-38ff5fa4cbf2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37114
86639 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.3711486639
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.1733364514
Short name T639
Test name
Test status
Simulation time 1458338621 ps
CPU time 54.54 seconds
Started Aug 14 04:47:45 PM PDT 24
Finished Aug 14 04:48:40 PM PDT 24
Peak memory 256124 kb
Host smart-9a5d6447-1174-42b0-91ca-e5686233fb2a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17333
64514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.1733364514
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.3889398908
Short name T682
Test name
Test status
Simulation time 2036159010 ps
CPU time 27 seconds
Started Aug 14 04:47:47 PM PDT 24
Finished Aug 14 04:48:14 PM PDT 24
Peak memory 256900 kb
Host smart-08366ba1-0e52-4d85-815e-80ae0b1e004a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38893
98908 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.3889398908
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.2270188523
Short name T578
Test name
Test status
Simulation time 3618791096 ps
CPU time 156.81 seconds
Started Aug 14 04:47:46 PM PDT 24
Finished Aug 14 04:50:23 PM PDT 24
Peak memory 257028 kb
Host smart-2cd01f95-3cd6-4a5e-9f8a-e6bb989f3b6d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2270188523 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_ha
ndler_stress_all.2270188523
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all_with_rand_reset.3419192926
Short name T527
Test name
Test status
Simulation time 3177260734 ps
CPU time 356.54 seconds
Started Aug 14 04:47:47 PM PDT 24
Finished Aug 14 04:53:44 PM PDT 24
Peak memory 268608 kb
Host smart-cef3811a-9be3-40f8-8708-9782bbdf9c09
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3419192926 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 26.alert_handler_stress_all_with_rand_reset.3419192926
Directory /workspace/26.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.2136112115
Short name T699
Test name
Test status
Simulation time 418144656204 ps
CPU time 1603.62 seconds
Started Aug 14 04:48:10 PM PDT 24
Finished Aug 14 05:14:54 PM PDT 24
Peak memory 281636 kb
Host smart-11f9fe8f-bbcf-4fd8-b635-b38f7de61ddb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2136112115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.2136112115
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.3504870146
Short name T628
Test name
Test status
Simulation time 1987151469 ps
CPU time 93.46 seconds
Started Aug 14 04:47:46 PM PDT 24
Finished Aug 14 04:49:20 PM PDT 24
Peak memory 256480 kb
Host smart-b2f26c3a-753f-4205-bcfa-d07128870097
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35048
70146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.3504870146
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.556157100
Short name T425
Test name
Test status
Simulation time 73740344 ps
CPU time 8.75 seconds
Started Aug 14 04:47:49 PM PDT 24
Finished Aug 14 04:47:58 PM PDT 24
Peak memory 255040 kb
Host smart-27f2fdbd-8f0e-496d-be03-9f8bbd37ec1b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=55615
7100 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.556157100
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.3962828341
Short name T533
Test name
Test status
Simulation time 151514539333 ps
CPU time 2036.55 seconds
Started Aug 14 04:47:54 PM PDT 24
Finished Aug 14 05:21:51 PM PDT 24
Peak memory 271912 kb
Host smart-cae1ec49-5200-445a-91af-3263e4c63e45
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3962828341 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.3962828341
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.2212114450
Short name T647
Test name
Test status
Simulation time 75499375268 ps
CPU time 1701.15 seconds
Started Aug 14 04:47:47 PM PDT 24
Finished Aug 14 05:16:08 PM PDT 24
Peak memory 289672 kb
Host smart-c7402cbf-e295-4e62-a20f-8947c4d39bb1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2212114450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.2212114450
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.2098220188
Short name T658
Test name
Test status
Simulation time 48374824238 ps
CPU time 491.19 seconds
Started Aug 14 04:47:43 PM PDT 24
Finished Aug 14 04:55:55 PM PDT 24
Peak memory 248880 kb
Host smart-d774fa84-0ab0-4aa5-99fe-634a25c8a5ca
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2098220188 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.2098220188
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.1300075780
Short name T679
Test name
Test status
Simulation time 3939370987 ps
CPU time 58.98 seconds
Started Aug 14 04:47:53 PM PDT 24
Finished Aug 14 04:48:52 PM PDT 24
Peak memory 248792 kb
Host smart-1e900c0e-b3a8-40c8-8258-5eb9518521f3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13000
75780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.1300075780
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.2956981065
Short name T120
Test name
Test status
Simulation time 1005721990 ps
CPU time 34.23 seconds
Started Aug 14 04:47:45 PM PDT 24
Finished Aug 14 04:48:19 PM PDT 24
Peak memory 256572 kb
Host smart-2043ee2e-163e-4b6f-9504-ced5247781d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29569
81065 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.2956981065
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.813585594
Short name T231
Test name
Test status
Simulation time 320433651 ps
CPU time 38.95 seconds
Started Aug 14 04:47:53 PM PDT 24
Finished Aug 14 04:48:32 PM PDT 24
Peak memory 249868 kb
Host smart-367302b7-be9f-4a72-93dd-5a96a1dfcea0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=81358
5594 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.813585594
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.3435313018
Short name T691
Test name
Test status
Simulation time 4861550626 ps
CPU time 28.09 seconds
Started Aug 14 04:48:05 PM PDT 24
Finished Aug 14 04:48:33 PM PDT 24
Peak memory 248840 kb
Host smart-29a127c6-bfb7-4e2e-a9a2-ed31cb55207d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34353
13018 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.3435313018
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.2376786142
Short name T401
Test name
Test status
Simulation time 5485168337 ps
CPU time 293.72 seconds
Started Aug 14 04:48:12 PM PDT 24
Finished Aug 14 04:53:06 PM PDT 24
Peak memory 256940 kb
Host smart-545fd5a0-30e5-4e50-bc1f-ae83d550147e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2376786142 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_ha
ndler_stress_all.2376786142
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all_with_rand_reset.2474716203
Short name T54
Test name
Test status
Simulation time 12425610706 ps
CPU time 433.66 seconds
Started Aug 14 04:47:43 PM PDT 24
Finished Aug 14 04:54:57 PM PDT 24
Peak memory 272112 kb
Host smart-ccfc2940-06e1-4272-9408-1fefef5528bb
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2474716203 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 27.alert_handler_stress_all_with_rand_reset.2474716203
Directory /workspace/27.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.4092315134
Short name T85
Test name
Test status
Simulation time 6122862383 ps
CPU time 54.05 seconds
Started Aug 14 04:47:35 PM PDT 24
Finished Aug 14 04:48:29 PM PDT 24
Peak memory 256420 kb
Host smart-623e1577-e7ce-46b2-aa7a-f8cf8738dbed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40923
15134 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.4092315134
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.3822828236
Short name T630
Test name
Test status
Simulation time 80288364 ps
CPU time 4.26 seconds
Started Aug 14 04:47:39 PM PDT 24
Finished Aug 14 04:47:43 PM PDT 24
Peak memory 239948 kb
Host smart-e96b9cd6-fb59-4116-a74a-07ba47db6a5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38228
28236 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.3822828236
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.1921024396
Short name T67
Test name
Test status
Simulation time 74802145869 ps
CPU time 1381.61 seconds
Started Aug 14 04:47:39 PM PDT 24
Finished Aug 14 05:10:41 PM PDT 24
Peak memory 272912 kb
Host smart-18159c34-a03e-4bd4-92e9-146dfa1e484e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1921024396 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.1921024396
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.1530463162
Short name T322
Test name
Test status
Simulation time 7628216476 ps
CPU time 319.03 seconds
Started Aug 14 04:47:42 PM PDT 24
Finished Aug 14 04:53:02 PM PDT 24
Peak memory 248824 kb
Host smart-269662ab-f29f-4cdd-90ca-912ae90af8c2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1530463162 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.1530463162
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.4110968984
Short name T366
Test name
Test status
Simulation time 2402471673 ps
CPU time 14.8 seconds
Started Aug 14 04:48:00 PM PDT 24
Finished Aug 14 04:48:15 PM PDT 24
Peak memory 254192 kb
Host smart-5bcec941-e538-48cd-9289-627f6b17a2e9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41109
68984 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.4110968984
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.3362648077
Short name T84
Test name
Test status
Simulation time 218323979 ps
CPU time 13.55 seconds
Started Aug 14 04:47:47 PM PDT 24
Finished Aug 14 04:48:01 PM PDT 24
Peak memory 248236 kb
Host smart-16e33833-9946-4f8a-a05f-92c7b0e96a98
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33626
48077 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.3362648077
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.3912089654
Short name T400
Test name
Test status
Simulation time 200864358 ps
CPU time 14.5 seconds
Started Aug 14 04:47:50 PM PDT 24
Finished Aug 14 04:48:05 PM PDT 24
Peak memory 248744 kb
Host smart-5e8aa7da-549d-442a-9cb6-ad5a17606da6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39120
89654 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.3912089654
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.372041304
Short name T583
Test name
Test status
Simulation time 1650296502 ps
CPU time 56.09 seconds
Started Aug 14 04:47:34 PM PDT 24
Finished Aug 14 04:48:30 PM PDT 24
Peak memory 256872 kb
Host smart-2b0ba805-3fa4-40d2-bf29-3ee6ac65e351
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37204
1304 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.372041304
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.2763269824
Short name T78
Test name
Test status
Simulation time 13803315783 ps
CPU time 1375.56 seconds
Started Aug 14 04:47:45 PM PDT 24
Finished Aug 14 05:10:41 PM PDT 24
Peak memory 289876 kb
Host smart-8bbc964c-b247-4e02-9951-5204797ec994
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2763269824 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_ha
ndler_stress_all.2763269824
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.2671832527
Short name T653
Test name
Test status
Simulation time 184656982333 ps
CPU time 2622.81 seconds
Started Aug 14 04:47:37 PM PDT 24
Finished Aug 14 05:31:20 PM PDT 24
Peak memory 284988 kb
Host smart-2b10291a-113d-47a7-be70-e1ad54530c0f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2671832527 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.2671832527
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.3707302564
Short name T101
Test name
Test status
Simulation time 5497643369 ps
CPU time 125.26 seconds
Started Aug 14 04:47:45 PM PDT 24
Finished Aug 14 04:49:50 PM PDT 24
Peak memory 257064 kb
Host smart-6366a7fe-2883-41ed-b2f6-f18262153c79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37073
02564 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.3707302564
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.3592220232
Short name T553
Test name
Test status
Simulation time 540413651 ps
CPU time 26.53 seconds
Started Aug 14 04:48:03 PM PDT 24
Finished Aug 14 04:48:29 PM PDT 24
Peak memory 256580 kb
Host smart-a2669a28-4c89-4623-b931-022acb4d6dfa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35922
20232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.3592220232
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.2437969268
Short name T344
Test name
Test status
Simulation time 96634819804 ps
CPU time 1698.11 seconds
Started Aug 14 04:47:45 PM PDT 24
Finished Aug 14 05:16:03 PM PDT 24
Peak memory 273140 kb
Host smart-df2149b2-21f7-4589-817b-46618495d4cc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2437969268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.2437969268
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.991352413
Short name T669
Test name
Test status
Simulation time 26518366297 ps
CPU time 1057.48 seconds
Started Aug 14 04:47:48 PM PDT 24
Finished Aug 14 05:05:25 PM PDT 24
Peak memory 284080 kb
Host smart-c85f0d21-90d7-437a-8423-bb319287e2a8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991352413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.991352413
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.3217098777
Short name T102
Test name
Test status
Simulation time 3854657885 ps
CPU time 165.86 seconds
Started Aug 14 04:47:45 PM PDT 24
Finished Aug 14 04:50:31 PM PDT 24
Peak memory 247680 kb
Host smart-1a303958-123f-4112-a538-cf7f4a92001d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3217098777 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.3217098777
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.4287587715
Short name T568
Test name
Test status
Simulation time 1056297377 ps
CPU time 21.39 seconds
Started Aug 14 04:47:47 PM PDT 24
Finished Aug 14 04:48:08 PM PDT 24
Peak memory 254796 kb
Host smart-6b345378-a96f-46c9-baab-eda7395a3d96
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42875
87715 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.4287587715
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.2160266268
Short name T544
Test name
Test status
Simulation time 266710035 ps
CPU time 15.08 seconds
Started Aug 14 04:47:44 PM PDT 24
Finished Aug 14 04:48:00 PM PDT 24
Peak memory 256560 kb
Host smart-41d3bb69-9113-45b4-ad7f-10c0b54de620
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21602
66268 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.2160266268
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.2728251100
Short name T398
Test name
Test status
Simulation time 1819391981 ps
CPU time 23.23 seconds
Started Aug 14 04:47:41 PM PDT 24
Finished Aug 14 04:48:05 PM PDT 24
Peak memory 249320 kb
Host smart-b87af894-1d56-41c5-ac02-9676a612f7bf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27282
51100 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.2728251100
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.724033023
Short name T130
Test name
Test status
Simulation time 1148004567 ps
CPU time 35.74 seconds
Started Aug 14 04:47:39 PM PDT 24
Finished Aug 14 04:48:15 PM PDT 24
Peak memory 248764 kb
Host smart-76437d48-ec23-41ca-8378-e370756b1cef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72403
3023 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.724033023
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.1261796866
Short name T89
Test name
Test status
Simulation time 4355392043 ps
CPU time 117.99 seconds
Started Aug 14 04:47:48 PM PDT 24
Finished Aug 14 04:49:46 PM PDT 24
Peak memory 257080 kb
Host smart-af0360bb-25ed-4853-8b37-1458d6fac815
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1261796866 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_ha
ndler_stress_all.1261796866
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all_with_rand_reset.3495296971
Short name T44
Test name
Test status
Simulation time 8296990303 ps
CPU time 219.74 seconds
Started Aug 14 04:47:48 PM PDT 24
Finished Aug 14 04:51:28 PM PDT 24
Peak memory 269300 kb
Host smart-1cf8cb1e-9d5f-4c4a-9411-fa641ffb6aa7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495296971 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.alert_handler_stress_all_with_rand_reset.3495296971
Directory /workspace/29.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.2744535180
Short name T213
Test name
Test status
Simulation time 13500519 ps
CPU time 2.33 seconds
Started Aug 14 04:47:01 PM PDT 24
Finished Aug 14 04:47:04 PM PDT 24
Peak memory 249056 kb
Host smart-9dd6aa1c-bdae-4672-b376-d8ca4f895ff1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2744535180 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.2744535180
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.1877386932
Short name T595
Test name
Test status
Simulation time 77676674255 ps
CPU time 1308.17 seconds
Started Aug 14 04:46:55 PM PDT 24
Finished Aug 14 05:08:43 PM PDT 24
Peak memory 288540 kb
Host smart-a7615385-6fa0-4983-aa95-82cc83112c81
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1877386932 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.1877386932
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.1389223105
Short name T419
Test name
Test status
Simulation time 328713560 ps
CPU time 14.89 seconds
Started Aug 14 04:46:55 PM PDT 24
Finished Aug 14 04:47:10 PM PDT 24
Peak memory 248740 kb
Host smart-be62e632-7967-4bc9-b441-d1b72d16c107
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1389223105 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.1389223105
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.3425233804
Short name T373
Test name
Test status
Simulation time 1296525011 ps
CPU time 106.94 seconds
Started Aug 14 04:46:57 PM PDT 24
Finished Aug 14 04:48:45 PM PDT 24
Peak memory 256600 kb
Host smart-85852952-c629-4363-8514-b546a7aac03c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34252
33804 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.3425233804
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.3872145929
Short name T579
Test name
Test status
Simulation time 315970018 ps
CPU time 20.18 seconds
Started Aug 14 04:47:02 PM PDT 24
Finished Aug 14 04:47:22 PM PDT 24
Peak memory 255800 kb
Host smart-a11344dc-8f49-48c3-9e53-f670e5c9060b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38721
45929 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.3872145929
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.2945919298
Short name T436
Test name
Test status
Simulation time 56292163807 ps
CPU time 1931.3 seconds
Started Aug 14 04:46:51 PM PDT 24
Finished Aug 14 05:19:03 PM PDT 24
Peak memory 281760 kb
Host smart-675e2f28-d1c6-4514-b9ea-890c55ac7939
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2945919298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.2945919298
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.175531839
Short name T21
Test name
Test status
Simulation time 626879800 ps
CPU time 36.13 seconds
Started Aug 14 04:46:57 PM PDT 24
Finished Aug 14 04:47:34 PM PDT 24
Peak memory 255996 kb
Host smart-51d44588-91e5-411c-ae6d-59405550d188
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17553
1839 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.175531839
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.2487158906
Short name T654
Test name
Test status
Simulation time 60714223 ps
CPU time 4.83 seconds
Started Aug 14 04:46:57 PM PDT 24
Finished Aug 14 04:47:02 PM PDT 24
Peak memory 240112 kb
Host smart-05c6d1fb-7224-4003-be2c-e52f5c6156e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24871
58906 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.2487158906
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.1984525240
Short name T9
Test name
Test status
Simulation time 568535370 ps
CPU time 25.3 seconds
Started Aug 14 04:46:44 PM PDT 24
Finished Aug 14 04:47:09 PM PDT 24
Peak memory 270952 kb
Host smart-7ec3d468-e51a-4127-aef7-30cd07ecee8a
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=1984525240 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.1984525240
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.38919473
Short name T396
Test name
Test status
Simulation time 1001702733 ps
CPU time 63.14 seconds
Started Aug 14 04:46:53 PM PDT 24
Finished Aug 14 04:47:56 PM PDT 24
Peak memory 249304 kb
Host smart-137e4303-455c-469f-afd9-0e5df51c0076
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38919
473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+
assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.38919473
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.3616427709
Short name T448
Test name
Test status
Simulation time 1373313016 ps
CPU time 14.32 seconds
Started Aug 14 04:46:57 PM PDT 24
Finished Aug 14 04:47:11 PM PDT 24
Peak memory 248692 kb
Host smart-ab4aa272-f51a-45b0-8eb0-b4379a067fbd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36164
27709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.3616427709
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.3102216570
Short name T585
Test name
Test status
Simulation time 737711645 ps
CPU time 75.14 seconds
Started Aug 14 04:47:09 PM PDT 24
Finished Aug 14 04:48:25 PM PDT 24
Peak memory 249732 kb
Host smart-e876cf28-789e-4295-a18b-7f1358754a25
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3102216570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_han
dler_stress_all.3102216570
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.2397282868
Short name T94
Test name
Test status
Simulation time 211343269749 ps
CPU time 2924.41 seconds
Started Aug 14 04:47:53 PM PDT 24
Finished Aug 14 05:36:38 PM PDT 24
Peak memory 289792 kb
Host smart-61768ac3-57f8-43ec-9b09-688573775be7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2397282868 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.2397282868
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.1538090570
Short name T522
Test name
Test status
Simulation time 4468401571 ps
CPU time 224.17 seconds
Started Aug 14 04:48:01 PM PDT 24
Finished Aug 14 04:51:45 PM PDT 24
Peak memory 251012 kb
Host smart-776f01e6-dfd5-475c-8545-baed8121aa16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15380
90570 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.1538090570
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.1339995211
Short name T123
Test name
Test status
Simulation time 3041040604 ps
CPU time 47.83 seconds
Started Aug 14 04:47:47 PM PDT 24
Finished Aug 14 04:48:35 PM PDT 24
Peak memory 248856 kb
Host smart-e773de07-cbb2-4d64-953c-57aaa07520fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13399
95211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.1339995211
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.1512292808
Short name T338
Test name
Test status
Simulation time 20355097478 ps
CPU time 861.23 seconds
Started Aug 14 04:47:47 PM PDT 24
Finished Aug 14 05:02:08 PM PDT 24
Peak memory 283808 kb
Host smart-5e30de55-34c7-441b-b9a3-668f32787d81
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1512292808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.1512292808
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.1867101367
Short name T588
Test name
Test status
Simulation time 24623534445 ps
CPU time 1468.28 seconds
Started Aug 14 04:47:51 PM PDT 24
Finished Aug 14 05:12:20 PM PDT 24
Peak memory 273364 kb
Host smart-761f9f2e-3283-486a-a4f5-f06b80e6ea0f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1867101367 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.1867101367
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.2158500814
Short name T288
Test name
Test status
Simulation time 1898269865 ps
CPU time 67.38 seconds
Started Aug 14 04:47:48 PM PDT 24
Finished Aug 14 04:48:56 PM PDT 24
Peak memory 248776 kb
Host smart-7be31af6-eb47-406e-90ed-41c516b21d4a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2158500814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.2158500814
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.3960757048
Short name T612
Test name
Test status
Simulation time 301808913 ps
CPU time 10.57 seconds
Started Aug 14 04:48:11 PM PDT 24
Finished Aug 14 04:48:22 PM PDT 24
Peak memory 248920 kb
Host smart-79dba579-4ad4-4450-8a42-0c4f42009a29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39607
57048 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.3960757048
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.88983460
Short name T384
Test name
Test status
Simulation time 329923363 ps
CPU time 9.96 seconds
Started Aug 14 04:47:58 PM PDT 24
Finished Aug 14 04:48:09 PM PDT 24
Peak memory 248328 kb
Host smart-6b084716-9443-4bbc-8746-0a578a6b13af
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88983
460 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.88983460
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.875824865
Short name T574
Test name
Test status
Simulation time 416416299 ps
CPU time 15.08 seconds
Started Aug 14 04:47:43 PM PDT 24
Finished Aug 14 04:47:58 PM PDT 24
Peak memory 255952 kb
Host smart-c7753e87-5762-402a-9bd7-3db111946db4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87582
4865 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.875824865
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.3863650979
Short name T673
Test name
Test status
Simulation time 1147774963 ps
CPU time 63.02 seconds
Started Aug 14 04:47:49 PM PDT 24
Finished Aug 14 04:48:52 PM PDT 24
Peak memory 256980 kb
Host smart-d3b5be37-59dd-44ba-8f36-677ab7d053ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38636
50979 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.3863650979
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.1342004797
Short name T499
Test name
Test status
Simulation time 98804010835 ps
CPU time 2660.35 seconds
Started Aug 14 04:47:38 PM PDT 24
Finished Aug 14 05:31:58 PM PDT 24
Peak memory 289780 kb
Host smart-b06ca419-1cca-4eda-84ad-cd21740df50c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1342004797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_ha
ndler_stress_all.1342004797
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all_with_rand_reset.2963081190
Short name T81
Test name
Test status
Simulation time 5787962542 ps
CPU time 149.95 seconds
Started Aug 14 04:47:54 PM PDT 24
Finished Aug 14 04:50:24 PM PDT 24
Peak memory 271868 kb
Host smart-8fbdf25d-912b-4846-952b-74b909002cca
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2963081190 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 30.alert_handler_stress_all_with_rand_reset.2963081190
Directory /workspace/30.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.1203224877
Short name T450
Test name
Test status
Simulation time 86975172721 ps
CPU time 2257.1 seconds
Started Aug 14 04:47:50 PM PDT 24
Finished Aug 14 05:25:28 PM PDT 24
Peak memory 288956 kb
Host smart-3713d89e-3635-44c4-8a31-905f7aafe202
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1203224877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.1203224877
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.1176291882
Short name T590
Test name
Test status
Simulation time 3900355377 ps
CPU time 171.57 seconds
Started Aug 14 04:47:47 PM PDT 24
Finished Aug 14 04:50:38 PM PDT 24
Peak memory 256344 kb
Host smart-813f9478-8559-4d6d-842a-8a1c4ec77e9b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11762
91882 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.1176291882
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.1383822170
Short name T687
Test name
Test status
Simulation time 645317794 ps
CPU time 49.05 seconds
Started Aug 14 04:48:00 PM PDT 24
Finished Aug 14 04:48:49 PM PDT 24
Peak memory 248792 kb
Host smart-aed2f55e-1ff4-4033-9b98-cc7ff5b6d6ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13838
22170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.1383822170
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.741851978
Short name T700
Test name
Test status
Simulation time 116237333862 ps
CPU time 1683.62 seconds
Started Aug 14 04:47:44 PM PDT 24
Finished Aug 14 05:15:48 PM PDT 24
Peak memory 281656 kb
Host smart-bae7641f-d4cb-4581-a185-813632b9b839
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=741851978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.741851978
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.3096262577
Short name T470
Test name
Test status
Simulation time 90839510207 ps
CPU time 1709.22 seconds
Started Aug 14 04:47:52 PM PDT 24
Finished Aug 14 05:16:22 PM PDT 24
Peak memory 273460 kb
Host smart-962a1ad3-86e2-4611-b0d3-01165a0ea061
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3096262577 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.3096262577
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.1409859658
Short name T309
Test name
Test status
Simulation time 36211276961 ps
CPU time 258.58 seconds
Started Aug 14 04:47:50 PM PDT 24
Finished Aug 14 04:52:08 PM PDT 24
Peak memory 248864 kb
Host smart-b88443a2-d664-4b0f-a262-420f9077485d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1409859658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.1409859658
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.2909962265
Short name T83
Test name
Test status
Simulation time 2498500098 ps
CPU time 18.41 seconds
Started Aug 14 04:47:47 PM PDT 24
Finished Aug 14 04:48:06 PM PDT 24
Peak memory 256320 kb
Host smart-9091edfb-2222-4a60-9daf-dfa7561f0b2c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29099
62265 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.2909962265
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.4227525609
Short name T613
Test name
Test status
Simulation time 481519780 ps
CPU time 9.32 seconds
Started Aug 14 04:47:49 PM PDT 24
Finished Aug 14 04:47:58 PM PDT 24
Peak memory 254000 kb
Host smart-bb6d01aa-a2dd-43fd-86a4-250e271d9321
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42275
25609 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.4227525609
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.728107726
Short name T246
Test name
Test status
Simulation time 306087003 ps
CPU time 28.31 seconds
Started Aug 14 04:47:59 PM PDT 24
Finished Aug 14 04:48:27 PM PDT 24
Peak memory 248748 kb
Host smart-5b186a4e-b390-438f-b999-e27494223b01
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72810
7726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.728107726
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.4070548877
Short name T128
Test name
Test status
Simulation time 2204053045 ps
CPU time 30.81 seconds
Started Aug 14 04:47:50 PM PDT 24
Finished Aug 14 04:48:21 PM PDT 24
Peak memory 256964 kb
Host smart-3a5b1178-fc64-49e0-96ed-f91d60631229
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40705
48877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.4070548877
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all.253700217
Short name T695
Test name
Test status
Simulation time 153971209665 ps
CPU time 1343.9 seconds
Started Aug 14 04:47:49 PM PDT 24
Finished Aug 14 05:10:13 PM PDT 24
Peak memory 268308 kb
Host smart-1e1c09b1-d34d-4f9f-a71f-a5ea60ef6aae
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=253700217 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_han
dler_stress_all.253700217
Directory /workspace/31.alert_handler_stress_all/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.896075738
Short name T548
Test name
Test status
Simulation time 64476176198 ps
CPU time 1103.56 seconds
Started Aug 14 04:47:54 PM PDT 24
Finished Aug 14 05:06:18 PM PDT 24
Peak memory 273304 kb
Host smart-30effa8a-400f-4a46-854d-e70e3d4e89d7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=896075738 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.896075738
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.385835121
Short name T610
Test name
Test status
Simulation time 11603592667 ps
CPU time 105.49 seconds
Started Aug 14 04:48:03 PM PDT 24
Finished Aug 14 04:49:48 PM PDT 24
Peak memory 256500 kb
Host smart-4c0d1bbd-6803-47bd-8527-7105d23d9aa4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38583
5121 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.385835121
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.877320629
Short name T377
Test name
Test status
Simulation time 60192691 ps
CPU time 4.62 seconds
Started Aug 14 04:47:47 PM PDT 24
Finished Aug 14 04:47:52 PM PDT 24
Peak memory 240208 kb
Host smart-37cb9d11-6599-4482-9fe5-538c54f83ea6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87732
0629 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.877320629
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.1650776676
Short name T45
Test name
Test status
Simulation time 16231209051 ps
CPU time 1412.28 seconds
Started Aug 14 04:47:51 PM PDT 24
Finished Aug 14 05:11:24 PM PDT 24
Peak memory 289844 kb
Host smart-c3df84d6-cdf8-4ce1-95f5-f20da3c6ec78
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1650776676 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.1650776676
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.2642767238
Short name T433
Test name
Test status
Simulation time 18244219757 ps
CPU time 1169.43 seconds
Started Aug 14 04:47:52 PM PDT 24
Finished Aug 14 05:07:22 PM PDT 24
Peak memory 287440 kb
Host smart-c2241554-4e55-4ae3-853a-0864a3b85b8c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2642767238 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.2642767238
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.1504668128
Short name T707
Test name
Test status
Simulation time 44768087 ps
CPU time 4.3 seconds
Started Aug 14 04:48:05 PM PDT 24
Finished Aug 14 04:48:10 PM PDT 24
Peak memory 251088 kb
Host smart-09dc6a6d-7d9b-45db-b8cb-4abd4fda1987
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15046
68128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.1504668128
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.1776546628
Short name T490
Test name
Test status
Simulation time 106911453 ps
CPU time 10.36 seconds
Started Aug 14 04:47:51 PM PDT 24
Finished Aug 14 04:48:02 PM PDT 24
Peak memory 248312 kb
Host smart-d0f515d9-d827-4efb-beb5-141496c7e732
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17765
46628 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.1776546628
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.1439565705
Short name T225
Test name
Test status
Simulation time 872141457 ps
CPU time 32.41 seconds
Started Aug 14 04:47:52 PM PDT 24
Finished Aug 14 04:48:25 PM PDT 24
Peak memory 248300 kb
Host smart-832278de-c5b5-4f8c-9eb3-51dbf15da0c1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14395
65705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.1439565705
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.1456223955
Short name T458
Test name
Test status
Simulation time 122794781 ps
CPU time 4.78 seconds
Started Aug 14 04:48:02 PM PDT 24
Finished Aug 14 04:48:06 PM PDT 24
Peak memory 251636 kb
Host smart-ba84ee8d-49ba-4480-940f-8f147246cb8e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14562
23955 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.1456223955
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.2085727191
Short name T545
Test name
Test status
Simulation time 83777333731 ps
CPU time 1019.81 seconds
Started Aug 14 04:48:01 PM PDT 24
Finished Aug 14 05:05:01 PM PDT 24
Peak memory 285296 kb
Host smart-27f34cc5-3ab3-4933-92ee-7e6a829e2613
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2085727191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.2085727191
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.1873582878
Short name T536
Test name
Test status
Simulation time 1699495889 ps
CPU time 96.48 seconds
Started Aug 14 04:48:09 PM PDT 24
Finished Aug 14 04:49:46 PM PDT 24
Peak memory 256468 kb
Host smart-97202fd7-8623-40c5-9e40-cdc861066de3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18735
82878 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.1873582878
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.3116077931
Short name T576
Test name
Test status
Simulation time 3689639047 ps
CPU time 46.54 seconds
Started Aug 14 04:47:49 PM PDT 24
Finished Aug 14 04:48:35 PM PDT 24
Peak memory 248952 kb
Host smart-f897a068-ee11-45c5-842d-3b26a144b8ea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31160
77931 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.3116077931
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.2684919724
Short name T506
Test name
Test status
Simulation time 50470994613 ps
CPU time 1147.18 seconds
Started Aug 14 04:47:52 PM PDT 24
Finished Aug 14 05:06:59 PM PDT 24
Peak memory 273484 kb
Host smart-8a8e25cb-a5cf-4676-b57d-fa06b23595a5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2684919724 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.2684919724
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.2680426007
Short name T449
Test name
Test status
Simulation time 140323626149 ps
CPU time 2274.44 seconds
Started Aug 14 04:47:48 PM PDT 24
Finished Aug 14 05:25:43 PM PDT 24
Peak memory 273180 kb
Host smart-32c2a38a-aa61-4b3a-96cc-801e0ac20f87
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2680426007 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.2680426007
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.3444961921
Short name T274
Test name
Test status
Simulation time 6607612302 ps
CPU time 257.34 seconds
Started Aug 14 04:47:58 PM PDT 24
Finished Aug 14 04:52:15 PM PDT 24
Peak memory 248736 kb
Host smart-57dd2b98-42da-4afd-94bb-5adfb69d386a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3444961921 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.3444961921
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.2456860089
Short name T674
Test name
Test status
Simulation time 5213278249 ps
CPU time 35.91 seconds
Started Aug 14 04:47:47 PM PDT 24
Finished Aug 14 04:48:23 PM PDT 24
Peak memory 256096 kb
Host smart-1809c1dc-c7bf-4e81-9114-7c02d6eeeb28
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24568
60089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.2456860089
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.2378674203
Short name T115
Test name
Test status
Simulation time 744602793 ps
CPU time 41.93 seconds
Started Aug 14 04:47:47 PM PDT 24
Finished Aug 14 04:48:29 PM PDT 24
Peak memory 256352 kb
Host smart-07ea7736-2162-4b9f-848b-8da2a3ea3c8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23786
74203 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.2378674203
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.3613575550
Short name T42
Test name
Test status
Simulation time 2099487487 ps
CPU time 63.97 seconds
Started Aug 14 04:47:48 PM PDT 24
Finished Aug 14 04:48:53 PM PDT 24
Peak memory 256088 kb
Host smart-d5b1ba15-7851-45ea-b816-92f98be2f213
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36135
75550 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.3613575550
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.1940009057
Short name T565
Test name
Test status
Simulation time 4325885188 ps
CPU time 64.99 seconds
Started Aug 14 04:47:47 PM PDT 24
Finished Aug 14 04:48:52 PM PDT 24
Peak memory 256132 kb
Host smart-06b48c2a-5609-47c8-ae31-7c6057654e35
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19400
09057 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.1940009057
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all_with_rand_reset.3542237630
Short name T61
Test name
Test status
Simulation time 2564515772 ps
CPU time 192.48 seconds
Started Aug 14 04:48:01 PM PDT 24
Finished Aug 14 04:51:14 PM PDT 24
Peak memory 265360 kb
Host smart-0a3d16c0-22c0-4984-af2d-e9455d83ceea
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3542237630 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.alert_handler_stress_all_with_rand_reset.3542237630
Directory /workspace/33.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.2870967988
Short name T650
Test name
Test status
Simulation time 154448271817 ps
CPU time 1637.73 seconds
Started Aug 14 04:48:03 PM PDT 24
Finished Aug 14 05:15:21 PM PDT 24
Peak memory 272916 kb
Host smart-a4416fe5-858d-4b51-84e4-b2c377f3ebf4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2870967988 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.2870967988
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.3066328484
Short name T466
Test name
Test status
Simulation time 3879853242 ps
CPU time 64.06 seconds
Started Aug 14 04:48:01 PM PDT 24
Finished Aug 14 04:49:06 PM PDT 24
Peak memory 256152 kb
Host smart-5c408c0b-4242-4145-b21a-b1856fb3c954
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30663
28484 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.3066328484
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.1460763599
Short name T388
Test name
Test status
Simulation time 177029066 ps
CPU time 12.08 seconds
Started Aug 14 04:47:52 PM PDT 24
Finished Aug 14 04:48:04 PM PDT 24
Peak memory 248784 kb
Host smart-6ab66123-b7a7-40e6-909a-eb38e3aef1ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14607
63599 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.1460763599
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.1476667619
Short name T346
Test name
Test status
Simulation time 8996203493 ps
CPU time 732.23 seconds
Started Aug 14 04:48:09 PM PDT 24
Finished Aug 14 05:00:21 PM PDT 24
Peak memory 273392 kb
Host smart-72be7645-15c6-4fbe-97e4-cb0bf6f2cd9c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1476667619 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.1476667619
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.2021569765
Short name T414
Test name
Test status
Simulation time 61516639600 ps
CPU time 1041.67 seconds
Started Aug 14 04:48:05 PM PDT 24
Finished Aug 14 05:05:27 PM PDT 24
Peak memory 272280 kb
Host smart-99447bfb-cfe2-4c8b-8d77-eb85c09d5b6e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2021569765 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.2021569765
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.3742579164
Short name T328
Test name
Test status
Simulation time 5430938310 ps
CPU time 214.05 seconds
Started Aug 14 04:47:50 PM PDT 24
Finished Aug 14 04:51:24 PM PDT 24
Peak memory 248864 kb
Host smart-daf1e534-b761-42e2-b25f-d28a5d2fd1db
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3742579164 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.3742579164
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.2610633992
Short name T126
Test name
Test status
Simulation time 382679576 ps
CPU time 13.67 seconds
Started Aug 14 04:48:02 PM PDT 24
Finished Aug 14 04:48:16 PM PDT 24
Peak memory 254668 kb
Host smart-c1ac5def-35ef-404e-8fe8-2f61b4f48236
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26106
33992 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.2610633992
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.4012768280
Short name T501
Test name
Test status
Simulation time 324604831 ps
CPU time 30.2 seconds
Started Aug 14 04:48:04 PM PDT 24
Finished Aug 14 04:48:35 PM PDT 24
Peak memory 256740 kb
Host smart-edd4478b-edf6-4e93-bf9b-fa60f17284a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40127
68280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.4012768280
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.1136036345
Short name T720
Test name
Test status
Simulation time 1619465780 ps
CPU time 27.73 seconds
Started Aug 14 04:47:58 PM PDT 24
Finished Aug 14 04:48:26 PM PDT 24
Peak memory 248092 kb
Host smart-8c77e31c-b574-442b-9412-672896036afd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11360
36345 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.1136036345
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.2003854694
Short name T296
Test name
Test status
Simulation time 1905534665 ps
CPU time 65.72 seconds
Started Aug 14 04:47:52 PM PDT 24
Finished Aug 14 04:48:58 PM PDT 24
Peak memory 248784 kb
Host smart-7ca118ac-745b-4242-8916-2c23e2f5540e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20038
54694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.2003854694
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.3013576356
Short name T255
Test name
Test status
Simulation time 270813392017 ps
CPU time 1355.65 seconds
Started Aug 14 04:47:52 PM PDT 24
Finished Aug 14 05:10:28 PM PDT 24
Peak memory 289576 kb
Host smart-267f39db-8d9b-451b-b5ca-5f0dbf0b3423
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3013576356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_ha
ndler_stress_all.3013576356
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.2168101411
Short name T46
Test name
Test status
Simulation time 90384879171 ps
CPU time 1363.74 seconds
Started Aug 14 04:47:54 PM PDT 24
Finished Aug 14 05:10:38 PM PDT 24
Peak memory 273360 kb
Host smart-2336de33-fb9c-41f2-ace9-2b550c3974e7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2168101411 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.2168101411
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.4227024806
Short name T424
Test name
Test status
Simulation time 1040569074 ps
CPU time 43.49 seconds
Started Aug 14 04:47:48 PM PDT 24
Finished Aug 14 04:48:32 PM PDT 24
Peak memory 257008 kb
Host smart-37f80ec4-f38e-440e-92da-89ea2faa471a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42270
24806 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.4227024806
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.1981020290
Short name T701
Test name
Test status
Simulation time 675271790 ps
CPU time 42.85 seconds
Started Aug 14 04:48:06 PM PDT 24
Finished Aug 14 04:48:49 PM PDT 24
Peak memory 257036 kb
Host smart-c4c8e86d-3026-4f53-87e1-0e3570134b61
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19810
20290 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.1981020290
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.2379497013
Short name T426
Test name
Test status
Simulation time 57925605360 ps
CPU time 1172.97 seconds
Started Aug 14 04:47:55 PM PDT 24
Finished Aug 14 05:07:28 PM PDT 24
Peak memory 272740 kb
Host smart-4127c25c-3ca8-40c4-bfa7-200bcdaf2f09
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379497013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.2379497013
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.4015724473
Short name T326
Test name
Test status
Simulation time 12093391961 ps
CPU time 505.62 seconds
Started Aug 14 04:48:06 PM PDT 24
Finished Aug 14 04:56:32 PM PDT 24
Peak memory 255356 kb
Host smart-04b0e2f2-54da-410a-b083-796d3b9f7c62
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4015724473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.4015724473
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.923455646
Short name T694
Test name
Test status
Simulation time 3221036993 ps
CPU time 47.21 seconds
Started Aug 14 04:47:50 PM PDT 24
Finished Aug 14 04:48:37 PM PDT 24
Peak memory 256560 kb
Host smart-c8cc29a5-2944-45aa-9995-dd8a18232f64
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92345
5646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.923455646
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.1164166115
Short name T390
Test name
Test status
Simulation time 427299017 ps
CPU time 7.11 seconds
Started Aug 14 04:47:47 PM PDT 24
Finished Aug 14 04:47:54 PM PDT 24
Peak memory 251696 kb
Host smart-f61e4d29-afd2-4227-961e-cb4ad9b55aee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11641
66115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.1164166115
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.530426174
Short name T597
Test name
Test status
Simulation time 998338622 ps
CPU time 9.04 seconds
Started Aug 14 04:48:17 PM PDT 24
Finished Aug 14 04:48:27 PM PDT 24
Peak memory 256496 kb
Host smart-50b829e2-e2b8-4a7f-8068-7bd3336e3d00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53042
6174 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.530426174
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.2193213799
Short name T626
Test name
Test status
Simulation time 745027349 ps
CPU time 47.32 seconds
Started Aug 14 04:48:07 PM PDT 24
Finished Aug 14 04:48:55 PM PDT 24
Peak memory 255920 kb
Host smart-d8ac2651-1dc4-43a9-812a-c5d755690fa6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21932
13799 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.2193213799
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.3503471830
Short name T252
Test name
Test status
Simulation time 3895685044 ps
CPU time 176.32 seconds
Started Aug 14 04:47:49 PM PDT 24
Finished Aug 14 04:50:45 PM PDT 24
Peak memory 256960 kb
Host smart-6189d29f-5857-4bac-904e-b9fba90c9520
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3503471830 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_ha
ndler_stress_all.3503471830
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.2481282924
Short name T601
Test name
Test status
Simulation time 23735758281 ps
CPU time 1377 seconds
Started Aug 14 04:47:51 PM PDT 24
Finished Aug 14 05:10:48 PM PDT 24
Peak memory 273296 kb
Host smart-bfc69bd8-ddd5-4b99-be4e-4da562ad668e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2481282924 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.2481282924
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.2659652327
Short name T440
Test name
Test status
Simulation time 1463789830 ps
CPU time 27.24 seconds
Started Aug 14 04:47:52 PM PDT 24
Finished Aug 14 04:48:19 PM PDT 24
Peak memory 256272 kb
Host smart-3b2201d5-de07-4cdb-8a1f-637ca038064a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26596
52327 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.2659652327
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.3899485191
Short name T428
Test name
Test status
Simulation time 70804618 ps
CPU time 9.61 seconds
Started Aug 14 04:48:13 PM PDT 24
Finished Aug 14 04:48:23 PM PDT 24
Peak memory 248396 kb
Host smart-10f94507-e469-4407-b265-8b2c4a3fa5d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38994
85191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.3899485191
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.4092769801
Short name T337
Test name
Test status
Simulation time 29381609832 ps
CPU time 1577.93 seconds
Started Aug 14 04:47:52 PM PDT 24
Finished Aug 14 05:14:10 PM PDT 24
Peak memory 282176 kb
Host smart-856b4d64-b6d5-446a-9e10-f905c6305b7f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4092769801 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.4092769801
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.856055146
Short name T127
Test name
Test status
Simulation time 11575625725 ps
CPU time 970.06 seconds
Started Aug 14 04:47:53 PM PDT 24
Finished Aug 14 05:04:03 PM PDT 24
Peak memory 273664 kb
Host smart-ef02d012-5f43-4b53-8668-d03ecfa20162
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=856055146 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.856055146
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.3018023808
Short name T310
Test name
Test status
Simulation time 11357325661 ps
CPU time 434.15 seconds
Started Aug 14 04:47:52 PM PDT 24
Finished Aug 14 04:55:07 PM PDT 24
Peak memory 248724 kb
Host smart-08f19128-d909-427c-b36f-c01e012e5469
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3018023808 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.3018023808
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.957669235
Short name T529
Test name
Test status
Simulation time 139919602 ps
CPU time 8.51 seconds
Started Aug 14 04:47:53 PM PDT 24
Finished Aug 14 04:48:01 PM PDT 24
Peak memory 254816 kb
Host smart-1b9a3a58-553e-44f2-9c97-8966fae5adc6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95766
9235 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.957669235
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.3902340042
Short name T129
Test name
Test status
Simulation time 266313495 ps
CPU time 24.85 seconds
Started Aug 14 04:48:01 PM PDT 24
Finished Aug 14 04:48:25 PM PDT 24
Peak memory 248284 kb
Host smart-c865993e-c5df-498f-a8ad-10a93f9604aa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39023
40042 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.3902340042
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.1257761231
Short name T462
Test name
Test status
Simulation time 1000951923 ps
CPU time 32.49 seconds
Started Aug 14 04:47:51 PM PDT 24
Finished Aug 14 04:48:23 PM PDT 24
Peak memory 256496 kb
Host smart-e0cebf8f-be12-4d70-ba02-93c2a665d44a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12577
61231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.1257761231
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.2043160380
Short name T559
Test name
Test status
Simulation time 800834729 ps
CPU time 28.43 seconds
Started Aug 14 04:47:53 PM PDT 24
Finished Aug 14 04:48:21 PM PDT 24
Peak memory 256952 kb
Host smart-140ea496-79f1-4e17-94a9-f900f96826b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20431
60380 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.2043160380
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.1761465705
Short name T59
Test name
Test status
Simulation time 56468732188 ps
CPU time 1804.43 seconds
Started Aug 14 04:47:52 PM PDT 24
Finished Aug 14 05:17:56 PM PDT 24
Peak memory 285192 kb
Host smart-8d101d95-4730-44c1-ac50-f03c6dd09b7c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1761465705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_ha
ndler_stress_all.1761465705
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.782362805
Short name T408
Test name
Test status
Simulation time 61680532885 ps
CPU time 1318.22 seconds
Started Aug 14 04:47:50 PM PDT 24
Finished Aug 14 05:09:48 PM PDT 24
Peak memory 289576 kb
Host smart-e98bfead-e9d3-4625-80b2-43a0e0c0f420
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=782362805 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.782362805
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.4033663522
Short name T474
Test name
Test status
Simulation time 19780967263 ps
CPU time 132.44 seconds
Started Aug 14 04:48:05 PM PDT 24
Finished Aug 14 04:50:17 PM PDT 24
Peak memory 256232 kb
Host smart-f2de1219-cb37-40b2-89fb-1184e3780977
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40336
63522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.4033663522
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.1913726656
Short name T99
Test name
Test status
Simulation time 925917051 ps
CPU time 15.6 seconds
Started Aug 14 04:48:08 PM PDT 24
Finished Aug 14 04:48:24 PM PDT 24
Peak memory 255248 kb
Host smart-90863269-6e23-4842-a5bc-9fe0e7dbe83a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19137
26656 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.1913726656
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.4131936254
Short name T314
Test name
Test status
Simulation time 37762154462 ps
CPU time 2155.01 seconds
Started Aug 14 04:47:51 PM PDT 24
Finished Aug 14 05:23:46 PM PDT 24
Peak memory 288916 kb
Host smart-b6a1cfaf-074e-49fb-a2b1-208d85d20d49
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4131936254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.4131936254
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.2465546873
Short name T618
Test name
Test status
Simulation time 155918712141 ps
CPU time 2043.62 seconds
Started Aug 14 04:48:06 PM PDT 24
Finished Aug 14 05:22:10 PM PDT 24
Peak memory 287672 kb
Host smart-0bfd2ad6-63d6-4f3d-ad26-7fa93c567cb3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2465546873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.2465546873
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.2254326166
Short name T304
Test name
Test status
Simulation time 26718457408 ps
CPU time 547.86 seconds
Started Aug 14 04:47:53 PM PDT 24
Finished Aug 14 04:57:01 PM PDT 24
Peak memory 248888 kb
Host smart-afbe207e-91de-4a68-aff5-183864a015a9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2254326166 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.2254326166
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.2466672814
Short name T468
Test name
Test status
Simulation time 1538101727 ps
CPU time 18.01 seconds
Started Aug 14 04:48:03 PM PDT 24
Finished Aug 14 04:48:21 PM PDT 24
Peak memory 248772 kb
Host smart-520e8d75-a9e7-4949-a3fe-b3d8afe872b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24666
72814 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.2466672814
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.1114701651
Short name T539
Test name
Test status
Simulation time 245385950 ps
CPU time 6.1 seconds
Started Aug 14 04:47:52 PM PDT 24
Finished Aug 14 04:47:58 PM PDT 24
Peak memory 240084 kb
Host smart-efc01c7d-e509-46aa-985d-be2bdd9d8c52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11147
01651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.1114701651
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.2427254402
Short name T611
Test name
Test status
Simulation time 12507125541 ps
CPU time 55.71 seconds
Started Aug 14 04:48:06 PM PDT 24
Finished Aug 14 04:49:01 PM PDT 24
Peak memory 248736 kb
Host smart-8252c66c-199c-42fb-bdbf-613c981832e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24272
54402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.2427254402
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.418263193
Short name T505
Test name
Test status
Simulation time 547456055 ps
CPU time 11.35 seconds
Started Aug 14 04:47:52 PM PDT 24
Finished Aug 14 04:48:03 PM PDT 24
Peak memory 253752 kb
Host smart-f51f621b-69cf-4309-9a84-9f0765fa0374
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41826
3193 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.418263193
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.2400218158
Short name T121
Test name
Test status
Simulation time 11274751124 ps
CPU time 788.88 seconds
Started Aug 14 04:48:10 PM PDT 24
Finished Aug 14 05:01:19 PM PDT 24
Peak memory 273204 kb
Host smart-077a352c-9bb7-4e1a-b352-834c3e039afc
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2400218158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_ha
ndler_stress_all.2400218158
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.4003557859
Short name T709
Test name
Test status
Simulation time 1475778652 ps
CPU time 92.29 seconds
Started Aug 14 04:47:52 PM PDT 24
Finished Aug 14 04:49:25 PM PDT 24
Peak memory 249752 kb
Host smart-14802192-0a5d-4664-b62c-0b4b1f7a5761
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40035
57859 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.4003557859
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.464946254
Short name T704
Test name
Test status
Simulation time 2907919588 ps
CPU time 49.93 seconds
Started Aug 14 04:47:49 PM PDT 24
Finished Aug 14 04:48:39 PM PDT 24
Peak memory 248852 kb
Host smart-1a396439-be29-48ad-b682-1dafea4389a6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46494
6254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.464946254
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.2105780419
Short name T489
Test name
Test status
Simulation time 66093395700 ps
CPU time 1128.6 seconds
Started Aug 14 04:47:55 PM PDT 24
Finished Aug 14 05:06:44 PM PDT 24
Peak memory 273432 kb
Host smart-95a54b9c-a403-4b7c-928c-15267dc91fb8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2105780419 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.2105780419
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.2236003557
Short name T385
Test name
Test status
Simulation time 36712181792 ps
CPU time 2098.79 seconds
Started Aug 14 04:48:10 PM PDT 24
Finished Aug 14 05:23:09 PM PDT 24
Peak memory 283412 kb
Host smart-f4169711-90f4-4442-8d4f-ea7a9c440509
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2236003557 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.2236003557
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.2606791088
Short name T40
Test name
Test status
Simulation time 20119111757 ps
CPU time 226.37 seconds
Started Aug 14 04:48:18 PM PDT 24
Finished Aug 14 04:52:05 PM PDT 24
Peak memory 255516 kb
Host smart-ae32b24f-f2dd-4500-89c7-3674bc829df8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2606791088 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.2606791088
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.1807485481
Short name T531
Test name
Test status
Simulation time 560572696 ps
CPU time 13.82 seconds
Started Aug 14 04:48:01 PM PDT 24
Finished Aug 14 04:48:15 PM PDT 24
Peak memory 255224 kb
Host smart-c464ee81-42e3-412d-a02b-d817fc210738
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18074
85481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.1807485481
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.2297312549
Short name T554
Test name
Test status
Simulation time 145839604 ps
CPU time 6.13 seconds
Started Aug 14 04:48:02 PM PDT 24
Finished Aug 14 04:48:08 PM PDT 24
Peak memory 248468 kb
Host smart-2e134d26-62e7-4110-a2b2-632bb257abd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22973
12549 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.2297312549
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.1975451051
Short name T109
Test name
Test status
Simulation time 619872943 ps
CPU time 42.66 seconds
Started Aug 14 04:47:49 PM PDT 24
Finished Aug 14 04:48:32 PM PDT 24
Peak memory 256464 kb
Host smart-df7b6a87-372b-4235-9cac-cbbc0fb9d216
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19754
51051 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.1975451051
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.565671849
Short name T683
Test name
Test status
Simulation time 71080804 ps
CPU time 3.58 seconds
Started Aug 14 04:48:05 PM PDT 24
Finished Aug 14 04:48:09 PM PDT 24
Peak memory 250972 kb
Host smart-251216b6-247b-41fb-972d-ce1da3253bf5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56567
1849 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.565671849
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.2282876683
Short name T569
Test name
Test status
Simulation time 6244422352 ps
CPU time 668.59 seconds
Started Aug 14 04:48:01 PM PDT 24
Finished Aug 14 04:59:10 PM PDT 24
Peak memory 272696 kb
Host smart-de81405e-8a96-4bdf-a55a-99d8c1044ffb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2282876683 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.2282876683
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.2471884352
Short name T523
Test name
Test status
Simulation time 12688565349 ps
CPU time 177.44 seconds
Started Aug 14 04:47:56 PM PDT 24
Finished Aug 14 04:50:53 PM PDT 24
Peak memory 250904 kb
Host smart-2a8b8c57-147a-4283-b5e7-7e2e84a609d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24718
84352 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.2471884352
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.2190099778
Short name T496
Test name
Test status
Simulation time 1629455763 ps
CPU time 51.8 seconds
Started Aug 14 04:47:52 PM PDT 24
Finished Aug 14 04:48:44 PM PDT 24
Peak memory 248788 kb
Host smart-ee139a5a-c0ce-461d-b6e4-527af511446c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21900
99778 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.2190099778
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.2981668260
Short name T696
Test name
Test status
Simulation time 17440379867 ps
CPU time 970.05 seconds
Started Aug 14 04:48:05 PM PDT 24
Finished Aug 14 05:04:15 PM PDT 24
Peak memory 272852 kb
Host smart-b5037223-5754-4c4b-a492-5db6c6b06707
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2981668260 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.2981668260
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.4116191372
Short name T581
Test name
Test status
Simulation time 45248427118 ps
CPU time 1334.76 seconds
Started Aug 14 04:47:57 PM PDT 24
Finished Aug 14 05:10:12 PM PDT 24
Peak memory 272332 kb
Host smart-00f7cd33-c51c-4190-a8e3-0d655037aeab
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4116191372 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.4116191372
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.1405110283
Short name T316
Test name
Test status
Simulation time 7430461322 ps
CPU time 79.56 seconds
Started Aug 14 04:47:55 PM PDT 24
Finished Aug 14 04:49:14 PM PDT 24
Peak memory 248796 kb
Host smart-2e01b10a-3a92-4c4e-8e79-e6da515ce874
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1405110283 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.1405110283
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.3432734945
Short name T567
Test name
Test status
Simulation time 418270373 ps
CPU time 36.5 seconds
Started Aug 14 04:47:53 PM PDT 24
Finished Aug 14 04:48:30 PM PDT 24
Peak memory 257004 kb
Host smart-2fff8d66-0943-4097-8b02-776256308c7f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34327
34945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.3432734945
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.2859563202
Short name T22
Test name
Test status
Simulation time 1139400146 ps
CPU time 70.36 seconds
Started Aug 14 04:47:54 PM PDT 24
Finished Aug 14 04:49:05 PM PDT 24
Peak memory 248644 kb
Host smart-61f49a66-d6af-4dab-a96e-13aaad8d9e94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28595
63202 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.2859563202
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.2790979389
Short name T659
Test name
Test status
Simulation time 862480058 ps
CPU time 33.77 seconds
Started Aug 14 04:47:56 PM PDT 24
Finished Aug 14 04:48:29 PM PDT 24
Peak memory 255768 kb
Host smart-fbe6ef3b-c4c3-420a-9976-2e52692dcc4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27909
79389 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.2790979389
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.592417985
Short name T668
Test name
Test status
Simulation time 879137253 ps
CPU time 46.53 seconds
Started Aug 14 04:47:51 PM PDT 24
Finished Aug 14 04:48:37 PM PDT 24
Peak memory 248700 kb
Host smart-548cf1e5-ef4e-42f0-8c4e-301ed4e22186
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59241
7985 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.592417985
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.4101398085
Short name T404
Test name
Test status
Simulation time 16765545891 ps
CPU time 254.65 seconds
Started Aug 14 04:47:53 PM PDT 24
Finished Aug 14 04:52:08 PM PDT 24
Peak memory 257140 kb
Host smart-71253301-83d1-4967-96ad-0436009cf074
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101398085 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_ha
ndler_stress_all.4101398085
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.3363834691
Short name T221
Test name
Test status
Simulation time 127374445 ps
CPU time 3.53 seconds
Started Aug 14 04:47:03 PM PDT 24
Finished Aug 14 04:47:07 PM PDT 24
Peak memory 248916 kb
Host smart-6ff1b0e8-da57-4efa-9123-c144f9a9dfa1
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3363834691 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.3363834691
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.722241850
Short name T43
Test name
Test status
Simulation time 56628491747 ps
CPU time 1205.82 seconds
Started Aug 14 04:47:01 PM PDT 24
Finished Aug 14 05:07:07 PM PDT 24
Peak memory 285452 kb
Host smart-b4676811-707e-48e7-bf6a-03b307d6d066
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=722241850 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.722241850
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.287744792
Short name T427
Test name
Test status
Simulation time 1093642436 ps
CPU time 26.23 seconds
Started Aug 14 04:47:07 PM PDT 24
Finished Aug 14 04:47:33 PM PDT 24
Peak memory 248764 kb
Host smart-fc993a06-2a8b-4cca-9ad5-e88616e2fde7
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=287744792 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.287744792
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.771040696
Short name T484
Test name
Test status
Simulation time 10153363304 ps
CPU time 148.36 seconds
Started Aug 14 04:47:07 PM PDT 24
Finished Aug 14 04:49:36 PM PDT 24
Peak memory 256380 kb
Host smart-d7098258-0f74-46d2-bb63-f4798a7ae49f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77104
0696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.771040696
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.3592950590
Short name T607
Test name
Test status
Simulation time 2002856920 ps
CPU time 32.02 seconds
Started Aug 14 04:47:05 PM PDT 24
Finished Aug 14 04:47:37 PM PDT 24
Peak memory 256584 kb
Host smart-560551b4-7b20-44fd-a113-580c073b561c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35929
50590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.3592950590
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.2957706244
Short name T278
Test name
Test status
Simulation time 14089735813 ps
CPU time 1323.34 seconds
Started Aug 14 04:47:02 PM PDT 24
Finished Aug 14 05:09:06 PM PDT 24
Peak memory 289836 kb
Host smart-9809e7bb-fa06-4489-bac9-1ac479f835c6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2957706244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.2957706244
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.1080131213
Short name T240
Test name
Test status
Simulation time 5316423468 ps
CPU time 118.17 seconds
Started Aug 14 04:47:01 PM PDT 24
Finished Aug 14 04:48:59 PM PDT 24
Peak memory 248596 kb
Host smart-a3c5e252-a833-47a0-9fd0-bd56c34f200e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1080131213 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.1080131213
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.907863563
Short name T64
Test name
Test status
Simulation time 565154836 ps
CPU time 29.53 seconds
Started Aug 14 04:47:12 PM PDT 24
Finished Aug 14 04:47:41 PM PDT 24
Peak memory 248772 kb
Host smart-bbf735ea-b02b-4bd5-81f6-976c599e3fbc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90786
3563 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.907863563
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.616105145
Short name T406
Test name
Test status
Simulation time 18867673921 ps
CPU time 68.3 seconds
Started Aug 14 04:47:19 PM PDT 24
Finished Aug 14 04:48:27 PM PDT 24
Peak memory 255916 kb
Host smart-eb018ae8-a02f-419e-b169-cc65cb2d25a4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61610
5145 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.616105145
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.3624932447
Short name T7
Test name
Test status
Simulation time 1920794200 ps
CPU time 26.21 seconds
Started Aug 14 04:47:02 PM PDT 24
Finished Aug 14 04:47:28 PM PDT 24
Peak memory 270828 kb
Host smart-e741ea7c-43eb-4894-8f95-90a77ae224bf
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3624932447 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.3624932447
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.950975098
Short name T260
Test name
Test status
Simulation time 458849427 ps
CPU time 15.89 seconds
Started Aug 14 04:47:03 PM PDT 24
Finished Aug 14 04:47:19 PM PDT 24
Peak memory 255124 kb
Host smart-5cc78bc1-eee6-425f-a4e4-092f3138aa34
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=95097
5098 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.950975098
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.3170037355
Short name T2
Test name
Test status
Simulation time 445001834 ps
CPU time 32.54 seconds
Started Aug 14 04:46:58 PM PDT 24
Finished Aug 14 04:47:31 PM PDT 24
Peak memory 248792 kb
Host smart-0e0974d1-8842-48c6-bd5f-5bfa5e0d2eb9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31700
37355 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.3170037355
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.2477095921
Short name T665
Test name
Test status
Simulation time 10519134232 ps
CPU time 953.03 seconds
Started Aug 14 04:47:32 PM PDT 24
Finished Aug 14 05:03:25 PM PDT 24
Peak memory 273432 kb
Host smart-e5f1875c-b137-4ea2-870f-bba4f09020ee
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2477095921 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_han
dler_stress_all.2477095921
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.3228896994
Short name T17
Test name
Test status
Simulation time 63368500837 ps
CPU time 1673.01 seconds
Started Aug 14 04:47:55 PM PDT 24
Finished Aug 14 05:15:49 PM PDT 24
Peak memory 273344 kb
Host smart-2267faf0-50d5-4f84-a2e9-272d524d43eb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3228896994 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.3228896994
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.2718116779
Short name T637
Test name
Test status
Simulation time 10823267737 ps
CPU time 147.92 seconds
Started Aug 14 04:48:08 PM PDT 24
Finished Aug 14 04:50:36 PM PDT 24
Peak memory 256600 kb
Host smart-05e67015-3692-4c84-b94f-da64ee43c1ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27181
16779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.2718116779
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.1006367779
Short name T389
Test name
Test status
Simulation time 163743282 ps
CPU time 10.94 seconds
Started Aug 14 04:47:58 PM PDT 24
Finished Aug 14 04:48:09 PM PDT 24
Peak memory 248388 kb
Host smart-39865b2b-60eb-439e-9612-c145735e5738
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10063
67779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.1006367779
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.4141291039
Short name T681
Test name
Test status
Simulation time 55182271855 ps
CPU time 3113.86 seconds
Started Aug 14 04:48:08 PM PDT 24
Finished Aug 14 05:40:03 PM PDT 24
Peak memory 289812 kb
Host smart-2c1e8e7a-2256-4c20-8a7b-550c1ade1cc2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4141291039 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.4141291039
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.2196526659
Short name T330
Test name
Test status
Simulation time 5881954157 ps
CPU time 114.34 seconds
Started Aug 14 04:47:53 PM PDT 24
Finished Aug 14 04:49:47 PM PDT 24
Peak memory 248880 kb
Host smart-bdf1d89f-4b8c-49c7-be35-ff609ceb34cb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2196526659 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.2196526659
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.1445552470
Short name T621
Test name
Test status
Simulation time 658626903 ps
CPU time 29.79 seconds
Started Aug 14 04:48:08 PM PDT 24
Finished Aug 14 04:48:38 PM PDT 24
Peak memory 256392 kb
Host smart-b0c0df7d-61d7-4b52-a422-03f993204dff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14455
52470 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.1445552470
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.625458740
Short name T453
Test name
Test status
Simulation time 180693943 ps
CPU time 11.84 seconds
Started Aug 14 04:48:11 PM PDT 24
Finished Aug 14 04:48:23 PM PDT 24
Peak memory 253920 kb
Host smart-86484157-f98f-43c1-bab6-e812e3a30f63
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=62545
8740 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.625458740
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.4262977445
Short name T500
Test name
Test status
Simulation time 1189612778 ps
CPU time 34.66 seconds
Started Aug 14 04:47:52 PM PDT 24
Finished Aug 14 04:48:27 PM PDT 24
Peak memory 256040 kb
Host smart-97807802-8976-425d-a500-a203932a73f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42629
77445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.4262977445
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.3120572001
Short name T582
Test name
Test status
Simulation time 104756861483 ps
CPU time 2255 seconds
Started Aug 14 04:48:13 PM PDT 24
Finished Aug 14 05:25:49 PM PDT 24
Peak memory 289136 kb
Host smart-3d6c5609-c90a-4048-8e57-c3a616f764f5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3120572001 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_ha
ndler_stress_all.3120572001
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.2005997993
Short name T596
Test name
Test status
Simulation time 49541572882 ps
CPU time 1345.49 seconds
Started Aug 14 04:48:11 PM PDT 24
Finished Aug 14 05:10:37 PM PDT 24
Peak memory 289320 kb
Host smart-9e84bdab-8e94-4aba-833e-ec80f8a13c72
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2005997993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.2005997993
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.2910182408
Short name T446
Test name
Test status
Simulation time 1944794355 ps
CPU time 151.56 seconds
Started Aug 14 04:48:01 PM PDT 24
Finished Aug 14 04:50:33 PM PDT 24
Peak memory 251924 kb
Host smart-db59270a-b9b2-4852-bf7e-5b8685a9fb68
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29101
82408 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.2910182408
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.583503696
Short name T86
Test name
Test status
Simulation time 554334376 ps
CPU time 8.46 seconds
Started Aug 14 04:48:02 PM PDT 24
Finished Aug 14 04:48:11 PM PDT 24
Peak memory 248404 kb
Host smart-f75951b4-d870-4514-9c84-47c0b9d055d3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58350
3696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.583503696
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.4138325880
Short name T320
Test name
Test status
Simulation time 77693118358 ps
CPU time 1441.15 seconds
Started Aug 14 04:47:54 PM PDT 24
Finished Aug 14 05:11:55 PM PDT 24
Peak memory 272412 kb
Host smart-d14c4dea-de1f-425d-8d58-ba3dec16d47e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4138325880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.4138325880
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.3859812886
Short name T649
Test name
Test status
Simulation time 24464235875 ps
CPU time 1619.65 seconds
Started Aug 14 04:48:04 PM PDT 24
Finished Aug 14 05:15:04 PM PDT 24
Peak memory 273204 kb
Host smart-3afe953f-2209-46e4-9a80-067c51f7ef19
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3859812886 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.3859812886
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.3531684441
Short name T230
Test name
Test status
Simulation time 21563428563 ps
CPU time 122.4 seconds
Started Aug 14 04:48:17 PM PDT 24
Finished Aug 14 04:50:20 PM PDT 24
Peak memory 248860 kb
Host smart-7b3be494-88f4-44ff-97ff-cff2a6922643
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3531684441 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.3531684441
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.4270155449
Short name T599
Test name
Test status
Simulation time 1656148208 ps
CPU time 21.13 seconds
Started Aug 14 04:48:10 PM PDT 24
Finished Aug 14 04:48:32 PM PDT 24
Peak memory 256400 kb
Host smart-21f04ce1-a78a-4e28-94a8-3744e37056ef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42701
55449 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.4270155449
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.3025122668
Short name T413
Test name
Test status
Simulation time 1099762387 ps
CPU time 26.46 seconds
Started Aug 14 04:48:06 PM PDT 24
Finished Aug 14 04:48:33 PM PDT 24
Peak memory 248288 kb
Host smart-43b247af-56e7-4438-a4ca-a9530d477ccf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30251
22668 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.3025122668
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.2251314810
Short name T367
Test name
Test status
Simulation time 70859856 ps
CPU time 5.39 seconds
Started Aug 14 04:48:01 PM PDT 24
Finished Aug 14 04:48:07 PM PDT 24
Peak memory 249324 kb
Host smart-4d8feb3d-54f0-4672-8cab-18ea7bfe3e93
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22513
14810 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.2251314810
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.2224371696
Short name T111
Test name
Test status
Simulation time 205431465 ps
CPU time 14.45 seconds
Started Aug 14 04:48:02 PM PDT 24
Finished Aug 14 04:48:17 PM PDT 24
Peak memory 255484 kb
Host smart-9d28475f-1a33-452e-bd99-f178857426f0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22243
71696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.2224371696
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.2320598775
Short name T261
Test name
Test status
Simulation time 24261083942 ps
CPU time 1506.76 seconds
Started Aug 14 04:48:07 PM PDT 24
Finished Aug 14 05:13:14 PM PDT 24
Peak memory 269460 kb
Host smart-a1abf8a5-ffe5-4048-949d-60eb5a885670
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2320598775 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_ha
ndler_stress_all.2320598775
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.3932452978
Short name T477
Test name
Test status
Simulation time 37762206654 ps
CPU time 1311.77 seconds
Started Aug 14 04:48:13 PM PDT 24
Finished Aug 14 05:10:05 PM PDT 24
Peak memory 287168 kb
Host smart-8d78d668-97df-45e7-b7c9-2f3dfc56e5bf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3932452978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.3932452978
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.379313400
Short name T609
Test name
Test status
Simulation time 5709654460 ps
CPU time 129.25 seconds
Started Aug 14 04:48:08 PM PDT 24
Finished Aug 14 04:50:17 PM PDT 24
Peak memory 250852 kb
Host smart-b62bd68c-ba2d-4c75-b5c8-254307ddf779
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37931
3400 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.379313400
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.3892195292
Short name T488
Test name
Test status
Simulation time 197087361 ps
CPU time 13.87 seconds
Started Aug 14 04:48:03 PM PDT 24
Finished Aug 14 04:48:17 PM PDT 24
Peak memory 248792 kb
Host smart-b6035d62-61ad-4fb9-b46e-c5dbcd40ee94
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38921
95292 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.3892195292
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.684929188
Short name T226
Test name
Test status
Simulation time 161120029460 ps
CPU time 1217.56 seconds
Started Aug 14 04:48:11 PM PDT 24
Finished Aug 14 05:08:29 PM PDT 24
Peak memory 284632 kb
Host smart-68235039-e123-4e03-9f4f-3b88048b61d5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=684929188 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.684929188
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.2839623697
Short name T692
Test name
Test status
Simulation time 38632156762 ps
CPU time 2159.46 seconds
Started Aug 14 04:48:02 PM PDT 24
Finished Aug 14 05:24:02 PM PDT 24
Peak memory 282704 kb
Host smart-b30bc73c-8abc-4b1e-a9dc-e475383380cf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2839623697 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.2839623697
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.1361905968
Short name T558
Test name
Test status
Simulation time 2304461637 ps
CPU time 86.46 seconds
Started Aug 14 04:48:08 PM PDT 24
Finished Aug 14 04:49:34 PM PDT 24
Peak memory 248916 kb
Host smart-377ac621-b236-4f89-8394-3d4cfdc9fe58
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1361905968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.1361905968
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.1527662600
Short name T417
Test name
Test status
Simulation time 524259362 ps
CPU time 29.06 seconds
Started Aug 14 04:48:02 PM PDT 24
Finished Aug 14 04:48:32 PM PDT 24
Peak memory 248784 kb
Host smart-0101eca5-c844-48ae-94f7-1b904eeb6ce3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15276
62600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.1527662600
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.3461321145
Short name T661
Test name
Test status
Simulation time 2119082110 ps
CPU time 32.1 seconds
Started Aug 14 04:48:18 PM PDT 24
Finished Aug 14 04:48:50 PM PDT 24
Peak memory 256480 kb
Host smart-242bcee8-bf1e-4835-b1ce-58ee32570ac1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34613
21145 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.3461321145
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.639985508
Short name T290
Test name
Test status
Simulation time 352899282 ps
CPU time 21.28 seconds
Started Aug 14 04:48:05 PM PDT 24
Finished Aug 14 04:48:26 PM PDT 24
Peak memory 248316 kb
Host smart-e5dab7a7-5ff6-44d8-beaf-7c0e10a74739
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63998
5508 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.639985508
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.2815658279
Short name T451
Test name
Test status
Simulation time 196460070 ps
CPU time 17.33 seconds
Started Aug 14 04:48:08 PM PDT 24
Finished Aug 14 04:48:25 PM PDT 24
Peak memory 248872 kb
Host smart-bd40a587-099e-4d4f-9da7-15f2a9dbd25e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28156
58279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.2815658279
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.3655204938
Short name T564
Test name
Test status
Simulation time 39243709215 ps
CPU time 2570.03 seconds
Started Aug 14 04:47:59 PM PDT 24
Finished Aug 14 05:30:49 PM PDT 24
Peak memory 289612 kb
Host smart-39f7ae39-464f-4ac6-a745-a860bc1de4f5
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3655204938 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_ha
ndler_stress_all.3655204938
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.1266744261
Short name T50
Test name
Test status
Simulation time 23799194990 ps
CPU time 1519.72 seconds
Started Aug 14 04:48:06 PM PDT 24
Finished Aug 14 05:13:26 PM PDT 24
Peak memory 282340 kb
Host smart-30f929b1-d0cc-4b06-971c-30a27a18c9e2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1266744261 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.1266744261
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.837834404
Short name T382
Test name
Test status
Simulation time 2104196240 ps
CPU time 94.57 seconds
Started Aug 14 04:48:08 PM PDT 24
Finished Aug 14 04:49:43 PM PDT 24
Peak memory 256556 kb
Host smart-f6971691-4cf4-4d3e-a5e0-c324ce6929d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=83783
4404 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.837834404
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.2337115235
Short name T526
Test name
Test status
Simulation time 805682666 ps
CPU time 23.19 seconds
Started Aug 14 04:48:02 PM PDT 24
Finished Aug 14 04:48:25 PM PDT 24
Peak memory 256908 kb
Host smart-ac241f7f-6f39-44fb-8a8f-973e77f64b58
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23371
15235 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.2337115235
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.2357833649
Short name T300
Test name
Test status
Simulation time 124210045667 ps
CPU time 1672.95 seconds
Started Aug 14 04:48:15 PM PDT 24
Finished Aug 14 05:16:08 PM PDT 24
Peak memory 272772 kb
Host smart-dadcbeb8-0f36-4152-a611-4515eab9b42f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2357833649 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.2357833649
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.227937540
Short name T617
Test name
Test status
Simulation time 43388527541 ps
CPU time 2673.5 seconds
Started Aug 14 04:48:05 PM PDT 24
Finished Aug 14 05:32:39 PM PDT 24
Peak memory 281588 kb
Host smart-d65e3744-bcc5-435e-ae96-ae67da45ce66
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=227937540 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.227937540
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.916581947
Short name T324
Test name
Test status
Simulation time 10208089708 ps
CPU time 426.97 seconds
Started Aug 14 04:48:01 PM PDT 24
Finished Aug 14 04:55:08 PM PDT 24
Peak memory 247712 kb
Host smart-aa3ebd77-44f7-4796-9bcd-41a8e5a39a29
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=916581947 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.916581947
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.2242873701
Short name T573
Test name
Test status
Simulation time 387174752 ps
CPU time 37.41 seconds
Started Aug 14 04:48:09 PM PDT 24
Finished Aug 14 04:48:46 PM PDT 24
Peak memory 256084 kb
Host smart-b1f0ae58-0426-47cf-8628-d3ffe7eebb11
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22428
73701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.2242873701
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.2397119069
Short name T91
Test name
Test status
Simulation time 2578739770 ps
CPU time 68.27 seconds
Started Aug 14 04:48:09 PM PDT 24
Finished Aug 14 04:49:17 PM PDT 24
Peak memory 257044 kb
Host smart-b5f6eeb4-05b7-4661-9ffa-51597790e6e3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23971
19069 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.2397119069
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.1483903423
Short name T547
Test name
Test status
Simulation time 1122443107 ps
CPU time 68.37 seconds
Started Aug 14 04:48:00 PM PDT 24
Finished Aug 14 04:49:08 PM PDT 24
Peak memory 256252 kb
Host smart-d14a354a-4911-4194-ab4c-425ced684287
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14839
03423 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.1483903423
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.3808719016
Short name T96
Test name
Test status
Simulation time 5108395767 ps
CPU time 45.37 seconds
Started Aug 14 04:48:09 PM PDT 24
Finished Aug 14 04:48:55 PM PDT 24
Peak memory 257076 kb
Host smart-2fdabce7-0075-47d6-8d66-987381691ee9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38087
19016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.3808719016
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all_with_rand_reset.1836088577
Short name T254
Test name
Test status
Simulation time 3233156461 ps
CPU time 182.28 seconds
Started Aug 14 04:48:04 PM PDT 24
Finished Aug 14 04:51:07 PM PDT 24
Peak memory 265432 kb
Host smart-4432d88d-85e6-4e35-8551-d260f5d4acb4
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1836088577 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.alert_handler_stress_all_with_rand_reset.1836088577
Directory /workspace/43.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.334109591
Short name T75
Test name
Test status
Simulation time 20830987893 ps
CPU time 1313.3 seconds
Started Aug 14 04:48:22 PM PDT 24
Finished Aug 14 05:10:15 PM PDT 24
Peak memory 272916 kb
Host smart-3111c94c-afa1-48e3-ae2a-14f9d36491b6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=334109591 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.334109591
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.1681455920
Short name T435
Test name
Test status
Simulation time 5705802303 ps
CPU time 21.52 seconds
Started Aug 14 04:48:03 PM PDT 24
Finished Aug 14 04:48:25 PM PDT 24
Peak memory 256176 kb
Host smart-097dddbe-1972-4065-91c2-d4db5db664fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16814
55920 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.1681455920
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.2057216092
Short name T264
Test name
Test status
Simulation time 1434327258 ps
CPU time 32.5 seconds
Started Aug 14 04:48:15 PM PDT 24
Finished Aug 14 04:48:47 PM PDT 24
Peak memory 248780 kb
Host smart-35ad94b9-e0a2-44ea-8d20-cdf821bcff10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20572
16092 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.2057216092
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.3745004341
Short name T339
Test name
Test status
Simulation time 76827239926 ps
CPU time 797.64 seconds
Started Aug 14 04:48:04 PM PDT 24
Finished Aug 14 05:01:22 PM PDT 24
Peak memory 273324 kb
Host smart-4ad14463-26b0-417e-9e93-694ca5cd710a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3745004341 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.3745004341
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.3030750864
Short name T31
Test name
Test status
Simulation time 50535307553 ps
CPU time 1458.61 seconds
Started Aug 14 04:48:04 PM PDT 24
Finished Aug 14 05:12:23 PM PDT 24
Peak memory 265256 kb
Host smart-40e5b374-031d-4e7a-b39c-6f48dedc05d1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3030750864 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.3030750864
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.2447763785
Short name T386
Test name
Test status
Simulation time 828981319 ps
CPU time 17.84 seconds
Started Aug 14 04:48:19 PM PDT 24
Finished Aug 14 04:48:37 PM PDT 24
Peak memory 255876 kb
Host smart-41a7869f-77a3-4609-8d72-9f51b0302f6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24477
63785 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.2447763785
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.1141658259
Short name T110
Test name
Test status
Simulation time 11156606809 ps
CPU time 34.63 seconds
Started Aug 14 04:48:03 PM PDT 24
Finished Aug 14 04:48:38 PM PDT 24
Peak memory 248440 kb
Host smart-fbefa749-3aca-4a17-ba88-0e60afa03f03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11416
58259 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.1141658259
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.3513994481
Short name T434
Test name
Test status
Simulation time 2036280853 ps
CPU time 19.32 seconds
Started Aug 14 04:48:19 PM PDT 24
Finished Aug 14 04:48:39 PM PDT 24
Peak memory 257064 kb
Host smart-52a6b00b-bdc3-49aa-90b9-e139a507e24d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35139
94481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.3513994481
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.1968255445
Short name T541
Test name
Test status
Simulation time 259348737409 ps
CPU time 3562.5 seconds
Started Aug 14 04:48:05 PM PDT 24
Finished Aug 14 05:47:28 PM PDT 24
Peak memory 289972 kb
Host smart-2b0c8eb4-574a-4393-9aaa-fd17b1b00603
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1968255445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_ha
ndler_stress_all.1968255445
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.1664183993
Short name T18
Test name
Test status
Simulation time 43067805661 ps
CPU time 881.08 seconds
Started Aug 14 04:48:13 PM PDT 24
Finished Aug 14 05:02:54 PM PDT 24
Peak memory 273452 kb
Host smart-3278bf3e-2d6b-443e-84c2-ecbc96be2254
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1664183993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.1664183993
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.1069899220
Short name T410
Test name
Test status
Simulation time 8930918545 ps
CPU time 123.7 seconds
Started Aug 14 04:48:04 PM PDT 24
Finished Aug 14 04:50:08 PM PDT 24
Peak memory 256548 kb
Host smart-81ec1d23-7943-45cf-ab59-c49480f3e23c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10698
99220 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.1069899220
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.4280141722
Short name T663
Test name
Test status
Simulation time 1963789851 ps
CPU time 40.17 seconds
Started Aug 14 04:48:18 PM PDT 24
Finished Aug 14 04:48:58 PM PDT 24
Peak memory 248416 kb
Host smart-e04a59e7-ecac-46cd-8d5d-61f709c3f26e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42801
41722 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.4280141722
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.1999182217
Short name T335
Test name
Test status
Simulation time 19232986105 ps
CPU time 1399.84 seconds
Started Aug 14 04:48:03 PM PDT 24
Finished Aug 14 05:11:23 PM PDT 24
Peak memory 288572 kb
Host smart-f7367b31-859d-489b-a8b8-b34bb3052c7e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1999182217 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.1999182217
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.347084409
Short name T313
Test name
Test status
Simulation time 5400786709 ps
CPU time 218.98 seconds
Started Aug 14 04:48:04 PM PDT 24
Finished Aug 14 04:51:43 PM PDT 24
Peak memory 248888 kb
Host smart-ae57615b-7c42-43ac-852f-5926ffee5555
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=347084409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.347084409
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.2551780346
Short name T376
Test name
Test status
Simulation time 980211070 ps
CPU time 44.66 seconds
Started Aug 14 04:48:19 PM PDT 24
Finished Aug 14 04:49:04 PM PDT 24
Peak memory 256144 kb
Host smart-1b4a3fc2-0b13-4063-80a0-0715dc845759
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25517
80346 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.2551780346
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.1569708572
Short name T509
Test name
Test status
Simulation time 148284822 ps
CPU time 5 seconds
Started Aug 14 04:48:05 PM PDT 24
Finished Aug 14 04:48:10 PM PDT 24
Peak memory 251344 kb
Host smart-b97a429f-39b7-495f-ab8a-23ab6cb41bd5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15697
08572 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.1569708572
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.2460623810
Short name T88
Test name
Test status
Simulation time 752315258 ps
CPU time 20.23 seconds
Started Aug 14 04:48:12 PM PDT 24
Finished Aug 14 04:48:32 PM PDT 24
Peak memory 256076 kb
Host smart-287dd2b6-100e-47b6-bee8-47da361aca7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24606
23810 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.2460623810
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.1720980752
Short name T66
Test name
Test status
Simulation time 311414308 ps
CPU time 20.93 seconds
Started Aug 14 04:48:02 PM PDT 24
Finished Aug 14 04:48:23 PM PDT 24
Peak memory 255408 kb
Host smart-a8fd1d3a-a762-4e18-b138-ed0ec6d8a2ee
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17209
80752 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.1720980752
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all_with_rand_reset.4063410040
Short name T445
Test name
Test status
Simulation time 720528853 ps
CPU time 47.1 seconds
Started Aug 14 04:48:16 PM PDT 24
Finished Aug 14 04:49:03 PM PDT 24
Peak memory 266204 kb
Host smart-abbc9a24-d5a4-4fb4-b684-4d982530dffa
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4063410040 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.alert_handler_stress_all_with_rand_reset.4063410040
Directory /workspace/45.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.1316299924
Short name T702
Test name
Test status
Simulation time 14146964468 ps
CPU time 1329.59 seconds
Started Aug 14 04:48:16 PM PDT 24
Finished Aug 14 05:10:26 PM PDT 24
Peak memory 288888 kb
Host smart-4d35c42c-ca46-4265-bd43-d2f5228ddc21
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1316299924 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.1316299924
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.3978105441
Short name T538
Test name
Test status
Simulation time 1128113413 ps
CPU time 33.19 seconds
Started Aug 14 04:48:21 PM PDT 24
Finished Aug 14 04:48:54 PM PDT 24
Peak memory 248512 kb
Host smart-4e22901d-c15e-4755-9e01-1993ce7cc41d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39781
05441 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.3978105441
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.1146143915
Short name T636
Test name
Test status
Simulation time 35645715 ps
CPU time 5.95 seconds
Started Aug 14 04:48:16 PM PDT 24
Finished Aug 14 04:48:23 PM PDT 24
Peak memory 248796 kb
Host smart-88554443-8bff-48fc-b3ab-76b03c11ba6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11461
43915 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.1146143915
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.1771395567
Short name T114
Test name
Test status
Simulation time 22455093456 ps
CPU time 1456.19 seconds
Started Aug 14 04:48:22 PM PDT 24
Finished Aug 14 05:12:38 PM PDT 24
Peak memory 273468 kb
Host smart-036ef9ad-e338-459f-a1f2-81b903b69308
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1771395567 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.1771395567
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.3185135364
Short name T227
Test name
Test status
Simulation time 52649240637 ps
CPU time 411.7 seconds
Started Aug 14 04:48:22 PM PDT 24
Finished Aug 14 04:55:14 PM PDT 24
Peak memory 248756 kb
Host smart-00ca0f15-9207-476c-baf7-c5f4f793324d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3185135364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.3185135364
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.1983398240
Short name T431
Test name
Test status
Simulation time 73203969 ps
CPU time 5.93 seconds
Started Aug 14 04:48:16 PM PDT 24
Finished Aug 14 04:48:22 PM PDT 24
Peak memory 240556 kb
Host smart-0bb023b1-148e-42fd-9814-8b57104353dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19833
98240 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.1983398240
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.899875708
Short name T379
Test name
Test status
Simulation time 72932084 ps
CPU time 5.36 seconds
Started Aug 14 04:48:21 PM PDT 24
Finished Aug 14 04:48:27 PM PDT 24
Peak memory 240044 kb
Host smart-0ed5a2a5-fb14-46d9-aa32-3b7ff1e2e92a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=89987
5708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.899875708
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.2023071422
Short name T49
Test name
Test status
Simulation time 2045544978 ps
CPU time 33.31 seconds
Started Aug 14 04:48:18 PM PDT 24
Finished Aug 14 04:48:52 PM PDT 24
Peak memory 255032 kb
Host smart-aca956c2-7cb5-4639-afe1-27a7233f404a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20230
71422 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.2023071422
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.1444578658
Short name T467
Test name
Test status
Simulation time 195175005 ps
CPU time 8.42 seconds
Started Aug 14 04:48:17 PM PDT 24
Finished Aug 14 04:48:25 PM PDT 24
Peak memory 254012 kb
Host smart-cead5058-4a7e-4d20-aaed-e13425f76aeb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14445
78658 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.1444578658
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.1847006754
Short name T251
Test name
Test status
Simulation time 833064116538 ps
CPU time 2899.52 seconds
Started Aug 14 04:48:19 PM PDT 24
Finished Aug 14 05:36:39 PM PDT 24
Peak memory 297888 kb
Host smart-e702fca8-2aa5-4b69-9d7f-5baf035842f7
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1847006754 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_ha
ndler_stress_all.1847006754
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.3088189254
Short name T70
Test name
Test status
Simulation time 10116914149 ps
CPU time 1112.65 seconds
Started Aug 14 04:48:31 PM PDT 24
Finished Aug 14 05:07:04 PM PDT 24
Peak memory 289612 kb
Host smart-23bf1fdc-c121-497c-863e-76c8faa22650
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3088189254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.3088189254
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.1722847401
Short name T498
Test name
Test status
Simulation time 7909090007 ps
CPU time 167.78 seconds
Started Aug 14 04:48:15 PM PDT 24
Finished Aug 14 04:51:03 PM PDT 24
Peak memory 256956 kb
Host smart-f33ed8e1-92ad-448f-87e3-b40eb7dad188
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17228
47401 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.1722847401
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.405275283
Short name T93
Test name
Test status
Simulation time 2277477230 ps
CPU time 12.45 seconds
Started Aug 14 04:48:21 PM PDT 24
Finished Aug 14 04:48:34 PM PDT 24
Peak memory 248340 kb
Host smart-c9305be8-7571-4fe7-8d8a-e4fe02ec981f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40527
5283 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.405275283
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.1499428826
Short name T348
Test name
Test status
Simulation time 208414785572 ps
CPU time 1475.09 seconds
Started Aug 14 04:48:19 PM PDT 24
Finished Aug 14 05:12:54 PM PDT 24
Peak memory 288916 kb
Host smart-038ed76d-5bde-4cea-b896-5d5e2c80b81a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1499428826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.1499428826
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.3138426375
Short name T608
Test name
Test status
Simulation time 7902329316 ps
CPU time 781.05 seconds
Started Aug 14 04:48:18 PM PDT 24
Finished Aug 14 05:01:19 PM PDT 24
Peak memory 273024 kb
Host smart-f30fcd4b-d7e0-480c-99f1-383d74a35694
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3138426375 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.3138426375
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.357380405
Short name T305
Test name
Test status
Simulation time 16369874267 ps
CPU time 322.62 seconds
Started Aug 14 04:48:20 PM PDT 24
Finished Aug 14 04:53:43 PM PDT 24
Peak memory 248800 kb
Host smart-1dd72c34-4622-49fb-b556-a4833f67e77d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=357380405 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.357380405
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.1173926557
Short name T631
Test name
Test status
Simulation time 720189851 ps
CPU time 47.68 seconds
Started Aug 14 04:48:19 PM PDT 24
Finished Aug 14 04:49:06 PM PDT 24
Peak memory 248704 kb
Host smart-7a077558-9696-4ccf-b571-2b44169267dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11739
26557 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.1173926557
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.968142391
Short name T273
Test name
Test status
Simulation time 280484517 ps
CPU time 31.3 seconds
Started Aug 14 04:48:16 PM PDT 24
Finished Aug 14 04:48:48 PM PDT 24
Peak memory 247900 kb
Host smart-d521b8b5-48da-4f6e-99b1-1ef2fac904d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=96814
2391 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.968142391
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.3298269212
Short name T644
Test name
Test status
Simulation time 1167462721 ps
CPU time 34.71 seconds
Started Aug 14 04:48:26 PM PDT 24
Finished Aug 14 04:49:01 PM PDT 24
Peak memory 248748 kb
Host smart-eaab715b-142b-444f-8818-7dd363e1026d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32982
69212 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.3298269212
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.4047607701
Short name T632
Test name
Test status
Simulation time 4872125908 ps
CPU time 68.88 seconds
Started Aug 14 04:48:17 PM PDT 24
Finished Aug 14 04:49:26 PM PDT 24
Peak memory 257004 kb
Host smart-eed53475-4236-469c-942e-8a3aacea3dc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40476
07701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.4047607701
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all_with_rand_reset.366137228
Short name T671
Test name
Test status
Simulation time 12546505125 ps
CPU time 374.31 seconds
Started Aug 14 04:48:21 PM PDT 24
Finished Aug 14 04:54:35 PM PDT 24
Peak memory 269400 kb
Host smart-5e047416-c43b-4431-9aa9-16d2fc5b9c1b
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=366137228 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 47.alert_handler_stress_all_with_rand_reset.366137228
Directory /workspace/47.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.328552496
Short name T397
Test name
Test status
Simulation time 13822061514 ps
CPU time 1190.61 seconds
Started Aug 14 04:48:21 PM PDT 24
Finished Aug 14 05:08:12 PM PDT 24
Peak memory 285808 kb
Host smart-a84e1474-ee50-4498-a1da-4313fab3083c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=328552496 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.328552496
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.2817533519
Short name T480
Test name
Test status
Simulation time 20147728020 ps
CPU time 294.23 seconds
Started Aug 14 04:48:23 PM PDT 24
Finished Aug 14 04:53:17 PM PDT 24
Peak memory 252036 kb
Host smart-cb00fbe7-958f-4abc-8d71-4efa90a72eac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28175
33519 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.2817533519
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.3757610368
Short name T718
Test name
Test status
Simulation time 384120979 ps
CPU time 26.2 seconds
Started Aug 14 04:48:17 PM PDT 24
Finished Aug 14 04:48:44 PM PDT 24
Peak memory 256968 kb
Host smart-1e8876ab-a2e3-4653-968c-f7015294b909
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37576
10368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.3757610368
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.3140213954
Short name T301
Test name
Test status
Simulation time 19607813665 ps
CPU time 854.91 seconds
Started Aug 14 04:48:23 PM PDT 24
Finished Aug 14 05:02:38 PM PDT 24
Peak memory 273256 kb
Host smart-15ff28ad-b96d-499f-9a32-1fe390015820
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3140213954 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.3140213954
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.2056493575
Short name T512
Test name
Test status
Simulation time 48656090507 ps
CPU time 1024.24 seconds
Started Aug 14 04:48:23 PM PDT 24
Finished Aug 14 05:05:27 PM PDT 24
Peak memory 288996 kb
Host smart-507357e2-0c48-4709-bf34-4d2f1a11b67d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2056493575 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.2056493575
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.2439974416
Short name T642
Test name
Test status
Simulation time 5139058690 ps
CPU time 216.34 seconds
Started Aug 14 04:48:23 PM PDT 24
Finished Aug 14 04:51:59 PM PDT 24
Peak memory 248808 kb
Host smart-3c38e97c-35f0-4651-92d1-b23be4f16fa8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2439974416 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.2439974416
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.2641866330
Short name T372
Test name
Test status
Simulation time 813763532 ps
CPU time 13.63 seconds
Started Aug 14 04:48:26 PM PDT 24
Finished Aug 14 04:48:39 PM PDT 24
Peak memory 255376 kb
Host smart-7f9f5703-2c6c-4c09-aa30-bf9f2d893652
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26418
66330 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.2641866330
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.4225249943
Short name T651
Test name
Test status
Simulation time 1041741542 ps
CPU time 23.42 seconds
Started Aug 14 04:48:22 PM PDT 24
Finished Aug 14 04:48:45 PM PDT 24
Peak memory 256520 kb
Host smart-7ae688c5-54ac-4b7a-937d-2558537e75cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42252
49943 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.4225249943
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.2002678590
Short name T58
Test name
Test status
Simulation time 3782993475 ps
CPU time 50.32 seconds
Started Aug 14 04:48:15 PM PDT 24
Finished Aug 14 04:49:06 PM PDT 24
Peak memory 256412 kb
Host smart-7c1501d4-8576-4b29-a89d-fab0804482b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20026
78590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.2002678590
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.1918079064
Short name T670
Test name
Test status
Simulation time 55765569 ps
CPU time 4.84 seconds
Started Aug 14 04:48:18 PM PDT 24
Finished Aug 14 04:48:23 PM PDT 24
Peak memory 251920 kb
Host smart-61dd7740-8853-492b-91c6-2dd0a034b8d0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19180
79064 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.1918079064
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.3634978926
Short name T259
Test name
Test status
Simulation time 68236057672 ps
CPU time 2089.99 seconds
Started Aug 14 04:48:24 PM PDT 24
Finished Aug 14 05:23:14 PM PDT 24
Peak memory 289800 kb
Host smart-ee5ad55a-366c-47c8-8206-390eecc8a82a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3634978926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_ha
ndler_stress_all.3634978926
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all_with_rand_reset.2571850976
Short name T697
Test name
Test status
Simulation time 15309359713 ps
CPU time 231.2 seconds
Started Aug 14 04:48:23 PM PDT 24
Finished Aug 14 04:52:15 PM PDT 24
Peak memory 273532 kb
Host smart-71a8b6b3-efe6-4537-a812-b0fb9e0d81ad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2571850976 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 48.alert_handler_stress_all_with_rand_reset.2571850976
Directory /workspace/48.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.2369464884
Short name T113
Test name
Test status
Simulation time 19328580266 ps
CPU time 1074.88 seconds
Started Aug 14 04:48:23 PM PDT 24
Finished Aug 14 05:06:18 PM PDT 24
Peak memory 265220 kb
Host smart-98337320-77d8-4634-9723-9312082b8ed8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2369464884 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.2369464884
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.249364298
Short name T625
Test name
Test status
Simulation time 6630557186 ps
CPU time 141.49 seconds
Started Aug 14 04:48:33 PM PDT 24
Finished Aug 14 04:50:54 PM PDT 24
Peak memory 251932 kb
Host smart-c864ead9-cda8-4dbc-b352-469aeb296af3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24936
4298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.249364298
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.3347875040
Short name T580
Test name
Test status
Simulation time 7484191061 ps
CPU time 51.52 seconds
Started Aug 14 04:48:22 PM PDT 24
Finished Aug 14 04:49:14 PM PDT 24
Peak memory 248736 kb
Host smart-9721519c-fca2-41f8-bdab-467023525bfd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33478
75040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.3347875040
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.3828229629
Short name T349
Test name
Test status
Simulation time 57327500902 ps
CPU time 1882.96 seconds
Started Aug 14 04:48:22 PM PDT 24
Finished Aug 14 05:19:45 PM PDT 24
Peak memory 283468 kb
Host smart-8c12f9df-7c6e-4425-9489-b828f73a0d2f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3828229629 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.3828229629
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.3513225382
Short name T514
Test name
Test status
Simulation time 20723902716 ps
CPU time 1306.69 seconds
Started Aug 14 04:48:28 PM PDT 24
Finished Aug 14 05:10:15 PM PDT 24
Peak memory 268360 kb
Host smart-7a29f996-4ba0-451d-b11b-718763722783
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3513225382 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.3513225382
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.1995279079
Short name T703
Test name
Test status
Simulation time 10364035535 ps
CPU time 329.24 seconds
Started Aug 14 04:48:22 PM PDT 24
Finished Aug 14 04:53:52 PM PDT 24
Peak memory 248816 kb
Host smart-d44868df-2d45-4d1e-a72c-7d0c44936258
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1995279079 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.1995279079
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.1427415507
Short name T713
Test name
Test status
Simulation time 332268910 ps
CPU time 32.15 seconds
Started Aug 14 04:48:22 PM PDT 24
Finished Aug 14 04:48:55 PM PDT 24
Peak memory 256588 kb
Host smart-852864b4-88cf-4f97-82ee-1e91ddc02d62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14274
15507 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.1427415507
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.2847979143
Short name T399
Test name
Test status
Simulation time 781297814 ps
CPU time 43.33 seconds
Started Aug 14 04:48:23 PM PDT 24
Finished Aug 14 04:49:06 PM PDT 24
Peak memory 256224 kb
Host smart-7f753e99-21e1-43c7-a0b4-7104afaa64bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28479
79143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.2847979143
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.256193607
Short name T629
Test name
Test status
Simulation time 879321740 ps
CPU time 50.89 seconds
Started Aug 14 04:48:26 PM PDT 24
Finished Aug 14 04:49:17 PM PDT 24
Peak memory 256052 kb
Host smart-826d9cf7-f4d0-44f6-972d-75145bb86a37
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25619
3607 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.256193607
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.1414186583
Short name T245
Test name
Test status
Simulation time 3920109082 ps
CPU time 55.47 seconds
Started Aug 14 04:48:33 PM PDT 24
Finished Aug 14 04:49:28 PM PDT 24
Peak memory 257096 kb
Host smart-fd656a21-0157-43fd-ab8c-094189cb2560
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14141
86583 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.1414186583
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.2576430479
Short name T73
Test name
Test status
Simulation time 22703445 ps
CPU time 2.24 seconds
Started Aug 14 04:46:55 PM PDT 24
Finished Aug 14 04:46:58 PM PDT 24
Peak memory 248904 kb
Host smart-55fc2e74-86c3-4654-acef-053792889a0e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2576430479 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.2576430479
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.961155620
Short name T35
Test name
Test status
Simulation time 15453457266 ps
CPU time 974.77 seconds
Started Aug 14 04:47:13 PM PDT 24
Finished Aug 14 05:03:28 PM PDT 24
Peak memory 273364 kb
Host smart-a89aeaad-38cc-43ca-9477-f85fdd697836
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=961155620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.961155620
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.1768998225
Short name T464
Test name
Test status
Simulation time 901821119 ps
CPU time 11.88 seconds
Started Aug 14 04:47:19 PM PDT 24
Finished Aug 14 04:47:31 PM PDT 24
Peak memory 248712 kb
Host smart-160ae4de-1e63-49cc-8411-53172193f5ea
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1768998225 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.1768998225
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.3132892199
Short name T234
Test name
Test status
Simulation time 30005647998 ps
CPU time 194.22 seconds
Started Aug 14 04:46:57 PM PDT 24
Finished Aug 14 04:50:12 PM PDT 24
Peak memory 257208 kb
Host smart-e1f023a7-553f-4c0e-9b36-4f6d2d6eee43
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31328
92199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.3132892199
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.3137870224
Short name T643
Test name
Test status
Simulation time 522508828 ps
CPU time 9.94 seconds
Started Aug 14 04:47:12 PM PDT 24
Finished Aug 14 04:47:22 PM PDT 24
Peak memory 253336 kb
Host smart-d466ab82-6f1b-42ad-a517-d1fc4a2dd964
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31378
70224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.3137870224
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.116128346
Short name T95
Test name
Test status
Simulation time 51751447097 ps
CPU time 1543.56 seconds
Started Aug 14 04:47:03 PM PDT 24
Finished Aug 14 05:12:47 PM PDT 24
Peak memory 272524 kb
Host smart-693f37c3-75ca-4d80-bffd-f243b0f4cff5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=116128346 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.116128346
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.3923457513
Short name T472
Test name
Test status
Simulation time 170813156349 ps
CPU time 2524.02 seconds
Started Aug 14 04:47:00 PM PDT 24
Finished Aug 14 05:29:05 PM PDT 24
Peak memory 281668 kb
Host smart-c4febb24-4a68-4033-bab6-687bab09acf7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3923457513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.3923457513
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.1049366341
Short name T641
Test name
Test status
Simulation time 35975582695 ps
CPU time 352.73 seconds
Started Aug 14 04:46:58 PM PDT 24
Finished Aug 14 04:52:51 PM PDT 24
Peak memory 247696 kb
Host smart-9ab0e096-95b0-4fb0-9c01-bf90d4c7b5a7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1049366341 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.1049366341
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.1256228615
Short name T722
Test name
Test status
Simulation time 223494479 ps
CPU time 8.23 seconds
Started Aug 14 04:46:58 PM PDT 24
Finished Aug 14 04:47:07 PM PDT 24
Peak memory 248832 kb
Host smart-e8466614-cce4-4dbe-82f8-926b0361b291
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12562
28615 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.1256228615
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.578232153
Short name T712
Test name
Test status
Simulation time 881228306 ps
CPU time 55.66 seconds
Started Aug 14 04:47:04 PM PDT 24
Finished Aug 14 04:47:59 PM PDT 24
Peak memory 248560 kb
Host smart-1ee830b4-5b2e-4a07-9bac-84eb93078677
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57823
2153 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.578232153
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.464040106
Short name T535
Test name
Test status
Simulation time 243522088 ps
CPU time 28.34 seconds
Started Aug 14 04:47:13 PM PDT 24
Finished Aug 14 04:47:41 PM PDT 24
Peak memory 248720 kb
Host smart-29b77029-0848-4611-88f4-2ca299a5f622
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46404
0106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.464040106
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.4153351813
Short name T235
Test name
Test status
Simulation time 93036910 ps
CPU time 9.73 seconds
Started Aug 14 04:46:57 PM PDT 24
Finished Aug 14 04:47:06 PM PDT 24
Peak memory 255024 kb
Host smart-9372a27a-533a-4d81-8da2-671a7a538b0e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41533
51813 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.4153351813
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.2711741604
Short name T494
Test name
Test status
Simulation time 104128411384 ps
CPU time 1798.33 seconds
Started Aug 14 04:47:08 PM PDT 24
Finished Aug 14 05:17:07 PM PDT 24
Peak memory 282896 kb
Host smart-c89b0198-92b2-4ffd-bd0f-f3405ca945d1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2711741604 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_han
dler_stress_all.2711741604
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all_with_rand_reset.1341857262
Short name T685
Test name
Test status
Simulation time 1417974012 ps
CPU time 171.5 seconds
Started Aug 14 04:47:22 PM PDT 24
Finished Aug 14 04:50:14 PM PDT 24
Peak memory 265312 kb
Host smart-5eaecd2f-a718-4aa4-8389-4752e72edc53
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1341857262 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.alert_handler_stress_all_with_rand_reset.1341857262
Directory /workspace/5.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.2699806237
Short name T219
Test name
Test status
Simulation time 31047174 ps
CPU time 3.3 seconds
Started Aug 14 04:47:01 PM PDT 24
Finished Aug 14 04:47:05 PM PDT 24
Peak memory 248920 kb
Host smart-670a4b30-94c5-44e0-88fd-ba34a42f3c6c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2699806237 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.2699806237
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.1347688249
Short name T537
Test name
Test status
Simulation time 10244995266 ps
CPU time 1124.73 seconds
Started Aug 14 04:46:59 PM PDT 24
Finished Aug 14 05:05:44 PM PDT 24
Peak memory 282812 kb
Host smart-e425460e-7ca5-4ffa-a997-408337aeb05c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1347688249 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.1347688249
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.1835218531
Short name T4
Test name
Test status
Simulation time 2215257768 ps
CPU time 14.27 seconds
Started Aug 14 04:47:01 PM PDT 24
Finished Aug 14 04:47:15 PM PDT 24
Peak memory 248912 kb
Host smart-86c8d271-9589-4bde-82b8-4849fb79a763
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1835218531 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.1835218531
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.630528209
Short name T504
Test name
Test status
Simulation time 389988131 ps
CPU time 21.82 seconds
Started Aug 14 04:47:15 PM PDT 24
Finished Aug 14 04:47:37 PM PDT 24
Peak memory 256236 kb
Host smart-19a8f7bc-7d58-4f02-aa50-37adde347908
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=63052
8209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.630528209
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.1003866240
Short name T229
Test name
Test status
Simulation time 262595079 ps
CPU time 8.48 seconds
Started Aug 14 04:47:09 PM PDT 24
Finished Aug 14 04:47:18 PM PDT 24
Peak memory 252660 kb
Host smart-c742f380-a02a-466f-b749-7382240b9512
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10038
66240 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.1003866240
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.3645404299
Short name T336
Test name
Test status
Simulation time 216548786792 ps
CPU time 2886.56 seconds
Started Aug 14 04:47:25 PM PDT 24
Finished Aug 14 05:35:32 PM PDT 24
Peak memory 289584 kb
Host smart-8c9fe153-b0a3-4e71-8098-dc73081cf0aa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3645404299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.3645404299
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.3903050760
Short name T16
Test name
Test status
Simulation time 151593619107 ps
CPU time 2061.03 seconds
Started Aug 14 04:47:08 PM PDT 24
Finished Aug 14 05:21:29 PM PDT 24
Peak memory 289032 kb
Host smart-d52b6b46-4fec-4de8-bb4f-9dbcbfe7c135
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3903050760 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.3903050760
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.2099562272
Short name T331
Test name
Test status
Simulation time 46699225771 ps
CPU time 489.66 seconds
Started Aug 14 04:46:58 PM PDT 24
Finished Aug 14 04:55:08 PM PDT 24
Peak memory 247620 kb
Host smart-3eed6218-59bb-4d9a-bfc4-8a8c365c76d4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2099562272 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.2099562272
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.2385895198
Short name T97
Test name
Test status
Simulation time 536108382 ps
CPU time 31.6 seconds
Started Aug 14 04:47:35 PM PDT 24
Finished Aug 14 04:48:07 PM PDT 24
Peak memory 248728 kb
Host smart-9e491198-1ba0-4770-8bcf-59ca4cd5be90
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23858
95198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.2385895198
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.3210213640
Short name T33
Test name
Test status
Simulation time 599731281 ps
CPU time 18.86 seconds
Started Aug 14 04:47:13 PM PDT 24
Finished Aug 14 04:47:32 PM PDT 24
Peak memory 248400 kb
Host smart-3931ff04-8338-41df-ac4c-e6ace5e011c2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32102
13640 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.3210213640
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.2543809480
Short name T686
Test name
Test status
Simulation time 433543285 ps
CPU time 8.85 seconds
Started Aug 14 04:46:58 PM PDT 24
Finished Aug 14 04:47:07 PM PDT 24
Peak memory 251192 kb
Host smart-7f705f81-967a-4e8e-ac42-e4c9e9654d3b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25438
09480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.2543809480
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.1813754286
Short name T491
Test name
Test status
Simulation time 367944961 ps
CPU time 24.71 seconds
Started Aug 14 04:47:13 PM PDT 24
Finished Aug 14 04:47:38 PM PDT 24
Peak memory 256228 kb
Host smart-16ab9990-31bf-48e6-b49e-8bea6391fb75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18137
54286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.1813754286
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.2828360513
Short name T92
Test name
Test status
Simulation time 11527192480 ps
CPU time 214.98 seconds
Started Aug 14 04:46:57 PM PDT 24
Finished Aug 14 04:50:32 PM PDT 24
Peak memory 257032 kb
Host smart-2762ab35-1f5d-4b6c-a110-91dccc5031a1
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2828360513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_han
dler_stress_all.2828360513
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all_with_rand_reset.1641486382
Short name T439
Test name
Test status
Simulation time 2560729191 ps
CPU time 92.31 seconds
Started Aug 14 04:46:59 PM PDT 24
Finished Aug 14 04:48:36 PM PDT 24
Peak memory 265444 kb
Host smart-f45d50b8-8bd4-4278-9505-8603d369afc9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1641486382 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.alert_handler_stress_all_with_rand_reset.1641486382
Directory /workspace/6.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.3932422907
Short name T215
Test name
Test status
Simulation time 16645838 ps
CPU time 2.63 seconds
Started Aug 14 04:47:00 PM PDT 24
Finished Aug 14 04:47:03 PM PDT 24
Peak memory 249044 kb
Host smart-2d0add96-1282-4fdf-a4f4-e3e452feb87e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3932422907 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.3932422907
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.3043732315
Short name T690
Test name
Test status
Simulation time 77836657566 ps
CPU time 2297.24 seconds
Started Aug 14 04:47:06 PM PDT 24
Finished Aug 14 05:25:23 PM PDT 24
Peak memory 281256 kb
Host smart-03d42610-8bfb-4cf3-9e9f-cdc752ae3209
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3043732315 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.3043732315
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.3159271931
Short name T511
Test name
Test status
Simulation time 3503485097 ps
CPU time 40.4 seconds
Started Aug 14 04:47:07 PM PDT 24
Finished Aug 14 04:47:47 PM PDT 24
Peak memory 248984 kb
Host smart-ea8815b2-f6d6-4160-b662-56eb81f0083c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3159271931 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.3159271931
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.148715780
Short name T706
Test name
Test status
Simulation time 18620396972 ps
CPU time 267.83 seconds
Started Aug 14 04:47:10 PM PDT 24
Finished Aug 14 04:51:38 PM PDT 24
Peak memory 256600 kb
Host smart-d352546e-64bf-43de-b7cf-92e341caf1b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14871
5780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.148715780
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.2255113633
Short name T409
Test name
Test status
Simulation time 1000640035 ps
CPU time 16.86 seconds
Started Aug 14 04:46:59 PM PDT 24
Finished Aug 14 04:47:16 PM PDT 24
Peak memory 248856 kb
Host smart-e1546b6d-a6e5-4e12-8fdc-8bbad393e9b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22551
13633 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.2255113633
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.817607019
Short name T238
Test name
Test status
Simulation time 90383000813 ps
CPU time 2534.85 seconds
Started Aug 14 04:47:16 PM PDT 24
Finished Aug 14 05:29:31 PM PDT 24
Peak memory 288812 kb
Host smart-83d7d14b-d18d-4e9f-9420-69cb9ed10799
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=817607019 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.817607019
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.2965285780
Short name T493
Test name
Test status
Simulation time 65037300837 ps
CPU time 1368.36 seconds
Started Aug 14 04:47:05 PM PDT 24
Finished Aug 14 05:09:54 PM PDT 24
Peak memory 288448 kb
Host smart-f8b08ae4-5252-4114-8643-85fba52658a5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2965285780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.2965285780
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.3108311260
Short name T277
Test name
Test status
Simulation time 35358275064 ps
CPU time 432.2 seconds
Started Aug 14 04:47:11 PM PDT 24
Finished Aug 14 04:54:28 PM PDT 24
Peak memory 247640 kb
Host smart-7616a7c8-e437-4953-a3db-90dd52b3c9bf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3108311260 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.3108311260
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.3062142704
Short name T442
Test name
Test status
Simulation time 182582307 ps
CPU time 4.23 seconds
Started Aug 14 04:47:07 PM PDT 24
Finished Aug 14 04:47:11 PM PDT 24
Peak memory 248832 kb
Host smart-b67c6ae8-3d0c-4d87-b377-feca1ccb4931
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30621
42704 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.3062142704
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.1905465745
Short name T297
Test name
Test status
Simulation time 2025784901 ps
CPU time 42.52 seconds
Started Aug 14 04:47:20 PM PDT 24
Finished Aug 14 04:48:02 PM PDT 24
Peak memory 256892 kb
Host smart-a32f6caf-236f-4436-9045-dea4e8b3e29a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19054
65745 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.1905465745
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.1879839192
Short name T721
Test name
Test status
Simulation time 1513574139 ps
CPU time 24.18 seconds
Started Aug 14 04:47:02 PM PDT 24
Finished Aug 14 04:47:27 PM PDT 24
Peak memory 256096 kb
Host smart-7fe84bb3-1918-498c-a400-7ab4a12ce7ce
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18798
39192 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.1879839192
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.2026097661
Short name T510
Test name
Test status
Simulation time 2950813022 ps
CPU time 54.09 seconds
Started Aug 14 04:47:06 PM PDT 24
Finished Aug 14 04:48:00 PM PDT 24
Peak memory 256992 kb
Host smart-dc3000c6-78a0-46de-aa10-2adfbe6a9651
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20260
97661 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.2026097661
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.897201117
Short name T60
Test name
Test status
Simulation time 12972471274 ps
CPU time 1188.61 seconds
Started Aug 14 04:47:03 PM PDT 24
Finished Aug 14 05:06:52 PM PDT 24
Peak memory 288520 kb
Host smart-7f91d5bf-6036-43d6-85b4-cac97c0e085f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=897201117 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_hand
ler_stress_all.897201117
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.286080118
Short name T217
Test name
Test status
Simulation time 30726180 ps
CPU time 3.19 seconds
Started Aug 14 04:47:30 PM PDT 24
Finished Aug 14 04:47:33 PM PDT 24
Peak memory 249048 kb
Host smart-1730eb62-a965-4c18-8503-287691d504dc
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=286080118 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.286080118
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.4182437000
Short name T87
Test name
Test status
Simulation time 33573664622 ps
CPU time 1161.94 seconds
Started Aug 14 04:47:08 PM PDT 24
Finished Aug 14 05:06:30 PM PDT 24
Peak memory 284500 kb
Host smart-89b3c564-034a-478e-aead-ebf933accf83
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4182437000 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.4182437000
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.156392306
Short name T550
Test name
Test status
Simulation time 1511745118 ps
CPU time 20.89 seconds
Started Aug 14 04:47:21 PM PDT 24
Finished Aug 14 04:47:42 PM PDT 24
Peak memory 248760 kb
Host smart-9f1ee854-a070-4de8-9524-720287077546
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=156392306 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.156392306
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.3585492409
Short name T542
Test name
Test status
Simulation time 3769620375 ps
CPU time 102.82 seconds
Started Aug 14 04:47:34 PM PDT 24
Finished Aug 14 04:49:17 PM PDT 24
Peak memory 257100 kb
Host smart-04d68535-9998-4662-ac14-6cf3df6bc11c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35854
92409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.3585492409
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.1483093036
Short name T241
Test name
Test status
Simulation time 226321193 ps
CPU time 18.6 seconds
Started Aug 14 04:47:19 PM PDT 24
Finished Aug 14 04:47:38 PM PDT 24
Peak memory 248212 kb
Host smart-ed21f1dd-2404-44e4-ae18-17c5e48299d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14830
93036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.1483093036
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.895071041
Short name T312
Test name
Test status
Simulation time 27859883520 ps
CPU time 1595.52 seconds
Started Aug 14 04:46:58 PM PDT 24
Finished Aug 14 05:13:34 PM PDT 24
Peak memory 272968 kb
Host smart-c2f97c7d-94bf-4695-a555-177a8ee683e0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=895071041 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.895071041
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.3643132395
Short name T242
Test name
Test status
Simulation time 89297204379 ps
CPU time 2512.6 seconds
Started Aug 14 04:47:28 PM PDT 24
Finished Aug 14 05:29:21 PM PDT 24
Peak memory 289812 kb
Host smart-9e69fd2d-28cc-4213-b52a-893bf55125b4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3643132395 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.3643132395
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.1652371433
Short name T327
Test name
Test status
Simulation time 45837160858 ps
CPU time 258.11 seconds
Started Aug 14 04:47:05 PM PDT 24
Finished Aug 14 04:51:23 PM PDT 24
Peak memory 248852 kb
Host smart-d1386472-0552-4059-9569-42f6074d756b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1652371433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.1652371433
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.2561719737
Short name T383
Test name
Test status
Simulation time 1118972981 ps
CPU time 15.81 seconds
Started Aug 14 04:47:01 PM PDT 24
Finished Aug 14 04:47:17 PM PDT 24
Peak memory 248836 kb
Host smart-0199438c-15af-4b51-94e3-4b97cfa616fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25617
19737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.2561719737
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.2487227534
Short name T381
Test name
Test status
Simulation time 502302301 ps
CPU time 14.22 seconds
Started Aug 14 04:47:14 PM PDT 24
Finished Aug 14 04:47:28 PM PDT 24
Peak memory 248792 kb
Host smart-7ee45a84-c92b-4959-84ca-928dc5efd852
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24872
27534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.2487227534
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.1109187433
Short name T370
Test name
Test status
Simulation time 97152138 ps
CPU time 10.5 seconds
Started Aug 14 04:47:15 PM PDT 24
Finished Aug 14 04:47:25 PM PDT 24
Peak memory 248744 kb
Host smart-4124c15f-9808-470b-82fd-708ede7d1024
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11091
87433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.1109187433
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.878940627
Short name T660
Test name
Test status
Simulation time 260004569 ps
CPU time 6.1 seconds
Started Aug 14 04:47:00 PM PDT 24
Finished Aug 14 04:47:06 PM PDT 24
Peak memory 250816 kb
Host smart-95f9efd9-c306-4c3e-85a7-63a51c5272df
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87894
0627 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.878940627
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all_with_rand_reset.2683995869
Short name T267
Test name
Test status
Simulation time 10867672519 ps
CPU time 162.04 seconds
Started Aug 14 04:47:00 PM PDT 24
Finished Aug 14 04:49:42 PM PDT 24
Peak memory 267616 kb
Host smart-9f91a33a-196f-4e0d-9030-30e9d25d7ed5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683995869 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.alert_handler_stress_all_with_rand_reset.2683995869
Directory /workspace/8.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.1092034716
Short name T222
Test name
Test status
Simulation time 35216415 ps
CPU time 3.39 seconds
Started Aug 14 04:47:27 PM PDT 24
Finished Aug 14 04:47:30 PM PDT 24
Peak memory 249040 kb
Host smart-beac57bc-b812-4196-b244-83e1fb752185
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1092034716 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.1092034716
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.429736614
Short name T422
Test name
Test status
Simulation time 9868495616 ps
CPU time 1103.81 seconds
Started Aug 14 04:47:01 PM PDT 24
Finished Aug 14 05:05:25 PM PDT 24
Peak memory 288732 kb
Host smart-d13b15c6-c52c-47a6-b3dd-714a2291a582
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=429736614 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.429736614
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.532735560
Short name T429
Test name
Test status
Simulation time 1046700294 ps
CPU time 24.94 seconds
Started Aug 14 04:47:18 PM PDT 24
Finished Aug 14 04:47:43 PM PDT 24
Peak memory 248624 kb
Host smart-e619810f-2357-4847-903c-3b2115a2f32c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=532735560 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.532735560
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.1866324191
Short name T623
Test name
Test status
Simulation time 4182414347 ps
CPU time 148.86 seconds
Started Aug 14 04:47:22 PM PDT 24
Finished Aug 14 04:49:51 PM PDT 24
Peak memory 257112 kb
Host smart-e5d174de-1b9e-456b-946c-7837a9999f6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18663
24191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.1866324191
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.615674657
Short name T666
Test name
Test status
Simulation time 4490128080 ps
CPU time 49.69 seconds
Started Aug 14 04:47:00 PM PDT 24
Finished Aug 14 04:47:50 PM PDT 24
Peak memory 248848 kb
Host smart-d83c62dc-2df7-491f-809d-728845d4845b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61567
4657 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.615674657
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.3516348062
Short name T298
Test name
Test status
Simulation time 12739925226 ps
CPU time 1363.68 seconds
Started Aug 14 04:46:59 PM PDT 24
Finished Aug 14 05:09:43 PM PDT 24
Peak memory 289800 kb
Host smart-e6e1f665-01fd-48f4-8ccd-84a3acb0923d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3516348062 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.3516348062
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.1711891559
Short name T444
Test name
Test status
Simulation time 24644208808 ps
CPU time 1612.51 seconds
Started Aug 14 04:47:02 PM PDT 24
Finished Aug 14 05:13:55 PM PDT 24
Peak memory 273472 kb
Host smart-f3bb9c50-a2f0-4612-8709-64ae4a194662
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711891559 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.1711891559
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.3129633972
Short name T307
Test name
Test status
Simulation time 14062170650 ps
CPU time 299.83 seconds
Started Aug 14 04:47:01 PM PDT 24
Finished Aug 14 04:52:01 PM PDT 24
Peak memory 248760 kb
Host smart-f9015954-bd15-4ad5-ac40-ac60da53f515
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3129633972 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.3129633972
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.2972336065
Short name T555
Test name
Test status
Simulation time 1039443259 ps
CPU time 18.41 seconds
Started Aug 14 04:47:15 PM PDT 24
Finished Aug 14 04:47:34 PM PDT 24
Peak memory 255168 kb
Host smart-8af54753-b302-4bd5-b7fa-54c7cbed0d7c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29723
36065 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.2972336065
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.1642281544
Short name T479
Test name
Test status
Simulation time 792528162 ps
CPU time 41.83 seconds
Started Aug 14 04:47:04 PM PDT 24
Finished Aug 14 04:47:46 PM PDT 24
Peak memory 256128 kb
Host smart-76ec3fde-6cdd-45ef-82cb-10f6f4650b18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16422
81544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.1642281544
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.539346318
Short name T441
Test name
Test status
Simulation time 1043262471 ps
CPU time 18.43 seconds
Started Aug 14 04:47:19 PM PDT 24
Finished Aug 14 04:47:38 PM PDT 24
Peak memory 248388 kb
Host smart-c55c9944-a6fc-440a-9672-99af2126ea70
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53934
6318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.539346318
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.943664571
Short name T455
Test name
Test status
Simulation time 656138782 ps
CPU time 5.04 seconds
Started Aug 14 04:47:09 PM PDT 24
Finished Aug 14 04:47:15 PM PDT 24
Peak memory 250940 kb
Host smart-a52ad0f2-921a-4e60-9c01-f5d752540571
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94366
4571 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.943664571
Directory /workspace/9.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.419208958
Short name T283
Test name
Test status
Simulation time 23420020460 ps
CPU time 1227.66 seconds
Started Aug 14 04:47:05 PM PDT 24
Finished Aug 14 05:07:33 PM PDT 24
Peak memory 288684 kb
Host smart-33798414-0683-46c9-92d3-b5e97d574950
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=419208958 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_hand
ler_stress_all.419208958
Directory /workspace/9.alert_handler_stress_all/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all_with_rand_reset.1818398081
Short name T619
Test name
Test status
Simulation time 2587814486 ps
CPU time 124.02 seconds
Started Aug 14 04:47:01 PM PDT 24
Finished Aug 14 04:49:05 PM PDT 24
Peak memory 273504 kb
Host smart-c1560515-30cb-4df9-a311-5c0f2169707d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1818398081 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 9.alert_handler_stress_all_with_rand_reset.1818398081
Directory /workspace/9.alert_handler_stress_all_with_rand_reset/latest
0% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100%