Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	77506	1			T15	1		T4	10		T5	33
class_i[0x1]	37885	1			T2	14		T6	2		T4	4
class_i[0x2]	49056	1			T2	1242		T15	12		T6	5
class_i[0x3]	23836	1			T4	9		T5	173		T27	158

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	45516	1			T2	4		T15	6		T6	1
alert[0x1]	49231	1			T2	712		T15	1		T6	3
alert[0x2]	47566	1			T2	5		T15	6		T6	1
alert[0x3]	45970	1			T2	535		T6	2		T4	5

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

187999

1

T2

1256

T15

13

T6

2

esc_ping_fail

284

1

T6

5

T17

4

T18

6

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	45435	1			T2	4		T15	6		T5	813
esc_integrity_fail	alert[0x1]	49163	1			T2	712		T15	1		T6	2
esc_integrity_fail	alert[0x2]	47493	1			T2	5		T15	6		T4	9
esc_integrity_fail	alert[0x3]	45908	1			T2	535		T4	5		T5	443
esc_ping_fail	alert[0x0]	81	1			T6	1		T17	2		T18	1
esc_ping_fail	alert[0x1]	68	1			T6	1		T18	2		T220	2
esc_ping_fail	alert[0x2]	73	1			T6	1		T17	1		T18	2
esc_ping_fail	alert[0x3]	62	1			T6	2		T17	1		T18	1

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	77437	1			T15	1		T4	10		T5	33
esc_integrity_fail	class_i[0x1]	37795	1			T2	14		T6	2		T4	4
esc_integrity_fail	class_i[0x2]	48985	1			T2	1242		T15	12		T5	17
esc_integrity_fail	class_i[0x3]	23782	1			T4	9		T5	173		T27	158
esc_ping_fail	class_i[0x0]	69	1			T18	6		T302	3		T298	2
esc_ping_fail	class_i[0x1]	90	1			T307	3		T241	11		T224	6
esc_ping_fail	class_i[0x2]	71	1			T6	5		T220	1		T228	8
esc_ping_fail	class_i[0x3]	54	1			T17	4		T220	8		T307	2