Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	547691932	0	0	631
tb.dut.u_edn_req.u_prim_packer_fifo.ValidOPairedWithReadyI_A	0	0	547691932	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AckPKnownO_A	0	0	547691932	547533520	0	0
tb.dut.CheckAccuCntDw	0	0	631	631	0	0
tb.dut.CheckEscCntDw	0	0	631	631	0	0
tb.dut.CheckNAlerts	0	0	631	631	0	0
tb.dut.CheckNClasses	0	0	631	631	0	0
tb.dut.CheckNEscSev	0	0	631	631	0	0
tb.dut.CrashdumpKnownO_A	0	0	547691932	547533520	0	0
tb.dut.EdnKnownO_A	0	0	547691932	547533520	0	0
tb.dut.EscPKnownO_A	0	0	547691932	547533520	0	0
tb.dut.FpvSecCmPingTimerCnterCheck_A	0	0	547691932	70	0	0
tb.dut.FpvSecCmPingTimerDoubleLfsrCheck_A	0	0	547691932	70	0	0
tb.dut.FpvSecCmPingTimerEscCnterCheck_A	0	0	547691932	70	0	0
tb.dut.FpvSecCmPingTimerFsmCheck_A	0	0	547691932	70	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	547691932	70	0	0
tb.dut.IrqAKnownO_A	0	0	547691932	547533520	0	0
tb.dut.IrqBKnownO_A	0	0	547691932	547533520	0	0
tb.dut.IrqCKnownO_A	0	0	547691932	547533520	0	0
tb.dut.IrqDKnownO_A	0	0	547691932	547533520	0	0
tb.dut.TlAReadyKnownO_A	0	0	547691932	547533520	0	0
tb.dut.TlDValidKnownO_A	0	0	547691932	547533520	0	0
tb.dut.alert_handler_csr_assert.TlulOOBAddrErr_A	0	0	573892434	237610	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_0_rd_A	0	0	573892434	16152	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_10_rd_A	0	0	573892434	12968	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_11_rd_A	0	0	573892434	14101	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_12_rd_A	0	0	573892434	14038	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_13_rd_A	0	0	573892434	14466	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_14_rd_A	0	0	573892434	14037	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_15_rd_A	0	0	573892434	16024	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_16_rd_A	0	0	573892434	13196	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_17_rd_A	0	0	573892434	16738	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_18_rd_A	0	0	573892434	15328	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_19_rd_A	0	0	573892434	14583	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_1_rd_A	0	0	573892434	14702	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_20_rd_A	0	0	573892434	13089	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_21_rd_A	0	0	573892434	15405	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_22_rd_A	0	0	573892434	13209	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_23_rd_A	0	0	573892434	13851	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_24_rd_A	0	0	573892434	14223	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_25_rd_A	0	0	573892434	15185	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_26_rd_A	0	0	573892434	14117	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_27_rd_A	0	0	573892434	16056	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_28_rd_A	0	0	573892434	14114	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_29_rd_A	0	0	573892434	14407	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_2_rd_A	0	0	573892434	14393	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_30_rd_A	0	0	573892434	13026	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_31_rd_A	0	0	573892434	15131	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_32_rd_A	0	0	573892434	14006	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_33_rd_A	0	0	573892434	14249	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_34_rd_A	0	0	573892434	13321	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_35_rd_A	0	0	573892434	15530	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_36_rd_A	0	0	573892434	14750	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_37_rd_A	0	0	573892434	14580	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_38_rd_A	0	0	573892434	13780	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_39_rd_A	0	0	573892434	13485	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_3_rd_A	0	0	573892434	14992	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_40_rd_A	0	0	573892434	13094	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_41_rd_A	0	0	573892434	14006	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_42_rd_A	0	0	573892434	15062	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_43_rd_A	0	0	573892434	14142	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_44_rd_A	0	0	573892434	14701	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_45_rd_A	0	0	573892434	15731	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_46_rd_A	0	0	573892434	14229	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_47_rd_A	0	0	573892434	14091	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_48_rd_A	0	0	573892434	13017	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_49_rd_A	0	0	573892434	14486	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_4_rd_A	0	0	573892434	13094	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_50_rd_A	0	0	573892434	15222	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_51_rd_A	0	0	573892434	13140	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_52_rd_A	0	0	573892434	13730	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_53_rd_A	0	0	573892434	14105	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_54_rd_A	0	0	573892434	14107	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_55_rd_A	0	0	573892434	15355	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_56_rd_A	0	0	573892434	17113	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_57_rd_A	0	0	573892434	15487	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_58_rd_A	0	0	573892434	15055	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_59_rd_A	0	0	573892434	16584	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_5_rd_A	0	0	573892434	13796	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_60_rd_A	0	0	573892434	15139	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_61_rd_A	0	0	573892434	15609	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_62_rd_A	0	0	573892434	14320	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_63_rd_A	0	0	573892434	14492	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_64_rd_A	0	0	573892434	15202	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_6_rd_A	0	0	573892434	15260	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_7_rd_A	0	0	573892434	14324	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_8_rd_A	0	0	573892434	16440	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_9_rd_A	0	0	573892434	14042	0	0
tb.dut.alert_handler_csr_assert.classa_regwen_rd_A	0	0	573892434	15237	0	0
tb.dut.alert_handler_csr_assert.classb_regwen_rd_A	0	0	573892434	14948	0	0
tb.dut.alert_handler_csr_assert.classc_regwen_rd_A	0	0	573892434	16610	0	0
tb.dut.alert_handler_csr_assert.classd_regwen_rd_A	0	0	573892434	16257	0	0
tb.dut.alert_handler_csr_assert.intr_enable_rd_A	0	0	573892434	27637	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_0_rd_A	0	0	573892434	14616	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_1_rd_A	0	0	573892434	15133	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_2_rd_A	0	0	573892434	15398	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_3_rd_A	0	0	573892434	13210	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_4_rd_A	0	0	573892434	15237	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_5_rd_A	0	0	573892434	15980	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_6_rd_A	0	0	573892434	14101	0	0
tb.dut.alert_handler_csr_assert.ping_timer_regwen_rd_A	0	0	573892434	12996	0	0
tb.dut.gen_classes[0].FpvSecCmAccuCnterCheck_A	0	0	547691932	70	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerCnterCheck_A	0	0	547691932	70	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerFsmCheck_A	0	0	547691932	70	0	0
tb.dut.gen_classes[0].u_accu.CountSaturateStable_A	0	0	547691932	2394	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigBkwd_A	0	0	547691932	132116	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigFwd_A	0	0	547691932	309786203	0	0
tb.dut.gen_classes[0].u_esc_timer.AccuFailToFsmError_A	0	0	547691932	167	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig0_A	0	0	547691932	822	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig1_A	0	0	547691932	37	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckClr_A	0	0	547691932	393	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckEn_A	0	0	547549190	217874333	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase0_A	0	0	547691932	873	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase1_A	0	0	547691932	845	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase2_A	0	0	547691932	825	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase3_A	0	0	547691932	792	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeout0_A	0	0	547691932	932	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt1_A	0	0	547691932	103248	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt2_A	0	0	547691932	831	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutStTrig_A	0	0	547691932	59	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStAllEscAsserted_A	0	0	547691932	1099	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStIsTerminal_A	0	0	547691932	889	0	0
tb.dut.gen_classes[0].u_esc_timer.EscStateOut_A	0	0	547547802	547479105	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs.AssertConnected_A	0	0	631	631	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs_A	0	0	547691932	547533520	0	0
tb.dut.gen_classes[1].FpvSecCmAccuCnterCheck_A	0	0	547691932	70	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerCnterCheck_A	0	0	547691932	70	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerFsmCheck_A	0	0	547691932	70	0	0
tb.dut.gen_classes[1].u_accu.CountSaturateStable_A	0	0	547691932	1421	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigBkwd_A	0	0	547691932	138724	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigFwd_A	0	0	547691932	310639548	0	0
tb.dut.gen_classes[1].u_esc_timer.AccuFailToFsmError_A	0	0	547691932	202	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig0_A	0	0	547691932	506	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig1_A	0	0	547691932	23	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckClr_A	0	0	547691932	233	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckEn_A	0	0	547549190	244105181	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase0_A	0	0	547691932	567	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase1_A	0	0	547691932	558	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase2_A	0	0	547691932	545	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase3_A	0	0	547691932	530	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeout0_A	0	0	547691932	803	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt1_A	0	0	547691932	101004	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt2_A	0	0	547691932	728	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutStTrig_A	0	0	547691932	50	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStAllEscAsserted_A	0	0	547691932	1155	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStIsTerminal_A	0	0	547691932	945	0	0
tb.dut.gen_classes[1].u_esc_timer.EscStateOut_A	0	0	547547802	547479105	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs.AssertConnected_A	0	0	631	631	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs_A	0	0	547691932	547533520	0	0
tb.dut.gen_classes[2].FpvSecCmAccuCnterCheck_A	0	0	547691932	70	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerCnterCheck_A	0	0	547691932	70	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerFsmCheck_A	0	0	547691932	70	0	0
tb.dut.gen_classes[2].u_accu.CountSaturateStable_A	0	0	547691932	7242	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigBkwd_A	0	0	547691932	164660	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigFwd_A	0	0	547691932	296562726	0	0
tb.dut.gen_classes[2].u_esc_timer.AccuFailToFsmError_A	0	0	547691932	230	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig0_A	0	0	547691932	490	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig1_A	0	0	547691932	18	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckClr_A	0	0	547691932	203	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckEn_A	0	0	547549190	230075401	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase0_A	0	0	547691932	536	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase1_A	0	0	547691932	526	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase2_A	0	0	547691932	512	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase3_A	0	0	547691932	502	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeout0_A	0	0	547691932	1139	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt1_A	0	0	547691932	108112	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt2_A	0	0	547691932	1074	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutStTrig_A	0	0	547691932	44	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStAllEscAsserted_A	0	0	547691932	1205	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStIsTerminal_A	0	0	547691932	995	0	0
tb.dut.gen_classes[2].u_esc_timer.EscStateOut_A	0	0	547547802	547479105	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs.AssertConnected_A	0	0	631	631	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs_A	0	0	547691932	547533520	0	0
tb.dut.gen_classes[3].FpvSecCmAccuCnterCheck_A	0	0	547691932	70	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerCnterCheck_A	0	0	547691932	70	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerFsmCheck_A	0	0	547691932	70	0	0
tb.dut.gen_classes[3].u_accu.CountSaturateStable_A	0	0	547691932	1687	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigBkwd_A	0	0	547691932	170101	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigFwd_A	0	0	547691932	302921272	0	0
tb.dut.gen_classes[3].u_esc_timer.AccuFailToFsmError_A	0	0	547691932	242	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig0_A	0	0	547691932	503	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig1_A	0	0	547691932	17	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckClr_A	0	0	547691932	233	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckEn_A	0	0	547549190	221322475	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase0_A	0	0	547691932	567	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase1_A	0	0	547691932	554	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase2_A	0	0	547691932	540	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase3_A	0	0	547691932	527	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeout0_A	0	0	547691932	461	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt1_A	0	0	547691932	55928	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt2_A	0	0	547691932	376	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutStTrig_A	0	0	547691932	63	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStAllEscAsserted_A	0	0	547691932	1167	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStIsTerminal_A	0	0	547691932	957	0	0
tb.dut.gen_classes[3].u_esc_timer.EscStateOut_A	0	0	547547802	547479105	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs.AssertConnected_A	0	0	631	631	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs_A	0	0	547691932	547533520	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	573892434	82168933	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	573892434	573216293	0	0
tb.dut.tlul_assert_device.aReadyKnown_A	0	0	573892434	573216293	0	0
tb.dut.tlul_assert_device.dKnown_A	0	0	573892434	146754116	0	0
tb.dut.tlul_assert_device.dKnown_AKnownEnable	0	0	573892434	573216293	0	0
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