Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
98.31	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	44	1	43	97.73

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_sig_index_cp	4	0	4	100.00	100	1	1	0
esc_sig_len_cp	11	0	11	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
len_per_esc_sig	44	1	43	97.73	100	1	1	0

Summary for Variable esc_sig_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_sig_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	195	1			T3	1		T12	1		T15	1
index[0x1]	149	1			T3	1		T12	1		T4	1
index[0x2]	189	1			T15	1		T4	1		T23	1
index[0x3]	192	1			T2	2		T3	1		T8	1

---

Summary for Variable esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for esc_sig_len_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
lens_less_than_1000[0]	231	1			T3	2		T12	1		T15	1
lens_less_than_1000[1]	142	1			T12	1		T15	1		T4	1
lens_less_than_1000[2]	101	1			T4	1		T24	1		T25	3
lens_less_than_1000[3]	52	1			T5	2		T33	1		T78	1
lens_less_than_1000[4]	63	1			T5	1		T22	1		T79	1
lens_less_than_1000[5]	54	1			T2	1		T7	1		T5	1
lens_less_than_1000[6]	27	1			T5	1		T17	1		T235	1
lens_less_than_1000[7]	21	1			T31	1		T34	1		T110	2
lens_less_than_1000[8]	11	1			T2	1		T110	1		T36	1
lens_less_than_1000[9]	4	1			T19	1		T35	1		T121	1
len_2	19	1			T3	1		T8	1		T20	1

---

Summary for Cross len_per_esc_sig

Samples crossed: esc_sig_index_cp esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	44	1	43	97.73	1

Automatically Generated Cross Bins for len_per_esc_sig

Uncovered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	NUMBER	STATUS
[index[0x3]]	[lens_less_than_1000[9]]	0	1	1

Covered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	lens_less_than_1000[0]	70	1			T3	1		T15	1		T4	1
index[0x0]	lens_less_than_1000[1]	39	1			T12	1		T79	1		T70	1
index[0x0]	lens_less_than_1000[2]	27	1			T4	1		T25	3		T219	1
index[0x0]	lens_less_than_1000[3]	12	1			T5	1		T248	1		T35	1
index[0x0]	lens_less_than_1000[4]	13	1			T22	1		T28	2		T224	1
index[0x0]	lens_less_than_1000[5]	18	1			T34	10		T111	1		T277	1
index[0x0]	lens_less_than_1000[6]	5	1			T5	1		T261	1		T278	1
index[0x0]	lens_less_than_1000[7]	6	1			T110	1		T279	1		T280	1
index[0x0]	lens_less_than_1000[8]	2	1			T236	1		T281	1		-	-
index[0x0]	lens_less_than_1000[9]	2	1			T19	1		T26	1		-	-
index[0x0]	len_2	1	1			T250	1		-	-		-	-
index[0x1]	lens_less_than_1000[0]	54	1			T3	1		T12	1		T4	1
index[0x1]	lens_less_than_1000[1]	21	1			T27	1		T22	1		T34	1
index[0x1]	lens_less_than_1000[2]	21	1			T52	1		T35	1		T46	1
index[0x1]	lens_less_than_1000[3]	9	1			T33	1		T236	1		T116	1
index[0x1]	lens_less_than_1000[4]	11	1			T81	1		T53	1		T246	1
index[0x1]	lens_less_than_1000[5]	12	1			T5	1		T83	1		T282	1
index[0x1]	lens_less_than_1000[6]	7	1			T17	1		T235	1		T283	1
index[0x1]	lens_less_than_1000[7]	4	1			T110	1		T93	1		T120	1
index[0x1]	lens_less_than_1000[8]	3	1			T110	1		T63	1		T284	1
index[0x1]	lens_less_than_1000[9]	1	1			T121	1		-	-		-	-
index[0x1]	len_2	6	1			T92	1		T66	1		T285	1
index[0x2]	lens_less_than_1000[0]	47	1			T23	1		T35	1		T80	1
index[0x2]	lens_less_than_1000[1]	43	1			T15	1		T4	1		T5	2
index[0x2]	lens_less_than_1000[2]	20	1			T24	1		T111	1		T93	1
index[0x2]	lens_less_than_1000[3]	17	1			T251	1		T88	1		T286	1
index[0x2]	lens_less_than_1000[4]	22	1			T5	1		T34	2		T35	1
index[0x2]	lens_less_than_1000[5]	15	1			T7	1		T35	2		T287	1
index[0x2]	lens_less_than_1000[6]	9	1			T98	2		T261	2		T288	1
index[0x2]	lens_less_than_1000[7]	5	1			T31	1		T34	1		T289	1
index[0x2]	lens_less_than_1000[8]	4	1			T36	1		T290	1		T278	2
index[0x2]	lens_less_than_1000[9]	1	1			T35	1		-	-		-	-
index[0x2]	len_2	6	1			T20	1		T119	1		T285	1
index[0x3]	lens_less_than_1000[0]	60	1			T33	3		T32	1		T34	4
index[0x3]	lens_less_than_1000[1]	39	1			T33	1		T39	2		T79	1
index[0x3]	lens_less_than_1000[2]	33	1			T31	1		T222	1		T242	1
index[0x3]	lens_less_than_1000[3]	14	1			T5	1		T78	1		T34	1
index[0x3]	lens_less_than_1000[4]	17	1			T79	1		T291	1		T65	1
index[0x3]	lens_less_than_1000[5]	9	1			T2	1		T292	1		T262	1
index[0x3]	lens_less_than_1000[6]	6	1			T50	1		T261	1		T64	1
index[0x3]	lens_less_than_1000[7]	6	1			T284	1		T293	1		T294	3
index[0x3]	lens_less_than_1000[8]	2	1			T2	1		T295	1		-	-
index[0x3]	len_2	6	1			T3	1		T8	1		T250	1