Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
87.04	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	7	33	82.50

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	7	33	82.50	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	59	1			T27	1		T52	1		T77	1
class_index[0x1]	50	1			T31	2		T35	1		T81	1
class_index[0x2]	43	1			T2	1		T3	1		T32	1
class_index[0x3]	63	1			T3	1		T5	2		T82	3

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	91	1			T5	1		T82	3		T31	2
intr_timeout_cnt[1]	55	1			T27	1		T32	1		T35	2
intr_timeout_cnt[2]	20	1			T5	1		T52	1		T77	1
intr_timeout_cnt[3]	12	1			T3	1		T36	1		T90	1
intr_timeout_cnt[4]	15	1			T3	1		T81	1		T54	1
intr_timeout_cnt[5]	3	1			T121	1		T124	2		-	-
intr_timeout_cnt[6]	5	1			T254	1		T255	2		T105	1
intr_timeout_cnt[7]	5	1			T2	1		T36	1		T68	1
intr_timeout_cnt[8]	5	1			T75	1		T36	1		T256	1
intr_timeout_cnt[9]	4	1			T31	1		T32	1		T81	1

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	7	33	82.50	7

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x0]]	[intr_timeout_cnt[5] , intr_timeout_cnt[6]]	--	--	2
[class_index[0x1]]	[intr_timeout_cnt[7]]	0	1	1
[class_index[0x2]]	[intr_timeout_cnt[5] , intr_timeout_cnt[6]]	--	--	2
[class_index[0x2]]	[intr_timeout_cnt[9]]	0	1	1
[class_index[0x3]]	[intr_timeout_cnt[8]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	29	1			T31	1		T36	1		T56	1
class_index[0x0]	intr_timeout_cnt[1]	15	1			T27	1		T81	1		T36	1
class_index[0x0]	intr_timeout_cnt[2]	6	1			T52	1		T77	1		T88	1
class_index[0x0]	intr_timeout_cnt[3]	1	1			T254	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[4]	4	1			T81	1		T257	1		T258	1
class_index[0x0]	intr_timeout_cnt[7]	1	1			T68	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[8]	1	1			T259	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[9]	2	1			T32	1		T65	1		-	-
class_index[0x1]	intr_timeout_cnt[0]	14	1			T31	1		T35	1		T81	1
class_index[0x1]	intr_timeout_cnt[1]	18	1			T91	1		T92	1		T260	1
class_index[0x1]	intr_timeout_cnt[2]	5	1			T261	1		T262	1		T257	1
class_index[0x1]	intr_timeout_cnt[3]	2	1			T263	1		T264	1		-	-
class_index[0x1]	intr_timeout_cnt[4]	4	1			T29	1		T265	1		T256	1
class_index[0x1]	intr_timeout_cnt[5]	1	1			T124	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[6]	3	1			T255	2		T105	1		-	-
class_index[0x1]	intr_timeout_cnt[8]	2	1			T75	1		T266	1		-	-
class_index[0x1]	intr_timeout_cnt[9]	1	1			T31	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[0]	10	1			T32	1		T267	1		T268	1
class_index[0x2]	intr_timeout_cnt[1]	16	1			T35	2		T89	1		T93	1
class_index[0x2]	intr_timeout_cnt[2]	3	1			T269	1		T270	1		T247	1
class_index[0x2]	intr_timeout_cnt[3]	6	1			T3	1		T90	1		T56	1
class_index[0x2]	intr_timeout_cnt[4]	3	1			T54	1		T255	1		T105	1
class_index[0x2]	intr_timeout_cnt[7]	3	1			T2	1		T36	1		T271	1
class_index[0x2]	intr_timeout_cnt[8]	2	1			T36	1		T256	1		-	-
class_index[0x3]	intr_timeout_cnt[0]	38	1			T5	1		T82	3		T34	1
class_index[0x3]	intr_timeout_cnt[1]	6	1			T32	1		T272	1		T273	1
class_index[0x3]	intr_timeout_cnt[2]	6	1			T5	1		T274	1		T256	2
class_index[0x3]	intr_timeout_cnt[3]	3	1			T36	1		T56	1		T275	1
class_index[0x3]	intr_timeout_cnt[4]	4	1			T3	1		T263	1		T262	1
class_index[0x3]	intr_timeout_cnt[5]	2	1			T121	1		T124	1		-	-
class_index[0x3]	intr_timeout_cnt[6]	2	1			T254	1		T276	1		-	-
class_index[0x3]	intr_timeout_cnt[7]	1	1			T105	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[9]	1	1			T81	1		-	-		-	-