Unified Coverage Report :: Group :: cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr	4	0	4	100.00	100	1	1	0
cp_intr_en	2	0	2	100.00	100	1	1	2
cp_intr_state	2	0	2	100.00	100	1	1	2

Crosses for Group cip_base_pkg::intr_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
intr_cg_cc	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	289581	1			T1	31		T2	20		T3	60
all_values[1]	289581	1			T1	31		T2	20		T3	60
all_values[2]	289581	1			T1	31		T2	20		T3	60
all_values[3]	289581	1			T1	31		T2	20		T3	60

---

Summary for Variable cp_intr_en

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_en

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

577048

1

T1

57

T2

27

T3

126

auto[1]

581276

1

T1

67

T2

53

T3

114

---

Summary for Variable cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Automatically Generated Bins	2	0	2	100.00

Automatically Generated Bins for cp_intr_state

Bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

auto[0]

675704

1

T1

123

T2

13

T3

117

auto[1]

482620

1

T1

1

T2

67

T3

123

---

Summary for Cross intr_cg_cc

Samples crossed: cp_intr cp_intr_en cp_intr_state

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for intr_cg_cc

Bins

cp_intr	cp_intr_en	cp_intr_state	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_values[0]	auto[0]	auto[0]	82958	1			T1	11		T2	1		T3	14
all_values[0]	auto[0]	auto[1]	61538	1			T1	1		T2	3		T3	14
all_values[0]	auto[1]	auto[0]	83630	1			T1	19		T2	2		T3	15
all_values[0]	auto[1]	auto[1]	61455	1			T2	14		T3	17		T12	6
all_values[1]	auto[0]	auto[0]	84047	1			T1	19		T2	2		T3	17
all_values[1]	auto[0]	auto[1]	59941	1			T2	9		T3	17		T12	8
all_values[1]	auto[1]	auto[0]	85645	1			T1	12		T2	2		T3	11
all_values[1]	auto[1]	auto[1]	59948	1			T2	7		T3	15		T12	2
all_values[2]	auto[0]	auto[0]	84154	1			T1	14		T2	1		T3	22
all_values[2]	auto[0]	auto[1]	60020	1			T2	6		T3	17		T12	4
all_values[2]	auto[1]	auto[0]	85524	1			T1	17		T2	1		T3	10
all_values[2]	auto[1]	auto[1]	59883	1			T2	12		T3	11		T12	4
all_values[3]	auto[0]	auto[0]	84378	1			T1	12		T2	2		T3	12
all_values[3]	auto[0]	auto[1]	60012	1			T2	3		T3	13		T12	6
all_values[3]	auto[1]	auto[0]	85368	1			T1	19		T2	2		T3	16
all_values[3]	auto[1]	auto[1]	59823	1			T2	13		T3	19		T12	4