Unified Coverage Report :: Group :: cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

Group : cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_cip_lib_0/cip_base_env_cov.sv

---

Summary for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	8	0	8	100.00
Crosses	16	0	16	100.00

Variables for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
cp_intr_pin	4	0	4	100.00	100	1	1	0
cp_intr_pin_value	4	0	4	100.00	100	1	1	0

Crosses for Group cip_base_pkg::intr_pins_cg::SHAPE{(num_interrupts - 1)=3}

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
cp_intr_pins_all_values	16	0	16	100.00	100	1	1	0

Summary for Variable cp_intr_pin

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	289581	1			T1	31		T2	20		T3	60
all_pins[1]	289581	1			T1	31		T2	20		T3	60
all_pins[2]	289581	1			T1	31		T2	20		T3	60
all_pins[3]	289581	1			T1	31		T2	20		T3	60

---

Summary for Variable cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for cp_intr_pin_value

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
values[0x0]	917215	1			T1	124		T2	34		T3	178
values[0x1]	241109	1			T2	46		T3	62		T12	16
transitions[0x0=>0x1]	159568	1			T2	21		T3	43		T12	11
transitions[0x1=>0x0]	159816	1			T2	22		T3	43		T12	11

---

Summary for Cross cp_intr_pins_all_values

Samples crossed: cp_intr_pin cp_intr_pin_value

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	16	0	16	100.00

Automatically Generated Cross Bins for cp_intr_pins_all_values

Bins

cp_intr_pin	cp_intr_pin_value	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
all_pins[0]	values[0x0]	228126	1			T1	31		T2	6		T3	43
all_pins[0]	values[0x1]	61455	1			T2	14		T3	17		T12	6
all_pins[0]	transitions[0x0=>0x1]	60903	1			T2	4		T3	16		T12	6
all_pins[0]	transitions[0x1=>0x0]	59519	1			T2	4		T3	18		T12	4
all_pins[1]	values[0x0]	229633	1			T1	31		T2	13		T3	45
all_pins[1]	values[0x1]	59948	1			T2	7		T3	15		T12	2
all_pins[1]	transitions[0x0=>0x1]	32670	1			T2	3		T3	6		T15	3
all_pins[1]	transitions[0x1=>0x0]	34177	1			T2	10		T3	8		T12	4
all_pins[2]	values[0x0]	229698	1			T1	31		T2	8		T3	49
all_pins[2]	values[0x1]	59883	1			T2	12		T3	11		T12	4
all_pins[2]	transitions[0x0=>0x1]	33044	1			T2	10		T3	7		T12	3
all_pins[2]	transitions[0x1=>0x0]	33109	1			T2	5		T3	11		T12	1
all_pins[3]	values[0x0]	229758	1			T1	31		T2	7		T3	41
all_pins[3]	values[0x1]	59823	1			T2	13		T3	19		T12	4
all_pins[3]	transitions[0x0=>0x1]	32951	1			T2	4		T3	14		T12	2
all_pins[3]	transitions[0x1=>0x0]	33011	1			T2	3		T3	6		T12	2