Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	24	0	24	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
accum_cnt_cp	6	0	6	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::accum_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	24	0	24	100.00	100	1	1	0

Summary for Variable accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	6	0	6	100.00

User Defined Bins for accum_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
accum_cnt_2000	83281	1			T19	307		T5	352		T27	1
accum_cnt_1000	173070	1			T8	1332		T19	874		T24	33
accum_cnt_100	18180	1			T8	260		T19	54		T24	42
accum_cnt_50	51314	1			T2	47		T3	26		T12	23
accum_cnt_10	178573	1			T1	24		T2	47		T3	72
accum_cnt_0	318901	1			T1	72		T2	42		T3	122

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Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	214574	1			T1	24		T2	34		T3	55
class_index[0x1]	214574	1			T1	24		T2	34		T3	55
class_index[0x2]	214574	1			T1	24		T2	34		T3	55
class_index[0x3]	214574	1			T1	24		T2	34		T3	55

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Summary for Cross class_cnt_cross

Samples crossed: class_index_cp accum_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	24	0	24	100.00

Automatically Generated Cross Bins for class_cnt_cross

Bins

class_index_cp	accum_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	accum_cnt_2000	17094	1			T39	510		T34	650		T81	256
class_index[0x0]	accum_cnt_1000	41415	1			T8	642		T24	20		T20	999
class_index[0x0]	accum_cnt_100	5868	1			T8	142		T24	17		T20	65
class_index[0x0]	accum_cnt_50	19049	1			T2	17		T3	2		T15	3
class_index[0x0]	accum_cnt_10	52279	1			T1	24		T2	9		T3	14
class_index[0x0]	accum_cnt_0	71565	1			T2	8		T3	39		T12	3
class_index[0x1]	accum_cnt_2000	21580	1			T19	307		T27	1		T20	464
class_index[0x1]	accum_cnt_1000	39073	1			T19	874		T5	27		T27	10
class_index[0x1]	accum_cnt_100	3415	1			T19	54		T5	33		T27	1
class_index[0x1]	accum_cnt_50	10027	1			T2	30		T12	9		T4	11
class_index[0x1]	accum_cnt_10	46269	1			T2	4		T3	9		T12	7
class_index[0x1]	accum_cnt_0	87455	1			T1	24		T3	46		T15	2
class_index[0x2]	accum_cnt_2000	22598	1			T5	352		T20	431		T21	692
class_index[0x2]	accum_cnt_1000	45685	1			T8	690		T5	549		T20	388
class_index[0x2]	accum_cnt_100	4316	1			T8	118		T5	33		T20	25
class_index[0x2]	accum_cnt_50	12465	1			T3	22		T12	2		T4	8
class_index[0x2]	accum_cnt_10	37809	1			T2	34		T3	31		T12	10
class_index[0x2]	accum_cnt_0	81682	1			T1	24		T3	2		T12	4
class_index[0x3]	accum_cnt_2000	22009	1			T21	627		T33	575		T87	495
class_index[0x3]	accum_cnt_1000	46897	1			T24	13		T5	8		T16	1052
class_index[0x3]	accum_cnt_100	4581	1			T24	25		T16	122		T21	29
class_index[0x3]	accum_cnt_50	9773	1			T3	2		T12	12		T13	12
class_index[0x3]	accum_cnt_10	42216	1			T3	18		T12	3		T15	21
class_index[0x3]	accum_cnt_0	78199	1			T1	24		T2	34		T3	35