Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	71	0	71	100.00
Crosses	138	0	138	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
alert_index_cp	65	0	65	100.00	100	1	1	0
class_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::alert_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	130	0	130	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	65	0	65	100.00

User Defined Bins for alert_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	8120	1			T4	4		T35	471		T110	215
alert[0x1]	6398	1			T27	22		T21	57		T22	151
alert[0x2]	3157	1			T27	4		T22	61		T33	6
alert[0x3]	2509	1			T15	1		T5	4		T84	10
alert[0x4]	6769	1			T22	557		T35	15		T220	1
alert[0x5]	7756	1			T5	5		T77	5		T33	3
alert[0x6]	7153	1			T22	6		T81	108		T73	2
alert[0x7]	4742	1			T15	23		T22	9		T84	1
alert[0x8]	4961	1			T34	2		T220	1		T241	1
alert[0x9]	7847	1			T5	28		T22	200		T35	53
alert[0xa]	7677	1			T84	2		T31	2		T35	102
alert[0xb]	2896	1			T22	32		T87	3		T220	1
alert[0xc]	9841	1			T84	3		T18	1		T34	3
alert[0xd]	2473	1			T52	11		T84	29		T28	86
alert[0xe]	3858	1			T6	1		T33	4		T84	4
alert[0xf]	2923	1			T17	1		T220	1		T28	1
alert[0x10]	7591	1			T15	9		T17	1		T18	1
alert[0x11]	2871	1			T5	2		T84	9		T34	1
alert[0x12]	6168	1			T6	1		T17	1		T18	1
alert[0x13]	4868	1			T4	2		T22	8		T17	1
alert[0x14]	11446	1			T22	1		T84	3		T17	1
alert[0x15]	9779	1			T5	10		T27	196		T126	1
alert[0x16]	4217	1			T16	1		T84	2		T34	1
alert[0x17]	7371	1			T15	1		T84	3		T31	1
alert[0x18]	9598	1			T15	10		T5	2		T27	14
alert[0x19]	11769	1			T4	9		T18	1		T81	246
alert[0x1a]	3644	1			T22	48		T33	1		T84	1
alert[0x1b]	9560	1			T35	5163		T28	9		T227	2
alert[0x1c]	1709	1			T6	1		T22	4		T84	1
alert[0x1d]	4731	1			T6	1		T22	26		T84	1
alert[0x1e]	2624	1			T6	1		T22	6		T84	1
alert[0x1f]	5619	1			T33	28		T84	6		T31	2
alert[0x20]	7155	1			T35	102		T220	1		T28	121
alert[0x21]	7215	1			T15	2		T18	1		T35	93
alert[0x22]	3316	1			T22	10		T33	20		T84	1
alert[0x23]	15102	1			T35	92		T81	6		T55	3
alert[0x24]	3834	1			T22	2		T33	5		T84	4
alert[0x25]	4149	1			T15	4		T5	1		T35	2
alert[0x26]	3147	1			T22	55		T84	4		T17	1
alert[0x27]	3304	1			T4	2		T5	5		T87	2
alert[0x28]	9549	1			T4	3		T22	96		T33	8
alert[0x29]	2304	1			T27	3		T110	35		T298	1
alert[0x2a]	6054	1			T4	11		T22	9		T31	1
alert[0x2b]	4059	1			T22	5		T35	69		T110	150
alert[0x2c]	5007	1			T8	1		T5	3		T21	2
alert[0x2d]	1729	1			T22	5		T87	1		T220	1
alert[0x2e]	6730	1			T5	3		T18	1		T35	111
alert[0x2f]	3951	1			T22	72		T33	1		T84	1
alert[0x30]	2853	1			T5	1		T84	21		T34	2
alert[0x31]	5326	1			T15	1		T4	1		T27	13
alert[0x32]	5612	1			T27	43		T22	21		T84	1
alert[0x33]	3499	1			T32	1		T18	1		T81	32
alert[0x34]	3379	1			T4	2		T110	28		T81	255
alert[0x35]	1859	1			T4	3		T22	2		T34	6
alert[0x36]	4040	1			T84	1		T18	1		T35	357
alert[0x37]	3319	1			T6	1		T22	2		T33	13
alert[0x38]	6684	1			T15	1		T22	249		T31	2
alert[0x39]	6219	1			T22	6		T84	3		T31	5
alert[0x3a]	4976	1			T33	8		T35	174		T110	34
alert[0x3b]	2865	1			T15	2		T6	2		T4	1
alert[0x3c]	8630	1			T6	1		T22	5		T33	4
alert[0x3d]	4108	1			T34	1		T224	1		T227	1
alert[0x3e]	3081	1			T52	1		T35	180		T81	14
alert[0x3f]	3926	1			T31	1		T35	14		T28	2
alert[0x40]	1889	1			T4	1		T35	116		T28	208

---

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	111152	1			T15	54		T6	1		T27	41
class_i[0x1]	61699	1			T6	7		T4	29		T8	1
class_i[0x2]	88059	1			T5	11		T16	1		T21	59
class_i[0x3]	90605	1			T6	1		T4	10		T22	86

---

Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

alert_integrity_fail

350871

1

T15

54

T4

39

T5

64

alert_ping_fail

644

1

T6

9

T8

1

T16

1

---

Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp alert_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	130	0	130	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	alert_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	alert[0x0]	8109	1			T4	4		T35	471		T110	215
alert_integrity_fail	alert[0x1]	6386	1			T27	22		T21	57		T22	151
alert_integrity_fail	alert[0x2]	3141	1			T27	4		T22	61		T33	6
alert_integrity_fail	alert[0x3]	2502	1			T15	1		T5	4		T84	10
alert_integrity_fail	alert[0x4]	6759	1			T22	557		T35	15		T28	699
alert_integrity_fail	alert[0x5]	7743	1			T5	5		T77	5		T33	3
alert_integrity_fail	alert[0x6]	7139	1			T22	6		T81	108		T59	90
alert_integrity_fail	alert[0x7]	4735	1			T15	23		T22	9		T84	1
alert_integrity_fail	alert[0x8]	4946	1			T34	2		T116	41		T250	62
alert_integrity_fail	alert[0x9]	7839	1			T5	28		T22	200		T35	53
alert_integrity_fail	alert[0xa]	7665	1			T84	2		T31	2		T35	102
alert_integrity_fail	alert[0xb]	2882	1			T22	32		T87	3		T55	17
alert_integrity_fail	alert[0xc]	9829	1			T84	3		T34	3		T250	41
alert_integrity_fail	alert[0xd]	2468	1			T52	11		T84	29		T28	86
alert_integrity_fail	alert[0xe]	3850	1			T33	4		T84	4		T81	2
alert_integrity_fail	alert[0xf]	2914	1			T28	1		T114	1		T250	378
alert_integrity_fail	alert[0x10]	7579	1			T15	9		T28	162		T55	80
alert_integrity_fail	alert[0x11]	2863	1			T5	2		T84	9		T34	1
alert_integrity_fail	alert[0x12]	6153	1			T34	1		T110	5186		T81	11
alert_integrity_fail	alert[0x13]	4856	1			T4	2		T22	8		T31	4
alert_integrity_fail	alert[0x14]	11431	1			T22	1		T84	3		T110	588
alert_integrity_fail	alert[0x15]	9768	1			T5	10		T27	196		T35	405
alert_integrity_fail	alert[0x16]	4206	1			T84	2		T34	1		T110	6
alert_integrity_fail	alert[0x17]	7367	1			T15	1		T84	3		T31	1
alert_integrity_fail	alert[0x18]	9587	1			T15	10		T5	2		T27	14
alert_integrity_fail	alert[0x19]	11760	1			T4	9		T81	246		T116	11
alert_integrity_fail	alert[0x1a]	3637	1			T22	48		T33	1		T84	1
alert_integrity_fail	alert[0x1b]	9546	1			T35	5163		T28	9		T116	163
alert_integrity_fail	alert[0x1c]	1701	1			T22	4		T84	1		T28	457
alert_integrity_fail	alert[0x1d]	4720	1			T22	26		T84	1		T34	8
alert_integrity_fail	alert[0x1e]	2618	1			T22	6		T84	1		T75	2
alert_integrity_fail	alert[0x1f]	5610	1			T33	28		T84	6		T31	2
alert_integrity_fail	alert[0x20]	7144	1			T35	102		T28	121		T36	9
alert_integrity_fail	alert[0x21]	7201	1			T15	2		T35	93		T81	8
alert_integrity_fail	alert[0x22]	3308	1			T22	10		T33	20		T84	1
alert_integrity_fail	alert[0x23]	15094	1			T35	92		T81	6		T55	3
alert_integrity_fail	alert[0x24]	3823	1			T22	2		T33	5		T84	4
alert_integrity_fail	alert[0x25]	4137	1			T15	4		T5	1		T35	2
alert_integrity_fail	alert[0x26]	3139	1			T22	55		T84	4		T35	33
alert_integrity_fail	alert[0x27]	3294	1			T4	2		T5	5		T87	2
alert_integrity_fail	alert[0x28]	9537	1			T4	3		T22	96		T33	8
alert_integrity_fail	alert[0x29]	2295	1			T27	3		T110	35		T55	6
alert_integrity_fail	alert[0x2a]	6046	1			T4	11		T22	9		T31	1
alert_integrity_fail	alert[0x2b]	4048	1			T22	5		T35	69		T110	150
alert_integrity_fail	alert[0x2c]	4992	1			T5	3		T21	2		T22	45
alert_integrity_fail	alert[0x2d]	1722	1			T22	5		T87	1		T81	221
alert_integrity_fail	alert[0x2e]	6717	1			T5	3		T35	111		T81	63
alert_integrity_fail	alert[0x2f]	3937	1			T22	72		T33	1		T84	1
alert_integrity_fail	alert[0x30]	2848	1			T5	1		T84	21		T34	2
alert_integrity_fail	alert[0x31]	5316	1			T15	1		T4	1		T27	13
alert_integrity_fail	alert[0x32]	5610	1			T27	43		T22	21		T84	1
alert_integrity_fail	alert[0x33]	3486	1			T32	1		T81	32		T56	1
alert_integrity_fail	alert[0x34]	3377	1			T4	2		T110	28		T81	255
alert_integrity_fail	alert[0x35]	1852	1			T4	3		T22	2		T34	6
alert_integrity_fail	alert[0x36]	4032	1			T84	1		T35	357		T56	1
alert_integrity_fail	alert[0x37]	3301	1			T22	2		T33	13		T31	2
alert_integrity_fail	alert[0x38]	6668	1			T15	1		T22	249		T31	2
alert_integrity_fail	alert[0x39]	6215	1			T22	6		T84	3		T31	5
alert_integrity_fail	alert[0x3a]	4962	1			T33	8		T35	174		T110	34
alert_integrity_fail	alert[0x3b]	2854	1			T15	2		T4	1		T113	283
alert_integrity_fail	alert[0x3c]	8623	1			T22	5		T33	4		T28	644
alert_integrity_fail	alert[0x3d]	4102	1			T34	1		T56	33		T250	1
alert_integrity_fail	alert[0x3e]	3075	1			T52	1		T35	180		T81	14
alert_integrity_fail	alert[0x3f]	3922	1			T31	1		T35	14		T28	2
alert_integrity_fail	alert[0x40]	1885	1			T4	1		T35	116		T28	208
alert_ping_fail	alert[0x0]	11	1			T220	1		T299	1		T300	1
alert_ping_fail	alert[0x1]	12	1			T224	1		T228	1		T301	1
alert_ping_fail	alert[0x2]	16	1			T17	1		T18	1		T241	2
alert_ping_fail	alert[0x3]	7	1			T220	2		T302	1		T301	1
alert_ping_fail	alert[0x4]	10	1			T220	1		T303	1		T304	1
alert_ping_fail	alert[0x5]	13	1			T241	1		T224	1		T305	1
alert_ping_fail	alert[0x6]	14	1			T73	2		T298	2		T306	1
alert_ping_fail	alert[0x7]	7	1			T17	1		T18	1		T307	1
alert_ping_fail	alert[0x8]	15	1			T220	1		T241	1		T308	2
alert_ping_fail	alert[0x9]	8	1			T241	2		T301	1		T300	1
alert_ping_fail	alert[0xa]	12	1			T302	1		T309	1		T310	1
alert_ping_fail	alert[0xb]	14	1			T220	1		T305	1		T303	1
alert_ping_fail	alert[0xc]	12	1			T18	1		T307	1		T309	1
alert_ping_fail	alert[0xd]	5	1			T305	1		T301	1		T311	1
alert_ping_fail	alert[0xe]	8	1			T6	1		T43	1		T301	1
alert_ping_fail	alert[0xf]	9	1			T17	1		T220	1		T224	1
alert_ping_fail	alert[0x10]	12	1			T17	1		T18	1		T220	1
alert_ping_fail	alert[0x11]	8	1			T224	1		T299	1		T305	1
alert_ping_fail	alert[0x12]	15	1			T6	1		T17	1		T18	1
alert_ping_fail	alert[0x13]	12	1			T17	1		T301	1		T312	1
alert_ping_fail	alert[0x14]	15	1			T17	1		T298	1		T43	1
alert_ping_fail	alert[0x15]	11	1			T126	1		T224	1		T313	1
alert_ping_fail	alert[0x16]	11	1			T16	1		T297	1		T228	1
alert_ping_fail	alert[0x17]	4	1			T298	1		T299	1		T314	1
alert_ping_fail	alert[0x18]	11	1			T220	1		T302	1		T241	1
alert_ping_fail	alert[0x19]	9	1			T18	1		T307	1		T306	1
alert_ping_fail	alert[0x1a]	7	1			T302	1		T43	1		T315	1
alert_ping_fail	alert[0x1b]	14	1			T227	2		T306	1		T228	1
alert_ping_fail	alert[0x1c]	8	1			T6	1		T43	1		T316	1
alert_ping_fail	alert[0x1d]	11	1			T6	1		T17	1		T18	1
alert_ping_fail	alert[0x1e]	6	1			T6	1		T18	1		T317	1
alert_ping_fail	alert[0x1f]	9	1			T297	1		T224	1		T318	2
alert_ping_fail	alert[0x20]	11	1			T220	1		T307	1		T224	1
alert_ping_fail	alert[0x21]	14	1			T18	1		T241	2		T305	1
alert_ping_fail	alert[0x22]	8	1			T18	1		T302	1		T241	1
alert_ping_fail	alert[0x23]	8	1			T301	1		T319	1		T318	2
alert_ping_fail	alert[0x24]	11	1			T18	1		T227	1		T43	1
alert_ping_fail	alert[0x25]	12	1			T307	1		T298	1		T300	1
alert_ping_fail	alert[0x26]	8	1			T17	1		T220	1		T302	1
alert_ping_fail	alert[0x27]	10	1			T299	1		T305	1		T301	1
alert_ping_fail	alert[0x28]	12	1			T126	1		T241	1		T228	1
alert_ping_fail	alert[0x29]	9	1			T298	1		T300	1		T320	1
alert_ping_fail	alert[0x2a]	8	1			T302	1		T241	1		T314	1
alert_ping_fail	alert[0x2b]	11	1			T220	1		T224	1		T227	2
alert_ping_fail	alert[0x2c]	15	1			T8	1		T297	1		T224	1
alert_ping_fail	alert[0x2d]	7	1			T220	1		T224	1		T299	1
alert_ping_fail	alert[0x2e]	13	1			T18	1		T220	1		T70	1
alert_ping_fail	alert[0x2f]	14	1			T296	2		T228	1		T321	1
alert_ping_fail	alert[0x30]	5	1			T227	1		T309	1		T303	1
alert_ping_fail	alert[0x31]	10	1			T302	1		T307	1		T43	1
alert_ping_fail	alert[0x32]	2	1			T314	1		T322	1		-	-
alert_ping_fail	alert[0x33]	13	1			T18	1		T224	2		T313	1
alert_ping_fail	alert[0x34]	2	1			T323	1		T324	1		-	-
alert_ping_fail	alert[0x35]	7	1			T227	1		T228	1		T300	1
alert_ping_fail	alert[0x36]	8	1			T18	1		T307	1		T43	2
alert_ping_fail	alert[0x37]	18	1			T6	1		T18	1		T220	1
alert_ping_fail	alert[0x38]	16	1			T18	1		T298	1		T227	2
alert_ping_fail	alert[0x39]	4	1			T315	1		T325	1		T326	1
alert_ping_fail	alert[0x3a]	14	1			T307	1		T228	1		T301	3
alert_ping_fail	alert[0x3b]	11	1			T6	2		T301	1		T300	1
alert_ping_fail	alert[0x3c]	7	1			T6	1		T227	2		T301	1
alert_ping_fail	alert[0x3d]	6	1			T224	1		T227	1		T313	1
alert_ping_fail	alert[0x3e]	6	1			T301	1		T319	1		T327	1
alert_ping_fail	alert[0x3f]	4	1			T312	1		T311	1		T328	1
alert_ping_fail	alert[0x40]	4	1			T329	1		T330	1		T311	1

---

Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert_integrity_fail	class_i[0x0]	110996	1			T15	54		T27	41		T22	11
alert_integrity_fail	class_i[0x1]	61538	1			T4	29		T5	53		T27	254
alert_integrity_fail	class_i[0x2]	87833	1			T5	11		T21	59		T22	1139
alert_integrity_fail	class_i[0x3]	90504	1			T4	10		T22	86		T33	24
alert_ping_fail	class_i[0x0]	156	1			T6	1		T17	8		T18	16
alert_ping_fail	class_i[0x1]	161	1			T6	7		T8	1		T220	1
alert_ping_fail	class_i[0x2]	226	1			T16	1		T126	2		T307	9
alert_ping_fail	class_i[0x3]	101	1			T6	1		T17	1		T220	1