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Total Coverage Summary 
SCORELINECONDTOGGLEFSMBRANCHASSERTGROUP
99.23 99.99 98.75 97.09 100.00 100.00 99.38 99.44


Total test records in report: 836
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T774 /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.3636110360 Aug 15 04:59:06 PM PDT 24 Aug 15 04:59:14 PM PDT 24 280005858 ps
T775 /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.57125866 Aug 15 04:58:30 PM PDT 24 Aug 15 04:59:18 PM PDT 24 2764084405 ps
T776 /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.3716378675 Aug 15 04:58:31 PM PDT 24 Aug 15 04:58:33 PM PDT 24 7852762 ps
T777 /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.2967739374 Aug 15 04:58:11 PM PDT 24 Aug 15 04:58:22 PM PDT 24 208403580 ps
T177 /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.941974511 Aug 15 04:58:05 PM PDT 24 Aug 15 04:58:37 PM PDT 24 895628923 ps
T778 /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.36819593 Aug 15 04:58:40 PM PDT 24 Aug 15 04:58:45 PM PDT 24 37802229 ps
T779 /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.1267498466 Aug 15 04:58:04 PM PDT 24 Aug 15 04:58:07 PM PDT 24 19803920 ps
T780 /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.1206172959 Aug 15 04:59:05 PM PDT 24 Aug 15 04:59:07 PM PDT 24 11872214 ps
T781 /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.2265623698 Aug 15 04:59:15 PM PDT 24 Aug 15 04:59:17 PM PDT 24 18617821 ps
T141 /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.2536244299 Aug 15 04:58:13 PM PDT 24 Aug 15 05:00:05 PM PDT 24 10279628548 ps
T171 /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.3581034170 Aug 15 04:58:21 PM PDT 24 Aug 15 04:58:24 PM PDT 24 22293627 ps
T147 /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.3053939089 Aug 15 04:58:37 PM PDT 24 Aug 15 05:03:22 PM PDT 24 4194824293 ps
T157 /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.2210011405 Aug 15 04:57:40 PM PDT 24 Aug 15 05:06:03 PM PDT 24 7394163294 ps
T782 /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.265646867 Aug 15 04:58:04 PM PDT 24 Aug 15 05:04:02 PM PDT 24 41595830530 ps
T783 /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.2426972076 Aug 15 04:58:49 PM PDT 24 Aug 15 04:58:55 PM PDT 24 36556253 ps
T784 /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.2013532856 Aug 15 04:57:40 PM PDT 24 Aug 15 04:58:06 PM PDT 24 173674752 ps
T785 /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.4205427298 Aug 15 04:58:12 PM PDT 24 Aug 15 04:58:17 PM PDT 24 51867065 ps
T786 /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.4093195387 Aug 15 04:58:38 PM PDT 24 Aug 15 04:59:02 PM PDT 24 186787905 ps
T154 /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.3748702207 Aug 15 04:58:31 PM PDT 24 Aug 15 05:14:09 PM PDT 24 81639058393 ps
T787 /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.1854146372 Aug 15 04:58:59 PM PDT 24 Aug 15 04:59:35 PM PDT 24 1840689382 ps
T152 /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.1998693116 Aug 15 04:58:40 PM PDT 24 Aug 15 05:09:54 PM PDT 24 4718694511 ps
T788 /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.1468307438 Aug 15 04:58:30 PM PDT 24 Aug 15 04:58:39 PM PDT 24 214336476 ps
T789 /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.3589975059 Aug 15 04:58:21 PM PDT 24 Aug 15 04:58:25 PM PDT 24 34969498 ps
T790 /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.4177765305 Aug 15 04:58:48 PM PDT 24 Aug 15 04:58:57 PM PDT 24 124183924 ps
T150 /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.2191927489 Aug 15 04:58:20 PM PDT 24 Aug 15 05:03:51 PM PDT 24 4675363723 ps
T791 /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.3629628955 Aug 15 04:58:56 PM PDT 24 Aug 15 04:59:22 PM PDT 24 359005257 ps
T146 /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.2639712182 Aug 15 04:58:31 PM PDT 24 Aug 15 05:00:07 PM PDT 24 928508547 ps
T792 /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.2319587787 Aug 15 04:57:57 PM PDT 24 Aug 15 04:58:01 PM PDT 24 68604281 ps
T151 /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.610064877 Aug 15 04:58:11 PM PDT 24 Aug 15 05:00:35 PM PDT 24 8696420130 ps
T155 /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.746583553 Aug 15 04:58:05 PM PDT 24 Aug 15 05:14:37 PM PDT 24 57326372585 ps
T164 /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.2357748714 Aug 15 04:57:45 PM PDT 24 Aug 15 05:00:11 PM PDT 24 2111175058 ps
T174 /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.1340853063 Aug 15 04:58:35 PM PDT 24 Aug 15 04:59:45 PM PDT 24 2226479096 ps
T793 /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.2043599794 Aug 15 04:58:15 PM PDT 24 Aug 15 04:58:19 PM PDT 24 67399272 ps
T794 /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.3217778549 Aug 15 04:57:58 PM PDT 24 Aug 15 04:58:11 PM PDT 24 960566591 ps
T795 /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.2930379829 Aug 15 04:59:06 PM PDT 24 Aug 15 04:59:08 PM PDT 24 28988681 ps
T796 /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.2619212524 Aug 15 04:58:31 PM PDT 24 Aug 15 04:58:54 PM PDT 24 157269610 ps
T160 /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.157005461 Aug 15 04:58:13 PM PDT 24 Aug 15 05:16:50 PM PDT 24 243273891849 ps
T797 /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.2373159553 Aug 15 04:57:47 PM PDT 24 Aug 15 04:57:53 PM PDT 24 144789758 ps
T798 /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.2246874901 Aug 15 04:58:34 PM PDT 24 Aug 15 04:58:40 PM PDT 24 42338297 ps
T799 /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.1000035488 Aug 15 04:58:39 PM PDT 24 Aug 15 04:59:01 PM PDT 24 466351442 ps
T800 /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.3491942018 Aug 15 04:58:31 PM PDT 24 Aug 15 04:58:59 PM PDT 24 1281322467 ps
T801 /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.1939641048 Aug 15 04:59:06 PM PDT 24 Aug 15 04:59:52 PM PDT 24 2671244992 ps
T802 /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.1010004678 Aug 15 04:58:47 PM PDT 24 Aug 15 04:59:01 PM PDT 24 189197391 ps
T803 /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.1479617684 Aug 15 04:59:04 PM PDT 24 Aug 15 04:59:31 PM PDT 24 1098826191 ps
T161 /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.3558067050 Aug 15 04:58:58 PM PDT 24 Aug 15 05:03:36 PM PDT 24 14289443772 ps
T804 /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.2143386926 Aug 15 04:58:30 PM PDT 24 Aug 15 04:58:38 PM PDT 24 77266656 ps
T805 /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.3926171899 Aug 15 04:59:13 PM PDT 24 Aug 15 04:59:15 PM PDT 24 13698661 ps
T806 /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.430448254 Aug 15 04:59:14 PM PDT 24 Aug 15 04:59:16 PM PDT 24 16370245 ps
T807 /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.1214996249 Aug 15 04:58:41 PM PDT 24 Aug 15 04:58:49 PM PDT 24 317376820 ps
T808 /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.3749153186 Aug 15 04:59:18 PM PDT 24 Aug 15 04:59:19 PM PDT 24 10516193 ps
T809 /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.1511809742 Aug 15 04:58:57 PM PDT 24 Aug 15 04:59:02 PM PDT 24 37606856 ps
T810 /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.3197287802 Aug 15 04:58:12 PM PDT 24 Aug 15 04:58:33 PM PDT 24 497703077 ps
T811 /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.1145647367 Aug 15 04:57:41 PM PDT 24 Aug 15 04:57:47 PM PDT 24 66718738 ps
T812 /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.3026859817 Aug 15 04:59:14 PM PDT 24 Aug 15 04:59:16 PM PDT 24 9919259 ps
T813 /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.57069397 Aug 15 04:57:58 PM PDT 24 Aug 15 04:58:00 PM PDT 24 13140298 ps
T814 /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.482154648 Aug 15 04:58:22 PM PDT 24 Aug 15 04:58:28 PM PDT 24 68034934 ps
T815 /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.1802177551 Aug 15 04:58:31 PM PDT 24 Aug 15 04:58:47 PM PDT 24 876453508 ps
T181 /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.416661400 Aug 15 04:58:59 PM PDT 24 Aug 15 04:59:07 PM PDT 24 154885782 ps
T816 /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.4096344980 Aug 15 04:58:58 PM PDT 24 Aug 15 04:59:03 PM PDT 24 127222529 ps
T139 /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.3511796841 Aug 15 04:58:02 PM PDT 24 Aug 15 05:04:00 PM PDT 24 2317856250 ps
T156 /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.2898919830 Aug 15 04:58:32 PM PDT 24 Aug 15 05:04:51 PM PDT 24 4413867917 ps
T817 /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.1190988221 Aug 15 04:57:41 PM PDT 24 Aug 15 04:57:46 PM PDT 24 172282035 ps
T818 /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.1547323488 Aug 15 04:58:30 PM PDT 24 Aug 15 04:58:52 PM PDT 24 323235773 ps
T819 /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.2580205020 Aug 15 04:59:15 PM PDT 24 Aug 15 04:59:17 PM PDT 24 11318663 ps
T159 /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.3567282047 Aug 15 04:58:34 PM PDT 24 Aug 15 05:01:40 PM PDT 24 3297157106 ps
T820 /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.1777888224 Aug 15 04:59:05 PM PDT 24 Aug 15 04:59:07 PM PDT 24 24307818 ps
T821 /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.1620484682 Aug 15 04:57:47 PM PDT 24 Aug 15 04:57:53 PM PDT 24 180184240 ps
T822 /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.431926210 Aug 15 04:58:12 PM PDT 24 Aug 15 04:58:17 PM PDT 24 202364435 ps
T823 /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.3961947005 Aug 15 04:57:48 PM PDT 24 Aug 15 05:04:02 PM PDT 24 18446814630 ps
T824 /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.3676819957 Aug 15 04:57:51 PM PDT 24 Aug 15 04:57:57 PM PDT 24 127920136 ps
T825 /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.157453204 Aug 15 04:58:21 PM PDT 24 Aug 15 05:06:15 PM PDT 24 6959471680 ps
T826 /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.2011718081 Aug 15 04:57:51 PM PDT 24 Aug 15 04:57:59 PM PDT 24 404286047 ps
T827 /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.2034756320 Aug 15 04:59:06 PM PDT 24 Aug 15 04:59:21 PM PDT 24 205095095 ps
T162 /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.3357997160 Aug 15 04:58:31 PM PDT 24 Aug 15 05:03:28 PM PDT 24 7597097881 ps
T355 /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.4084736264 Aug 15 04:58:49 PM PDT 24 Aug 15 05:17:12 PM PDT 24 60909392207 ps
T828 /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.2802934145 Aug 15 04:58:39 PM PDT 24 Aug 15 04:58:40 PM PDT 24 44839034 ps
T158 /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.337324029 Aug 15 04:58:04 PM PDT 24 Aug 15 05:03:38 PM PDT 24 4921336099 ps
T829 /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.1932241588 Aug 15 04:59:06 PM PDT 24 Aug 15 04:59:08 PM PDT 24 12524115 ps
T830 /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.2228220557 Aug 15 04:58:48 PM PDT 24 Aug 15 04:58:50 PM PDT 24 8531110 ps
T831 /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.1047831273 Aug 15 04:59:13 PM PDT 24 Aug 15 04:59:15 PM PDT 24 18479223 ps
T832 /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.1738546979 Aug 15 04:59:05 PM PDT 24 Aug 15 04:59:07 PM PDT 24 11444465 ps
T833 /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.3245950994 Aug 15 04:57:47 PM PDT 24 Aug 15 04:57:48 PM PDT 24 12578681 ps
T163 /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.3840048395 Aug 15 04:58:30 PM PDT 24 Aug 15 05:00:14 PM PDT 24 9512316471 ps
T834 /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.618531524 Aug 15 04:58:13 PM PDT 24 Aug 15 04:58:53 PM PDT 24 924091299 ps
T835 /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.59332874 Aug 15 04:58:12 PM PDT 24 Aug 15 04:58:48 PM PDT 24 1354771994 ps
T836 /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.2628420102 Aug 15 04:58:05 PM PDT 24 Aug 15 04:58:12 PM PDT 24 267353093 ps

Test location /workspace/coverage/default/48.alert_handler_stress_all_with_rand_reset.229515561
Short name T4
Test name
Test status
Simulation time 5054221337 ps
CPU time 358.53 seconds
Started Aug 15 05:04:44 PM PDT 24
Finished Aug 15 05:10:43 PM PDT 24
Peak memory 272848 kb
Host smart-c105f596-21f5-48e8-b8af-9179fc9db171
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=229515561 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 48.alert_handler_stress_all_with_rand_reset.229515561
Directory /workspace/48.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all_with_rand_reset.1177683903
Short name T22
Test name
Test status
Simulation time 3983809498 ps
CPU time 497.7 seconds
Started Aug 15 05:01:22 PM PDT 24
Finished Aug 15 05:09:40 PM PDT 24
Peak memory 271684 kb
Host smart-50ae25b5-823b-40f0-9e88-d67cf0382f7d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1177683903 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 21.alert_handler_stress_all_with_rand_reset.1177683903
Directory /workspace/21.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all.1110356097
Short name T35
Test name
Test status
Simulation time 104377696308 ps
CPU time 1781.5 seconds
Started Aug 15 05:00:53 PM PDT 24
Finished Aug 15 05:30:36 PM PDT 24
Peak memory 289640 kb
Host smart-8988a14a-1c7e-4c4a-b525-3553304652cc
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1110356097 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_ha
ndler_stress_all.1110356097
Directory /workspace/17.alert_handler_stress_all/latest

Test location /workspace/coverage/default/1.alert_handler_sec_cm.2299931667
Short name T10
Test name
Test status
Simulation time 927189403 ps
CPU time 13.86 seconds
Started Aug 15 04:59:36 PM PDT 24
Finished Aug 15 04:59:50 PM PDT 24
Peak memory 271308 kb
Host smart-4244b544-0972-4152-a52e-e1abe3106482
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=2299931667 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sec_cm.2299931667
Directory /workspace/1.alert_handler_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_mem_rw_with_rand_reset.432212737
Short name T197
Test name
Test status
Simulation time 609699703 ps
CPU time 11.76 seconds
Started Aug 15 04:57:40 PM PDT 24
Finished Aug 15 04:57:52 PM PDT 24
Peak memory 256700 kb
Host smart-f612f9a9-e377-43be-9b56-2c9a97393330
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=432212737 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 0.alert_handler_csr_mem_rw_with_rand_reset.432212737
Directory /workspace/0.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/default/13.alert_handler_entropy_stress.3434766020
Short name T96
Test name
Test status
Simulation time 239708759 ps
CPU time 11.84 seconds
Started Aug 15 05:00:37 PM PDT 24
Finished Aug 15 05:00:49 PM PDT 24
Peak memory 248652 kb
Host smart-b47b9e81-43cf-4dbe-870e-359f375a63b0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3434766020 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy_stress.3434766020
Directory /workspace/13.alert_handler_entropy_stress/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors_with_csr_rw.2119660710
Short name T133
Test name
Test status
Simulation time 99602364253 ps
CPU time 1006.77 seconds
Started Aug 15 04:58:48 PM PDT 24
Finished Aug 15 05:15:35 PM PDT 24
Peak memory 265888 kb
Host smart-52461b06-a07f-484e-ac26-41d67c50c192
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2119660710 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 15.alert_handler_shadow_reg_errors_with_csr_rw.2119660710
Directory /workspace/15.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all_with_rand_reset.2042894827
Short name T36
Test name
Test status
Simulation time 14665928399 ps
CPU time 235.37 seconds
Started Aug 15 05:04:01 PM PDT 24
Finished Aug 15 05:07:56 PM PDT 24
Peak memory 268624 kb
Host smart-3c1c4e36-23b5-4acd-adb5-38de785c47ad
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2042894827 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 43.alert_handler_stress_all_with_rand_reset.2042894827
Directory /workspace/43.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.alert_handler_lpg_stub_clk.3490361730
Short name T107
Test name
Test status
Simulation time 35719106240 ps
CPU time 1061.62 seconds
Started Aug 15 05:00:13 PM PDT 24
Finished Aug 15 05:17:55 PM PDT 24
Peak memory 265204 kb
Host smart-50e4a3c9-1c9a-4f4a-8c29-22f0355aaf0b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3490361730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg_stub_clk.3490361730
Directory /workspace/9.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_lpg.2162728723
Short name T16
Test name
Test status
Simulation time 232136645862 ps
CPU time 3366.81 seconds
Started Aug 15 05:00:55 PM PDT 24
Finished Aug 15 05:57:02 PM PDT 24
Peak memory 288328 kb
Host smart-eb6af807-e06b-4587-8bb3-4869c17fd9d4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2162728723 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg.2162728723
Directory /workspace/17.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all.160365412
Short name T81
Test name
Test status
Simulation time 145110311644 ps
CPU time 1226.77 seconds
Started Aug 15 05:02:19 PM PDT 24
Finished Aug 15 05:22:46 PM PDT 24
Peak memory 286544 kb
Host smart-f68f9c9a-d0e0-4707-ae18-0e358797ede9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=160365412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_han
dler_stress_all.160365412
Directory /workspace/29.alert_handler_stress_all/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all_with_rand_reset.1794211100
Short name T124
Test name
Test status
Simulation time 20774320947 ps
CPU time 381.51 seconds
Started Aug 15 05:04:36 PM PDT 24
Finished Aug 15 05:10:58 PM PDT 24
Peak memory 267616 kb
Host smart-b406b7c3-f613-43ae-bcce-fda2337d9c0d
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1794211100 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 47.alert_handler_stress_all_with_rand_reset.1794211100
Directory /workspace/47.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors.1688465498
Short name T135
Test name
Test status
Simulation time 9478307509 ps
CPU time 314.56 seconds
Started Aug 15 04:58:22 PM PDT 24
Finished Aug 15 05:03:37 PM PDT 24
Peak memory 265764 kb
Host smart-bc035be2-bc43-4b77-922f-ae9847fb329f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1688465498 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_shadow_reg_erro
rs.1688465498
Directory /workspace/8.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_intg_err.3705791841
Short name T167
Test name
Test status
Simulation time 218231719 ps
CPU time 25.92 seconds
Started Aug 15 04:58:39 PM PDT 24
Finished Aug 15 04:59:05 PM PDT 24
Peak memory 240684 kb
Host smart-97dc5abf-ff9e-419a-854a-a50c967b8c6d
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3705791841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_intg_err.3705791841
Directory /workspace/13.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors_with_csr_rw.4078869535
Short name T142
Test name
Test status
Simulation time 5813427301 ps
CPU time 595.12 seconds
Started Aug 15 04:59:06 PM PDT 24
Finished Aug 15 05:09:02 PM PDT 24
Peak memory 273032 kb
Host smart-2aa70592-75c0-4a6a-a79e-3dc7494fa0c8
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4078869535 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 19.alert_handler_shadow_reg_errors_with_csr_rw.4078869535
Directory /workspace/19.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/38.alert_handler_entropy.3498398133
Short name T116
Test name
Test status
Simulation time 21118708967 ps
CPU time 1318.45 seconds
Started Aug 15 05:03:26 PM PDT 24
Finished Aug 15 05:25:25 PM PDT 24
Peak memory 273188 kb
Host smart-41b03d56-f78a-4c47-b1ff-fdc6e3ddb79c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3498398133 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_entropy.3498398133
Directory /workspace/38.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors_with_csr_rw.746583553
Short name T155
Test name
Test status
Simulation time 57326372585 ps
CPU time 992.28 seconds
Started Aug 15 04:58:05 PM PDT 24
Finished Aug 15 05:14:37 PM PDT 24
Peak memory 265708 kb
Host smart-5035b165-144d-4716-8f2f-c44c3b180da5
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=746583553 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 4.alert_handler_shadow_reg_errors_with_csr_rw.746583553
Directory /workspace/4.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/10.alert_handler_lpg.888904371
Short name T333
Test name
Test status
Simulation time 190717959607 ps
CPU time 2749.4 seconds
Started Aug 15 05:00:21 PM PDT 24
Finished Aug 15 05:46:11 PM PDT 24
Peak memory 287348 kb
Host smart-2a7d59b6-5e03-4141-a4b4-a55cb0f079db
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=888904371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg.888904371
Directory /workspace/10.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all.3343818099
Short name T5
Test name
Test status
Simulation time 9678366935 ps
CPU time 1017.92 seconds
Started Aug 15 05:00:00 PM PDT 24
Finished Aug 15 05:16:58 PM PDT 24
Peak memory 286672 kb
Host smart-12b24e45-6654-41a0-bb63-73f972bd9516
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3343818099 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_han
dler_stress_all.3343818099
Directory /workspace/6.alert_handler_stress_all/latest

Test location /workspace/coverage/default/10.alert_handler_ping_timeout.2083089143
Short name T220
Test name
Test status
Simulation time 21351271842 ps
CPU time 469.03 seconds
Started Aug 15 05:00:25 PM PDT 24
Finished Aug 15 05:08:15 PM PDT 24
Peak memory 248824 kb
Host smart-00e0af57-c2fc-417e-9f12-c7207d74946f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2083089143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_ping_timeout.2083089143
Directory /workspace/10.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/33.alert_handler_intr_test.3922228875
Short name T348
Test name
Test status
Simulation time 12216312 ps
CPU time 1.45 seconds
Started Aug 15 04:59:15 PM PDT 24
Finished Aug 15 04:59:17 PM PDT 24
Peak memory 236828 kb
Host smart-e8096823-04ad-4def-941e-dbcee2891b7b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3922228875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 33.alert_handler_intr_test.3922228875
Directory /workspace/33.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors.3357997160
Short name T162
Test name
Test status
Simulation time 7597097881 ps
CPU time 296.78 seconds
Started Aug 15 04:58:31 PM PDT 24
Finished Aug 15 05:03:28 PM PDT 24
Peak memory 265652 kb
Host smart-53201da8-d618-4dbb-af23-8164102779eb
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3357997160 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_shadow_reg_err
ors.3357997160
Directory /workspace/12.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors.2713975055
Short name T128
Test name
Test status
Simulation time 16633852655 ps
CPU time 127.19 seconds
Started Aug 15 04:58:57 PM PDT 24
Finished Aug 15 05:01:05 PM PDT 24
Peak memory 265548 kb
Host smart-b0215870-6931-46b5-af5e-5dfb54863226
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2713975055 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_shadow_reg_err
ors.2713975055
Directory /workspace/17.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/12.alert_handler_lpg.1162886241
Short name T225
Test name
Test status
Simulation time 166440486255 ps
CPU time 2567.82 seconds
Started Aug 15 05:00:29 PM PDT 24
Finished Aug 15 05:43:17 PM PDT 24
Peak memory 289780 kb
Host smart-fc293ab0-e17c-499d-8ad5-77860969bdbc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1162886241 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg.1162886241
Directory /workspace/12.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_ping_timeout.3443068248
Short name T301
Test name
Test status
Simulation time 15570571519 ps
CPU time 491.09 seconds
Started Aug 15 05:02:10 PM PDT 24
Finished Aug 15 05:10:21 PM PDT 24
Peak memory 248668 kb
Host smart-ff4475ae-77cd-43f6-8b74-9573538aa7d7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3443068248 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_ping_timeout.3443068248
Directory /workspace/28.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all.1883735036
Short name T34
Test name
Test status
Simulation time 194510613975 ps
CPU time 1857.75 seconds
Started Aug 15 05:03:44 PM PDT 24
Finished Aug 15 05:34:42 PM PDT 24
Peak memory 289168 kb
Host smart-b42d40ce-c6fe-4aa7-a103-59eb52e80225
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1883735036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_ha
ndler_stress_all.1883735036
Directory /workspace/41.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_ping_timeout.1380513034
Short name T314
Test name
Test status
Simulation time 11838170186 ps
CPU time 450.02 seconds
Started Aug 15 05:00:00 PM PDT 24
Finished Aug 15 05:07:30 PM PDT 24
Peak memory 247728 kb
Host smart-7b594598-9a91-453a-a4e0-88e1c863163d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1380513034 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_ping_timeout.1380513034
Directory /workspace/8.alert_handler_ping_timeout/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors_with_csr_rw.1948719479
Short name T148
Test name
Test status
Simulation time 32505397511 ps
CPU time 1300.02 seconds
Started Aug 15 04:58:41 PM PDT 24
Finished Aug 15 05:20:21 PM PDT 24
Peak memory 265612 kb
Host smart-76314d41-0943-483d-acdd-5d28db4ad166
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1948719479 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 13.alert_handler_shadow_reg_errors_with_csr_rw.1948719479
Directory /workspace/13.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/34.alert_handler_lpg.1199827826
Short name T7
Test name
Test status
Simulation time 111470253648 ps
CPU time 1852.01 seconds
Started Aug 15 05:02:54 PM PDT 24
Finished Aug 15 05:33:46 PM PDT 24
Peak memory 273324 kb
Host smart-2edfe1c2-4238-4a36-b427-ee92d5d16bac
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1199827826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg.1199827826
Directory /workspace/34.alert_handler_lpg/latest

Test location /workspace/coverage/default/14.alert_handler_ping_timeout.3622946815
Short name T311
Test name
Test status
Simulation time 66061296908 ps
CPU time 730.06 seconds
Started Aug 15 05:00:38 PM PDT 24
Finished Aug 15 05:12:49 PM PDT 24
Peak memory 248840 kb
Host smart-7cb32edd-17f7-4d91-bcda-7780c7747d07
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3622946815 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_ping_timeout.3622946815
Directory /workspace/14.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg.3897951985
Short name T282
Test name
Test status
Simulation time 400214055131 ps
CPU time 1932.61 seconds
Started Aug 15 04:59:34 PM PDT 24
Finished Aug 15 05:31:47 PM PDT 24
Peak memory 273396 kb
Host smart-4d230621-23cf-4359-a3eb-7326bef59a92
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3897951985 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg.3897951985
Directory /workspace/3.alert_handler_lpg/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all.4016988684
Short name T105
Test name
Test status
Simulation time 37328773540 ps
CPU time 1548.5 seconds
Started Aug 15 05:00:26 PM PDT 24
Finished Aug 15 05:26:15 PM PDT 24
Peak memory 305356 kb
Host smart-cacd9a80-e854-424a-890d-222e08772f9d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4016988684 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_ha
ndler_stress_all.4016988684
Directory /workspace/12.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_intg_err.274817840
Short name T175
Test name
Test status
Simulation time 309893604 ps
CPU time 43.5 seconds
Started Aug 15 04:57:49 PM PDT 24
Finished Aug 15 04:58:32 PM PDT 24
Peak memory 240604 kb
Host smart-ec7f0d96-421a-4d03-9a93-44a5b556ff59
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=274817840 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_intg_err.274817840
Directory /workspace/1.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/22.alert_handler_entropy.3854828847
Short name T60
Test name
Test status
Simulation time 38014959219 ps
CPU time 2005.8 seconds
Started Aug 15 05:01:33 PM PDT 24
Finished Aug 15 05:34:59 PM PDT 24
Peak memory 289180 kb
Host smart-9dc22151-ce79-4f33-bda7-b4370591a962
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3854828847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_entropy.3854828847
Directory /workspace/22.alert_handler_entropy/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors.3567282047
Short name T159
Test name
Test status
Simulation time 3297157106 ps
CPU time 185.73 seconds
Started Aug 15 04:58:34 PM PDT 24
Finished Aug 15 05:01:40 PM PDT 24
Peak memory 270280 kb
Host smart-04993438-09e8-4d07-9f2c-1987b9d17b4e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3567282047 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_shadow_reg_err
ors.3567282047
Directory /workspace/11.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/48.alert_handler_intr_test.3838177438
Short name T352
Test name
Test status
Simulation time 11767785 ps
CPU time 1.29 seconds
Started Aug 15 04:59:14 PM PDT 24
Finished Aug 15 04:59:15 PM PDT 24
Peak memory 236796 kb
Host smart-2fb6d06c-7f5d-4812-9590-2fcdefc2b7b7
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3838177438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 48.alert_handler_intr_test.3838177438
Directory /workspace/48.alert_handler_intr_test/latest

Test location /workspace/coverage/default/0.alert_handler_stress_all.2986976258
Short name T471
Test name
Test status
Simulation time 147310679690 ps
CPU time 2535.06 seconds
Started Aug 15 04:59:22 PM PDT 24
Finished Aug 15 05:41:38 PM PDT 24
Peak memory 289536 kb
Host smart-64e5c851-ba29-4730-aa79-f54a4f76d50a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2986976258 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_han
dler_stress_all.2986976258
Directory /workspace/0.alert_handler_stress_all/latest

Test location /workspace/coverage/default/13.alert_handler_lpg.338500538
Short name T336
Test name
Test status
Simulation time 29979516357 ps
CPU time 1936.89 seconds
Started Aug 15 05:00:37 PM PDT 24
Finished Aug 15 05:32:55 PM PDT 24
Peak memory 283980 kb
Host smart-f69d48fd-ff77-4f83-8a65-842d8d3f3b68
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=338500538 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg.338500538
Directory /workspace/13.alert_handler_lpg/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors_with_csr_rw.2026032557
Short name T136
Test name
Test status
Simulation time 49093515893 ps
CPU time 943.83 seconds
Started Aug 15 04:57:46 PM PDT 24
Finished Aug 15 05:13:31 PM PDT 24
Peak memory 265588 kb
Host smart-f88149e8-4ee0-4aaf-ad54-7eb1afc47af4
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2026032557 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 1.alert_handler_shadow_reg_errors_with_csr_rw.2026032557
Directory /workspace/1.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/27.alert_handler_stress_all.61710311
Short name T114
Test name
Test status
Simulation time 116722920484 ps
CPU time 1180.45 seconds
Started Aug 15 05:02:06 PM PDT 24
Finished Aug 15 05:21:47 PM PDT 24
Peak memory 281700 kb
Host smart-2448e32f-07ff-4bab-9b4b-82c036d65ae0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=61710311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_hand
ler_stress_all.61710311
Directory /workspace/27.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_lpg.4047736191
Short name T696
Test name
Test status
Simulation time 245420034045 ps
CPU time 2169.4 seconds
Started Aug 15 05:01:14 PM PDT 24
Finished Aug 15 05:37:24 PM PDT 24
Peak memory 289172 kb
Host smart-dfa3c606-dce2-473f-80a7-2e2a52c22d3f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4047736191 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg.4047736191
Directory /workspace/19.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_stress_all_with_rand_reset.241848541
Short name T262
Test name
Test status
Simulation time 10253630939 ps
CPU time 161.12 seconds
Started Aug 15 05:02:27 PM PDT 24
Finished Aug 15 05:05:08 PM PDT 24
Peak memory 265268 kb
Host smart-629c935e-d6df-4d75-a0f7-2c091cd9f7d2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=241848541 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 31.alert_handler_stress_all_with_rand_reset.241848541
Directory /workspace/31.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.alert_handler_ping_timeout.2628941729
Short name T298
Test name
Test status
Simulation time 18084897323 ps
CPU time 160.18 seconds
Started Aug 15 04:59:48 PM PDT 24
Finished Aug 15 05:02:28 PM PDT 24
Peak memory 255180 kb
Host smart-89d65c7f-22d1-49e6-8691-f8bba8ce5854
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2628941729 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_ping_timeout.2628941729
Directory /workspace/6.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all_with_rand_reset.3395193922
Short name T32
Test name
Test status
Simulation time 9057357715 ps
CPU time 148.19 seconds
Started Aug 15 05:00:53 PM PDT 24
Finished Aug 15 05:03:21 PM PDT 24
Peak memory 265972 kb
Host smart-ff66514c-91a5-4819-8f63-8283233060fc
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3395193922 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 14.alert_handler_stress_all_with_rand_reset.3395193922
Directory /workspace/14.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_intg_err.2942725950
Short name T180
Test name
Test status
Simulation time 38667485 ps
CPU time 2.86 seconds
Started Aug 15 04:57:48 PM PDT 24
Finished Aug 15 04:57:51 PM PDT 24
Peak memory 238056 kb
Host smart-f7420c77-28ee-41f0-9b88-4d4ff837c4b5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2942725950 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_intg_err.2942725950
Directory /workspace/2.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/default/2.alert_handler_sec_cm.643703894
Short name T40
Test name
Test status
Simulation time 886450328 ps
CPU time 23.14 seconds
Started Aug 15 04:59:33 PM PDT 24
Finished Aug 15 04:59:57 PM PDT 24
Peak memory 276656 kb
Host smart-7db9d04e-8ec3-438f-bcb9-0446968570ce
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=643703894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sec_cm.643703894
Directory /workspace/2.alert_handler_sec_cm/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors.2191927489
Short name T150
Test name
Test status
Simulation time 4675363723 ps
CPU time 330.83 seconds
Started Aug 15 04:58:20 PM PDT 24
Finished Aug 15 05:03:51 PM PDT 24
Peak memory 265656 kb
Host smart-be6fcb0d-8931-4aea-9564-85ca777cb2ef
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2191927489 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_shadow_reg_erro
rs.2191927489
Directory /workspace/7.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/49.alert_handler_ping_timeout.3747470961
Short name T676
Test name
Test status
Simulation time 15613233563 ps
CPU time 508.59 seconds
Started Aug 15 05:04:46 PM PDT 24
Finished Aug 15 05:13:14 PM PDT 24
Peak memory 247804 kb
Host smart-47f53c9b-1b20-4356-a737-3f196ad0f930
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3747470961 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_ping_timeout.3747470961
Directory /workspace/49.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_alert_accum_saturation.2429140368
Short name T212
Test name
Test status
Simulation time 132682912 ps
CPU time 2.39 seconds
Started Aug 15 04:59:24 PM PDT 24
Finished Aug 15 04:59:27 PM PDT 24
Peak memory 248784 kb
Host smart-7519d5d8-7c8a-4e76-87b6-5c15ada573c7
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2429140368 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_alert_accum_saturation.2429140368
Directory /workspace/0.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/1.alert_handler_alert_accum_saturation.1241223351
Short name T201
Test name
Test status
Simulation time 35547728 ps
CPU time 3.26 seconds
Started Aug 15 04:59:33 PM PDT 24
Finished Aug 15 04:59:36 PM PDT 24
Peak memory 248932 kb
Host smart-bc6ebb22-8008-4a6f-9f9d-952a2ba571c5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1241223351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_alert_accum_saturation.1241223351
Directory /workspace/1.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/12.alert_handler_alert_accum_saturation.1480664386
Short name T217
Test name
Test status
Simulation time 45789617 ps
CPU time 2.72 seconds
Started Aug 15 05:00:25 PM PDT 24
Finished Aug 15 05:00:28 PM PDT 24
Peak memory 248956 kb
Host smart-dda7e152-6211-4c6a-ba99-a6edc68222a3
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1480664386 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_alert_accum_saturation.1480664386
Directory /workspace/12.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/17.alert_handler_alert_accum_saturation.626588722
Short name T72
Test name
Test status
Simulation time 17243109 ps
CPU time 2.91 seconds
Started Aug 15 05:00:52 PM PDT 24
Finished Aug 15 05:00:55 PM PDT 24
Peak memory 248880 kb
Host smart-5928707b-ed33-4c32-8de0-a8e22bf1b1d5
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=626588722 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_alert_accum_saturation.626588722
Directory /workspace/17.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_shadow_reg_errors.13557892
Short name T138
Test name
Test status
Simulation time 1791500339 ps
CPU time 223.51 seconds
Started Aug 15 04:58:48 PM PDT 24
Finished Aug 15 05:02:32 PM PDT 24
Peak memory 273744 kb
Host smart-137402be-e6c3-42ab-8e57-7503e0d997f9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=13557892 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_shadow_reg_error
s.13557892
Directory /workspace/15.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/default/13.alert_handler_random_alerts.3927719916
Short name T590
Test name
Test status
Simulation time 530408451 ps
CPU time 29.43 seconds
Started Aug 15 05:00:38 PM PDT 24
Finished Aug 15 05:01:07 PM PDT 24
Peak memory 256000 kb
Host smart-a6becc9a-486e-4efc-bf24-44682c9e0a13
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39277
19916 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_alerts.3927719916
Directory /workspace/13.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all_with_rand_reset.2195736020
Short name T31
Test name
Test status
Simulation time 5969435184 ps
CPU time 315.58 seconds
Started Aug 15 05:01:13 PM PDT 24
Finished Aug 15 05:06:29 PM PDT 24
Peak memory 269652 kb
Host smart-364a79bd-86cd-479f-a993-d74159fadcd2
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2195736020 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 19.alert_handler_stress_all_with_rand_reset.2195736020
Directory /workspace/19.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/22.alert_handler_lpg.1235632829
Short name T310
Test name
Test status
Simulation time 37733185499 ps
CPU time 2165.49 seconds
Started Aug 15 05:01:34 PM PDT 24
Finished Aug 15 05:37:39 PM PDT 24
Peak memory 288856 kb
Host smart-df36f22f-2be0-434c-98b0-2e5b0f0db26c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1235632829 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg.1235632829
Directory /workspace/22.alert_handler_lpg/latest

Test location /workspace/coverage/default/24.alert_handler_sig_int_fail.1854732054
Short name T254
Test name
Test status
Simulation time 199979622 ps
CPU time 28.81 seconds
Started Aug 15 05:01:41 PM PDT 24
Finished Aug 15 05:02:10 PM PDT 24
Peak memory 247808 kb
Host smart-804a88c7-aa2a-4c84-95be-77536939d2e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18547
32054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_sig_int_fail.1854732054
Directory /workspace/24.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_entropy.311498993
Short name T284
Test name
Test status
Simulation time 230770233546 ps
CPU time 3451.23 seconds
Started Aug 15 05:02:04 PM PDT 24
Finished Aug 15 05:59:35 PM PDT 24
Peak memory 281512 kb
Host smart-55dbdd26-8cc2-4c7f-ab52-148954fa73f3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=311498993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_entropy.311498993
Directory /workspace/27.alert_handler_entropy/latest

Test location /workspace/coverage/default/27.alert_handler_ping_timeout.2477964945
Short name T323
Test name
Test status
Simulation time 41568171745 ps
CPU time 281.54 seconds
Started Aug 15 05:02:04 PM PDT 24
Finished Aug 15 05:06:45 PM PDT 24
Peak memory 248788 kb
Host smart-cde3454c-078e-4145-a91e-4db159206a3c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2477964945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_ping_timeout.2477964945
Directory /workspace/27.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all.2958097388
Short name T29
Test name
Test status
Simulation time 12222163153 ps
CPU time 1241.75 seconds
Started Aug 15 05:00:00 PM PDT 24
Finished Aug 15 05:20:42 PM PDT 24
Peak memory 289164 kb
Host smart-1094e41e-de2d-4687-8420-9a57194d9b38
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2958097388 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_han
dler_stress_all.2958097388
Directory /workspace/7.alert_handler_stress_all/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all_with_rand_reset.454471415
Short name T84
Test name
Test status
Simulation time 597976157 ps
CPU time 85.91 seconds
Started Aug 15 05:01:22 PM PDT 24
Finished Aug 15 05:02:48 PM PDT 24
Peak memory 266324 kb
Host smart-7a509323-0fc7-41bc-9927-a44366e384f3
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=454471415 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 20.alert_handler_stress_all_with_rand_reset.454471415
Directory /workspace/20.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors_with_csr_rw.3961947005
Short name T823
Test name
Test status
Simulation time 18446814630 ps
CPU time 374.04 seconds
Started Aug 15 04:57:48 PM PDT 24
Finished Aug 15 05:04:02 PM PDT 24
Peak memory 265644 kb
Host smart-329ebb90-44ed-482b-8e2a-815ffc1d6803
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3961947005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 2.alert_handler_shadow_reg_errors_with_csr_rw.3961947005
Directory /workspace/2.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/default/10.alert_handler_random_classes.92592789
Short name T26
Test name
Test status
Simulation time 1375544238 ps
CPU time 32.02 seconds
Started Aug 15 05:00:17 PM PDT 24
Finished Aug 15 05:00:49 PM PDT 24
Peak memory 248348 kb
Host smart-d9578f94-561d-4e5c-8814-7cc9971f0e2d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92592
789 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_classes.92592789
Directory /workspace/10.alert_handler_random_classes/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_intr_test.2604730205
Short name T748
Test name
Test status
Simulation time 7272732 ps
CPU time 1.39 seconds
Started Aug 15 04:57:48 PM PDT 24
Finished Aug 15 04:57:50 PM PDT 24
Peak memory 236884 kb
Host smart-b3d6c201-bf0e-4184-a26b-29ede13a8d35
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2604730205 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_intr_test.2604730205
Directory /workspace/1.alert_handler_intr_test/latest

Test location /workspace/coverage/default/1.alert_handler_smoke.2366916595
Short name T286
Test name
Test status
Simulation time 2866017368 ps
CPU time 24.71 seconds
Started Aug 15 04:59:23 PM PDT 24
Finished Aug 15 04:59:48 PM PDT 24
Peak memory 256140 kb
Host smart-93716cce-7229-4929-9f16-ec2c2e59c2fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23669
16595 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_smoke.2366916595
Directory /workspace/1.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_esc_intr_timeout.2990648727
Short name T92
Test name
Test status
Simulation time 327795464 ps
CPU time 10.6 seconds
Started Aug 15 05:00:35 PM PDT 24
Finished Aug 15 05:00:46 PM PDT 24
Peak memory 248316 kb
Host smart-94db54c6-1f82-400a-97d5-883c6a06360c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29906
48727 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_intr_timeout.2990648727
Directory /workspace/13.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/13.alert_handler_ping_timeout.1925145964
Short name T326
Test name
Test status
Simulation time 19960715648 ps
CPU time 213.09 seconds
Started Aug 15 05:00:36 PM PDT 24
Finished Aug 15 05:04:09 PM PDT 24
Peak memory 248760 kb
Host smart-8b8f2c91-50e6-450d-839f-6c93b60dcc43
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1925145964 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_ping_timeout.1925145964
Directory /workspace/13.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_sig_int_fail.2496165204
Short name T75
Test name
Test status
Simulation time 998164279 ps
CPU time 21.28 seconds
Started Aug 15 05:01:06 PM PDT 24
Finished Aug 15 05:01:27 PM PDT 24
Peak memory 255636 kb
Host smart-d5cf3ed0-eeee-4602-acbd-e600a6bb043f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24961
65204 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_sig_int_fail.2496165204
Directory /workspace/18.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/19.alert_handler_sig_int_fail.1723279861
Short name T263
Test name
Test status
Simulation time 260126759 ps
CPU time 9.94 seconds
Started Aug 15 05:01:15 PM PDT 24
Finished Aug 15 05:01:25 PM PDT 24
Peak memory 248028 kb
Host smart-4b97346e-5a34-4983-8d7c-bd0f450858d8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17232
79861 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_sig_int_fail.1723279861
Directory /workspace/19.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all.1394786406
Short name T236
Test name
Test status
Simulation time 329478297323 ps
CPU time 4430.42 seconds
Started Aug 15 04:59:35 PM PDT 24
Finished Aug 15 06:13:26 PM PDT 24
Peak memory 305324 kb
Host smart-8092259f-a469-4796-8cfa-1024e62cc37d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1394786406 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_han
dler_stress_all.1394786406
Directory /workspace/2.alert_handler_stress_all/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all_with_rand_reset.863217158
Short name T68
Test name
Test status
Simulation time 2158815578 ps
CPU time 205.53 seconds
Started Aug 15 05:01:49 PM PDT 24
Finished Aug 15 05:05:15 PM PDT 24
Peak memory 267944 kb
Host smart-8369b297-bc09-452d-a363-653e30ec9397
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=863217158 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 25.alert_handler_stress_all_with_rand_reset.863217158
Directory /workspace/25.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all.2152767480
Short name T120
Test name
Test status
Simulation time 22352075037 ps
CPU time 1223.83 seconds
Started Aug 15 05:02:37 PM PDT 24
Finished Aug 15 05:23:02 PM PDT 24
Peak memory 265200 kb
Host smart-7a5a28a7-03af-4236-bc5c-bc844877cc66
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2152767480 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_ha
ndler_stress_all.2152767480
Directory /workspace/32.alert_handler_stress_all/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all_with_rand_reset.1520074861
Short name T121
Test name
Test status
Simulation time 23032800206 ps
CPU time 161.84 seconds
Started Aug 15 05:03:14 PM PDT 24
Finished Aug 15 05:05:56 PM PDT 24
Peak memory 266196 kb
Host smart-e4142174-8dfc-48c5-966c-1bbfbdee5b61
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1520074861 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 36.alert_handler_stress_all_with_rand_reset.1520074861
Directory /workspace/36.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.alert_handler_esc_intr_timeout.1430601890
Short name T270
Test name
Test status
Simulation time 4723216476 ps
CPU time 73.71 seconds
Started Aug 15 05:03:35 PM PDT 24
Finished Aug 15 05:04:49 PM PDT 24
Peak memory 248532 kb
Host smart-e323ce7d-9a06-4c84-ae17-fae1f7a6b268
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14306
01890 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_intr_timeout.1430601890
Directory /workspace/40.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all.2215974996
Short name T250
Test name
Test status
Simulation time 202862289725 ps
CPU time 2711.52 seconds
Started Aug 15 05:03:58 PM PDT 24
Finished Aug 15 05:49:10 PM PDT 24
Peak memory 289176 kb
Host smart-33072a8c-8552-4731-83dd-cbfb6c30d960
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2215974996 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_ha
ndler_stress_all.2215974996
Directory /workspace/42.alert_handler_stress_all/latest

Test location /workspace/coverage/default/43.alert_handler_sig_int_fail.3064917995
Short name T2
Test name
Test status
Simulation time 4458243543 ps
CPU time 76.87 seconds
Started Aug 15 05:03:59 PM PDT 24
Finished Aug 15 05:05:16 PM PDT 24
Peak memory 256840 kb
Host smart-b35b56db-0368-47b1-8703-b60b7821d351
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30649
17995 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_sig_int_fail.3064917995
Directory /workspace/43.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all.2950744899
Short name T259
Test name
Test status
Simulation time 275794238588 ps
CPU time 4106.94 seconds
Started Aug 15 05:04:07 PM PDT 24
Finished Aug 15 06:12:34 PM PDT 24
Peak memory 298004 kb
Host smart-ee7f5a97-410c-4747-84ba-47effb4ca9d8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2950744899 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_ha
ndler_stress_all.2950744899
Directory /workspace/44.alert_handler_stress_all/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_intg_err.1340853063
Short name T174
Test name
Test status
Simulation time 2226479096 ps
CPU time 69.76 seconds
Started Aug 15 04:58:35 PM PDT 24
Finished Aug 15 04:59:45 PM PDT 24
Peak memory 240756 kb
Host smart-8a24f58b-18cd-4d11-9402-0cb4aef77b03
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1340853063 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_intg_err.1340853063
Directory /workspace/10.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors.3558067050
Short name T161
Test name
Test status
Simulation time 14289443772 ps
CPU time 278.21 seconds
Started Aug 15 04:58:58 PM PDT 24
Finished Aug 15 05:03:36 PM PDT 24
Peak memory 265624 kb
Host smart-9c1b5661-1492-44a1-aa4c-7ba78f5ecf94
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3558067050 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_shadow_reg_err
ors.3558067050
Directory /workspace/18.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_intg_err.2390170353
Short name T178
Test name
Test status
Simulation time 100750721 ps
CPU time 3.23 seconds
Started Aug 15 04:58:12 PM PDT 24
Finished Aug 15 04:58:15 PM PDT 24
Peak memory 237964 kb
Host smart-b69f1a6b-1ec2-4ade-8216-468e867adcad
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2390170353 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_intg_err.2390170353
Directory /workspace/6.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_intg_err.3781310554
Short name T176
Test name
Test status
Simulation time 174193641 ps
CPU time 2.76 seconds
Started Aug 15 04:58:40 PM PDT 24
Finished Aug 15 04:58:43 PM PDT 24
Peak memory 236832 kb
Host smart-381c38e7-83a8-4c02-9a2e-46e20d4dfae0
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3781310554 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_intg_err.3781310554
Directory /workspace/12.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_intg_err.3541489730
Short name T173
Test name
Test status
Simulation time 228346813 ps
CPU time 9.84 seconds
Started Aug 15 04:58:39 PM PDT 24
Finished Aug 15 04:58:50 PM PDT 24
Peak memory 237760 kb
Host smart-cfb2cc03-cd2f-4131-9bbe-317670e29eb3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3541489730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_intg_err.3541489730
Directory /workspace/14.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_intg_err.3124886537
Short name T172
Test name
Test status
Simulation time 896463306 ps
CPU time 66.96 seconds
Started Aug 15 04:58:32 PM PDT 24
Finished Aug 15 04:59:39 PM PDT 24
Peak memory 246264 kb
Host smart-a7e87d37-988d-4334-80b2-5189ac586b3e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3124886537 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_intg_err.3124886537
Directory /workspace/9.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors_with_csr_rw.2210011405
Short name T157
Test name
Test status
Simulation time 7394163294 ps
CPU time 502.04 seconds
Started Aug 15 04:57:40 PM PDT 24
Finished Aug 15 05:06:03 PM PDT 24
Peak memory 270368 kb
Host smart-468c13b7-f82e-404c-913e-991141dbd8a5
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2210011405 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 0.alert_handler_shadow_reg_errors_with_csr_rw.2210011405
Directory /workspace/0.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_intg_err.2538247218
Short name T187
Test name
Test status
Simulation time 37723614 ps
CPU time 3.75 seconds
Started Aug 15 04:57:41 PM PDT 24
Finished Aug 15 04:57:45 PM PDT 24
Peak memory 237764 kb
Host smart-deaaae2b-50c0-468b-becc-28f3a6ef8c3e
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=2538247218 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_intg_err.2538247218
Directory /workspace/0.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_shadow_reg_errors_with_csr_rw.2898919830
Short name T156
Test name
Test status
Simulation time 4413867917 ps
CPU time 378.64 seconds
Started Aug 15 04:58:32 PM PDT 24
Finished Aug 15 05:04:51 PM PDT 24
Peak memory 265584 kb
Host smart-3a102df7-69b1-4d89-9d00-5716aa6a2711
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2898919830 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 11.alert_handler_shadow_reg_errors_with_csr_rw.2898919830
Directory /workspace/11.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_intg_err.3298539487
Short name T165
Test name
Test status
Simulation time 108621479 ps
CPU time 6.08 seconds
Started Aug 15 04:58:47 PM PDT 24
Finished Aug 15 04:58:53 PM PDT 24
Peak memory 238012 kb
Host smart-edf8d391-a3d3-450d-8d9d-bd402c67f000
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3298539487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_intg_err.3298539487
Directory /workspace/15.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_intg_err.416661400
Short name T181
Test name
Test status
Simulation time 154885782 ps
CPU time 7.73 seconds
Started Aug 15 04:58:59 PM PDT 24
Finished Aug 15 04:59:07 PM PDT 24
Peak memory 236852 kb
Host smart-6c76858d-c028-409d-85ca-089174e46c4a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=416661400 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_intg_err.416661400
Directory /workspace/17.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_intg_err.941974511
Short name T177
Test name
Test status
Simulation time 895628923 ps
CPU time 32.19 seconds
Started Aug 15 04:58:05 PM PDT 24
Finished Aug 15 04:58:37 PM PDT 24
Peak memory 246116 kb
Host smart-9e2ca202-6be6-4e27-bd8b-a6f3c21e4bd5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=941974511 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_intg_err.941974511
Directory /workspace/4.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors.2536244299
Short name T141
Test name
Test status
Simulation time 10279628548 ps
CPU time 111.28 seconds
Started Aug 15 04:58:13 PM PDT 24
Finished Aug 15 05:00:05 PM PDT 24
Peak memory 266684 kb
Host smart-d82cead5-b544-4104-a186-532206d59ed2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2536244299 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_shadow_reg_erro
rs.2536244299
Directory /workspace/6.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_intg_err.562732550
Short name T182
Test name
Test status
Simulation time 1092175524 ps
CPU time 69.85 seconds
Started Aug 15 04:58:21 PM PDT 24
Finished Aug 15 04:59:31 PM PDT 24
Peak memory 245956 kb
Host smart-12d90ea2-ebad-4bb1-bbb7-38c37e25b0e5
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=562732550 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_intg_err.562732550
Directory /workspace/8.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_intg_err.4014072754
Short name T179
Test name
Test status
Simulation time 36890523 ps
CPU time 2.37 seconds
Started Aug 15 04:59:09 PM PDT 24
Finished Aug 15 04:59:12 PM PDT 24
Peak memory 237740 kb
Host smart-d0b29cc2-bf87-4f2d-b83e-60fd5bb267c4
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4014072754 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_intg_err.4014072754
Directory /workspace/19.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_intg_err.4034510641
Short name T183
Test name
Test status
Simulation time 352132471 ps
CPU time 48.49 seconds
Started Aug 15 04:57:56 PM PDT 24
Finished Aug 15 04:58:45 PM PDT 24
Peak memory 240664 kb
Host smart-8d6c7366-83a0-4d0c-bc51-4e9f6338d99a
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=4034510641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_intg_err.4034510641
Directory /workspace/3.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_intg_err.3581034170
Short name T171
Test name
Test status
Simulation time 22293627 ps
CPU time 2.55 seconds
Started Aug 15 04:58:21 PM PDT 24
Finished Aug 15 04:58:24 PM PDT 24
Peak memory 237756 kb
Host smart-6d5b17fd-5f10-4b05-bbea-58494d3c7476
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=3581034170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_intg_err.3581034170
Directory /workspace/7.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_aliasing.2826658978
Short name T189
Test name
Test status
Simulation time 15699853428 ps
CPU time 271.63 seconds
Started Aug 15 04:57:40 PM PDT 24
Finished Aug 15 05:02:11 PM PDT 24
Peak memory 240784 kb
Host smart-5cccdcb2-f1e1-4b75-b85b-81406011295b
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2826658978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_aliasing.2826658978
Directory /workspace/0.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_bit_bash.56906217
Short name T744
Test name
Test status
Simulation time 11629635198 ps
CPU time 366.91 seconds
Started Aug 15 04:57:42 PM PDT 24
Finished Aug 15 05:03:49 PM PDT 24
Peak memory 236868 kb
Host smart-b9601555-ec0f-4d61-850e-2a6d845b0b2a
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=56906217 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_bit_bash.56906217
Directory /workspace/0.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_hw_reset.1190988221
Short name T817
Test name
Test status
Simulation time 172282035 ps
CPU time 5.2 seconds
Started Aug 15 04:57:41 PM PDT 24
Finished Aug 15 04:57:46 PM PDT 24
Peak memory 240704 kb
Host smart-0b636cd3-c19d-4e8a-916e-b7f20091c32a
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1190988221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_hw_reset.1190988221
Directory /workspace/0.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_csr_rw.1145647367
Short name T811
Test name
Test status
Simulation time 66718738 ps
CPU time 5.82 seconds
Started Aug 15 04:57:41 PM PDT 24
Finished Aug 15 04:57:47 PM PDT 24
Peak memory 237744 kb
Host smart-689ca106-611d-4344-9ece-aad083366406
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1145647367 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_csr_rw.1145647367
Directory /workspace/0.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_intr_test.2374769107
Short name T751
Test name
Test status
Simulation time 7958719 ps
CPU time 1.51 seconds
Started Aug 15 04:57:40 PM PDT 24
Finished Aug 15 04:57:42 PM PDT 24
Peak memory 236864 kb
Host smart-5eb5069f-9315-48ee-bded-6c499a85a797
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2374769107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_intr_test.2374769107
Directory /workspace/0.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_same_csr_outstanding.2013532856
Short name T784
Test name
Test status
Simulation time 173674752 ps
CPU time 25.83 seconds
Started Aug 15 04:57:40 PM PDT 24
Finished Aug 15 04:58:06 PM PDT 24
Peak memory 248916 kb
Host smart-0bde4c39-4f04-4b96-bc86-aedfde81e2f8
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2013532856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_same_csr_out
standing.2013532856
Directory /workspace/0.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_shadow_reg_errors.3310668252
Short name T140
Test name
Test status
Simulation time 18127041051 ps
CPU time 296.19 seconds
Started Aug 15 04:57:40 PM PDT 24
Finished Aug 15 05:02:37 PM PDT 24
Peak memory 265676 kb
Host smart-bf29e954-1a2d-4521-a362-d64e4ee05b9e
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3310668252 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_shadow_reg_erro
rs.3310668252
Directory /workspace/0.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/0.alert_handler_tl_errors.728596983
Short name T765
Test name
Test status
Simulation time 689368151 ps
CPU time 16.55 seconds
Started Aug 15 04:57:42 PM PDT 24
Finished Aug 15 04:57:58 PM PDT 24
Peak memory 256392 kb
Host smart-dbbe936d-432f-412d-a4b7-0d6e7fc15191
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=728596983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 0.alert_handler_tl_errors.728596983
Directory /workspace/0.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_aliasing.2038956539
Short name T728
Test name
Test status
Simulation time 22326601389 ps
CPU time 141.7 seconds
Started Aug 15 04:57:50 PM PDT 24
Finished Aug 15 05:00:12 PM PDT 24
Peak memory 240760 kb
Host smart-c452c532-df66-4925-b7a3-9274cba1ef45
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2038956539 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_aliasing.2038956539
Directory /workspace/1.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_bit_bash.3817714526
Short name T184
Test name
Test status
Simulation time 5444838900 ps
CPU time 107.48 seconds
Started Aug 15 04:57:47 PM PDT 24
Finished Aug 15 04:59:35 PM PDT 24
Peak memory 240752 kb
Host smart-9feaacff-8bfe-4b9e-b192-6dd482d7031b
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3817714526 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_bit_bash.3817714526
Directory /workspace/1.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_hw_reset.3676819957
Short name T824
Test name
Test status
Simulation time 127920136 ps
CPU time 5.98 seconds
Started Aug 15 04:57:51 PM PDT 24
Finished Aug 15 04:57:57 PM PDT 24
Peak memory 248908 kb
Host smart-9bd289ba-34b9-4070-93a2-9de2029f0b67
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3676819957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_hw_reset.3676819957
Directory /workspace/1.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_mem_rw_with_rand_reset.3094108005
Short name T721
Test name
Test status
Simulation time 33470158 ps
CPU time 5.77 seconds
Started Aug 15 04:57:49 PM PDT 24
Finished Aug 15 04:57:55 PM PDT 24
Peak memory 241180 kb
Host smart-0f0877f0-9b02-4334-88ad-be20d7c27ec7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3094108005 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 1.alert_handler_csr_mem_rw_with_rand_reset.3094108005
Directory /workspace/1.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_csr_rw.1620484682
Short name T821
Test name
Test status
Simulation time 180184240 ps
CPU time 5.64 seconds
Started Aug 15 04:57:47 PM PDT 24
Finished Aug 15 04:57:53 PM PDT 24
Peak memory 237780 kb
Host smart-2eeb753e-8bfb-4a80-848e-21c96499e1a0
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1620484682 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_csr_rw.1620484682
Directory /workspace/1.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_same_csr_outstanding.2807035741
Short name T770
Test name
Test status
Simulation time 1268591819 ps
CPU time 38.76 seconds
Started Aug 15 04:57:47 PM PDT 24
Finished Aug 15 04:58:26 PM PDT 24
Peak memory 244976 kb
Host smart-3b8f02fa-f942-42c4-93f1-57b214975bcd
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2807035741 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_same_csr_out
standing.2807035741
Directory /workspace/1.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_shadow_reg_errors.2357748714
Short name T164
Test name
Test status
Simulation time 2111175058 ps
CPU time 145.43 seconds
Started Aug 15 04:57:45 PM PDT 24
Finished Aug 15 05:00:11 PM PDT 24
Peak memory 265608 kb
Host smart-64ecf376-02b5-4f3c-bd83-c9fa1d9d776c
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2357748714 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_shadow_reg_erro
rs.2357748714
Directory /workspace/1.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/1.alert_handler_tl_errors.4130690250
Short name T750
Test name
Test status
Simulation time 134503909 ps
CPU time 7.49 seconds
Started Aug 15 04:57:46 PM PDT 24
Finished Aug 15 04:57:54 PM PDT 24
Peak memory 254572 kb
Host smart-b4dc61f6-5105-482c-bf6d-99e63214982a
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4130690250 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 1.alert_handler_tl_errors.4130690250
Directory /workspace/1.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_mem_rw_with_rand_reset.2143386926
Short name T804
Test name
Test status
Simulation time 77266656 ps
CPU time 7.81 seconds
Started Aug 15 04:58:30 PM PDT 24
Finished Aug 15 04:58:38 PM PDT 24
Peak memory 240868 kb
Host smart-25338e1a-3e70-4739-a38f-403e80854888
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2143386926 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 10.alert_handler_csr_mem_rw_with_rand_reset.2143386926
Directory /workspace/10.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_csr_rw.1468307438
Short name T788
Test name
Test status
Simulation time 214336476 ps
CPU time 8.62 seconds
Started Aug 15 04:58:30 PM PDT 24
Finished Aug 15 04:58:39 PM PDT 24
Peak memory 236828 kb
Host smart-adbe0381-310f-4e22-94b4-b344bf387b67
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1468307438 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_csr_rw.1468307438
Directory /workspace/10.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_intr_test.2665249221
Short name T739
Test name
Test status
Simulation time 6720390 ps
CPU time 1.5 seconds
Started Aug 15 04:58:31 PM PDT 24
Finished Aug 15 04:58:33 PM PDT 24
Peak memory 236800 kb
Host smart-a490b720-672e-492b-8494-5bcd9c93e630
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2665249221 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_intr_test.2665249221
Directory /workspace/10.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_same_csr_outstanding.2619212524
Short name T796
Test name
Test status
Simulation time 157269610 ps
CPU time 22.76 seconds
Started Aug 15 04:58:31 PM PDT 24
Finished Aug 15 04:58:54 PM PDT 24
Peak memory 248876 kb
Host smart-e280ff8e-5f00-42d6-9905-e84fb5d4ceea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2619212524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_same_csr_ou
tstanding.2619212524
Directory /workspace/10.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors.3840048395
Short name T163
Test name
Test status
Simulation time 9512316471 ps
CPU time 102.97 seconds
Started Aug 15 04:58:30 PM PDT 24
Finished Aug 15 05:00:14 PM PDT 24
Peak memory 265652 kb
Host smart-df58b207-c5cb-4d00-962a-b96b09b8eed8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3840048395 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_shadow_reg_err
ors.3840048395
Directory /workspace/10.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_shadow_reg_errors_with_csr_rw.42060555
Short name T130
Test name
Test status
Simulation time 138781948925 ps
CPU time 468.27 seconds
Started Aug 15 04:58:30 PM PDT 24
Finished Aug 15 05:06:19 PM PDT 24
Peak memory 269568 kb
Host smart-d805da19-c186-492f-b967-86e1c8b452a6
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42060555 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_
TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -
cm_name 10.alert_handler_shadow_reg_errors_with_csr_rw.42060555
Directory /workspace/10.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/10.alert_handler_tl_errors.1435103104
Short name T763
Test name
Test status
Simulation time 1322932614 ps
CPU time 21.68 seconds
Started Aug 15 04:58:30 PM PDT 24
Finished Aug 15 04:58:51 PM PDT 24
Peak memory 255648 kb
Host smart-be58c3ad-e86f-44f5-80d1-65497126fdac
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1435103104 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 10.alert_handler_tl_errors.1435103104
Directory /workspace/10.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_mem_rw_with_rand_reset.2246874901
Short name T798
Test name
Test status
Simulation time 42338297 ps
CPU time 5.54 seconds
Started Aug 15 04:58:34 PM PDT 24
Finished Aug 15 04:58:40 PM PDT 24
Peak memory 255944 kb
Host smart-515f060c-f57b-4f7e-9824-2517aaee969a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2246874901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 11.alert_handler_csr_mem_rw_with_rand_reset.2246874901
Directory /workspace/11.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_csr_rw.2022789589
Short name T194
Test name
Test status
Simulation time 61092193 ps
CPU time 5.38 seconds
Started Aug 15 04:58:31 PM PDT 24
Finished Aug 15 04:58:37 PM PDT 24
Peak memory 237728 kb
Host smart-09bde318-e49b-4362-a5a8-8564b3ad95d3
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2022789589 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_csr_rw.2022789589
Directory /workspace/11.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_intr_test.3794167235
Short name T754
Test name
Test status
Simulation time 12886711 ps
CPU time 1.64 seconds
Started Aug 15 04:58:33 PM PDT 24
Finished Aug 15 04:58:35 PM PDT 24
Peak memory 237764 kb
Host smart-7406ce9b-585f-46b9-a177-3f8a218df079
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3794167235 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_intr_test.3794167235
Directory /workspace/11.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_same_csr_outstanding.57125866
Short name T775
Test name
Test status
Simulation time 2764084405 ps
CPU time 47.41 seconds
Started Aug 15 04:58:30 PM PDT 24
Finished Aug 15 04:59:18 PM PDT 24
Peak memory 246024 kb
Host smart-3220622c-b3b2-4dd7-9af1-9e694ae76f05
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=57125866 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_same_csr_outs
tanding.57125866
Directory /workspace/11.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_errors.3491942018
Short name T800
Test name
Test status
Simulation time 1281322467 ps
CPU time 27.31 seconds
Started Aug 15 04:58:31 PM PDT 24
Finished Aug 15 04:58:59 PM PDT 24
Peak memory 246396 kb
Host smart-4c1d07b3-921a-4bc9-a431-0510eed8689e
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3491942018 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_errors.3491942018
Directory /workspace/11.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/11.alert_handler_tl_intg_err.1099927891
Short name T166
Test name
Test status
Simulation time 25401072 ps
CPU time 2.27 seconds
Started Aug 15 04:58:34 PM PDT 24
Finished Aug 15 04:58:36 PM PDT 24
Peak memory 236600 kb
Host smart-96232852-6fc0-48fb-8cc3-856dac7f7169
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1099927891 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 11.alert_handler_tl_intg_err.1099927891
Directory /workspace/11.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_mem_rw_with_rand_reset.2789571867
Short name T715
Test name
Test status
Simulation time 214826791 ps
CPU time 5.97 seconds
Started Aug 15 04:58:38 PM PDT 24
Finished Aug 15 04:58:45 PM PDT 24
Peak memory 256976 kb
Host smart-4a35e0aa-bb77-4aca-b9d2-0980795f6cf1
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2789571867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 12.alert_handler_csr_mem_rw_with_rand_reset.2789571867
Directory /workspace/12.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_csr_rw.1447971003
Short name T717
Test name
Test status
Simulation time 141320006 ps
CPU time 5.15 seconds
Started Aug 15 04:58:40 PM PDT 24
Finished Aug 15 04:58:45 PM PDT 24
Peak memory 237764 kb
Host smart-2323605b-03e1-4190-bfac-c682e522f8f6
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1447971003 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_csr_rw.1447971003
Directory /workspace/12.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_intr_test.2802934145
Short name T828
Test name
Test status
Simulation time 44839034 ps
CPU time 1.37 seconds
Started Aug 15 04:58:39 PM PDT 24
Finished Aug 15 04:58:40 PM PDT 24
Peak memory 237580 kb
Host smart-62d61fbd-af66-428d-af21-ca59d52b2bfa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2802934145 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_intr_test.2802934145
Directory /workspace/12.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_same_csr_outstanding.4093195387
Short name T786
Test name
Test status
Simulation time 186787905 ps
CPU time 23.77 seconds
Started Aug 15 04:58:38 PM PDT 24
Finished Aug 15 04:59:02 PM PDT 24
Peak memory 245044 kb
Host smart-9f6ccacb-7a20-48c6-9f9a-b2ac882cc076
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=4093195387 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_same_csr_ou
tstanding.4093195387
Directory /workspace/12.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_shadow_reg_errors_with_csr_rw.1232434849
Short name T149
Test name
Test status
Simulation time 8763381998 ps
CPU time 662.23 seconds
Started Aug 15 04:58:32 PM PDT 24
Finished Aug 15 05:09:35 PM PDT 24
Peak memory 265588 kb
Host smart-9001ca32-b019-44ee-8793-edb8d48a8cee
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1232434849 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 12.alert_handler_shadow_reg_errors_with_csr_rw.1232434849
Directory /workspace/12.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/12.alert_handler_tl_errors.1214996249
Short name T807
Test name
Test status
Simulation time 317376820 ps
CPU time 7.63 seconds
Started Aug 15 04:58:41 PM PDT 24
Finished Aug 15 04:58:49 PM PDT 24
Peak memory 248848 kb
Host smart-408e5dba-3fe4-492d-98d1-2c836f1074bc
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1214996249 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 12.alert_handler_tl_errors.1214996249
Directory /workspace/12.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_mem_rw_with_rand_reset.36819593
Short name T778
Test name
Test status
Simulation time 37802229 ps
CPU time 5.28 seconds
Started Aug 15 04:58:40 PM PDT 24
Finished Aug 15 04:58:45 PM PDT 24
Peak memory 255828 kb
Host smart-66a6e556-aad8-4d4e-a23e-7d40e12bb42e
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36819593 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TES
T_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_
name 13.alert_handler_csr_mem_rw_with_rand_reset.36819593
Directory /workspace/13.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_csr_rw.2947858370
Short name T192
Test name
Test status
Simulation time 100497374 ps
CPU time 8.53 seconds
Started Aug 15 04:58:39 PM PDT 24
Finished Aug 15 04:58:47 PM PDT 24
Peak memory 240728 kb
Host smart-763aa4a0-b7a2-4a63-bf68-7405a37285c8
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2947858370 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_csr_rw.2947858370
Directory /workspace/13.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_intr_test.681612533
Short name T773
Test name
Test status
Simulation time 9879087 ps
CPU time 1.27 seconds
Started Aug 15 04:58:37 PM PDT 24
Finished Aug 15 04:58:39 PM PDT 24
Peak memory 237728 kb
Host smart-bfcff534-8c9c-4d63-95e7-7e8d433ff657
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=681612533 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_intr_test.681612533
Directory /workspace/13.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_same_csr_outstanding.1000035488
Short name T799
Test name
Test status
Simulation time 466351442 ps
CPU time 21.72 seconds
Started Aug 15 04:58:39 PM PDT 24
Finished Aug 15 04:59:01 PM PDT 24
Peak memory 240664 kb
Host smart-7261e916-1c22-48ca-9895-e2fd3ace0388
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1000035488 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_same_csr_ou
tstanding.1000035488
Directory /workspace/13.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_shadow_reg_errors.3053939089
Short name T147
Test name
Test status
Simulation time 4194824293 ps
CPU time 285.05 seconds
Started Aug 15 04:58:37 PM PDT 24
Finished Aug 15 05:03:22 PM PDT 24
Peak memory 265392 kb
Host smart-9b6a3321-d4b4-4161-ac6f-2122411c6e5a
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=3053939089 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_shadow_reg_err
ors.3053939089
Directory /workspace/13.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/13.alert_handler_tl_errors.2655942027
Short name T735
Test name
Test status
Simulation time 4717594158 ps
CPU time 18.6 seconds
Started Aug 15 04:58:41 PM PDT 24
Finished Aug 15 04:58:59 PM PDT 24
Peak memory 249016 kb
Host smart-0ae41822-26fb-47e2-8a62-07f6dd913211
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2655942027 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 13.alert_handler_tl_errors.2655942027
Directory /workspace/13.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_mem_rw_with_rand_reset.630281591
Short name T356
Test name
Test status
Simulation time 423064641 ps
CPU time 9.88 seconds
Started Aug 15 04:58:48 PM PDT 24
Finished Aug 15 04:58:58 PM PDT 24
Peak memory 240984 kb
Host smart-11e27a87-1e9d-4b24-8a81-6d88268edff8
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=630281591 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 14.alert_handler_csr_mem_rw_with_rand_reset.630281591
Directory /workspace/14.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_csr_rw.1212205659
Short name T745
Test name
Test status
Simulation time 180318365 ps
CPU time 5.36 seconds
Started Aug 15 04:58:46 PM PDT 24
Finished Aug 15 04:58:51 PM PDT 24
Peak memory 237728 kb
Host smart-662f87e1-0073-4427-965a-accc4ddc4501
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1212205659 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_csr_rw.1212205659
Directory /workspace/14.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_intr_test.4250673378
Short name T760
Test name
Test status
Simulation time 9883494 ps
CPU time 1.57 seconds
Started Aug 15 04:58:48 PM PDT 24
Finished Aug 15 04:58:49 PM PDT 24
Peak memory 236896 kb
Host smart-1127cdd4-1e50-4c4d-9dd9-6116dc12a0df
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4250673378 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_intr_test.4250673378
Directory /workspace/14.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_same_csr_outstanding.2385518298
Short name T185
Test name
Test status
Simulation time 516687342 ps
CPU time 41.63 seconds
Started Aug 15 04:58:49 PM PDT 24
Finished Aug 15 04:59:31 PM PDT 24
Peak memory 245888 kb
Host smart-2749de81-9ee1-4ac7-9b2f-717b67dc65ee
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2385518298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_same_csr_ou
tstanding.2385518298
Directory /workspace/14.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors.565326689
Short name T131
Test name
Test status
Simulation time 3984538108 ps
CPU time 156.46 seconds
Started Aug 15 04:58:39 PM PDT 24
Finished Aug 15 05:01:16 PM PDT 24
Peak memory 267920 kb
Host smart-d128cbf5-a653-4dfa-9430-f34e8a2d78d1
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=565326689 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_shadow_reg_erro
rs.565326689
Directory /workspace/14.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_shadow_reg_errors_with_csr_rw.1998693116
Short name T152
Test name
Test status
Simulation time 4718694511 ps
CPU time 673.46 seconds
Started Aug 15 04:58:40 PM PDT 24
Finished Aug 15 05:09:54 PM PDT 24
Peak memory 265624 kb
Host smart-1838bf71-abff-414d-b19d-234a1008d309
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1998693116 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 14.alert_handler_shadow_reg_errors_with_csr_rw.1998693116
Directory /workspace/14.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/14.alert_handler_tl_errors.3194862612
Short name T725
Test name
Test status
Simulation time 1050630451 ps
CPU time 10.59 seconds
Started Aug 15 04:58:38 PM PDT 24
Finished Aug 15 04:58:49 PM PDT 24
Peak memory 256776 kb
Host smart-0732ae54-46dd-4931-87bf-2dfaa1a2babf
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3194862612 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 14.alert_handler_tl_errors.3194862612
Directory /workspace/14.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_mem_rw_with_rand_reset.4177765305
Short name T790
Test name
Test status
Simulation time 124183924 ps
CPU time 9.22 seconds
Started Aug 15 04:58:48 PM PDT 24
Finished Aug 15 04:58:57 PM PDT 24
Peak memory 238348 kb
Host smart-8cff0fea-d766-4771-93d9-6e0a8ada9b5a
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4177765305 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 15.alert_handler_csr_mem_rw_with_rand_reset.4177765305
Directory /workspace/15.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_csr_rw.2426972076
Short name T783
Test name
Test status
Simulation time 36556253 ps
CPU time 5.89 seconds
Started Aug 15 04:58:49 PM PDT 24
Finished Aug 15 04:58:55 PM PDT 24
Peak memory 237772 kb
Host smart-8d84cbc7-fe34-4e70-9353-3743c695b9b5
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2426972076 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_csr_rw.2426972076
Directory /workspace/15.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_intr_test.2228220557
Short name T830
Test name
Test status
Simulation time 8531110 ps
CPU time 1.28 seconds
Started Aug 15 04:58:48 PM PDT 24
Finished Aug 15 04:58:50 PM PDT 24
Peak memory 237776 kb
Host smart-fd92cf1f-f7d3-4fa0-92a8-6c5b5c10f350
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2228220557 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_intr_test.2228220557
Directory /workspace/15.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_same_csr_outstanding.2291269187
Short name T193
Test name
Test status
Simulation time 525559871 ps
CPU time 43.47 seconds
Started Aug 15 04:58:47 PM PDT 24
Finished Aug 15 04:59:31 PM PDT 24
Peak memory 245940 kb
Host smart-e154c90a-ce32-464a-b41a-203ff0ffa4de
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2291269187 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_same_csr_ou
tstanding.2291269187
Directory /workspace/15.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/15.alert_handler_tl_errors.1010004678
Short name T802
Test name
Test status
Simulation time 189197391 ps
CPU time 13.6 seconds
Started Aug 15 04:58:47 PM PDT 24
Finished Aug 15 04:59:01 PM PDT 24
Peak memory 255076 kb
Host smart-91e6b48d-bf21-4edd-b6b1-4b57cc229ce2
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1010004678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 15.alert_handler_tl_errors.1010004678
Directory /workspace/15.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_mem_rw_with_rand_reset.449695265
Short name T186
Test name
Test status
Simulation time 86999062 ps
CPU time 6.27 seconds
Started Aug 15 04:59:00 PM PDT 24
Finished Aug 15 04:59:06 PM PDT 24
Peak memory 240772 kb
Host smart-f1e73533-46cc-4b09-a439-fb1c21fa6158
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=449695265 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 16.alert_handler_csr_mem_rw_with_rand_reset.449695265
Directory /workspace/16.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_csr_rw.1632018180
Short name T732
Test name
Test status
Simulation time 248499560 ps
CPU time 5.68 seconds
Started Aug 15 04:58:58 PM PDT 24
Finished Aug 15 04:59:04 PM PDT 24
Peak memory 240668 kb
Host smart-bc414b80-8f36-46ab-a8b5-988374fd1070
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1632018180 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_csr_rw.1632018180
Directory /workspace/16.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_intr_test.1678880975
Short name T741
Test name
Test status
Simulation time 11176669 ps
CPU time 1.67 seconds
Started Aug 15 04:58:57 PM PDT 24
Finished Aug 15 04:58:58 PM PDT 24
Peak memory 237728 kb
Host smart-497306fa-82ac-4c27-b39c-70b5b875eca0
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1678880975 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_intr_test.1678880975
Directory /workspace/16.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_same_csr_outstanding.3368243631
Short name T730
Test name
Test status
Simulation time 724194495 ps
CPU time 23.45 seconds
Started Aug 15 04:58:57 PM PDT 24
Finished Aug 15 04:59:21 PM PDT 24
Peak memory 245920 kb
Host smart-561e4b8e-aa48-473e-b7f9-a8a21e2ecf4e
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3368243631 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_same_csr_ou
tstanding.3368243631
Directory /workspace/16.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors.1374433370
Short name T144
Test name
Test status
Simulation time 965159271 ps
CPU time 118.24 seconds
Started Aug 15 04:58:50 PM PDT 24
Finished Aug 15 05:00:49 PM PDT 24
Peak memory 265528 kb
Host smart-bc020b6b-e822-4fde-814f-76c13a229a48
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=1374433370 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_shadow_reg_err
ors.1374433370
Directory /workspace/16.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_shadow_reg_errors_with_csr_rw.4084736264
Short name T355
Test name
Test status
Simulation time 60909392207 ps
CPU time 1102.31 seconds
Started Aug 15 04:58:49 PM PDT 24
Finished Aug 15 05:17:12 PM PDT 24
Peak memory 265672 kb
Host smart-c68df04c-77d3-47ac-ad17-181f56ddd348
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4084736264 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 16.alert_handler_shadow_reg_errors_with_csr_rw.4084736264
Directory /workspace/16.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_errors.3629628955
Short name T791
Test name
Test status
Simulation time 359005257 ps
CPU time 25.81 seconds
Started Aug 15 04:58:56 PM PDT 24
Finished Aug 15 04:59:22 PM PDT 24
Peak memory 257104 kb
Host smart-5e4cd4fc-7eb0-439c-ab56-cac0046d1222
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3629628955 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_errors.3629628955
Directory /workspace/16.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/16.alert_handler_tl_intg_err.518675868
Short name T734
Test name
Test status
Simulation time 2187668165 ps
CPU time 40.76 seconds
Started Aug 15 04:58:58 PM PDT 24
Finished Aug 15 04:59:39 PM PDT 24
Peak memory 237904 kb
Host smart-d3bf1431-6c06-4eb3-ae08-d1ea6d1156da
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=518675868 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 16.alert_handler_tl_intg_err.518675868
Directory /workspace/16.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_mem_rw_with_rand_reset.1980489700
Short name T756
Test name
Test status
Simulation time 41006795 ps
CPU time 5.79 seconds
Started Aug 15 04:59:01 PM PDT 24
Finished Aug 15 04:59:07 PM PDT 24
Peak memory 248980 kb
Host smart-4affbc50-75c4-46dc-acda-b956915bb8cd
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1980489700 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 17.alert_handler_csr_mem_rw_with_rand_reset.1980489700
Directory /workspace/17.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_csr_rw.1918768958
Short name T190
Test name
Test status
Simulation time 136027526 ps
CPU time 9.72 seconds
Started Aug 15 04:58:56 PM PDT 24
Finished Aug 15 04:59:06 PM PDT 24
Peak memory 237640 kb
Host smart-6cc393d4-3d0e-4cc0-bef8-e5e481720dff
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1918768958 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_csr_rw.1918768958
Directory /workspace/17.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_intr_test.3443337402
Short name T746
Test name
Test status
Simulation time 6664183 ps
CPU time 1.54 seconds
Started Aug 15 04:58:59 PM PDT 24
Finished Aug 15 04:59:00 PM PDT 24
Peak memory 237672 kb
Host smart-3df71082-e029-4f9b-8191-4a62a05a3584
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3443337402 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_intr_test.3443337402
Directory /workspace/17.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_same_csr_outstanding.505439772
Short name T722
Test name
Test status
Simulation time 91135018 ps
CPU time 12.82 seconds
Started Aug 15 04:58:58 PM PDT 24
Finished Aug 15 04:59:11 PM PDT 24
Peak memory 240720 kb
Host smart-cb630d99-8c10-4e3e-83b3-4c58afe26e38
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=505439772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +e
n_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_same_csr_out
standing.505439772
Directory /workspace/17.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_shadow_reg_errors_with_csr_rw.4249672216
Short name T129
Test name
Test status
Simulation time 2197928767 ps
CPU time 342.17 seconds
Started Aug 15 04:58:57 PM PDT 24
Finished Aug 15 05:04:40 PM PDT 24
Peak memory 265636 kb
Host smart-8827f78d-1524-4d68-b70c-7e07e80f6000
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4249672216 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 17.alert_handler_shadow_reg_errors_with_csr_rw.4249672216
Directory /workspace/17.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/17.alert_handler_tl_errors.4096344980
Short name T816
Test name
Test status
Simulation time 127222529 ps
CPU time 4.67 seconds
Started Aug 15 04:58:58 PM PDT 24
Finished Aug 15 04:59:03 PM PDT 24
Peak memory 248128 kb
Host smart-9f44a211-086e-4494-867e-3725a839ebb6
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4096344980 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 17.alert_handler_tl_errors.4096344980
Directory /workspace/17.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_mem_rw_with_rand_reset.3636110360
Short name T774
Test name
Test status
Simulation time 280005858 ps
CPU time 6.98 seconds
Started Aug 15 04:59:06 PM PDT 24
Finished Aug 15 04:59:14 PM PDT 24
Peak memory 240740 kb
Host smart-4c329e63-239e-4906-87ad-fdac889bca17
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3636110360 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 18.alert_handler_csr_mem_rw_with_rand_reset.3636110360
Directory /workspace/18.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_csr_rw.3908852231
Short name T188
Test name
Test status
Simulation time 71137924 ps
CPU time 6.04 seconds
Started Aug 15 04:59:06 PM PDT 24
Finished Aug 15 04:59:12 PM PDT 24
Peak memory 237772 kb
Host smart-379581be-b2ad-4dcc-86eb-ee6320d5adfd
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3908852231 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_csr_rw.3908852231
Directory /workspace/18.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_intr_test.99783820
Short name T747
Test name
Test status
Simulation time 6327940 ps
CPU time 1.4 seconds
Started Aug 15 04:59:08 PM PDT 24
Finished Aug 15 04:59:10 PM PDT 24
Peak memory 236884 kb
Host smart-4ed69ac5-cc66-4574-bb44-bdc7f7f93726
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=99783820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_intr_test.99783820
Directory /workspace/18.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_same_csr_outstanding.1939641048
Short name T801
Test name
Test status
Simulation time 2671244992 ps
CPU time 45.12 seconds
Started Aug 15 04:59:06 PM PDT 24
Finished Aug 15 04:59:52 PM PDT 24
Peak memory 246004 kb
Host smart-ad2cee32-e0ac-4b18-9ec1-9dc582c03fe3
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1939641048 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_same_csr_ou
tstanding.1939641048
Directory /workspace/18.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_shadow_reg_errors_with_csr_rw.749719128
Short name T153
Test name
Test status
Simulation time 6357914767 ps
CPU time 446.66 seconds
Started Aug 15 04:59:01 PM PDT 24
Finished Aug 15 05:06:28 PM PDT 24
Peak memory 270168 kb
Host smart-beb029bb-a90e-486a-b225-78eab599fd90
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=749719128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 18.alert_handler_shadow_reg_errors_with_csr_rw.749719128
Directory /workspace/18.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_errors.1511809742
Short name T809
Test name
Test status
Simulation time 37606856 ps
CPU time 4.8 seconds
Started Aug 15 04:58:57 PM PDT 24
Finished Aug 15 04:59:02 PM PDT 24
Peak memory 248720 kb
Host smart-0b3c9f7d-28af-4a3d-9571-42ce39dae93c
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1511809742 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_errors.1511809742
Directory /workspace/18.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/18.alert_handler_tl_intg_err.1854146372
Short name T787
Test name
Test status
Simulation time 1840689382 ps
CPU time 35.81 seconds
Started Aug 15 04:58:59 PM PDT 24
Finished Aug 15 04:59:35 PM PDT 24
Peak memory 246336 kb
Host smart-35963c35-363e-4f05-a8ae-c6c5941007c3
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=1854146372 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1
-cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 18.alert_handler_tl_intg_err.1854146372
Directory /workspace/18.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_mem_rw_with_rand_reset.2939442463
Short name T762
Test name
Test status
Simulation time 76949610 ps
CPU time 11.12 seconds
Started Aug 15 04:59:05 PM PDT 24
Finished Aug 15 04:59:16 PM PDT 24
Peak memory 254232 kb
Host smart-e964ceb9-4d7f-4fe1-84d3-2cf437817154
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2939442463 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 19.alert_handler_csr_mem_rw_with_rand_reset.2939442463
Directory /workspace/19.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_csr_rw.1618118038
Short name T758
Test name
Test status
Simulation time 49840332 ps
CPU time 5.27 seconds
Started Aug 15 04:59:05 PM PDT 24
Finished Aug 15 04:59:10 PM PDT 24
Peak memory 237776 kb
Host smart-ad8734e8-dd17-4aed-9f2a-a2900afd718b
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1618118038 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_csr_rw.1618118038
Directory /workspace/19.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_intr_test.890945040
Short name T169
Test name
Test status
Simulation time 11154529 ps
CPU time 1.58 seconds
Started Aug 15 04:59:06 PM PDT 24
Finished Aug 15 04:59:07 PM PDT 24
Peak memory 236856 kb
Host smart-61dbe51d-1e7e-4413-9423-110a2c9b46f9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=890945040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_intr_test.890945040
Directory /workspace/19.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_same_csr_outstanding.1479617684
Short name T803
Test name
Test status
Simulation time 1098826191 ps
CPU time 27.03 seconds
Started Aug 15 04:59:04 PM PDT 24
Finished Aug 15 04:59:31 PM PDT 24
Peak memory 245960 kb
Host smart-ce8d60c9-9bfd-42ed-a9d7-4213578905ea
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1479617684 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_same_csr_ou
tstanding.1479617684
Directory /workspace/19.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_shadow_reg_errors.2101250731
Short name T145
Test name
Test status
Simulation time 3011291963 ps
CPU time 164.5 seconds
Started Aug 15 04:59:06 PM PDT 24
Finished Aug 15 05:01:50 PM PDT 24
Peak memory 265568 kb
Host smart-1192451f-8fa7-43f5-a2b5-41d2bc79e0e2
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2101250731 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_shadow_reg_err
ors.2101250731
Directory /workspace/19.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/19.alert_handler_tl_errors.2034756320
Short name T827
Test name
Test status
Simulation time 205095095 ps
CPU time 14.12 seconds
Started Aug 15 04:59:06 PM PDT 24
Finished Aug 15 04:59:21 PM PDT 24
Peak memory 254840 kb
Host smart-250f6826-e0d6-446d-aee9-badc8b89bae4
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2034756320 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 19.alert_handler_tl_errors.2034756320
Directory /workspace/19.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_aliasing.3567067669
Short name T195
Test name
Test status
Simulation time 13302494240 ps
CPU time 223.84 seconds
Started Aug 15 04:57:56 PM PDT 24
Finished Aug 15 05:01:40 PM PDT 24
Peak memory 240628 kb
Host smart-2b296c6c-5f7a-4bb9-b176-63efe79acfcf
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=3567067669 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_aliasing.3567067669
Directory /workspace/2.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_bit_bash.2192157487
Short name T759
Test name
Test status
Simulation time 40808756338 ps
CPU time 438.56 seconds
Started Aug 15 04:57:56 PM PDT 24
Finished Aug 15 05:05:15 PM PDT 24
Peak memory 237828 kb
Host smart-ea629ff5-48d8-493d-958f-9c940b23fdfb
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2192157487 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_bit_bash.2192157487
Directory /workspace/2.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_hw_reset.2373159553
Short name T797
Test name
Test status
Simulation time 144789758 ps
CPU time 5.68 seconds
Started Aug 15 04:57:47 PM PDT 24
Finished Aug 15 04:57:53 PM PDT 24
Peak memory 240668 kb
Host smart-ebd52bbb-7be3-47b5-8032-57fd3b1e2134
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2373159553 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_hw_reset.2373159553
Directory /workspace/2.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_mem_rw_with_rand_reset.2319587787
Short name T792
Test name
Test status
Simulation time 68604281 ps
CPU time 3.61 seconds
Started Aug 15 04:57:57 PM PDT 24
Finished Aug 15 04:58:01 PM PDT 24
Peak memory 237772 kb
Host smart-cf5b9b59-7171-4f83-9bda-e14cfecdf98c
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2319587787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 2.alert_handler_csr_mem_rw_with_rand_reset.2319587787
Directory /workspace/2.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_csr_rw.250255367
Short name T720
Test name
Test status
Simulation time 104556108 ps
CPU time 8.53 seconds
Started Aug 15 04:57:57 PM PDT 24
Finished Aug 15 04:58:05 PM PDT 24
Peak memory 237752 kb
Host smart-f99c7b65-e6fa-4691-b737-0254b544da28
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=250255367 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_csr_rw.250255367
Directory /workspace/2.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_intr_test.3245950994
Short name T833
Test name
Test status
Simulation time 12578681 ps
CPU time 1.32 seconds
Started Aug 15 04:57:47 PM PDT 24
Finished Aug 15 04:57:48 PM PDT 24
Peak memory 237708 kb
Host smart-b23117ab-0e5e-4033-8b03-ea07a0d95061
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3245950994 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_intr_test.3245950994
Directory /workspace/2.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_same_csr_outstanding.3217778549
Short name T794
Test name
Test status
Simulation time 960566591 ps
CPU time 12.19 seconds
Started Aug 15 04:57:58 PM PDT 24
Finished Aug 15 04:58:11 PM PDT 24
Peak memory 240692 kb
Host smart-65190867-3091-4a2e-bbab-c8acaa28714a
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3217778549 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_same_csr_out
standing.3217778549
Directory /workspace/2.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_shadow_reg_errors.2831297409
Short name T132
Test name
Test status
Simulation time 8235339633 ps
CPU time 187.25 seconds
Started Aug 15 04:57:47 PM PDT 24
Finished Aug 15 05:00:54 PM PDT 24
Peak memory 265680 kb
Host smart-4e593160-c2e5-4b86-9748-9b3d030b3667
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2831297409 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_shadow_reg_erro
rs.2831297409
Directory /workspace/2.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/2.alert_handler_tl_errors.2011718081
Short name T826
Test name
Test status
Simulation time 404286047 ps
CPU time 7.73 seconds
Started Aug 15 04:57:51 PM PDT 24
Finished Aug 15 04:57:59 PM PDT 24
Peak memory 249976 kb
Host smart-e88b413a-ff95-45e8-8b90-d6adf73cc035
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2011718081 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 2.alert_handler_tl_errors.2011718081
Directory /workspace/2.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/20.alert_handler_intr_test.201461257
Short name T755
Test name
Test status
Simulation time 13208658 ps
CPU time 1.51 seconds
Started Aug 15 04:59:05 PM PDT 24
Finished Aug 15 04:59:07 PM PDT 24
Peak memory 236860 kb
Host smart-bf1a3a92-01ed-4eb2-95c1-06fba493b8af
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=201461257 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 20.alert_handler_intr_test.201461257
Directory /workspace/20.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/21.alert_handler_intr_test.1932241588
Short name T829
Test name
Test status
Simulation time 12524115 ps
CPU time 1.5 seconds
Started Aug 15 04:59:06 PM PDT 24
Finished Aug 15 04:59:08 PM PDT 24
Peak memory 237780 kb
Host smart-3cd3af3e-29f8-4279-a473-8a29ba1f727e
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1932241588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 21.alert_handler_intr_test.1932241588
Directory /workspace/21.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/22.alert_handler_intr_test.1777888224
Short name T820
Test name
Test status
Simulation time 24307818 ps
CPU time 1.56 seconds
Started Aug 15 04:59:05 PM PDT 24
Finished Aug 15 04:59:07 PM PDT 24
Peak memory 237712 kb
Host smart-46e93ae6-1a19-4212-9904-f2f23ca2d893
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1777888224 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 22.alert_handler_intr_test.1777888224
Directory /workspace/22.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/23.alert_handler_intr_test.1738546979
Short name T832
Test name
Test status
Simulation time 11444465 ps
CPU time 1.62 seconds
Started Aug 15 04:59:05 PM PDT 24
Finished Aug 15 04:59:07 PM PDT 24
Peak memory 236880 kb
Host smart-26ee9a8b-12c2-4861-9fee-ddd78da40dee
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1738546979 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 23.alert_handler_intr_test.1738546979
Directory /workspace/23.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/24.alert_handler_intr_test.949504978
Short name T761
Test name
Test status
Simulation time 8238116 ps
CPU time 1.55 seconds
Started Aug 15 04:59:07 PM PDT 24
Finished Aug 15 04:59:08 PM PDT 24
Peak memory 235744 kb
Host smart-11815e49-19c2-44b9-801e-c670d90108b2
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=949504978 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 24.alert_handler_intr_test.949504978
Directory /workspace/24.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/25.alert_handler_intr_test.1931082970
Short name T350
Test name
Test status
Simulation time 10650270 ps
CPU time 1.34 seconds
Started Aug 15 04:59:06 PM PDT 24
Finished Aug 15 04:59:08 PM PDT 24
Peak memory 237672 kb
Host smart-0ecbc653-ae9a-46a3-af69-a20a74b66b01
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1931082970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 25.alert_handler_intr_test.1931082970
Directory /workspace/25.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/26.alert_handler_intr_test.1206172959
Short name T780
Test name
Test status
Simulation time 11872214 ps
CPU time 1.39 seconds
Started Aug 15 04:59:05 PM PDT 24
Finished Aug 15 04:59:07 PM PDT 24
Peak memory 237728 kb
Host smart-a22aff96-f4e7-45ec-a4d6-3c55fd0ec4d5
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1206172959 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 26.alert_handler_intr_test.1206172959
Directory /workspace/26.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/27.alert_handler_intr_test.2930379829
Short name T795
Test name
Test status
Simulation time 28988681 ps
CPU time 1.55 seconds
Started Aug 15 04:59:06 PM PDT 24
Finished Aug 15 04:59:08 PM PDT 24
Peak memory 237780 kb
Host smart-d11ba56f-1c70-4805-80b9-3d2c469980b6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2930379829 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 27.alert_handler_intr_test.2930379829
Directory /workspace/27.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/28.alert_handler_intr_test.560693264
Short name T742
Test name
Test status
Simulation time 8688754 ps
CPU time 1.56 seconds
Started Aug 15 04:59:05 PM PDT 24
Finished Aug 15 04:59:07 PM PDT 24
Peak memory 237732 kb
Host smart-bf97f763-a838-45cb-8360-faf36e74fe84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=560693264 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 28.alert_handler_intr_test.560693264
Directory /workspace/28.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/29.alert_handler_intr_test.348792003
Short name T733
Test name
Test status
Simulation time 10834418 ps
CPU time 1.55 seconds
Started Aug 15 04:59:14 PM PDT 24
Finished Aug 15 04:59:16 PM PDT 24
Peak memory 237676 kb
Host smart-26146fc2-4543-44e7-925f-eebfdd9d456d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=348792003 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 29.alert_handler_intr_test.348792003
Directory /workspace/29.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_aliasing.265646867
Short name T782
Test name
Test status
Simulation time 41595830530 ps
CPU time 358.01 seconds
Started Aug 15 04:58:04 PM PDT 24
Finished Aug 15 05:04:02 PM PDT 24
Peak memory 240760 kb
Host smart-d2c29614-3afc-4b4a-a003-1eee7258a067
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=265646867 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_aliasing.265646867
Directory /workspace/3.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_bit_bash.1409391660
Short name T768
Test name
Test status
Simulation time 2639083906 ps
CPU time 105.49 seconds
Started Aug 15 04:58:04 PM PDT 24
Finished Aug 15 04:59:50 PM PDT 24
Peak memory 237820 kb
Host smart-ee1d668a-2313-4801-bdbe-21fee2f338d4
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1409391660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_bit_bash.1409391660
Directory /workspace/3.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_hw_reset.791656880
Short name T716
Test name
Test status
Simulation time 254971134 ps
CPU time 9.97 seconds
Started Aug 15 04:57:58 PM PDT 24
Finished Aug 15 04:58:08 PM PDT 24
Peak memory 240788 kb
Host smart-1e5cdab0-ee1e-4dfa-95eb-9fd2af198f96
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=791656880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_hw_reset.791656880
Directory /workspace/3.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_mem_rw_with_rand_reset.3245069036
Short name T737
Test name
Test status
Simulation time 470723165 ps
CPU time 9.49 seconds
Started Aug 15 04:58:03 PM PDT 24
Finished Aug 15 04:58:13 PM PDT 24
Peak memory 238512 kb
Host smart-9ceb079e-a3d2-43d6-b432-0e5d6a79ef57
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3245069036 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 3.alert_handler_csr_mem_rw_with_rand_reset.3245069036
Directory /workspace/3.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_csr_rw.3453789108
Short name T736
Test name
Test status
Simulation time 146765920 ps
CPU time 3.64 seconds
Started Aug 15 04:57:56 PM PDT 24
Finished Aug 15 04:58:00 PM PDT 24
Peak memory 237724 kb
Host smart-3e555060-fa6e-403b-9df6-ae5aa157c474
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3453789108 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_csr_rw.3453789108
Directory /workspace/3.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_intr_test.57069397
Short name T813
Test name
Test status
Simulation time 13140298 ps
CPU time 1.51 seconds
Started Aug 15 04:57:58 PM PDT 24
Finished Aug 15 04:58:00 PM PDT 24
Peak memory 236888 kb
Host smart-179381fc-c82c-4a1f-9a22-26eb9a16ef96
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=57069397 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_intr_test.57069397
Directory /workspace/3.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_same_csr_outstanding.2248171194
Short name T769
Test name
Test status
Simulation time 184552239 ps
CPU time 23.79 seconds
Started Aug 15 04:58:05 PM PDT 24
Finished Aug 15 04:58:28 PM PDT 24
Peak memory 245948 kb
Host smart-9acade81-226f-4cbb-a11d-a07dd4a1ff94
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=2248171194 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_same_csr_out
standing.2248171194
Directory /workspace/3.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors.528634799
Short name T134
Test name
Test status
Simulation time 6601882884 ps
CPU time 246.73 seconds
Started Aug 15 04:57:57 PM PDT 24
Finished Aug 15 05:02:04 PM PDT 24
Peak memory 265596 kb
Host smart-ce54672f-1223-4abd-b95b-43a09c0a745f
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=528634799 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_shadow_reg_error
s.528634799
Directory /workspace/3.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_shadow_reg_errors_with_csr_rw.3511796841
Short name T139
Test name
Test status
Simulation time 2317856250 ps
CPU time 358.18 seconds
Started Aug 15 04:58:02 PM PDT 24
Finished Aug 15 05:04:00 PM PDT 24
Peak memory 265580 kb
Host smart-f8c8c7dc-d7d7-4bf2-91a9-b7979fb4096c
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3511796841 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 3.alert_handler_shadow_reg_errors_with_csr_rw.3511796841
Directory /workspace/3.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/3.alert_handler_tl_errors.151966449
Short name T740
Test name
Test status
Simulation time 326228514 ps
CPU time 11.04 seconds
Started Aug 15 04:57:58 PM PDT 24
Finished Aug 15 04:58:09 PM PDT 24
Peak memory 248984 kb
Host smart-8d9cfd09-eea5-4353-93bc-fa26df9cb22f
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=151966449 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 3.alert_handler_tl_errors.151966449
Directory /workspace/3.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/30.alert_handler_intr_test.3706539109
Short name T766
Test name
Test status
Simulation time 19657760 ps
CPU time 1.47 seconds
Started Aug 15 04:59:14 PM PDT 24
Finished Aug 15 04:59:16 PM PDT 24
Peak memory 237752 kb
Host smart-f087ae94-6eee-49c7-8a40-2d99779815c6
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3706539109 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 30.alert_handler_intr_test.3706539109
Directory /workspace/30.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/31.alert_handler_intr_test.3235865792
Short name T752
Test name
Test status
Simulation time 9584466 ps
CPU time 1.32 seconds
Started Aug 15 04:59:18 PM PDT 24
Finished Aug 15 04:59:20 PM PDT 24
Peak memory 236692 kb
Host smart-ea850a41-7757-4b76-8965-c2ba23b7e719
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3235865792 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 31.alert_handler_intr_test.3235865792
Directory /workspace/31.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/32.alert_handler_intr_test.343599679
Short name T749
Test name
Test status
Simulation time 10258243 ps
CPU time 1.3 seconds
Started Aug 15 04:59:16 PM PDT 24
Finished Aug 15 04:59:17 PM PDT 24
Peak memory 237792 kb
Host smart-b9883f6d-423d-4614-bda6-6dd9b2893236
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=343599679 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 32.alert_handler_intr_test.343599679
Directory /workspace/32.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/34.alert_handler_intr_test.430448254
Short name T806
Test name
Test status
Simulation time 16370245 ps
CPU time 1.43 seconds
Started Aug 15 04:59:14 PM PDT 24
Finished Aug 15 04:59:16 PM PDT 24
Peak memory 236824 kb
Host smart-0f692d8b-0060-493e-a809-1f95ddfb424d
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=430448254 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 34.alert_handler_intr_test.430448254
Directory /workspace/34.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/35.alert_handler_intr_test.2020660812
Short name T753
Test name
Test status
Simulation time 25817590 ps
CPU time 1.47 seconds
Started Aug 15 04:59:14 PM PDT 24
Finished Aug 15 04:59:15 PM PDT 24
Peak memory 236728 kb
Host smart-d7a922a1-f02d-481f-8c24-496b8cfb8b76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2020660812 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 35.alert_handler_intr_test.2020660812
Directory /workspace/35.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/36.alert_handler_intr_test.68305344
Short name T757
Test name
Test status
Simulation time 15103965 ps
CPU time 1.38 seconds
Started Aug 15 04:59:12 PM PDT 24
Finished Aug 15 04:59:14 PM PDT 24
Peak memory 236880 kb
Host smart-f8091f13-db23-442b-bbdd-658f062fd0e9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=68305344 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+
fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 36.alert_handler_intr_test.68305344
Directory /workspace/36.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/37.alert_handler_intr_test.1996397951
Short name T726
Test name
Test status
Simulation time 6784545 ps
CPU time 1.39 seconds
Started Aug 15 04:59:13 PM PDT 24
Finished Aug 15 04:59:15 PM PDT 24
Peak memory 235880 kb
Host smart-f5bc3b10-040b-4fe3-88eb-5f4d0c865cf8
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1996397951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 37.alert_handler_intr_test.1996397951
Directory /workspace/37.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/38.alert_handler_intr_test.3479218857
Short name T240
Test name
Test status
Simulation time 13771012 ps
CPU time 1.75 seconds
Started Aug 15 04:59:14 PM PDT 24
Finished Aug 15 04:59:16 PM PDT 24
Peak memory 237780 kb
Host smart-fe3e1934-cf84-4805-8916-5e3f414b55c9
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3479218857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 38.alert_handler_intr_test.3479218857
Directory /workspace/38.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/39.alert_handler_intr_test.430581561
Short name T168
Test name
Test status
Simulation time 7955182 ps
CPU time 1.45 seconds
Started Aug 15 04:59:14 PM PDT 24
Finished Aug 15 04:59:15 PM PDT 24
Peak memory 236872 kb
Host smart-80e529b0-aaa3-4818-a047-f1605b266423
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=430581561 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 39.alert_handler_intr_test.430581561
Directory /workspace/39.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_aliasing.4088970007
Short name T738
Test name
Test status
Simulation time 27770619545 ps
CPU time 317.28 seconds
Started Aug 15 04:58:04 PM PDT 24
Finished Aug 15 05:03:21 PM PDT 24
Peak memory 241848 kb
Host smart-d049cb98-a355-428d-8538-557f22ef06ab
User root
Command /workspace/cover_reg_top/simv +csr_aliasing +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=4088970007 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_aliasing.4088970007
Directory /workspace/4.alert_handler_csr_aliasing/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_bit_bash.1398500426
Short name T743
Test name
Test status
Simulation time 821366860 ps
CPU time 102.45 seconds
Started Aug 15 04:58:05 PM PDT 24
Finished Aug 15 04:59:47 PM PDT 24
Peak memory 236816 kb
Host smart-f1b96730-b7fa-4f15-8be3-329251a4a144
User root
Command /workspace/cover_reg_top/simv +csr_bit_bash +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=1398500426 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_bit_bash.1398500426
Directory /workspace/4.alert_handler_csr_bit_bash/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_hw_reset.2628420102
Short name T836
Test name
Test status
Simulation time 267353093 ps
CPU time 6.97 seconds
Started Aug 15 04:58:05 PM PDT 24
Finished Aug 15 04:58:12 PM PDT 24
Peak memory 248864 kb
Host smart-14b35025-3d10-442d-93e6-c3bba87c831e
User root
Command /workspace/cover_reg_top/simv +csr_hw_reset +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/
sim.tcl +ntb_random_seed=2628420102 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_hw_reset.2628420102
Directory /workspace/4.alert_handler_csr_hw_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_mem_rw_with_rand_reset.935148019
Short name T198
Test name
Test status
Simulation time 132297895 ps
CPU time 7.15 seconds
Started Aug 15 04:58:11 PM PDT 24
Finished Aug 15 04:58:18 PM PDT 24
Peak memory 253556 kb
Host smart-81dd565d-27ac-46b0-8388-0b69132aca70
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=935148019 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 4.alert_handler_csr_mem_rw_with_rand_reset.935148019
Directory /workspace/4.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_csr_rw.1267498466
Short name T779
Test name
Test status
Simulation time 19803920 ps
CPU time 3.26 seconds
Started Aug 15 04:58:04 PM PDT 24
Finished Aug 15 04:58:07 PM PDT 24
Peak memory 239680 kb
Host smart-145cf749-1985-47ee-ac7d-497bfa4dcda9
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1267498466 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_csr_rw.1267498466
Directory /workspace/4.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_intr_test.3273705135
Short name T349
Test name
Test status
Simulation time 12821449 ps
CPU time 1.37 seconds
Started Aug 15 04:58:04 PM PDT 24
Finished Aug 15 04:58:06 PM PDT 24
Peak memory 236032 kb
Host smart-e794057c-14fa-460a-b0ad-8b19d92fe4fa
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3273705135 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_intr_test.3273705135
Directory /workspace/4.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_same_csr_outstanding.1747154054
Short name T191
Test name
Test status
Simulation time 353113849 ps
CPU time 27.55 seconds
Started Aug 15 04:58:06 PM PDT 24
Finished Aug 15 04:58:33 PM PDT 24
Peak memory 245944 kb
Host smart-89c964d6-1a29-4ee2-a287-776f51dd8965
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1747154054 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_same_csr_out
standing.1747154054
Directory /workspace/4.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_shadow_reg_errors.337324029
Short name T158
Test name
Test status
Simulation time 4921336099 ps
CPU time 334.21 seconds
Started Aug 15 04:58:04 PM PDT 24
Finished Aug 15 05:03:38 PM PDT 24
Peak memory 265636 kb
Host smart-df7845c5-8411-4391-b7f7-6938b03b0ae9
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=337324029 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_shadow_reg_error
s.337324029
Directory /workspace/4.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/4.alert_handler_tl_errors.2096547125
Short name T727
Test name
Test status
Simulation time 151660033 ps
CPU time 6.62 seconds
Started Aug 15 04:58:04 PM PDT 24
Finished Aug 15 04:58:11 PM PDT 24
Peak memory 251380 kb
Host smart-0f68189b-c20f-429a-a7e5-b4423d2d6be9
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2096547125 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 4.alert_handler_tl_errors.2096547125
Directory /workspace/4.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/40.alert_handler_intr_test.2460239669
Short name T351
Test name
Test status
Simulation time 37654592 ps
CPU time 1.36 seconds
Started Aug 15 04:59:14 PM PDT 24
Finished Aug 15 04:59:16 PM PDT 24
Peak memory 236744 kb
Host smart-274ee8e9-2ca9-4110-b60d-b7cd506e8537
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2460239669 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 40.alert_handler_intr_test.2460239669
Directory /workspace/40.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/41.alert_handler_intr_test.1047831273
Short name T831
Test name
Test status
Simulation time 18479223 ps
CPU time 1.47 seconds
Started Aug 15 04:59:13 PM PDT 24
Finished Aug 15 04:59:15 PM PDT 24
Peak memory 237744 kb
Host smart-635be17a-18e0-4e9b-9442-815a0250fc4c
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1047831273 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 41.alert_handler_intr_test.1047831273
Directory /workspace/41.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/42.alert_handler_intr_test.2494740600
Short name T170
Test name
Test status
Simulation time 9884587 ps
CPU time 1.58 seconds
Started Aug 15 04:59:19 PM PDT 24
Finished Aug 15 04:59:20 PM PDT 24
Peak memory 237692 kb
Host smart-33271905-1cf5-4d59-ad2b-032a63c7a7ea
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2494740600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 42.alert_handler_intr_test.2494740600
Directory /workspace/42.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/43.alert_handler_intr_test.2265623698
Short name T781
Test name
Test status
Simulation time 18617821 ps
CPU time 1.45 seconds
Started Aug 15 04:59:15 PM PDT 24
Finished Aug 15 04:59:17 PM PDT 24
Peak memory 236828 kb
Host smart-ca59e9e7-d2b9-407f-a08e-173bf8da6a84
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2265623698 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 43.alert_handler_intr_test.2265623698
Directory /workspace/43.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/44.alert_handler_intr_test.3926171899
Short name T805
Test name
Test status
Simulation time 13698661 ps
CPU time 1.54 seconds
Started Aug 15 04:59:13 PM PDT 24
Finished Aug 15 04:59:15 PM PDT 24
Peak memory 236772 kb
Host smart-b1ee191c-4e15-4bb2-9978-f5881c3f4de1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3926171899 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 44.alert_handler_intr_test.3926171899
Directory /workspace/44.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/45.alert_handler_intr_test.2227700442
Short name T239
Test name
Test status
Simulation time 11602603 ps
CPU time 1.42 seconds
Started Aug 15 04:59:12 PM PDT 24
Finished Aug 15 04:59:14 PM PDT 24
Peak memory 237720 kb
Host smart-c8631857-dfa6-4cd2-8213-ff02d09b11cc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2227700442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 45.alert_handler_intr_test.2227700442
Directory /workspace/45.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/46.alert_handler_intr_test.2580205020
Short name T819
Test name
Test status
Simulation time 11318663 ps
CPU time 1.71 seconds
Started Aug 15 04:59:15 PM PDT 24
Finished Aug 15 04:59:17 PM PDT 24
Peak memory 237756 kb
Host smart-d30af59b-0c01-4cd1-a5d1-4393ca9c0f76
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2580205020 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 46.alert_handler_intr_test.2580205020
Directory /workspace/46.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/47.alert_handler_intr_test.3026859817
Short name T812
Test name
Test status
Simulation time 9919259 ps
CPU time 1.55 seconds
Started Aug 15 04:59:14 PM PDT 24
Finished Aug 15 04:59:16 PM PDT 24
Peak memory 236812 kb
Host smart-0accab94-2a2f-46dc-b2dc-ccfc98d5827b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3026859817 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 47.alert_handler_intr_test.3026859817
Directory /workspace/47.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/49.alert_handler_intr_test.3749153186
Short name T808
Test name
Test status
Simulation time 10516193 ps
CPU time 1.36 seconds
Started Aug 15 04:59:18 PM PDT 24
Finished Aug 15 04:59:19 PM PDT 24
Peak memory 236804 kb
Host smart-8642fa8e-5e1e-4775-bbdd-9452f70685e1
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3749153186 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 49.alert_handler_intr_test.3749153186
Directory /workspace/49.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_mem_rw_with_rand_reset.431926210
Short name T822
Test name
Test status
Simulation time 202364435 ps
CPU time 4.97 seconds
Started Aug 15 04:58:12 PM PDT 24
Finished Aug 15 04:58:17 PM PDT 24
Peak memory 238672 kb
Host smart-4ab5b8f9-b0a5-49ae-8556-3126de380e99
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=431926210 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TE
ST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm
_name 5.alert_handler_csr_mem_rw_with_rand_reset.431926210
Directory /workspace/5.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_csr_rw.4205427298
Short name T785
Test name
Test status
Simulation time 51867065 ps
CPU time 4.33 seconds
Started Aug 15 04:58:12 PM PDT 24
Finished Aug 15 04:58:17 PM PDT 24
Peak memory 236884 kb
Host smart-86d15cae-5871-44e1-bfe5-fc8b1762c737
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=4205427298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_csr_rw.4205427298
Directory /workspace/5.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_intr_test.773888276
Short name T353
Test name
Test status
Simulation time 8700349 ps
CPU time 1.63 seconds
Started Aug 15 04:58:12 PM PDT 24
Finished Aug 15 04:58:14 PM PDT 24
Peak memory 236764 kb
Host smart-27184ea4-a3e9-4a92-9c2b-e0bae7cd37fc
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=773888276 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_intr_test.773888276
Directory /workspace/5.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_same_csr_outstanding.59332874
Short name T835
Test name
Test status
Simulation time 1354771994 ps
CPU time 35.97 seconds
Started Aug 15 04:58:12 PM PDT 24
Finished Aug 15 04:58:48 PM PDT 24
Peak memory 245904 kb
Host smart-d8e05650-32b3-4ba6-9148-c3ec75928a57
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=59332874 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en
_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_same_csr_outst
anding.59332874
Directory /workspace/5.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors.610064877
Short name T151
Test name
Test status
Simulation time 8696420130 ps
CPU time 143.48 seconds
Started Aug 15 04:58:11 PM PDT 24
Finished Aug 15 05:00:35 PM PDT 24
Peak memory 265640 kb
Host smart-8329d92d-3fcc-4cbf-9a0e-9007a82bc3c8
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=610064877 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_c
ov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_shadow_reg_error
s.610064877
Directory /workspace/5.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_shadow_reg_errors_with_csr_rw.157005461
Short name T160
Test name
Test status
Simulation time 243273891849 ps
CPU time 1116.42 seconds
Started Aug 15 04:58:13 PM PDT 24
Finished Aug 15 05:16:50 PM PDT 24
Peak memory 265600 kb
Host smart-5894b56a-70cc-4049-abb5-15a7a5884d5e
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157005461 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 5.alert_handler_shadow_reg_errors_with_csr_rw.157005461
Directory /workspace/5.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_errors.1060879750
Short name T714
Test name
Test status
Simulation time 1771001584 ps
CPU time 8.83 seconds
Started Aug 15 04:58:13 PM PDT 24
Finished Aug 15 04:58:22 PM PDT 24
Peak memory 248692 kb
Host smart-a5686ed2-cf47-4f3e-b27b-f6575b36ded3
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=1060879750 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_errors.1060879750
Directory /workspace/5.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/5.alert_handler_tl_intg_err.618531524
Short name T834
Test name
Test status
Simulation time 924091299 ps
CPU time 40.22 seconds
Started Aug 15 04:58:13 PM PDT 24
Finished Aug 15 04:58:53 PM PDT 24
Peak memory 240652 kb
Host smart-56f3cbbd-ae76-4f99-8bcd-d6cf416212ea
User root
Command /workspace/cover_reg_top/simv +run_tl_intg_err +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/too
ls/sim.tcl +ntb_random_seed=618531524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 5.alert_handler_tl_intg_err.618531524
Directory /workspace/5.alert_handler_tl_intg_err/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_mem_rw_with_rand_reset.2967739374
Short name T777
Test name
Test status
Simulation time 208403580 ps
CPU time 10.41 seconds
Started Aug 15 04:58:11 PM PDT 24
Finished Aug 15 04:58:22 PM PDT 24
Peak memory 252172 kb
Host smart-2e88f82c-0103-419b-a306-f083c39bd0f7
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2967739374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 6.alert_handler_csr_mem_rw_with_rand_reset.2967739374
Directory /workspace/6.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_csr_rw.2043599794
Short name T793
Test name
Test status
Simulation time 67399272 ps
CPU time 3.32 seconds
Started Aug 15 04:58:15 PM PDT 24
Finished Aug 15 04:58:19 PM PDT 24
Peak memory 240696 kb
Host smart-21e5f0d0-1244-467c-abc0-8ff196991212
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=2043599794 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_csr_rw.2043599794
Directory /workspace/6.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_intr_test.4133549626
Short name T724
Test name
Test status
Simulation time 15062886 ps
CPU time 1.25 seconds
Started Aug 15 04:58:11 PM PDT 24
Finished Aug 15 04:58:12 PM PDT 24
Peak memory 235684 kb
Host smart-effc0e91-9468-40a9-9f96-9b6680f69fef
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=4133549626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_intr_test.4133549626
Directory /workspace/6.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_same_csr_outstanding.1974311852
Short name T729
Test name
Test status
Simulation time 89223049 ps
CPU time 10.89 seconds
Started Aug 15 04:58:17 PM PDT 24
Finished Aug 15 04:58:28 PM PDT 24
Peak memory 245064 kb
Host smart-04313270-85f9-4d5c-bbba-ac4504182baa
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1974311852 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_same_csr_out
standing.1974311852
Directory /workspace/6.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_shadow_reg_errors_with_csr_rw.717207620
Short name T137
Test name
Test status
Simulation time 16423653434 ps
CPU time 1177.65 seconds
Started Aug 15 04:58:12 PM PDT 24
Finished Aug 15 05:17:50 PM PDT 24
Peak memory 265812 kb
Host smart-4ff2c534-9c2f-47a7-8a99-8b2c205af3bf
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=717207620 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 6.alert_handler_shadow_reg_errors_with_csr_rw.717207620
Directory /workspace/6.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/6.alert_handler_tl_errors.3197287802
Short name T810
Test name
Test status
Simulation time 497703077 ps
CPU time 20.37 seconds
Started Aug 15 04:58:12 PM PDT 24
Finished Aug 15 04:58:33 PM PDT 24
Peak memory 257076 kb
Host smart-f956f840-a68e-495e-8e58-08bd73f6a609
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3197287802 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 6.alert_handler_tl_errors.3197287802
Directory /workspace/6.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_mem_rw_with_rand_reset.4023153517
Short name T354
Test name
Test status
Simulation time 208143410 ps
CPU time 10.69 seconds
Started Aug 15 04:58:26 PM PDT 24
Finished Aug 15 04:58:37 PM PDT 24
Peak memory 249972 kb
Host smart-fc534426-6303-417f-b6b8-414e75cfbfcb
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4023153517 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 7.alert_handler_csr_mem_rw_with_rand_reset.4023153517
Directory /workspace/7.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_csr_rw.3589975059
Short name T789
Test name
Test status
Simulation time 34969498 ps
CPU time 4.25 seconds
Started Aug 15 04:58:21 PM PDT 24
Finished Aug 15 04:58:25 PM PDT 24
Peak memory 240640 kb
Host smart-7ac75e7c-74bd-486d-acfd-05116cff3883
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=3589975059 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_csr_rw.3589975059
Directory /workspace/7.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_intr_test.3220090779
Short name T767
Test name
Test status
Simulation time 22039429 ps
CPU time 1.35 seconds
Started Aug 15 04:58:22 PM PDT 24
Finished Aug 15 04:58:23 PM PDT 24
Peak memory 236884 kb
Host smart-e2caa618-4855-4502-a492-a643061cf210
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3220090779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_intr_test.3220090779
Directory /workspace/7.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_same_csr_outstanding.3189363992
Short name T196
Test name
Test status
Simulation time 503416215 ps
CPU time 21.72 seconds
Started Aug 15 04:58:21 PM PDT 24
Finished Aug 15 04:58:43 PM PDT 24
Peak memory 245888 kb
Host smart-8328c5db-305c-4eb6-8cca-310339095265
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=3189363992 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_same_csr_out
standing.3189363992
Directory /workspace/7.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_shadow_reg_errors_with_csr_rw.2648165664
Short name T143
Test name
Test status
Simulation time 10194539893 ps
CPU time 376.88 seconds
Started Aug 15 04:58:21 PM PDT 24
Finished Aug 15 05:04:38 PM PDT 24
Peak memory 265524 kb
Host smart-b49cd5f6-f5eb-4c3d-a540-12bd63594d40
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2648165664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 7.alert_handler_shadow_reg_errors_with_csr_rw.2648165664
Directory /workspace/7.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/7.alert_handler_tl_errors.3390504271
Short name T764
Test name
Test status
Simulation time 73479766 ps
CPU time 9.7 seconds
Started Aug 15 04:58:21 PM PDT 24
Finished Aug 15 04:58:30 PM PDT 24
Peak memory 248976 kb
Host smart-b7731195-4274-4a61-8158-012d4ddb4620
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3390504271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 7.alert_handler_tl_errors.3390504271
Directory /workspace/7.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_mem_rw_with_rand_reset.2838379999
Short name T723
Test name
Test status
Simulation time 127027387 ps
CPU time 10.27 seconds
Started Aug 15 04:58:21 PM PDT 24
Finished Aug 15 04:58:32 PM PDT 24
Peak memory 248944 kb
Host smart-11799cbe-e093-4627-b639-3b7aaa793904
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2838379999 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 8.alert_handler_csr_mem_rw_with_rand_reset.2838379999
Directory /workspace/8.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_csr_rw.482154648
Short name T814
Test name
Test status
Simulation time 68034934 ps
CPU time 5.89 seconds
Started Aug 15 04:58:22 PM PDT 24
Finished Aug 15 04:58:28 PM PDT 24
Peak memory 237748 kb
Host smart-8ddeeea8-f245-4fbf-ad26-bdeaa3056696
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=482154648 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+c
ond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_csr_rw.482154648
Directory /workspace/8.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_intr_test.2828839322
Short name T772
Test name
Test status
Simulation time 10903782 ps
CPU time 1.28 seconds
Started Aug 15 04:58:26 PM PDT 24
Finished Aug 15 04:58:28 PM PDT 24
Peak memory 237764 kb
Host smart-86e2ff49-ee7b-4aa5-9d06-8ef54646f3b3
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2828839322 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_intr_test.2828839322
Directory /workspace/8.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_same_csr_outstanding.1566415360
Short name T731
Test name
Test status
Simulation time 995898173 ps
CPU time 19.86 seconds
Started Aug 15 04:58:22 PM PDT 24
Finished Aug 15 04:58:42 PM PDT 24
Peak memory 245964 kb
Host smart-6ca8a42a-dcf7-49a2-a59d-7f7e9d509472
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1566415360 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_same_csr_out
standing.1566415360
Directory /workspace/8.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_shadow_reg_errors_with_csr_rw.157453204
Short name T825
Test name
Test status
Simulation time 6959471680 ps
CPU time 473.05 seconds
Started Aug 15 04:58:21 PM PDT 24
Finished Aug 15 05:06:15 PM PDT 24
Peak memory 265816 kb
Host smart-bfbf141e-cc39-410e-9ca6-50ada4e4ede5
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=157453204 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM
_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 8.alert_handler_shadow_reg_errors_with_csr_rw.157453204
Directory /workspace/8.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/8.alert_handler_tl_errors.2032432379
Short name T771
Test name
Test status
Simulation time 548935930 ps
CPU time 7.6 seconds
Started Aug 15 04:58:21 PM PDT 24
Finished Aug 15 04:58:29 PM PDT 24
Peak memory 251988 kb
Host smart-d312b3c8-b794-4886-98f8-f486a7910a06
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=2032432379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 8.alert_handler_tl_errors.2032432379
Directory /workspace/8.alert_handler_tl_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_mem_rw_with_rand_reset.1802177551
Short name T815
Test name
Test status
Simulation time 876453508 ps
CPU time 16.11 seconds
Started Aug 15 04:58:31 PM PDT 24
Finished Aug 15 04:58:47 PM PDT 24
Peak memory 251932 kb
Host smart-095328d0-b6da-4212-b5bc-35b47e7785fc
User root
Command /workspace/cover_reg_top/simv +run_csr_mem_rw_with_rand_reset +test_timeout_ns=10000000000 +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue
-ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1802177551 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_T
EST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -c
m_name 9.alert_handler_csr_mem_rw_with_rand_reset.1802177551
Directory /workspace/9.alert_handler_csr_mem_rw_with_rand_reset/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_csr_rw.1013893433
Short name T719
Test name
Test status
Simulation time 91884094 ps
CPU time 9.22 seconds
Started Aug 15 04:58:31 PM PDT 24
Finished Aug 15 04:58:41 PM PDT 24
Peak memory 237692 kb
Host smart-1f52c01b-9b61-4eb7-8d27-e5fa1b6b5bea
User root
Command /workspace/cover_reg_top/simv +csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tc
l +ntb_random_seed=1013893433 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_csr_rw.1013893433
Directory /workspace/9.alert_handler_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_intr_test.3716378675
Short name T776
Test name
Test status
Simulation time 7852762 ps
CPU time 1.44 seconds
Started Aug 15 04:58:31 PM PDT 24
Finished Aug 15 04:58:33 PM PDT 24
Peak memory 235792 kb
Host smart-d9917157-1a71-4375-b272-0d031519f58b
User root
Command /workspace/cover_reg_top/simv +run_intr_test +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=3716378675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+con
d+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_intr_test.3716378675
Directory /workspace/9.alert_handler_intr_test/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_same_csr_outstanding.1547323488
Short name T818
Test name
Test status
Simulation time 323235773 ps
CPU time 21.8 seconds
Started Aug 15 04:58:30 PM PDT 24
Finished Aug 15 04:58:52 PM PDT 24
Peak memory 245984 kb
Host smart-c5f86468-69ae-4558-a711-6a420125597d
User root
Command /workspace/cover_reg_top/simv +run_same_csr_outstanding +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/
hw/dv/tools/sim.tcl +ntb_random_seed=1547323488 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +
en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_same_csr_out
standing.1547323488
Directory /workspace/9.alert_handler_same_csr_outstanding/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors.2639712182
Short name T146
Test name
Test status
Simulation time 928508547 ps
CPU time 95.61 seconds
Started Aug 15 04:58:31 PM PDT 24
Finished Aug 15 05:00:07 PM PDT 24
Peak memory 265612 kb
Host smart-26ee79cb-766e-4862-a406-702b1df56393
User root
Command /workspace/cover_reg_top/simv +run_shadow_reg_errors +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/
dv/tools/sim.tcl +ntb_random_seed=2639712182 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_
cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_shadow_reg_erro
rs.2639712182
Directory /workspace/9.alert_handler_shadow_reg_errors/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_shadow_reg_errors_with_csr_rw.3748702207
Short name T154
Test name
Test status
Simulation time 81639058393 ps
CPU time 938.72 seconds
Started Aug 15 04:58:31 PM PDT 24
Finished Aug 15 05:14:09 PM PDT 24
Peak memory 273716 kb
Host smart-e60843fd-1c32-43f5-80f2-c9f785b370a0
User root
Command /workspace/cover_reg_top/simv +test_timeout_ns=500_000_000 +run_shadow_reg_errors_with_csr_rw +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqu
eue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3748702207 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UV
M_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null
-cm_name 9.alert_handler_shadow_reg_errors_with_csr_rw.3748702207
Directory /workspace/9.alert_handler_shadow_reg_errors_with_csr_rw/latest

Test location /workspace/coverage/cover_reg_top/9.alert_handler_tl_errors.595412654
Short name T718
Test name
Test status
Simulation time 1004447151 ps
CPU time 20.48 seconds
Started Aug 15 04:58:30 PM PDT 24
Finished Aug 15 04:58:51 PM PDT 24
Peak memory 255624 kb
Host smart-cb6e77ea-836c-43f2-9074-f053e1da8257
User root
Command /workspace/cover_reg_top/simv +run_tl_errors +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +
ntb_random_seed=595412654 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond
+fsm+tgl+branch+assert -cm_dir /workspace/coverage/cover_reg_top.vdb -cm_log /dev/null -cm_name 9.alert_handler_tl_errors.595412654
Directory /workspace/9.alert_handler_tl_errors/latest

Test location /workspace/coverage/default/0.alert_handler_entropy.1097301282
Short name T646
Test name
Test status
Simulation time 24049111329 ps
CPU time 1511.5 seconds
Started Aug 15 04:59:24 PM PDT 24
Finished Aug 15 05:24:35 PM PDT 24
Peak memory 273032 kb
Host smart-ecd6d899-132f-4993-b2be-f073c1461910
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1097301282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy.1097301282
Directory /workspace/0.alert_handler_entropy/latest

Test location /workspace/coverage/default/0.alert_handler_entropy_stress.896595450
Short name T244
Test name
Test status
Simulation time 194402338 ps
CPU time 11.17 seconds
Started Aug 15 04:59:24 PM PDT 24
Finished Aug 15 04:59:35 PM PDT 24
Peak memory 248684 kb
Host smart-ee851fe5-f044-4cba-9751-1832938c7634
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=896595450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_entropy_stress.896595450
Directory /workspace/0.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/0.alert_handler_esc_alert_accum.2798592532
Short name T573
Test name
Test status
Simulation time 70299292 ps
CPU time 5.18 seconds
Started Aug 15 04:59:14 PM PDT 24
Finished Aug 15 04:59:19 PM PDT 24
Peak memory 240568 kb
Host smart-0d4cdd04-9d86-43d9-866b-2a16584bcc91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27985
92532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_alert_accum.2798592532
Directory /workspace/0.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/0.alert_handler_esc_intr_timeout.1658064774
Short name T682
Test name
Test status
Simulation time 101192351 ps
CPU time 10.35 seconds
Started Aug 15 04:59:18 PM PDT 24
Finished Aug 15 04:59:29 PM PDT 24
Peak memory 248624 kb
Host smart-1cac62b7-0ad2-4459-803e-eea76cfa472c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16580
64774 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_esc_intr_timeout.1658064774
Directory /workspace/0.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_lpg.2681403144
Short name T335
Test name
Test status
Simulation time 7903437324 ps
CPU time 883.78 seconds
Started Aug 15 04:59:27 PM PDT 24
Finished Aug 15 05:14:11 PM PDT 24
Peak memory 273340 kb
Host smart-696cafc3-c146-48f1-ab31-541210194917
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2681403144 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg.2681403144
Directory /workspace/0.alert_handler_lpg/latest

Test location /workspace/coverage/default/0.alert_handler_lpg_stub_clk.2548930237
Short name T398
Test name
Test status
Simulation time 44255531226 ps
CPU time 2534.63 seconds
Started Aug 15 04:59:23 PM PDT 24
Finished Aug 15 05:41:38 PM PDT 24
Peak memory 281660 kb
Host smart-e9e08ebe-a85f-4de6-a21c-f41c6389f0ea
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2548930237 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_lpg_stub_clk.2548930237
Directory /workspace/0.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/0.alert_handler_ping_timeout.1540492736
Short name T227
Test name
Test status
Simulation time 58221724989 ps
CPU time 440.6 seconds
Started Aug 15 04:59:23 PM PDT 24
Finished Aug 15 05:06:44 PM PDT 24
Peak memory 248684 kb
Host smart-3865d2cd-7384-4dc5-8796-ae90918de4f0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1540492736 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_ping_timeout.1540492736
Directory /workspace/0.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/0.alert_handler_random_alerts.311806742
Short name T506
Test name
Test status
Simulation time 1074445889 ps
CPU time 28.84 seconds
Started Aug 15 04:59:16 PM PDT 24
Finished Aug 15 04:59:45 PM PDT 24
Peak memory 256208 kb
Host smart-bfa171f4-7f47-46c6-99fc-4d8f0386bae5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31180
6742 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_alerts.311806742
Directory /workspace/0.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/0.alert_handler_random_classes.3009604828
Short name T393
Test name
Test status
Simulation time 1198615511 ps
CPU time 40.06 seconds
Started Aug 15 04:59:15 PM PDT 24
Finished Aug 15 04:59:55 PM PDT 24
Peak memory 256912 kb
Host smart-307e9d58-1e76-4e6e-826e-1df7894d669d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30096
04828 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_random_classes.3009604828
Directory /workspace/0.alert_handler_random_classes/latest

Test location /workspace/coverage/default/0.alert_handler_sec_cm.3011184474
Short name T41
Test name
Test status
Simulation time 346398031 ps
CPU time 20.86 seconds
Started Aug 15 04:59:22 PM PDT 24
Finished Aug 15 04:59:43 PM PDT 24
Peak memory 270900 kb
Host smart-03b7f229-bbb9-4de5-b53c-ddbdef902216
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=3011184474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sec_cm.3011184474
Directory /workspace/0.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/0.alert_handler_sig_int_fail.2612089069
Short name T476
Test name
Test status
Simulation time 2961918667 ps
CPU time 38.84 seconds
Started Aug 15 04:59:27 PM PDT 24
Finished Aug 15 05:00:06 PM PDT 24
Peak memory 256556 kb
Host smart-ad11cd4e-364c-4ef5-a024-10d930e50d6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26120
89069 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_sig_int_fail.2612089069
Directory /workspace/0.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/0.alert_handler_smoke.1411894764
Short name T670
Test name
Test status
Simulation time 4208353793 ps
CPU time 68.56 seconds
Started Aug 15 04:59:13 PM PDT 24
Finished Aug 15 05:00:22 PM PDT 24
Peak memory 248684 kb
Host smart-6b2d73b2-0938-4d4a-ac4c-6d8d57f9170e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14118
94764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 0.alert_handler_smoke.1411894764
Directory /workspace/0.alert_handler_smoke/latest

Test location /workspace/coverage/default/1.alert_handler_entropy.3459631827
Short name T555
Test name
Test status
Simulation time 44805209942 ps
CPU time 2741.02 seconds
Started Aug 15 04:59:22 PM PDT 24
Finished Aug 15 05:45:04 PM PDT 24
Peak memory 288832 kb
Host smart-6711479f-f96f-49cb-8285-5e041251ad5e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3459631827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy.3459631827
Directory /workspace/1.alert_handler_entropy/latest

Test location /workspace/coverage/default/1.alert_handler_entropy_stress.1385120791
Short name T431
Test name
Test status
Simulation time 3364422603 ps
CPU time 33.62 seconds
Started Aug 15 04:59:23 PM PDT 24
Finished Aug 15 04:59:57 PM PDT 24
Peak memory 248772 kb
Host smart-e5ad0db0-5625-46d7-85a7-5808c279401d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1385120791 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_entropy_stress.1385120791
Directory /workspace/1.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/1.alert_handler_esc_alert_accum.822505662
Short name T287
Test name
Test status
Simulation time 8077441421 ps
CPU time 271.24 seconds
Started Aug 15 04:59:25 PM PDT 24
Finished Aug 15 05:03:56 PM PDT 24
Peak memory 256280 kb
Host smart-6ed8ad94-78f3-4492-b8b8-68a28af6f5a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=82250
5662 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_alert_accum.822505662
Directory /workspace/1.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/1.alert_handler_esc_intr_timeout.3693778835
Short name T595
Test name
Test status
Simulation time 266258027 ps
CPU time 12.91 seconds
Started Aug 15 04:59:23 PM PDT 24
Finished Aug 15 04:59:36 PM PDT 24
Peak memory 256176 kb
Host smart-16bee49e-36bd-4f4f-889c-bc1eb651e468
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36937
78835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_esc_intr_timeout.3693778835
Directory /workspace/1.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_lpg.3286124722
Short name T8
Test name
Test status
Simulation time 20491053700 ps
CPU time 950.54 seconds
Started Aug 15 04:59:24 PM PDT 24
Finished Aug 15 05:15:15 PM PDT 24
Peak memory 273272 kb
Host smart-d06800b5-3c74-4ad7-8d90-e88b1eea69e7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3286124722 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg.3286124722
Directory /workspace/1.alert_handler_lpg/latest

Test location /workspace/coverage/default/1.alert_handler_lpg_stub_clk.2796650665
Short name T421
Test name
Test status
Simulation time 18977637829 ps
CPU time 1334.4 seconds
Started Aug 15 04:59:24 PM PDT 24
Finished Aug 15 05:21:38 PM PDT 24
Peak memory 272852 kb
Host smart-d9d9f38e-8237-4f3f-a0e4-36bb9790b237
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2796650665 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_lpg_stub_clk.2796650665
Directory /workspace/1.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/1.alert_handler_ping_timeout.88886006
Short name T312
Test name
Test status
Simulation time 12838029142 ps
CPU time 135.85 seconds
Started Aug 15 04:59:24 PM PDT 24
Finished Aug 15 05:01:40 PM PDT 24
Peak memory 248792 kb
Host smart-31bb6701-9005-4c5d-a169-901e7f6d6751
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88886006 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_ping_timeout.88886006
Directory /workspace/1.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/1.alert_handler_random_alerts.501450522
Short name T617
Test name
Test status
Simulation time 200237110 ps
CPU time 7.21 seconds
Started Aug 15 04:59:24 PM PDT 24
Finished Aug 15 04:59:31 PM PDT 24
Peak memory 254504 kb
Host smart-e4d1d399-ff4f-4a1e-acfa-6b3a8bacf082
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50145
0522 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_alerts.501450522
Directory /workspace/1.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/1.alert_handler_random_classes.4073855243
Short name T510
Test name
Test status
Simulation time 4512084824 ps
CPU time 66.4 seconds
Started Aug 15 04:59:23 PM PDT 24
Finished Aug 15 05:00:29 PM PDT 24
Peak memory 248860 kb
Host smart-b6d6e210-07bc-4600-9425-804a259cc141
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40738
55243 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_random_classes.4073855243
Directory /workspace/1.alert_handler_random_classes/latest

Test location /workspace/coverage/default/1.alert_handler_sig_int_fail.2074193011
Short name T77
Test name
Test status
Simulation time 115724209 ps
CPU time 13.49 seconds
Started Aug 15 04:59:23 PM PDT 24
Finished Aug 15 04:59:37 PM PDT 24
Peak memory 256880 kb
Host smart-e65d400b-95e7-4347-90fa-ff704252e041
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20741
93011 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_handler_sig_int_fail.2074193011
Directory /workspace/1.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/1.alert_handler_stress_all.2664328909
Short name T527
Test name
Test status
Simulation time 33168495776 ps
CPU time 1875.04 seconds
Started Aug 15 04:59:35 PM PDT 24
Finished Aug 15 05:30:51 PM PDT 24
Peak memory 281652 kb
Host smart-63ca3290-4139-4caa-a1fa-c7118e3735f3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2664328909 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 1.alert_han
dler_stress_all.2664328909
Directory /workspace/1.alert_handler_stress_all/latest

Test location /workspace/coverage/default/10.alert_handler_alert_accum_saturation.3896085071
Short name T202
Test name
Test status
Simulation time 59402768 ps
CPU time 4.86 seconds
Started Aug 15 05:00:16 PM PDT 24
Finished Aug 15 05:00:21 PM PDT 24
Peak memory 248856 kb
Host smart-f7ce0c9d-182a-4fc3-9c57-0e5c45f3696a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3896085071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_alert_accum_saturation.3896085071
Directory /workspace/10.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/10.alert_handler_entropy.3539274875
Short name T242
Test name
Test status
Simulation time 42483443062 ps
CPU time 2392.4 seconds
Started Aug 15 05:00:24 PM PDT 24
Finished Aug 15 05:40:17 PM PDT 24
Peak memory 289484 kb
Host smart-9d49fdd1-cd26-491c-b357-56acf5881396
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3539274875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy.3539274875
Directory /workspace/10.alert_handler_entropy/latest

Test location /workspace/coverage/default/10.alert_handler_entropy_stress.1920239317
Short name T448
Test name
Test status
Simulation time 658953510 ps
CPU time 11.48 seconds
Started Aug 15 05:00:16 PM PDT 24
Finished Aug 15 05:00:27 PM PDT 24
Peak memory 248652 kb
Host smart-1f298ebc-d64e-421e-87ce-a499389907af
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1920239317 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_entropy_stress.1920239317
Directory /workspace/10.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/10.alert_handler_esc_alert_accum.2794767974
Short name T382
Test name
Test status
Simulation time 3253635388 ps
CPU time 148.39 seconds
Started Aug 15 05:00:18 PM PDT 24
Finished Aug 15 05:02:46 PM PDT 24
Peak memory 256144 kb
Host smart-7be5909f-39fb-4575-9701-7d1b458b2667
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27947
67974 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_alert_accum.2794767974
Directory /workspace/10.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/10.alert_handler_esc_intr_timeout.3869125104
Short name T403
Test name
Test status
Simulation time 537636795 ps
CPU time 36.34 seconds
Started Aug 15 05:00:15 PM PDT 24
Finished Aug 15 05:00:51 PM PDT 24
Peak memory 247984 kb
Host smart-3ffd2efd-26fe-4338-a567-90761f1e0be5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38691
25104 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_esc_intr_timeout.3869125104
Directory /workspace/10.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/10.alert_handler_lpg_stub_clk.1639176686
Short name T508
Test name
Test status
Simulation time 27441383989 ps
CPU time 1640.81 seconds
Started Aug 15 05:00:21 PM PDT 24
Finished Aug 15 05:27:42 PM PDT 24
Peak memory 272356 kb
Host smart-aeed3e97-841b-4b64-a0b6-616da7a45e57
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1639176686 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_lpg_stub_clk.1639176686
Directory /workspace/10.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/10.alert_handler_random_alerts.469897687
Short name T648
Test name
Test status
Simulation time 559547063 ps
CPU time 18.83 seconds
Started Aug 15 05:00:13 PM PDT 24
Finished Aug 15 05:00:32 PM PDT 24
Peak memory 256636 kb
Host smart-fbd4d3bb-e416-49b1-8cd0-944a8f07c4b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46989
7687 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_random_alerts.469897687
Directory /workspace/10.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/10.alert_handler_sig_int_fail.3508562647
Short name T384
Test name
Test status
Simulation time 525347347 ps
CPU time 7.52 seconds
Started Aug 15 05:00:18 PM PDT 24
Finished Aug 15 05:00:26 PM PDT 24
Peak memory 248716 kb
Host smart-80aec3f8-bc65-4065-a7de-f16b4a2d3b77
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35085
62647 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_sig_int_fail.3508562647
Directory /workspace/10.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/10.alert_handler_smoke.587906583
Short name T626
Test name
Test status
Simulation time 356948785 ps
CPU time 20.98 seconds
Started Aug 15 05:00:13 PM PDT 24
Finished Aug 15 05:00:34 PM PDT 24
Peak memory 256916 kb
Host smart-934d1174-4c40-456b-993b-b76fe1b1ef69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58790
6583 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_handler_smoke.587906583
Directory /workspace/10.alert_handler_smoke/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all.1155123678
Short name T102
Test name
Test status
Simulation time 66526457397 ps
CPU time 3881.89 seconds
Started Aug 15 05:00:17 PM PDT 24
Finished Aug 15 06:04:59 PM PDT 24
Peak memory 305656 kb
Host smart-1687a87e-2f5b-4f1a-83db-6c65b045dccd
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1155123678 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 10.alert_ha
ndler_stress_all.1155123678
Directory /workspace/10.alert_handler_stress_all/latest

Test location /workspace/coverage/default/10.alert_handler_stress_all_with_rand_reset.789836183
Short name T600
Test name
Test status
Simulation time 28936256553 ps
CPU time 281.83 seconds
Started Aug 15 05:00:16 PM PDT 24
Finished Aug 15 05:04:58 PM PDT 24
Peak memory 273520 kb
Host smart-25df2444-64c1-42e1-814d-5dbcbe029a9e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=789836183 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 10.alert_handler_stress_all_with_rand_reset.789836183
Directory /workspace/10.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/11.alert_handler_alert_accum_saturation.13259152
Short name T210
Test name
Test status
Simulation time 20590433 ps
CPU time 3.18 seconds
Started Aug 15 05:00:26 PM PDT 24
Finished Aug 15 05:00:30 PM PDT 24
Peak memory 248976 kb
Host smart-cb763e16-7649-467c-8eb7-119afc3778c0
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=13259152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_alert_accum_saturation.13259152
Directory /workspace/11.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/11.alert_handler_entropy.3139301591
Short name T493
Test name
Test status
Simulation time 587835460700 ps
CPU time 2216.86 seconds
Started Aug 15 05:00:24 PM PDT 24
Finished Aug 15 05:37:22 PM PDT 24
Peak memory 283420 kb
Host smart-aecaee5c-c94e-4b50-802f-481cca279660
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3139301591 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy.3139301591
Directory /workspace/11.alert_handler_entropy/latest

Test location /workspace/coverage/default/11.alert_handler_entropy_stress.3598509013
Short name T553
Test name
Test status
Simulation time 505185241 ps
CPU time 15.14 seconds
Started Aug 15 05:00:28 PM PDT 24
Finished Aug 15 05:00:43 PM PDT 24
Peak memory 248728 kb
Host smart-9dec01f0-c700-4df9-8b43-de1f4adfe6e8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3598509013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_entropy_stress.3598509013
Directory /workspace/11.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/11.alert_handler_esc_alert_accum.3857651498
Short name T443
Test name
Test status
Simulation time 78538906 ps
CPU time 7.45 seconds
Started Aug 15 05:00:21 PM PDT 24
Finished Aug 15 05:00:28 PM PDT 24
Peak memory 251604 kb
Host smart-9fded79f-76bc-4e63-9b02-36753c92cb81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38576
51498 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_alert_accum.3857651498
Directory /workspace/11.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/11.alert_handler_esc_intr_timeout.2917890880
Short name T525
Test name
Test status
Simulation time 372109815 ps
CPU time 9.42 seconds
Started Aug 15 05:00:25 PM PDT 24
Finished Aug 15 05:00:34 PM PDT 24
Peak memory 248204 kb
Host smart-800dfdad-48b6-4856-bfb1-b3c744011197
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29178
90880 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_esc_intr_timeout.2917890880
Directory /workspace/11.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_lpg.1407028705
Short name T561
Test name
Test status
Simulation time 153681083283 ps
CPU time 2160.3 seconds
Started Aug 15 05:00:25 PM PDT 24
Finished Aug 15 05:36:26 PM PDT 24
Peak memory 287988 kb
Host smart-807c119d-e90e-40b7-b9d0-63dc63f2e6e3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1407028705 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg.1407028705
Directory /workspace/11.alert_handler_lpg/latest

Test location /workspace/coverage/default/11.alert_handler_lpg_stub_clk.1439435639
Short name T104
Test name
Test status
Simulation time 39016156548 ps
CPU time 964.28 seconds
Started Aug 15 05:00:25 PM PDT 24
Finished Aug 15 05:16:29 PM PDT 24
Peak memory 273176 kb
Host smart-fd303c51-50df-421f-aa62-78f663c72656
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1439435639 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_lpg_stub_clk.1439435639
Directory /workspace/11.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/11.alert_handler_ping_timeout.3120311677
Short name T18
Test name
Test status
Simulation time 40396732491 ps
CPU time 428.71 seconds
Started Aug 15 05:00:17 PM PDT 24
Finished Aug 15 05:07:26 PM PDT 24
Peak memory 248784 kb
Host smart-8b4c6c1a-9557-40f6-8dd3-dac33b92ab2b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3120311677 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_ping_timeout.3120311677
Directory /workspace/11.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/11.alert_handler_random_alerts.1251235245
Short name T233
Test name
Test status
Simulation time 1336103527 ps
CPU time 28.13 seconds
Started Aug 15 05:00:15 PM PDT 24
Finished Aug 15 05:00:43 PM PDT 24
Peak memory 256236 kb
Host smart-b825a63c-7237-4509-bf51-e068634f9bc2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12512
35245 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_alerts.1251235245
Directory /workspace/11.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/11.alert_handler_random_classes.3882112327
Short name T468
Test name
Test status
Simulation time 748276019 ps
CPU time 34.71 seconds
Started Aug 15 05:00:16 PM PDT 24
Finished Aug 15 05:00:51 PM PDT 24
Peak memory 248760 kb
Host smart-09c32fa4-93ef-4c7e-a4dc-f5bcc64239fb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38821
12327 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_random_classes.3882112327
Directory /workspace/11.alert_handler_random_classes/latest

Test location /workspace/coverage/default/11.alert_handler_sig_int_fail.4055926389
Short name T434
Test name
Test status
Simulation time 352148981 ps
CPU time 24.72 seconds
Started Aug 15 05:00:25 PM PDT 24
Finished Aug 15 05:00:50 PM PDT 24
Peak memory 248100 kb
Host smart-6102176a-ee64-4cf4-bd17-f98ffd80a678
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40559
26389 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_sig_int_fail.4055926389
Directory /workspace/11.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/11.alert_handler_smoke.3335501393
Short name T234
Test name
Test status
Simulation time 52982988 ps
CPU time 2.67 seconds
Started Aug 15 05:00:17 PM PDT 24
Finished Aug 15 05:00:20 PM PDT 24
Peak memory 248772 kb
Host smart-e2e8cb8c-d11a-46a9-b056-3141f478ce4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33355
01393 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_handler_smoke.3335501393
Directory /workspace/11.alert_handler_smoke/latest

Test location /workspace/coverage/default/11.alert_handler_stress_all.2073730719
Short name T289
Test name
Test status
Simulation time 3839783432 ps
CPU time 223.07 seconds
Started Aug 15 05:00:28 PM PDT 24
Finished Aug 15 05:04:11 PM PDT 24
Peak memory 257044 kb
Host smart-3ab16610-6e23-41eb-a8fe-67802304246d
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2073730719 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 11.alert_ha
ndler_stress_all.2073730719
Directory /workspace/11.alert_handler_stress_all/latest

Test location /workspace/coverage/default/12.alert_handler_entropy.4089886314
Short name T673
Test name
Test status
Simulation time 93517080243 ps
CPU time 1364.13 seconds
Started Aug 15 05:00:27 PM PDT 24
Finished Aug 15 05:23:12 PM PDT 24
Peak memory 272716 kb
Host smart-e6c38a5f-c6e6-4974-8be2-7b6d64a384c5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4089886314 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy.4089886314
Directory /workspace/12.alert_handler_entropy/latest

Test location /workspace/coverage/default/12.alert_handler_entropy_stress.2152364925
Short name T383
Test name
Test status
Simulation time 3321226773 ps
CPU time 38.92 seconds
Started Aug 15 05:00:28 PM PDT 24
Finished Aug 15 05:01:07 PM PDT 24
Peak memory 247276 kb
Host smart-57501702-08f5-49f4-8952-c9a915181b43
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2152364925 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_entropy_stress.2152364925
Directory /workspace/12.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/12.alert_handler_esc_alert_accum.3163344726
Short name T544
Test name
Test status
Simulation time 1995218640 ps
CPU time 61.33 seconds
Started Aug 15 05:00:28 PM PDT 24
Finished Aug 15 05:01:30 PM PDT 24
Peak memory 256384 kb
Host smart-3dd1c3f8-d822-4f37-bafa-f28feb9244fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31633
44726 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_alert_accum.3163344726
Directory /workspace/12.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/12.alert_handler_esc_intr_timeout.1119396934
Short name T88
Test name
Test status
Simulation time 321592455 ps
CPU time 15.13 seconds
Started Aug 15 05:00:26 PM PDT 24
Finished Aug 15 05:00:42 PM PDT 24
Peak memory 256664 kb
Host smart-26f50494-4a45-426b-ba91-bdce8353be62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11193
96934 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_esc_intr_timeout.1119396934
Directory /workspace/12.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_lpg_stub_clk.2476082206
Short name T103
Test name
Test status
Simulation time 28947921449 ps
CPU time 1950.28 seconds
Started Aug 15 05:00:27 PM PDT 24
Finished Aug 15 05:32:58 PM PDT 24
Peak memory 289768 kb
Host smart-3d4ca3f8-4750-4f3b-804f-3517daf68459
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2476082206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_lpg_stub_clk.2476082206
Directory /workspace/12.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/12.alert_handler_ping_timeout.90115806
Short name T241
Test name
Test status
Simulation time 35927241753 ps
CPU time 391.52 seconds
Started Aug 15 05:00:27 PM PDT 24
Finished Aug 15 05:06:58 PM PDT 24
Peak memory 248820 kb
Host smart-8e60321c-2442-49d4-8447-b9803c8be424
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90115806 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_ping_timeout.90115806
Directory /workspace/12.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/12.alert_handler_random_alerts.534508918
Short name T485
Test name
Test status
Simulation time 2567007828 ps
CPU time 40.9 seconds
Started Aug 15 05:00:27 PM PDT 24
Finished Aug 15 05:01:08 PM PDT 24
Peak memory 256592 kb
Host smart-5a25e450-9cb4-4615-bcb4-341197622f4c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53450
8918 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_alerts.534508918
Directory /workspace/12.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/12.alert_handler_random_classes.868486303
Short name T627
Test name
Test status
Simulation time 2657603027 ps
CPU time 23.15 seconds
Started Aug 15 05:00:28 PM PDT 24
Finished Aug 15 05:00:51 PM PDT 24
Peak memory 246716 kb
Host smart-2a5ec368-4b7f-4e72-94fb-566a322b7b5d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86848
6303 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_random_classes.868486303
Directory /workspace/12.alert_handler_random_classes/latest

Test location /workspace/coverage/default/12.alert_handler_sig_int_fail.1954349262
Short name T54
Test name
Test status
Simulation time 10498161811 ps
CPU time 49.03 seconds
Started Aug 15 05:00:26 PM PDT 24
Finished Aug 15 05:01:15 PM PDT 24
Peak memory 248860 kb
Host smart-ad1ab51d-51dd-4b8e-9a55-4f5069473d4d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19543
49262 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_sig_int_fail.1954349262
Directory /workspace/12.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/12.alert_handler_smoke.3070334711
Short name T49
Test name
Test status
Simulation time 375691734 ps
CPU time 11.61 seconds
Started Aug 15 05:00:29 PM PDT 24
Finished Aug 15 05:00:40 PM PDT 24
Peak memory 247352 kb
Host smart-070cec8f-ec68-4edd-8258-db5dd54df360
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30703
34711 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 12.alert_handler_smoke.3070334711
Directory /workspace/12.alert_handler_smoke/latest

Test location /workspace/coverage/default/12.alert_handler_stress_all_with_rand_reset.4194245176
Short name T638
Test name
Test status
Simulation time 29446841030 ps
CPU time 490.29 seconds
Started Aug 15 05:00:27 PM PDT 24
Finished Aug 15 05:08:38 PM PDT 24
Peak memory 272844 kb
Host smart-7052ea07-4b48-402d-9d26-698814d0b150
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4194245176 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 12.alert_handler_stress_all_with_rand_reset.4194245176
Directory /workspace/12.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/13.alert_handler_alert_accum_saturation.250470571
Short name T200
Test name
Test status
Simulation time 22403082 ps
CPU time 2.3 seconds
Started Aug 15 05:00:37 PM PDT 24
Finished Aug 15 05:00:40 PM PDT 24
Peak memory 248872 kb
Host smart-e344dc0c-b402-4c8f-bf40-a679a064df53
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=250470571 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_alert_accum_saturation.250470571
Directory /workspace/13.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/13.alert_handler_entropy.299755497
Short name T628
Test name
Test status
Simulation time 38947479845 ps
CPU time 2523.22 seconds
Started Aug 15 05:00:37 PM PDT 24
Finished Aug 15 05:42:41 PM PDT 24
Peak memory 289116 kb
Host smart-f253fee2-0007-4b24-acff-6d3628f7e421
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=299755497 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_entropy.299755497
Directory /workspace/13.alert_handler_entropy/latest

Test location /workspace/coverage/default/13.alert_handler_esc_alert_accum.68693988
Short name T435
Test name
Test status
Simulation time 1998607253 ps
CPU time 63.9 seconds
Started Aug 15 05:00:37 PM PDT 24
Finished Aug 15 05:01:41 PM PDT 24
Peak memory 249240 kb
Host smart-6062d8df-9193-4fc5-9f14-275bb728d164
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68693
988 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_esc_alert_accum.68693988
Directory /workspace/13.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/13.alert_handler_lpg_stub_clk.1053741524
Short name T591
Test name
Test status
Simulation time 9003772738 ps
CPU time 940.5 seconds
Started Aug 15 05:00:37 PM PDT 24
Finished Aug 15 05:16:18 PM PDT 24
Peak memory 273316 kb
Host smart-b0670669-444e-46a1-a4c5-a539db61df1b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1053741524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_lpg_stub_clk.1053741524
Directory /workspace/13.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/13.alert_handler_random_classes.1472461645
Short name T79
Test name
Test status
Simulation time 492827843 ps
CPU time 33.02 seconds
Started Aug 15 05:00:36 PM PDT 24
Finished Aug 15 05:01:10 PM PDT 24
Peak memory 248184 kb
Host smart-e1002d36-f4ad-48ef-8921-3346524707ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14724
61645 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_random_classes.1472461645
Directory /workspace/13.alert_handler_random_classes/latest

Test location /workspace/coverage/default/13.alert_handler_sig_int_fail.2159956970
Short name T44
Test name
Test status
Simulation time 183196309 ps
CPU time 8.34 seconds
Started Aug 15 05:00:37 PM PDT 24
Finished Aug 15 05:00:45 PM PDT 24
Peak memory 248752 kb
Host smart-4b47ea14-6ec5-4613-b183-c736e0d316be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21599
56970 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_sig_int_fail.2159956970
Directory /workspace/13.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/13.alert_handler_smoke.1100920152
Short name T231
Test name
Test status
Simulation time 1743970075 ps
CPU time 51.21 seconds
Started Aug 15 05:00:35 PM PDT 24
Finished Aug 15 05:01:27 PM PDT 24
Peak memory 256920 kb
Host smart-b4e198c5-e515-47a2-b7a9-b915f891f254
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11009
20152 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_handler_smoke.1100920152
Directory /workspace/13.alert_handler_smoke/latest

Test location /workspace/coverage/default/13.alert_handler_stress_all.2458138698
Short name T439
Test name
Test status
Simulation time 39791367415 ps
CPU time 2294.4 seconds
Started Aug 15 05:00:37 PM PDT 24
Finished Aug 15 05:38:52 PM PDT 24
Peak memory 289008 kb
Host smart-89dab203-455c-431f-ac3b-29e1837f09c2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2458138698 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 13.alert_ha
ndler_stress_all.2458138698
Directory /workspace/13.alert_handler_stress_all/latest

Test location /workspace/coverage/default/14.alert_handler_alert_accum_saturation.517414932
Short name T214
Test name
Test status
Simulation time 183220537 ps
CPU time 3.58 seconds
Started Aug 15 05:00:44 PM PDT 24
Finished Aug 15 05:00:48 PM PDT 24
Peak memory 248968 kb
Host smart-3fe96d22-3c71-4664-9f3f-46ba5fd6441d
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=517414932 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_alert_accum_saturation.517414932
Directory /workspace/14.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/14.alert_handler_entropy.1230400549
Short name T293
Test name
Test status
Simulation time 69046031993 ps
CPU time 2351.26 seconds
Started Aug 15 05:00:37 PM PDT 24
Finished Aug 15 05:39:49 PM PDT 24
Peak memory 281572 kb
Host smart-1b5670e6-f6b7-47ba-8980-9296c6fef1ee
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1230400549 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy.1230400549
Directory /workspace/14.alert_handler_entropy/latest

Test location /workspace/coverage/default/14.alert_handler_entropy_stress.859249279
Short name T656
Test name
Test status
Simulation time 474257676 ps
CPU time 8.7 seconds
Started Aug 15 05:00:44 PM PDT 24
Finished Aug 15 05:00:53 PM PDT 24
Peak memory 248752 kb
Host smart-05fe1b7c-5b45-4178-bfbe-216649e90379
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=859249279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_entropy_stress.859249279
Directory /workspace/14.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/14.alert_handler_esc_alert_accum.2068090568
Short name T378
Test name
Test status
Simulation time 2431871480 ps
CPU time 40.23 seconds
Started Aug 15 05:00:36 PM PDT 24
Finished Aug 15 05:01:16 PM PDT 24
Peak memory 256340 kb
Host smart-2ce370a8-14f3-4bdf-a1d8-949bca1a14ba
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20680
90568 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_alert_accum.2068090568
Directory /workspace/14.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/14.alert_handler_esc_intr_timeout.1878480192
Short name T519
Test name
Test status
Simulation time 236500005 ps
CPU time 14.01 seconds
Started Aug 15 05:00:35 PM PDT 24
Finished Aug 15 05:00:49 PM PDT 24
Peak memory 256204 kb
Host smart-784dc6d6-08d7-4d9c-b3b3-8a761cb12cea
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18784
80192 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_esc_intr_timeout.1878480192
Directory /workspace/14.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/14.alert_handler_lpg.1571246366
Short name T338
Test name
Test status
Simulation time 14766320309 ps
CPU time 1421.26 seconds
Started Aug 15 05:00:53 PM PDT 24
Finished Aug 15 05:24:35 PM PDT 24
Peak memory 289452 kb
Host smart-2b08df31-014c-44f9-a502-7ad1211f5447
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1571246366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg.1571246366
Directory /workspace/14.alert_handler_lpg/latest

Test location /workspace/coverage/default/14.alert_handler_lpg_stub_clk.1041461665
Short name T404
Test name
Test status
Simulation time 9559941267 ps
CPU time 1166.36 seconds
Started Aug 15 05:00:44 PM PDT 24
Finished Aug 15 05:20:11 PM PDT 24
Peak memory 289488 kb
Host smart-17a5e6e0-5a17-48ea-a00b-33f5f05dac03
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1041461665 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_lpg_stub_clk.1041461665
Directory /workspace/14.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/14.alert_handler_random_alerts.2535267997
Short name T490
Test name
Test status
Simulation time 555697478 ps
CPU time 35.19 seconds
Started Aug 15 05:00:36 PM PDT 24
Finished Aug 15 05:01:12 PM PDT 24
Peak memory 256144 kb
Host smart-a8f12cfd-ac07-482a-bf7f-21d4db26e8e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25352
67997 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_alerts.2535267997
Directory /workspace/14.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/14.alert_handler_random_classes.2632724670
Short name T460
Test name
Test status
Simulation time 1610312046 ps
CPU time 36.97 seconds
Started Aug 15 05:00:36 PM PDT 24
Finished Aug 15 05:01:13 PM PDT 24
Peak memory 256832 kb
Host smart-77ca6950-ab61-4c71-948b-be848a555d84
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26327
24670 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_random_classes.2632724670
Directory /workspace/14.alert_handler_random_classes/latest

Test location /workspace/coverage/default/14.alert_handler_sig_int_fail.524475637
Short name T258
Test name
Test status
Simulation time 10162220947 ps
CPU time 52.74 seconds
Started Aug 15 05:00:38 PM PDT 24
Finished Aug 15 05:01:31 PM PDT 24
Peak memory 256948 kb
Host smart-c7e41f5e-ea4a-4813-9b9b-b89e2dc32dd3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52447
5637 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_sig_int_fail.524475637
Directory /workspace/14.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/14.alert_handler_smoke.2455319792
Short name T95
Test name
Test status
Simulation time 595987520 ps
CPU time 39.56 seconds
Started Aug 15 05:00:36 PM PDT 24
Finished Aug 15 05:01:15 PM PDT 24
Peak memory 248756 kb
Host smart-2817833e-572d-43d6-8a6d-ca0c39dff686
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24553
19792 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_handler_smoke.2455319792
Directory /workspace/14.alert_handler_smoke/latest

Test location /workspace/coverage/default/14.alert_handler_stress_all.75772427
Short name T48
Test name
Test status
Simulation time 991771737 ps
CPU time 37.41 seconds
Started Aug 15 05:00:44 PM PDT 24
Finished Aug 15 05:01:22 PM PDT 24
Peak memory 256800 kb
Host smart-bdf7c309-944d-434e-9427-e5f144065e46
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=75772427 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_hand
ler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 14.alert_hand
ler_stress_all.75772427
Directory /workspace/14.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_alert_accum_saturation.3224826404
Short name T209
Test name
Test status
Simulation time 35880488 ps
CPU time 2.29 seconds
Started Aug 15 05:00:53 PM PDT 24
Finished Aug 15 05:00:56 PM PDT 24
Peak memory 248792 kb
Host smart-1aee4a59-9c8e-4c10-91f6-d75ae5e0e4a8
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3224826404 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_alert_accum_saturation.3224826404
Directory /workspace/15.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/15.alert_handler_entropy.758287398
Short name T647
Test name
Test status
Simulation time 29506564661 ps
CPU time 1756.68 seconds
Started Aug 15 05:00:45 PM PDT 24
Finished Aug 15 05:30:02 PM PDT 24
Peak memory 273016 kb
Host smart-f421afc2-1ffb-4755-a298-17bb8f0121ff
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=758287398 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy.758287398
Directory /workspace/15.alert_handler_entropy/latest

Test location /workspace/coverage/default/15.alert_handler_entropy_stress.4252973244
Short name T385
Test name
Test status
Simulation time 1232877223 ps
CPU time 28.63 seconds
Started Aug 15 05:00:47 PM PDT 24
Finished Aug 15 05:01:15 PM PDT 24
Peak memory 248676 kb
Host smart-87f20ddf-fc49-49a3-8fa8-fbd17789185f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4252973244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_entropy_stress.4252973244
Directory /workspace/15.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/15.alert_handler_esc_alert_accum.3331179494
Short name T359
Test name
Test status
Simulation time 6127881822 ps
CPU time 123.24 seconds
Started Aug 15 05:00:46 PM PDT 24
Finished Aug 15 05:02:49 PM PDT 24
Peak memory 257032 kb
Host smart-f3ee51ed-b71b-4366-b03f-301b4647a791
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33311
79494 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_alert_accum.3331179494
Directory /workspace/15.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/15.alert_handler_esc_intr_timeout.2357328993
Short name T85
Test name
Test status
Simulation time 610371118 ps
CPU time 21.58 seconds
Started Aug 15 05:00:54 PM PDT 24
Finished Aug 15 05:01:16 PM PDT 24
Peak memory 248128 kb
Host smart-39ced339-5e19-4876-8d36-18da7edce69b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23573
28993 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_esc_intr_timeout.2357328993
Directory /workspace/15.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_lpg.3243662176
Short name T308
Test name
Test status
Simulation time 101442611393 ps
CPU time 1423.14 seconds
Started Aug 15 05:00:46 PM PDT 24
Finished Aug 15 05:24:30 PM PDT 24
Peak memory 272960 kb
Host smart-69b51d22-74f4-4257-bcc5-836e734dd5ce
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3243662176 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg.3243662176
Directory /workspace/15.alert_handler_lpg/latest

Test location /workspace/coverage/default/15.alert_handler_lpg_stub_clk.1963209717
Short name T697
Test name
Test status
Simulation time 85607709668 ps
CPU time 2748.3 seconds
Started Aug 15 05:00:55 PM PDT 24
Finished Aug 15 05:46:44 PM PDT 24
Peak memory 288680 kb
Host smart-a8265e9e-7c8a-433d-b35d-37d7dfa4dcdd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1963209717 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_lpg_stub_clk.1963209717
Directory /workspace/15.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/15.alert_handler_ping_timeout.1077758983
Short name T598
Test name
Test status
Simulation time 5652642773 ps
CPU time 225.9 seconds
Started Aug 15 05:00:54 PM PDT 24
Finished Aug 15 05:04:40 PM PDT 24
Peak memory 248632 kb
Host smart-655e21fc-4923-49ca-8fa6-8119df2b2801
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1077758983 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_ping_timeout.1077758983
Directory /workspace/15.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/15.alert_handler_random_alerts.2581822552
Short name T417
Test name
Test status
Simulation time 1265512389 ps
CPU time 33.98 seconds
Started Aug 15 05:00:45 PM PDT 24
Finished Aug 15 05:01:19 PM PDT 24
Peak memory 256264 kb
Host smart-0122dea3-81b1-47d1-8198-d6fe8899d3fa
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25818
22552 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_alerts.2581822552
Directory /workspace/15.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/15.alert_handler_random_classes.4152988734
Short name T237
Test name
Test status
Simulation time 433949924 ps
CPU time 28.77 seconds
Started Aug 15 05:00:44 PM PDT 24
Finished Aug 15 05:01:13 PM PDT 24
Peak memory 256888 kb
Host smart-16ece7bc-1ae9-4677-a5a0-ca127d07cb65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41529
88734 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_random_classes.4152988734
Directory /workspace/15.alert_handler_random_classes/latest

Test location /workspace/coverage/default/15.alert_handler_sig_int_fail.2644718227
Short name T504
Test name
Test status
Simulation time 502988311 ps
CPU time 35.34 seconds
Started Aug 15 05:00:44 PM PDT 24
Finished Aug 15 05:01:20 PM PDT 24
Peak memory 247968 kb
Host smart-faa61967-2ab9-42ee-9cef-d7d736a45744
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26447
18227 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_sig_int_fail.2644718227
Directory /workspace/15.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/15.alert_handler_smoke.2620992921
Short name T372
Test name
Test status
Simulation time 587507034 ps
CPU time 33.38 seconds
Started Aug 15 05:00:44 PM PDT 24
Finished Aug 15 05:01:18 PM PDT 24
Peak memory 256908 kb
Host smart-c3894b50-9b01-4dae-8e2d-df40d0f1d0a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26209
92921 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_handler_smoke.2620992921
Directory /workspace/15.alert_handler_smoke/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all.3495224946
Short name T65
Test name
Test status
Simulation time 244241721718 ps
CPU time 3753.41 seconds
Started Aug 15 05:00:44 PM PDT 24
Finished Aug 15 06:03:18 PM PDT 24
Peak memory 289704 kb
Host smart-fd5e0e37-8293-4ed9-a372-62f6347c75c9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3495224946 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 15.alert_ha
ndler_stress_all.3495224946
Directory /workspace/15.alert_handler_stress_all/latest

Test location /workspace/coverage/default/15.alert_handler_stress_all_with_rand_reset.4066929699
Short name T246
Test name
Test status
Simulation time 11445570097 ps
CPU time 277.02 seconds
Started Aug 15 05:00:46 PM PDT 24
Finished Aug 15 05:05:23 PM PDT 24
Peak memory 266596 kb
Host smart-0691fd9f-fa5a-4c36-9e1c-57c4ddb2cc79
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4066929699 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 15.alert_handler_stress_all_with_rand_reset.4066929699
Directory /workspace/15.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/16.alert_handler_alert_accum_saturation.541625267
Short name T211
Test name
Test status
Simulation time 35922803 ps
CPU time 2.28 seconds
Started Aug 15 05:00:53 PM PDT 24
Finished Aug 15 05:00:55 PM PDT 24
Peak memory 248868 kb
Host smart-cb6c8d16-b495-4686-b1cd-52fd8ef89aff
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=541625267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_alert_accum_saturation.541625267
Directory /workspace/16.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/16.alert_handler_entropy.3630205003
Short name T58
Test name
Test status
Simulation time 15032522735 ps
CPU time 1352.03 seconds
Started Aug 15 05:00:53 PM PDT 24
Finished Aug 15 05:23:25 PM PDT 24
Peak memory 285444 kb
Host smart-0089dd48-087b-468f-bcc5-bb929b178541
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3630205003 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy.3630205003
Directory /workspace/16.alert_handler_entropy/latest

Test location /workspace/coverage/default/16.alert_handler_entropy_stress.1628396323
Short name T518
Test name
Test status
Simulation time 1352851074 ps
CPU time 17.83 seconds
Started Aug 15 05:00:53 PM PDT 24
Finished Aug 15 05:01:11 PM PDT 24
Peak memory 248656 kb
Host smart-df553d4b-2eec-47d6-84eb-a8b9472fc794
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1628396323 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_entropy_stress.1628396323
Directory /workspace/16.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/16.alert_handler_esc_alert_accum.2827727302
Short name T399
Test name
Test status
Simulation time 1191250740 ps
CPU time 27.22 seconds
Started Aug 15 05:00:51 PM PDT 24
Finished Aug 15 05:01:19 PM PDT 24
Peak memory 248776 kb
Host smart-9905cbbd-a09f-49e0-b641-4305f98e677a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28277
27302 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_alert_accum.2827727302
Directory /workspace/16.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/16.alert_handler_esc_intr_timeout.2672474077
Short name T419
Test name
Test status
Simulation time 716354525 ps
CPU time 37.94 seconds
Started Aug 15 05:00:52 PM PDT 24
Finished Aug 15 05:01:30 PM PDT 24
Peak memory 248736 kb
Host smart-45e5d615-552d-46b4-9afb-3d934c70068b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26724
74077 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_esc_intr_timeout.2672474077
Directory /workspace/16.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_lpg.2458378351
Short name T339
Test name
Test status
Simulation time 13195838534 ps
CPU time 1005.15 seconds
Started Aug 15 05:00:53 PM PDT 24
Finished Aug 15 05:17:38 PM PDT 24
Peak memory 273276 kb
Host smart-4a5d76a4-f68f-472a-9959-cb40e6e1ded0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2458378351 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg.2458378351
Directory /workspace/16.alert_handler_lpg/latest

Test location /workspace/coverage/default/16.alert_handler_lpg_stub_clk.2313806557
Short name T514
Test name
Test status
Simulation time 65724778113 ps
CPU time 1090.37 seconds
Started Aug 15 05:00:58 PM PDT 24
Finished Aug 15 05:19:09 PM PDT 24
Peak memory 287828 kb
Host smart-26f54bd1-a6f7-4668-8ac7-daeeec325c2e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2313806557 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_lpg_stub_clk.2313806557
Directory /workspace/16.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/16.alert_handler_ping_timeout.3376579395
Short name T325
Test name
Test status
Simulation time 17386143613 ps
CPU time 191.47 seconds
Started Aug 15 05:00:52 PM PDT 24
Finished Aug 15 05:04:04 PM PDT 24
Peak memory 248776 kb
Host smart-f5dc4aae-c8a4-4222-b68f-ff237e489acf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3376579395 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_ping_timeout.3376579395
Directory /workspace/16.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/16.alert_handler_random_alerts.1791925588
Short name T685
Test name
Test status
Simulation time 74076635 ps
CPU time 6.75 seconds
Started Aug 15 05:00:53 PM PDT 24
Finished Aug 15 05:01:00 PM PDT 24
Peak memory 250552 kb
Host smart-25fd15cc-a75c-426e-84e7-1cae07fc207d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17919
25588 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_alerts.1791925588
Directory /workspace/16.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/16.alert_handler_random_classes.1312570263
Short name T599
Test name
Test status
Simulation time 174403676 ps
CPU time 6.97 seconds
Started Aug 15 05:00:46 PM PDT 24
Finished Aug 15 05:00:53 PM PDT 24
Peak memory 239612 kb
Host smart-d154c2d4-2990-4351-aedf-eb284eae657f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13125
70263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_random_classes.1312570263
Directory /workspace/16.alert_handler_random_classes/latest

Test location /workspace/coverage/default/16.alert_handler_sig_int_fail.1566460147
Short name T671
Test name
Test status
Simulation time 302504113 ps
CPU time 26.02 seconds
Started Aug 15 05:00:52 PM PDT 24
Finished Aug 15 05:01:19 PM PDT 24
Peak memory 247968 kb
Host smart-77ffe2ac-1f30-4e62-a929-781108127c1c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15664
60147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_sig_int_fail.1566460147
Directory /workspace/16.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/16.alert_handler_smoke.4137092198
Short name T429
Test name
Test status
Simulation time 4002956036 ps
CPU time 62.33 seconds
Started Aug 15 05:00:45 PM PDT 24
Finished Aug 15 05:01:47 PM PDT 24
Peak memory 256056 kb
Host smart-cc4d00a2-1f59-4133-94a6-a50b4d9cf595
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41370
92198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_handler_smoke.4137092198
Directory /workspace/16.alert_handler_smoke/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all.3742563828
Short name T503
Test name
Test status
Simulation time 53341760428 ps
CPU time 2950.13 seconds
Started Aug 15 05:00:54 PM PDT 24
Finished Aug 15 05:50:05 PM PDT 24
Peak memory 289320 kb
Host smart-8c1a1b34-2d3e-43d2-bd14-0fa6ffd5be3c
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3742563828 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 16.alert_ha
ndler_stress_all.3742563828
Directory /workspace/16.alert_handler_stress_all/latest

Test location /workspace/coverage/default/16.alert_handler_stress_all_with_rand_reset.167756088
Short name T109
Test name
Test status
Simulation time 1298475491 ps
CPU time 154.59 seconds
Started Aug 15 05:00:51 PM PDT 24
Finished Aug 15 05:03:26 PM PDT 24
Peak memory 265344 kb
Host smart-47ce1c96-3b47-4091-b8a4-f50b6746f535
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=167756088 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 16.alert_handler_stress_all_with_rand_reset.167756088
Directory /workspace/16.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/17.alert_handler_entropy.3946283370
Short name T545
Test name
Test status
Simulation time 146834032074 ps
CPU time 2245.65 seconds
Started Aug 15 05:00:52 PM PDT 24
Finished Aug 15 05:38:18 PM PDT 24
Peak memory 288936 kb
Host smart-52381854-4a20-45a2-b582-6b930e81a40c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3946283370 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy.3946283370
Directory /workspace/17.alert_handler_entropy/latest

Test location /workspace/coverage/default/17.alert_handler_entropy_stress.3385121833
Short name T616
Test name
Test status
Simulation time 1010367947 ps
CPU time 14.24 seconds
Started Aug 15 05:00:53 PM PDT 24
Finished Aug 15 05:01:08 PM PDT 24
Peak memory 248672 kb
Host smart-6a65706e-4744-4da6-b77d-b80dc05a958f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3385121833 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_entropy_stress.3385121833
Directory /workspace/17.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/17.alert_handler_esc_alert_accum.3098189451
Short name T463
Test name
Test status
Simulation time 13993965146 ps
CPU time 196.61 seconds
Started Aug 15 05:00:52 PM PDT 24
Finished Aug 15 05:04:09 PM PDT 24
Peak memory 256164 kb
Host smart-4dce1091-4fbc-4fcc-965c-015ad53f84f9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30981
89451 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_alert_accum.3098189451
Directory /workspace/17.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/17.alert_handler_esc_intr_timeout.3094020234
Short name T437
Test name
Test status
Simulation time 737629970 ps
CPU time 53.15 seconds
Started Aug 15 05:00:53 PM PDT 24
Finished Aug 15 05:01:46 PM PDT 24
Peak memory 248312 kb
Host smart-bbe0dbcb-9768-4777-8e2d-56c2696c7cfc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30940
20234 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_esc_intr_timeout.3094020234
Directory /workspace/17.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_lpg_stub_clk.1273473900
Short name T376
Test name
Test status
Simulation time 6947793007 ps
CPU time 615.32 seconds
Started Aug 15 05:00:55 PM PDT 24
Finished Aug 15 05:11:10 PM PDT 24
Peak memory 272584 kb
Host smart-0cd88cdb-027e-4885-8c02-474007264c38
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1273473900 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_lpg_stub_clk.1273473900
Directory /workspace/17.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/17.alert_handler_ping_timeout.2411079900
Short name T320
Test name
Test status
Simulation time 6157193216 ps
CPU time 134.7 seconds
Started Aug 15 05:00:51 PM PDT 24
Finished Aug 15 05:03:06 PM PDT 24
Peak memory 248716 kb
Host smart-9732d0c6-356a-4df6-8e3f-699d247ad185
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2411079900 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_ping_timeout.2411079900
Directory /workspace/17.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/17.alert_handler_random_alerts.3448135610
Short name T361
Test name
Test status
Simulation time 269953152 ps
CPU time 24.13 seconds
Started Aug 15 05:00:53 PM PDT 24
Finished Aug 15 05:01:17 PM PDT 24
Peak memory 256220 kb
Host smart-73736841-fdcf-49d0-a2b6-f622b1ad09a9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34481
35610 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_alerts.3448135610
Directory /workspace/17.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/17.alert_handler_random_classes.271431326
Short name T449
Test name
Test status
Simulation time 3616804820 ps
CPU time 56.55 seconds
Started Aug 15 05:00:52 PM PDT 24
Finished Aug 15 05:01:49 PM PDT 24
Peak memory 248696 kb
Host smart-9152b37b-847f-42fe-8102-f44fb1d633e2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27143
1326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_random_classes.271431326
Directory /workspace/17.alert_handler_random_classes/latest

Test location /workspace/coverage/default/17.alert_handler_sig_int_fail.2434345704
Short name T265
Test name
Test status
Simulation time 141497870 ps
CPU time 23.04 seconds
Started Aug 15 05:00:51 PM PDT 24
Finished Aug 15 05:01:15 PM PDT 24
Peak memory 248752 kb
Host smart-7670ad34-726f-45c9-a06a-0638190978b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24343
45704 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_sig_int_fail.2434345704
Directory /workspace/17.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/17.alert_handler_smoke.1181974002
Short name T589
Test name
Test status
Simulation time 600889779 ps
CPU time 23.34 seconds
Started Aug 15 05:00:55 PM PDT 24
Finished Aug 15 05:01:19 PM PDT 24
Peak memory 255984 kb
Host smart-1396aa8f-9633-48d6-b66d-cd3171816fe3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11819
74002 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 17.alert_handler_smoke.1181974002
Directory /workspace/17.alert_handler_smoke/latest

Test location /workspace/coverage/default/17.alert_handler_stress_all_with_rand_reset.3833543277
Short name T711
Test name
Test status
Simulation time 1315352808 ps
CPU time 131.1 seconds
Started Aug 15 05:00:54 PM PDT 24
Finished Aug 15 05:03:06 PM PDT 24
Peak memory 265284 kb
Host smart-e8d5baac-9732-40ca-a9b4-9bfea638e464
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3833543277 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 17.alert_handler_stress_all_with_rand_reset.3833543277
Directory /workspace/17.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/18.alert_handler_alert_accum_saturation.805054868
Short name T213
Test name
Test status
Simulation time 68143164 ps
CPU time 3.67 seconds
Started Aug 15 05:01:03 PM PDT 24
Finished Aug 15 05:01:07 PM PDT 24
Peak memory 248892 kb
Host smart-f1ae1449-e0c8-430c-8614-993694086ebb
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=805054868 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_alert_accum_saturation.805054868
Directory /workspace/18.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/18.alert_handler_entropy.175184555
Short name T665
Test name
Test status
Simulation time 33739383656 ps
CPU time 2038.55 seconds
Started Aug 15 05:01:04 PM PDT 24
Finished Aug 15 05:35:03 PM PDT 24
Peak memory 281560 kb
Host smart-8259183d-423b-4d2f-b576-1f1ce4846112
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=175184555 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy.175184555
Directory /workspace/18.alert_handler_entropy/latest

Test location /workspace/coverage/default/18.alert_handler_entropy_stress.3397414857
Short name T578
Test name
Test status
Simulation time 501917128 ps
CPU time 8.53 seconds
Started Aug 15 05:01:03 PM PDT 24
Finished Aug 15 05:01:12 PM PDT 24
Peak memory 248668 kb
Host smart-afe08f4c-fa01-4729-8e60-1567ee0c499f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3397414857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_entropy_stress.3397414857
Directory /workspace/18.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/18.alert_handler_esc_alert_accum.347262131
Short name T442
Test name
Test status
Simulation time 305684444 ps
CPU time 8.47 seconds
Started Aug 15 05:01:03 PM PDT 24
Finished Aug 15 05:01:11 PM PDT 24
Peak memory 255108 kb
Host smart-cff37d4b-3710-4376-aea2-67ea9b5c186c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34726
2131 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_alert_accum.347262131
Directory /workspace/18.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/18.alert_handler_esc_intr_timeout.1629423654
Short name T458
Test name
Test status
Simulation time 242234596 ps
CPU time 19.32 seconds
Started Aug 15 05:01:07 PM PDT 24
Finished Aug 15 05:01:26 PM PDT 24
Peak memory 256176 kb
Host smart-33a2b380-1ca5-4849-bbec-293f0a79d72b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16294
23654 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_esc_intr_timeout.1629423654
Directory /workspace/18.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_lpg.2053052106
Short name T321
Test name
Test status
Simulation time 66699532040 ps
CPU time 1356.62 seconds
Started Aug 15 05:01:05 PM PDT 24
Finished Aug 15 05:23:42 PM PDT 24
Peak memory 289136 kb
Host smart-eff8046d-c29a-4bbc-b453-f9bbf419a507
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2053052106 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg.2053052106
Directory /workspace/18.alert_handler_lpg/latest

Test location /workspace/coverage/default/18.alert_handler_lpg_stub_clk.996926060
Short name T566
Test name
Test status
Simulation time 52676266099 ps
CPU time 1604.09 seconds
Started Aug 15 05:01:06 PM PDT 24
Finished Aug 15 05:27:50 PM PDT 24
Peak memory 269292 kb
Host smart-2adad88c-bc99-4d74-bb0b-fd01883aea6b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=996926060 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_lpg_stub_clk.996926060
Directory /workspace/18.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/18.alert_handler_ping_timeout.2774181462
Short name T329
Test name
Test status
Simulation time 21750540511 ps
CPU time 463.08 seconds
Started Aug 15 05:01:04 PM PDT 24
Finished Aug 15 05:08:47 PM PDT 24
Peak memory 248708 kb
Host smart-779bc401-326c-4830-bd73-c585ca452cc8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2774181462 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_ping_timeout.2774181462
Directory /workspace/18.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/18.alert_handler_random_alerts.3877072781
Short name T97
Test name
Test status
Simulation time 1667810255 ps
CPU time 40.15 seconds
Started Aug 15 05:01:03 PM PDT 24
Finished Aug 15 05:01:43 PM PDT 24
Peak memory 255928 kb
Host smart-4c04f119-fa2e-4c08-b395-552ae8c7d876
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38770
72781 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_alerts.3877072781
Directory /workspace/18.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/18.alert_handler_random_classes.1886005061
Short name T67
Test name
Test status
Simulation time 237865158 ps
CPU time 14.02 seconds
Started Aug 15 05:01:03 PM PDT 24
Finished Aug 15 05:01:18 PM PDT 24
Peak memory 247888 kb
Host smart-35019b06-997a-4ca8-8ddf-664bc196359e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18860
05061 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_random_classes.1886005061
Directory /workspace/18.alert_handler_random_classes/latest

Test location /workspace/coverage/default/18.alert_handler_smoke.3332409611
Short name T511
Test name
Test status
Simulation time 248784718 ps
CPU time 24.98 seconds
Started Aug 15 05:01:05 PM PDT 24
Finished Aug 15 05:01:30 PM PDT 24
Peak memory 256800 kb
Host smart-f5d45031-bfdf-4b78-aef6-aeff0c3dbd2b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33324
09611 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_handler_smoke.3332409611
Directory /workspace/18.alert_handler_smoke/latest

Test location /workspace/coverage/default/18.alert_handler_stress_all.1768316881
Short name T592
Test name
Test status
Simulation time 12233696918 ps
CPU time 254.35 seconds
Started Aug 15 05:01:03 PM PDT 24
Finished Aug 15 05:05:18 PM PDT 24
Peak memory 256468 kb
Host smart-1394ded5-a641-46ef-8cfe-9553d988d98f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1768316881 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 18.alert_ha
ndler_stress_all.1768316881
Directory /workspace/18.alert_handler_stress_all/latest

Test location /workspace/coverage/default/19.alert_handler_alert_accum_saturation.259462772
Short name T203
Test name
Test status
Simulation time 24030839 ps
CPU time 2.4 seconds
Started Aug 15 05:01:14 PM PDT 24
Finished Aug 15 05:01:17 PM PDT 24
Peak memory 248980 kb
Host smart-78c6180f-4c7a-494f-927b-ee9fd9a6406c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=259462772 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_alert_accum_saturation.259462772
Directory /workspace/19.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/19.alert_handler_entropy.2639652758
Short name T661
Test name
Test status
Simulation time 176614499555 ps
CPU time 2399.45 seconds
Started Aug 15 05:01:13 PM PDT 24
Finished Aug 15 05:41:13 PM PDT 24
Peak memory 286456 kb
Host smart-98f213aa-a179-4218-8f13-b44ec84c7c00
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2639652758 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy.2639652758
Directory /workspace/19.alert_handler_entropy/latest

Test location /workspace/coverage/default/19.alert_handler_entropy_stress.817202076
Short name T436
Test name
Test status
Simulation time 532241176 ps
CPU time 13.09 seconds
Started Aug 15 05:01:13 PM PDT 24
Finished Aug 15 05:01:27 PM PDT 24
Peak memory 248764 kb
Host smart-09fe2873-fdae-4346-a29f-123f37b60f9a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=817202076 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+fs
m+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_entropy_stress.817202076
Directory /workspace/19.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/19.alert_handler_esc_alert_accum.462825720
Short name T700
Test name
Test status
Simulation time 8500547437 ps
CPU time 134.34 seconds
Started Aug 15 05:01:13 PM PDT 24
Finished Aug 15 05:03:27 PM PDT 24
Peak memory 256884 kb
Host smart-a2ba8057-3899-4f8d-94a8-d1c7949e0c32
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46282
5720 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_alert_accum.462825720
Directory /workspace/19.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/19.alert_handler_esc_intr_timeout.1968964107
Short name T395
Test name
Test status
Simulation time 4590746322 ps
CPU time 18.35 seconds
Started Aug 15 05:01:13 PM PDT 24
Finished Aug 15 05:01:31 PM PDT 24
Peak memory 248420 kb
Host smart-dfcc3d1b-51ae-486e-95b8-c77f6956099e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19689
64107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_esc_intr_timeout.1968964107
Directory /workspace/19.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_lpg_stub_clk.1609627327
Short name T615
Test name
Test status
Simulation time 116615545242 ps
CPU time 2409.52 seconds
Started Aug 15 05:01:13 PM PDT 24
Finished Aug 15 05:41:23 PM PDT 24
Peak memory 289480 kb
Host smart-8db91a77-ef26-4498-9ea8-059af8ea5aea
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1609627327 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_lpg_stub_clk.1609627327
Directory /workspace/19.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/19.alert_handler_ping_timeout.3306608049
Short name T562
Test name
Test status
Simulation time 18987005578 ps
CPU time 200.44 seconds
Started Aug 15 05:01:14 PM PDT 24
Finished Aug 15 05:04:35 PM PDT 24
Peak memory 248024 kb
Host smart-ac462715-b35c-4880-95d0-8cc0a51ac559
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306608049 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_ping_timeout.3306608049
Directory /workspace/19.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/19.alert_handler_random_alerts.1107605858
Short name T456
Test name
Test status
Simulation time 1255863820 ps
CPU time 26.1 seconds
Started Aug 15 05:01:18 PM PDT 24
Finished Aug 15 05:01:44 PM PDT 24
Peak memory 248788 kb
Host smart-678f9eb2-b5db-4469-b920-86c7a52a4573
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11076
05858 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_alerts.1107605858
Directory /workspace/19.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/19.alert_handler_random_classes.1092253648
Short name T260
Test name
Test status
Simulation time 960834085 ps
CPU time 51.04 seconds
Started Aug 15 05:01:14 PM PDT 24
Finished Aug 15 05:02:05 PM PDT 24
Peak memory 248144 kb
Host smart-f16ab9a4-4aca-4655-9b6e-5d21a9f17d1d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10922
53648 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_random_classes.1092253648
Directory /workspace/19.alert_handler_random_classes/latest

Test location /workspace/coverage/default/19.alert_handler_smoke.2241967579
Short name T454
Test name
Test status
Simulation time 737910165 ps
CPU time 37.63 seconds
Started Aug 15 05:01:12 PM PDT 24
Finished Aug 15 05:01:50 PM PDT 24
Peak memory 256900 kb
Host smart-e2472842-d2fd-4eaa-ae70-78f5e5777dc3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22419
67579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_handler_smoke.2241967579
Directory /workspace/19.alert_handler_smoke/latest

Test location /workspace/coverage/default/19.alert_handler_stress_all.2541516450
Short name T499
Test name
Test status
Simulation time 11180262015 ps
CPU time 1110.87 seconds
Started Aug 15 05:01:15 PM PDT 24
Finished Aug 15 05:19:46 PM PDT 24
Peak memory 289564 kb
Host smart-79882adb-fb48-4e0c-85df-dcaf573f4be3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2541516450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 19.alert_ha
ndler_stress_all.2541516450
Directory /workspace/19.alert_handler_stress_all/latest

Test location /workspace/coverage/default/2.alert_handler_alert_accum_saturation.2934470519
Short name T216
Test name
Test status
Simulation time 94852361 ps
CPU time 3.2 seconds
Started Aug 15 04:59:35 PM PDT 24
Finished Aug 15 04:59:39 PM PDT 24
Peak memory 248976 kb
Host smart-7962dce7-3858-45e5-b34f-c82910005b9b
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2934470519 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_alert_accum_saturation.2934470519
Directory /workspace/2.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/2.alert_handler_entropy.1799554163
Short name T268
Test name
Test status
Simulation time 82604126117 ps
CPU time 873.25 seconds
Started Aug 15 04:59:33 PM PDT 24
Finished Aug 15 05:14:06 PM PDT 24
Peak memory 273388 kb
Host smart-300e7415-1cd2-4ac7-ae24-4454c6a50b6d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1799554163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy.1799554163
Directory /workspace/2.alert_handler_entropy/latest

Test location /workspace/coverage/default/2.alert_handler_entropy_stress.2127052816
Short name T502
Test name
Test status
Simulation time 118736440 ps
CPU time 7.38 seconds
Started Aug 15 04:59:37 PM PDT 24
Finished Aug 15 04:59:45 PM PDT 24
Peak memory 248708 kb
Host smart-14360640-c3aa-4a0c-915e-aee16a33eac3
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2127052816 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_entropy_stress.2127052816
Directory /workspace/2.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/2.alert_handler_esc_alert_accum.1718289746
Short name T411
Test name
Test status
Simulation time 710779267 ps
CPU time 35.21 seconds
Started Aug 15 04:59:37 PM PDT 24
Finished Aug 15 05:00:13 PM PDT 24
Peak memory 256180 kb
Host smart-c42193a9-34ea-401b-b822-5ffbf6f8d720
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17182
89746 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_alert_accum.1718289746
Directory /workspace/2.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/2.alert_handler_esc_intr_timeout.1023937979
Short name T445
Test name
Test status
Simulation time 1125650413 ps
CPU time 25.58 seconds
Started Aug 15 04:59:33 PM PDT 24
Finished Aug 15 04:59:59 PM PDT 24
Peak memory 255468 kb
Host smart-20156a7c-f472-4dfc-9271-a57005574010
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10239
37979 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_esc_intr_timeout.1023937979
Directory /workspace/2.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_lpg.2250974578
Short name T296
Test name
Test status
Simulation time 876829559671 ps
CPU time 2454.89 seconds
Started Aug 15 04:59:37 PM PDT 24
Finished Aug 15 05:40:33 PM PDT 24
Peak memory 281592 kb
Host smart-fc344614-18a8-4175-8990-b068ea485da3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2250974578 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg.2250974578
Directory /workspace/2.alert_handler_lpg/latest

Test location /workspace/coverage/default/2.alert_handler_lpg_stub_clk.1498169562
Short name T684
Test name
Test status
Simulation time 124921778585 ps
CPU time 1926.26 seconds
Started Aug 15 04:59:36 PM PDT 24
Finished Aug 15 05:31:43 PM PDT 24
Peak memory 288856 kb
Host smart-d61de411-4310-4479-8d0c-f816886ae26f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1498169562 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_lpg_stub_clk.1498169562
Directory /workspace/2.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/2.alert_handler_ping_timeout.1477373793
Short name T6
Test name
Test status
Simulation time 5518817279 ps
CPU time 227.74 seconds
Started Aug 15 04:59:34 PM PDT 24
Finished Aug 15 05:03:22 PM PDT 24
Peak memory 248840 kb
Host smart-aab92e5e-69f7-4677-ad28-8a4051aac73e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1477373793 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_ping_timeout.1477373793
Directory /workspace/2.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/2.alert_handler_random_alerts.1976404287
Short name T568
Test name
Test status
Simulation time 3632176313 ps
CPU time 61.46 seconds
Started Aug 15 04:59:36 PM PDT 24
Finished Aug 15 05:00:38 PM PDT 24
Peak memory 256052 kb
Host smart-230d3570-bbae-41ba-b846-0517994f4291
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19764
04287 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_alerts.1976404287
Directory /workspace/2.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/2.alert_handler_random_classes.2930722555
Short name T689
Test name
Test status
Simulation time 89824937 ps
CPU time 7.47 seconds
Started Aug 15 04:59:32 PM PDT 24
Finished Aug 15 04:59:39 PM PDT 24
Peak memory 252408 kb
Host smart-44e67ca4-484c-48ca-a02b-7fad29c71e12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29307
22555 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_random_classes.2930722555
Directory /workspace/2.alert_handler_random_classes/latest

Test location /workspace/coverage/default/2.alert_handler_sig_int_fail.1524060244
Short name T406
Test name
Test status
Simulation time 185752688 ps
CPU time 20.24 seconds
Started Aug 15 04:59:32 PM PDT 24
Finished Aug 15 04:59:52 PM PDT 24
Peak memory 256948 kb
Host smart-295639be-d264-42d6-9544-cea45f9b625f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15240
60244 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_sig_int_fail.1524060244
Directory /workspace/2.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/2.alert_handler_smoke.916600148
Short name T556
Test name
Test status
Simulation time 5989917002 ps
CPU time 28.06 seconds
Started Aug 15 04:59:37 PM PDT 24
Finished Aug 15 05:00:06 PM PDT 24
Peak memory 255984 kb
Host smart-c0c467e0-d7df-4508-a06d-7f8ece657263
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=91660
0148 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 2.alert_handler_smoke.916600148
Directory /workspace/2.alert_handler_smoke/latest

Test location /workspace/coverage/default/2.alert_handler_stress_all_with_rand_reset.829586919
Short name T630
Test name
Test status
Simulation time 3054401153 ps
CPU time 249.95 seconds
Started Aug 15 04:59:36 PM PDT 24
Finished Aug 15 05:03:46 PM PDT 24
Peak memory 265368 kb
Host smart-0de13238-e6fb-4dcc-ae61-24a29d1d86ba
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=829586919 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 2.alert_handler_stress_all_with_rand_reset.829586919
Directory /workspace/2.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/20.alert_handler_entropy.2976483016
Short name T694
Test name
Test status
Simulation time 40761431667 ps
CPU time 1019.44 seconds
Started Aug 15 05:01:13 PM PDT 24
Finished Aug 15 05:18:13 PM PDT 24
Peak memory 273008 kb
Host smart-d8de61d0-e83e-4aa6-98e1-e78a04b45d64
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2976483016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_entropy.2976483016
Directory /workspace/20.alert_handler_entropy/latest

Test location /workspace/coverage/default/20.alert_handler_esc_alert_accum.2399852647
Short name T115
Test name
Test status
Simulation time 3516952493 ps
CPU time 147.7 seconds
Started Aug 15 05:01:13 PM PDT 24
Finished Aug 15 05:03:41 PM PDT 24
Peak memory 257060 kb
Host smart-b7739b16-bd12-4897-92b7-4339c763d5e6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23998
52647 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_alert_accum.2399852647
Directory /workspace/20.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/20.alert_handler_esc_intr_timeout.1491917651
Short name T397
Test name
Test status
Simulation time 201558238 ps
CPU time 16.31 seconds
Started Aug 15 05:01:14 PM PDT 24
Finished Aug 15 05:01:31 PM PDT 24
Peak memory 255960 kb
Host smart-b1ca6c15-1d12-4808-9a5b-e65ab3ade5e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14919
17651 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_esc_intr_timeout.1491917651
Directory /workspace/20.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_lpg.2376359474
Short name T357
Test name
Test status
Simulation time 30318400660 ps
CPU time 831.19 seconds
Started Aug 15 05:01:13 PM PDT 24
Finished Aug 15 05:15:05 PM PDT 24
Peak memory 273368 kb
Host smart-c34a8e90-5c04-4ad9-9b6e-92b5cc770d3f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2376359474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg.2376359474
Directory /workspace/20.alert_handler_lpg/latest

Test location /workspace/coverage/default/20.alert_handler_lpg_stub_clk.4055903117
Short name T108
Test name
Test status
Simulation time 16290486780 ps
CPU time 740.47 seconds
Started Aug 15 05:01:22 PM PDT 24
Finished Aug 15 05:13:43 PM PDT 24
Peak memory 265172 kb
Host smart-8b30ea6c-4ef7-4353-ba07-b40bed7aa7e4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4055903117 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_lpg_stub_clk.4055903117
Directory /workspace/20.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/20.alert_handler_ping_timeout.2269836381
Short name T318
Test name
Test status
Simulation time 6411331411 ps
CPU time 265.3 seconds
Started Aug 15 05:01:14 PM PDT 24
Finished Aug 15 05:05:40 PM PDT 24
Peak memory 248804 kb
Host smart-dc786843-0205-4043-8264-f38e831b45c0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2269836381 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_ping_timeout.2269836381
Directory /workspace/20.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/20.alert_handler_random_alerts.1529047964
Short name T658
Test name
Test status
Simulation time 1048329005 ps
CPU time 18.14 seconds
Started Aug 15 05:01:14 PM PDT 24
Finished Aug 15 05:01:32 PM PDT 24
Peak memory 248688 kb
Host smart-788e4370-a182-459c-8bbe-959d502ce76c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15290
47964 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_alerts.1529047964
Directory /workspace/20.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/20.alert_handler_random_classes.1952804483
Short name T123
Test name
Test status
Simulation time 186481141 ps
CPU time 14.12 seconds
Started Aug 15 05:01:16 PM PDT 24
Finished Aug 15 05:01:30 PM PDT 24
Peak memory 247888 kb
Host smart-66726758-6967-49f9-9da7-95a42a3a99e0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19528
04483 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_random_classes.1952804483
Directory /workspace/20.alert_handler_random_classes/latest

Test location /workspace/coverage/default/20.alert_handler_sig_int_fail.2040651382
Short name T564
Test name
Test status
Simulation time 57093798 ps
CPU time 4.5 seconds
Started Aug 15 05:01:15 PM PDT 24
Finished Aug 15 05:01:19 PM PDT 24
Peak memory 239884 kb
Host smart-8c16f826-36ef-4079-b58c-92fcb92388f7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20406
51382 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_sig_int_fail.2040651382
Directory /workspace/20.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/20.alert_handler_smoke.1287254779
Short name T235
Test name
Test status
Simulation time 281308546 ps
CPU time 17.8 seconds
Started Aug 15 05:01:15 PM PDT 24
Finished Aug 15 05:01:33 PM PDT 24
Peak memory 253796 kb
Host smart-305b690d-e671-4a2d-b5c7-05420920d5a0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12872
54779 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_handler_smoke.1287254779
Directory /workspace/20.alert_handler_smoke/latest

Test location /workspace/coverage/default/20.alert_handler_stress_all.2360427088
Short name T271
Test name
Test status
Simulation time 40093980651 ps
CPU time 2562.72 seconds
Started Aug 15 05:01:24 PM PDT 24
Finished Aug 15 05:44:07 PM PDT 24
Peak memory 289736 kb
Host smart-4c2649a7-5cdd-49ba-b4c3-84322215b937
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2360427088 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 20.alert_ha
ndler_stress_all.2360427088
Directory /workspace/20.alert_handler_stress_all/latest

Test location /workspace/coverage/default/21.alert_handler_entropy.3327655838
Short name T605
Test name
Test status
Simulation time 10484913636 ps
CPU time 1048.07 seconds
Started Aug 15 05:01:28 PM PDT 24
Finished Aug 15 05:18:56 PM PDT 24
Peak memory 271196 kb
Host smart-144645e9-ee6b-4f08-aad9-d2bf59f3fb26
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3327655838 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_entropy.3327655838
Directory /workspace/21.alert_handler_entropy/latest

Test location /workspace/coverage/default/21.alert_handler_esc_alert_accum.542951950
Short name T386
Test name
Test status
Simulation time 3877957127 ps
CPU time 112.35 seconds
Started Aug 15 05:01:24 PM PDT 24
Finished Aug 15 05:03:17 PM PDT 24
Peak memory 255988 kb
Host smart-b438b982-b7ae-4b8f-8d94-b2a5f66f7fe9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54295
1950 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_alert_accum.542951950
Directory /workspace/21.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/21.alert_handler_esc_intr_timeout.2795792227
Short name T554
Test name
Test status
Simulation time 3711955015 ps
CPU time 46.51 seconds
Started Aug 15 05:01:22 PM PDT 24
Finished Aug 15 05:02:09 PM PDT 24
Peak memory 256284 kb
Host smart-d6cf676a-ccfd-439c-a768-06b304f107c6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27957
92227 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_esc_intr_timeout.2795792227
Directory /workspace/21.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_lpg.1660320104
Short name T667
Test name
Test status
Simulation time 35999884923 ps
CPU time 2125.09 seconds
Started Aug 15 05:01:23 PM PDT 24
Finished Aug 15 05:36:48 PM PDT 24
Peak memory 288112 kb
Host smart-11ba75b9-d465-4aa1-8827-4d4b9c7dca05
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1660320104 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg.1660320104
Directory /workspace/21.alert_handler_lpg/latest

Test location /workspace/coverage/default/21.alert_handler_lpg_stub_clk.3278469237
Short name T245
Test name
Test status
Simulation time 13237276875 ps
CPU time 1352.87 seconds
Started Aug 15 05:01:25 PM PDT 24
Finished Aug 15 05:23:58 PM PDT 24
Peak memory 281736 kb
Host smart-069f742a-eaf2-4579-944e-52ba849174f0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278469237 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_lpg_stub_clk.3278469237
Directory /workspace/21.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/21.alert_handler_ping_timeout.3192754526
Short name T698
Test name
Test status
Simulation time 27183203513 ps
CPU time 603.01 seconds
Started Aug 15 05:01:28 PM PDT 24
Finished Aug 15 05:11:31 PM PDT 24
Peak memory 256984 kb
Host smart-360b1335-f5c8-45a2-89a4-9061605b895f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3192754526 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_ping_timeout.3192754526
Directory /workspace/21.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/21.alert_handler_random_alerts.1886690986
Short name T392
Test name
Test status
Simulation time 151062475 ps
CPU time 15.5 seconds
Started Aug 15 05:01:23 PM PDT 24
Finished Aug 15 05:01:38 PM PDT 24
Peak memory 248776 kb
Host smart-3dd84b1b-9bcd-4909-b9c2-05898bc22b48
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18866
90986 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_alerts.1886690986
Directory /workspace/21.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/21.alert_handler_random_classes.3538311664
Short name T467
Test name
Test status
Simulation time 550044844 ps
CPU time 24.4 seconds
Started Aug 15 05:01:22 PM PDT 24
Finished Aug 15 05:01:47 PM PDT 24
Peak memory 248668 kb
Host smart-fcd47ecb-9243-477f-8752-70680316399d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35383
11664 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_random_classes.3538311664
Directory /workspace/21.alert_handler_random_classes/latest

Test location /workspace/coverage/default/21.alert_handler_sig_int_fail.2679455077
Short name T373
Test name
Test status
Simulation time 826056810 ps
CPU time 14.12 seconds
Started Aug 15 05:01:25 PM PDT 24
Finished Aug 15 05:01:39 PM PDT 24
Peak memory 248988 kb
Host smart-9113f7da-a8d0-4298-935c-fd321ffc4dad
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26794
55077 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_sig_int_fail.2679455077
Directory /workspace/21.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/21.alert_handler_smoke.86418498
Short name T640
Test name
Test status
Simulation time 969340469 ps
CPU time 25.03 seconds
Started Aug 15 05:01:22 PM PDT 24
Finished Aug 15 05:01:48 PM PDT 24
Peak memory 256832 kb
Host smart-48535cb4-0047-4a71-80df-adfb5dd69a44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86418
498 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_handler_smoke.86418498
Directory /workspace/21.alert_handler_smoke/latest

Test location /workspace/coverage/default/21.alert_handler_stress_all.3681545576
Short name T535
Test name
Test status
Simulation time 1439852252 ps
CPU time 40.21 seconds
Started Aug 15 05:01:28 PM PDT 24
Finished Aug 15 05:02:08 PM PDT 24
Peak memory 255736 kb
Host smart-7a1f8ed5-c5dc-41c4-9e8e-9c8b37b088e3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3681545576 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 21.alert_ha
ndler_stress_all.3681545576
Directory /workspace/21.alert_handler_stress_all/latest

Test location /workspace/coverage/default/22.alert_handler_esc_alert_accum.2813445908
Short name T455
Test name
Test status
Simulation time 1868023298 ps
CPU time 111.02 seconds
Started Aug 15 05:01:22 PM PDT 24
Finished Aug 15 05:03:13 PM PDT 24
Peak memory 256976 kb
Host smart-3048c6d4-984a-4c08-a137-eed38b2da849
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28134
45908 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_alert_accum.2813445908
Directory /workspace/22.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/22.alert_handler_esc_intr_timeout.3501162684
Short name T572
Test name
Test status
Simulation time 827863103 ps
CPU time 55.78 seconds
Started Aug 15 05:01:23 PM PDT 24
Finished Aug 15 05:02:19 PM PDT 24
Peak memory 256940 kb
Host smart-0388daad-88ce-499e-8d1b-862b96096a14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35011
62684 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_esc_intr_timeout.3501162684
Directory /workspace/22.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_lpg_stub_clk.4176236515
Short name T415
Test name
Test status
Simulation time 193602410148 ps
CPU time 2188.38 seconds
Started Aug 15 05:01:33 PM PDT 24
Finished Aug 15 05:38:02 PM PDT 24
Peak memory 273240 kb
Host smart-9a880e24-86dd-48be-8d83-97ab6c161afe
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176236515 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_lpg_stub_clk.4176236515
Directory /workspace/22.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/22.alert_handler_ping_timeout.1685989457
Short name T313
Test name
Test status
Simulation time 7527567656 ps
CPU time 302.25 seconds
Started Aug 15 05:01:33 PM PDT 24
Finished Aug 15 05:06:35 PM PDT 24
Peak memory 248704 kb
Host smart-17a685fa-15b4-4e9e-a93f-2a4a28ee4aa2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1685989457 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_ping_timeout.1685989457
Directory /workspace/22.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/22.alert_handler_random_alerts.4288049510
Short name T238
Test name
Test status
Simulation time 3106159194 ps
CPU time 47.42 seconds
Started Aug 15 05:01:23 PM PDT 24
Finished Aug 15 05:02:11 PM PDT 24
Peak memory 256336 kb
Host smart-ba577c96-9340-49f2-ab69-3e210872e387
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42880
49510 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_alerts.4288049510
Directory /workspace/22.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/22.alert_handler_random_classes.3569945783
Short name T122
Test name
Test status
Simulation time 2075991630 ps
CPU time 30.85 seconds
Started Aug 15 05:01:22 PM PDT 24
Finished Aug 15 05:01:53 PM PDT 24
Peak memory 256144 kb
Host smart-26046f62-3c96-4be8-a8f6-3b1e84e60c06
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35699
45783 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_random_classes.3569945783
Directory /workspace/22.alert_handler_random_classes/latest

Test location /workspace/coverage/default/22.alert_handler_sig_int_fail.3116692831
Short name T27
Test name
Test status
Simulation time 6248543647 ps
CPU time 38.27 seconds
Started Aug 15 05:01:24 PM PDT 24
Finished Aug 15 05:02:03 PM PDT 24
Peak memory 248556 kb
Host smart-819a2579-f3d4-437f-a6a8-1274788d96fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31166
92831 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_sig_int_fail.3116692831
Directory /workspace/22.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/22.alert_handler_smoke.161458945
Short name T221
Test name
Test status
Simulation time 440988073 ps
CPU time 14.54 seconds
Started Aug 15 05:01:28 PM PDT 24
Finished Aug 15 05:01:42 PM PDT 24
Peak memory 253508 kb
Host smart-8eaf7585-d2a5-4f45-bf2f-d68362f3800a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16145
8945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_handler_smoke.161458945
Directory /workspace/22.alert_handler_smoke/latest

Test location /workspace/coverage/default/22.alert_handler_stress_all.3880871263
Short name T274
Test name
Test status
Simulation time 2177694216 ps
CPU time 193.78 seconds
Started Aug 15 05:01:33 PM PDT 24
Finished Aug 15 05:04:47 PM PDT 24
Peak memory 256968 kb
Host smart-fdc73719-42e8-4286-a99f-c8ddd8dbedc9
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3880871263 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 22.alert_ha
ndler_stress_all.3880871263
Directory /workspace/22.alert_handler_stress_all/latest

Test location /workspace/coverage/default/23.alert_handler_entropy.2318531219
Short name T613
Test name
Test status
Simulation time 167852585730 ps
CPU time 2556.07 seconds
Started Aug 15 05:01:34 PM PDT 24
Finished Aug 15 05:44:10 PM PDT 24
Peak memory 289060 kb
Host smart-0404c5a6-46d9-4248-aada-dd15476459c2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2318531219 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_entropy.2318531219
Directory /workspace/23.alert_handler_entropy/latest

Test location /workspace/coverage/default/23.alert_handler_esc_alert_accum.565899262
Short name T291
Test name
Test status
Simulation time 9309839316 ps
CPU time 247.2 seconds
Started Aug 15 05:01:31 PM PDT 24
Finished Aug 15 05:05:39 PM PDT 24
Peak memory 256928 kb
Host smart-c8938aeb-6ed3-4cb8-a4ef-34c4872e8c9d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56589
9262 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_alert_accum.565899262
Directory /workspace/23.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/23.alert_handler_esc_intr_timeout.10193309
Short name T470
Test name
Test status
Simulation time 82032155 ps
CPU time 8.36 seconds
Started Aug 15 05:01:34 PM PDT 24
Finished Aug 15 05:01:42 PM PDT 24
Peak memory 248004 kb
Host smart-9311eb6f-bf50-47b0-9b4b-6c4dfdba078d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10193
309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_esc_intr_timeout.10193309
Directory /workspace/23.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_lpg.3250007136
Short name T69
Test name
Test status
Simulation time 12929367230 ps
CPU time 1089.24 seconds
Started Aug 15 05:01:33 PM PDT 24
Finished Aug 15 05:19:43 PM PDT 24
Peak memory 272992 kb
Host smart-a466108a-f2d1-47c4-9285-9ee4e188b3c3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3250007136 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg.3250007136
Directory /workspace/23.alert_handler_lpg/latest

Test location /workspace/coverage/default/23.alert_handler_lpg_stub_clk.2211598666
Short name T230
Test name
Test status
Simulation time 32421870472 ps
CPU time 1340.07 seconds
Started Aug 15 05:01:32 PM PDT 24
Finished Aug 15 05:23:53 PM PDT 24
Peak memory 289024 kb
Host smart-971214c1-d802-4c82-8d01-bf68546abddd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2211598666 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_lpg_stub_clk.2211598666
Directory /workspace/23.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/23.alert_handler_ping_timeout.1592282535
Short name T330
Test name
Test status
Simulation time 30672596419 ps
CPU time 591.29 seconds
Started Aug 15 05:01:31 PM PDT 24
Finished Aug 15 05:11:23 PM PDT 24
Peak memory 248776 kb
Host smart-9425075f-4d36-4a61-90e8-e9e7b6d3fa78
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1592282535 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_ping_timeout.1592282535
Directory /workspace/23.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/23.alert_handler_random_alerts.584433215
Short name T466
Test name
Test status
Simulation time 1678299915 ps
CPU time 33.76 seconds
Started Aug 15 05:01:33 PM PDT 24
Finished Aug 15 05:02:07 PM PDT 24
Peak memory 256916 kb
Host smart-7a48d621-4f3c-45b7-b7b1-a445650948ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58443
3215 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_alerts.584433215
Directory /workspace/23.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/23.alert_handler_random_classes.2200816467
Short name T288
Test name
Test status
Simulation time 1599619585 ps
CPU time 29.61 seconds
Started Aug 15 05:01:34 PM PDT 24
Finished Aug 15 05:02:04 PM PDT 24
Peak memory 256524 kb
Host smart-bcad3417-a30b-4b12-be4d-aec7c45d6d21
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22008
16467 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_random_classes.2200816467
Directory /workspace/23.alert_handler_random_classes/latest

Test location /workspace/coverage/default/23.alert_handler_sig_int_fail.1080375633
Short name T52
Test name
Test status
Simulation time 157864914 ps
CPU time 20.5 seconds
Started Aug 15 05:01:32 PM PDT 24
Finished Aug 15 05:01:53 PM PDT 24
Peak memory 248124 kb
Host smart-49970e45-9539-4128-b24e-4931271ff436
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10803
75633 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_sig_int_fail.1080375633
Directory /workspace/23.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/23.alert_handler_smoke.874496820
Short name T653
Test name
Test status
Simulation time 112109189 ps
CPU time 4.64 seconds
Started Aug 15 05:01:33 PM PDT 24
Finished Aug 15 05:01:38 PM PDT 24
Peak memory 253728 kb
Host smart-5d37854f-d71b-4514-8409-01d7116b5d16
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87449
6820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_handler_smoke.874496820
Directory /workspace/23.alert_handler_smoke/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all.2257840702
Short name T583
Test name
Test status
Simulation time 1814826246 ps
CPU time 43.14 seconds
Started Aug 15 05:01:47 PM PDT 24
Finished Aug 15 05:02:30 PM PDT 24
Peak memory 255892 kb
Host smart-97377eb8-4a02-4094-b2e3-878f899be2a2
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2257840702 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 23.alert_ha
ndler_stress_all.2257840702
Directory /workspace/23.alert_handler_stress_all/latest

Test location /workspace/coverage/default/23.alert_handler_stress_all_with_rand_reset.2523258765
Short name T99
Test name
Test status
Simulation time 3779230810 ps
CPU time 132.66 seconds
Started Aug 15 05:01:41 PM PDT 24
Finished Aug 15 05:03:54 PM PDT 24
Peak memory 272736 kb
Host smart-846b8f5c-4394-493e-838f-dcbac84bb5ae
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2523258765 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 23.alert_handler_stress_all_with_rand_reset.2523258765
Directory /workspace/23.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/24.alert_handler_entropy.2022527063
Short name T574
Test name
Test status
Simulation time 62382905271 ps
CPU time 2242.23 seconds
Started Aug 15 05:01:47 PM PDT 24
Finished Aug 15 05:39:09 PM PDT 24
Peak memory 289536 kb
Host smart-f5801012-16d0-43f4-91d6-527800bfd9ca
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2022527063 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_entropy.2022527063
Directory /workspace/24.alert_handler_entropy/latest

Test location /workspace/coverage/default/24.alert_handler_esc_alert_accum.3579326405
Short name T515
Test name
Test status
Simulation time 7168742822 ps
CPU time 136.53 seconds
Started Aug 15 05:01:42 PM PDT 24
Finished Aug 15 05:03:59 PM PDT 24
Peak memory 255088 kb
Host smart-1d7df31c-a4ce-4496-add3-0eae6a2b04fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35793
26405 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_alert_accum.3579326405
Directory /workspace/24.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/24.alert_handler_esc_intr_timeout.1396567539
Short name T692
Test name
Test status
Simulation time 1731529800 ps
CPU time 25.04 seconds
Started Aug 15 05:01:41 PM PDT 24
Finished Aug 15 05:02:07 PM PDT 24
Peak memory 256960 kb
Host smart-d8693964-23b9-4d73-ad42-352fe3f4321b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13965
67539 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_esc_intr_timeout.1396567539
Directory /workspace/24.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_lpg.3483491168
Short name T690
Test name
Test status
Simulation time 41144648160 ps
CPU time 1685.14 seconds
Started Aug 15 05:01:47 PM PDT 24
Finished Aug 15 05:29:52 PM PDT 24
Peak memory 289328 kb
Host smart-b1a1e8b1-7530-40b2-a19e-e757137015c4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3483491168 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg.3483491168
Directory /workspace/24.alert_handler_lpg/latest

Test location /workspace/coverage/default/24.alert_handler_lpg_stub_clk.185235870
Short name T380
Test name
Test status
Simulation time 7868071219 ps
CPU time 592.63 seconds
Started Aug 15 05:01:45 PM PDT 24
Finished Aug 15 05:11:38 PM PDT 24
Peak memory 265044 kb
Host smart-9863d6b2-40e3-46ed-b7bc-a87aece3ef5d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=185235870 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_lpg_stub_clk.185235870
Directory /workspace/24.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/24.alert_handler_ping_timeout.1711314304
Short name T328
Test name
Test status
Simulation time 45815760135 ps
CPU time 489.5 seconds
Started Aug 15 05:01:42 PM PDT 24
Finished Aug 15 05:09:51 PM PDT 24
Peak memory 247332 kb
Host smart-97ceca07-0bb9-46de-9085-b6d8eee48d96
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1711314304 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_ping_timeout.1711314304
Directory /workspace/24.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/24.alert_handler_random_alerts.1226917514
Short name T365
Test name
Test status
Simulation time 1878740477 ps
CPU time 27.78 seconds
Started Aug 15 05:01:41 PM PDT 24
Finished Aug 15 05:02:09 PM PDT 24
Peak memory 248692 kb
Host smart-b85c3d71-e76f-41cf-b97b-303aa5e7fde9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12269
17514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_alerts.1226917514
Directory /workspace/24.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/24.alert_handler_random_classes.1855478147
Short name T609
Test name
Test status
Simulation time 2035172843 ps
CPU time 30.35 seconds
Started Aug 15 05:01:41 PM PDT 24
Finished Aug 15 05:02:11 PM PDT 24
Peak memory 256040 kb
Host smart-a41ffd21-167c-4bae-a5c6-ead454e1f6c9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18554
78147 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_random_classes.1855478147
Directory /workspace/24.alert_handler_random_classes/latest

Test location /workspace/coverage/default/24.alert_handler_smoke.3571798273
Short name T249
Test name
Test status
Simulation time 359358772 ps
CPU time 24.94 seconds
Started Aug 15 05:01:47 PM PDT 24
Finished Aug 15 05:02:12 PM PDT 24
Peak memory 256088 kb
Host smart-62c2949e-f296-4024-8124-875a5b09dd52
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35717
98273 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_handler_smoke.3571798273
Directory /workspace/24.alert_handler_smoke/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all.3525353952
Short name T481
Test name
Test status
Simulation time 138842304 ps
CPU time 8.41 seconds
Started Aug 15 05:01:44 PM PDT 24
Finished Aug 15 05:01:53 PM PDT 24
Peak memory 248616 kb
Host smart-907c64c7-8d93-4441-bba7-b3eb388a4727
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3525353952 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 24.alert_ha
ndler_stress_all.3525353952
Directory /workspace/24.alert_handler_stress_all/latest

Test location /workspace/coverage/default/24.alert_handler_stress_all_with_rand_reset.824286979
Short name T550
Test name
Test status
Simulation time 13375694504 ps
CPU time 224.55 seconds
Started Aug 15 05:01:50 PM PDT 24
Finished Aug 15 05:05:35 PM PDT 24
Peak memory 266456 kb
Host smart-abf6a321-a575-4e3c-8b98-65163dfbc350
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=824286979 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 24.alert_handler_stress_all_with_rand_reset.824286979
Directory /workspace/24.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/25.alert_handler_entropy.1548706747
Short name T538
Test name
Test status
Simulation time 36134543913 ps
CPU time 888.65 seconds
Started Aug 15 05:01:50 PM PDT 24
Finished Aug 15 05:16:39 PM PDT 24
Peak memory 273248 kb
Host smart-4bbbca5d-72df-4f6f-9e59-5ceed417e44f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1548706747 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_entropy.1548706747
Directory /workspace/25.alert_handler_entropy/latest

Test location /workspace/coverage/default/25.alert_handler_esc_alert_accum.577305022
Short name T498
Test name
Test status
Simulation time 1904558728 ps
CPU time 42.8 seconds
Started Aug 15 05:01:50 PM PDT 24
Finished Aug 15 05:02:33 PM PDT 24
Peak memory 256308 kb
Host smart-f059e627-f5f2-4be5-87ea-71406c1fc788
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57730
5022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_alert_accum.577305022
Directory /workspace/25.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/25.alert_handler_esc_intr_timeout.3835203789
Short name T666
Test name
Test status
Simulation time 295232470 ps
CPU time 26.76 seconds
Started Aug 15 05:01:49 PM PDT 24
Finished Aug 15 05:02:16 PM PDT 24
Peak memory 256672 kb
Host smart-7a71fc5c-6e66-4435-9b37-09e1aec1be8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38352
03789 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_esc_intr_timeout.3835203789
Directory /workspace/25.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_lpg.261616538
Short name T344
Test name
Test status
Simulation time 76770538469 ps
CPU time 2060.33 seconds
Started Aug 15 05:01:51 PM PDT 24
Finished Aug 15 05:36:12 PM PDT 24
Peak memory 272700 kb
Host smart-304bd4bd-a9da-4d89-a561-be372f358068
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=261616538 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg.261616538
Directory /workspace/25.alert_handler_lpg/latest

Test location /workspace/coverage/default/25.alert_handler_lpg_stub_clk.1356597730
Short name T414
Test name
Test status
Simulation time 76089847914 ps
CPU time 1082.77 seconds
Started Aug 15 05:01:49 PM PDT 24
Finished Aug 15 05:19:52 PM PDT 24
Peak memory 272452 kb
Host smart-60c3110e-4db0-416c-a555-1412fdf127aa
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1356597730 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_lpg_stub_clk.1356597730
Directory /workspace/25.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/25.alert_handler_ping_timeout.1464106835
Short name T319
Test name
Test status
Simulation time 12604464756 ps
CPU time 134.34 seconds
Started Aug 15 05:01:49 PM PDT 24
Finished Aug 15 05:04:04 PM PDT 24
Peak memory 248852 kb
Host smart-039679ff-1918-48f2-995e-7b43603fdab5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1464106835 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_ping_timeout.1464106835
Directory /workspace/25.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/25.alert_handler_random_alerts.866198586
Short name T453
Test name
Test status
Simulation time 248500419 ps
CPU time 6.93 seconds
Started Aug 15 05:01:52 PM PDT 24
Finished Aug 15 05:01:59 PM PDT 24
Peak memory 248772 kb
Host smart-04bcd620-1679-4184-a10b-d6efa3013b5f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=86619
8586 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_alerts.866198586
Directory /workspace/25.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/25.alert_handler_random_classes.4226596111
Short name T457
Test name
Test status
Simulation time 1257011866 ps
CPU time 33.46 seconds
Started Aug 15 05:01:50 PM PDT 24
Finished Aug 15 05:02:23 PM PDT 24
Peak memory 247828 kb
Host smart-55a7b5d4-ef1b-44ad-9044-a2a20688afa0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42265
96111 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_random_classes.4226596111
Directory /workspace/25.alert_handler_random_classes/latest

Test location /workspace/coverage/default/25.alert_handler_sig_int_fail.4091700039
Short name T528
Test name
Test status
Simulation time 210416588 ps
CPU time 29.94 seconds
Started Aug 15 05:01:48 PM PDT 24
Finished Aug 15 05:02:19 PM PDT 24
Peak memory 248816 kb
Host smart-68288157-8c30-42e9-ad80-9d360ce1f2fe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40917
00039 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_sig_int_fail.4091700039
Directory /workspace/25.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/25.alert_handler_smoke.1596603304
Short name T610
Test name
Test status
Simulation time 5162176073 ps
CPU time 52.38 seconds
Started Aug 15 05:01:50 PM PDT 24
Finished Aug 15 05:02:43 PM PDT 24
Peak memory 248700 kb
Host smart-541a9c16-20f1-4069-8d94-5298ccff55a3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15966
03304 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_handler_smoke.1596603304
Directory /workspace/25.alert_handler_smoke/latest

Test location /workspace/coverage/default/25.alert_handler_stress_all.3494461912
Short name T542
Test name
Test status
Simulation time 2685432529 ps
CPU time 29.32 seconds
Started Aug 15 05:01:50 PM PDT 24
Finished Aug 15 05:02:20 PM PDT 24
Peak memory 256872 kb
Host smart-e3d96d81-10e6-434c-9f1a-927e98af6690
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3494461912 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 25.alert_ha
ndler_stress_all.3494461912
Directory /workspace/25.alert_handler_stress_all/latest

Test location /workspace/coverage/default/26.alert_handler_entropy.4102415655
Short name T243
Test name
Test status
Simulation time 31603741473 ps
CPU time 1907.37 seconds
Started Aug 15 05:02:02 PM PDT 24
Finished Aug 15 05:33:50 PM PDT 24
Peak memory 269200 kb
Host smart-b2ddd9df-2052-4c27-b942-e95bed856ff4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102415655 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_entropy.4102415655
Directory /workspace/26.alert_handler_entropy/latest

Test location /workspace/coverage/default/26.alert_handler_esc_alert_accum.1135874768
Short name T94
Test name
Test status
Simulation time 93275621 ps
CPU time 6.2 seconds
Started Aug 15 05:02:04 PM PDT 24
Finished Aug 15 05:02:10 PM PDT 24
Peak memory 253728 kb
Host smart-c9f45f2f-d3e8-4cde-8d54-1e1d23163f12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11358
74768 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_alert_accum.1135874768
Directory /workspace/26.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/26.alert_handler_esc_intr_timeout.1660084035
Short name T452
Test name
Test status
Simulation time 775629445 ps
CPU time 44.94 seconds
Started Aug 15 05:02:02 PM PDT 24
Finished Aug 15 05:02:47 PM PDT 24
Peak memory 248692 kb
Host smart-648ea25e-7caf-4a52-8d5c-406fea01c200
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16600
84035 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_esc_intr_timeout.1660084035
Directory /workspace/26.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_lpg.1689337095
Short name T576
Test name
Test status
Simulation time 142750948522 ps
CPU time 2199.35 seconds
Started Aug 15 05:02:04 PM PDT 24
Finished Aug 15 05:38:43 PM PDT 24
Peak memory 273376 kb
Host smart-e5134179-e2a0-4303-a993-49c5ee27471c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1689337095 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg.1689337095
Directory /workspace/26.alert_handler_lpg/latest

Test location /workspace/coverage/default/26.alert_handler_lpg_stub_clk.2469358713
Short name T50
Test name
Test status
Simulation time 18604479325 ps
CPU time 1377.8 seconds
Started Aug 15 05:02:02 PM PDT 24
Finished Aug 15 05:25:00 PM PDT 24
Peak memory 289544 kb
Host smart-1ed22f10-6a44-4049-b686-7f44d3da5ef1
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2469358713 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_lpg_stub_clk.2469358713
Directory /workspace/26.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/26.alert_handler_ping_timeout.3278341629
Short name T224
Test name
Test status
Simulation time 23239776547 ps
CPU time 498.66 seconds
Started Aug 15 05:02:04 PM PDT 24
Finished Aug 15 05:10:23 PM PDT 24
Peak memory 255552 kb
Host smart-a94fddfc-5450-4133-8caa-a92cd3557722
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3278341629 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_ping_timeout.3278341629
Directory /workspace/26.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/26.alert_handler_random_alerts.1947658521
Short name T536
Test name
Test status
Simulation time 431164583 ps
CPU time 17.7 seconds
Started Aug 15 05:02:03 PM PDT 24
Finished Aug 15 05:02:21 PM PDT 24
Peak memory 248676 kb
Host smart-a44a27b4-b767-491c-8266-5d21e86628e8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19476
58521 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_alerts.1947658521
Directory /workspace/26.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/26.alert_handler_random_classes.900198979
Short name T575
Test name
Test status
Simulation time 848741980 ps
CPU time 60.22 seconds
Started Aug 15 05:02:03 PM PDT 24
Finished Aug 15 05:03:03 PM PDT 24
Peak memory 248512 kb
Host smart-cf5b510b-4708-4a3a-b841-246697401cb6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=90019
8979 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_random_classes.900198979
Directory /workspace/26.alert_handler_random_classes/latest

Test location /workspace/coverage/default/26.alert_handler_sig_int_fail.3172384629
Short name T412
Test name
Test status
Simulation time 1398056750 ps
CPU time 45.33 seconds
Started Aug 15 05:02:04 PM PDT 24
Finished Aug 15 05:02:50 PM PDT 24
Peak memory 256164 kb
Host smart-4d36e7a6-c840-4fce-960a-604ce1d5dc62
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31723
84629 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_sig_int_fail.3172384629
Directory /workspace/26.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/26.alert_handler_smoke.2613775209
Short name T577
Test name
Test status
Simulation time 1993633503 ps
CPU time 25.56 seconds
Started Aug 15 05:01:50 PM PDT 24
Finished Aug 15 05:02:15 PM PDT 24
Peak memory 256940 kb
Host smart-7be5706d-bf03-42cc-8456-23c56b78afe6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26137
75209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_handler_smoke.2613775209
Directory /workspace/26.alert_handler_smoke/latest

Test location /workspace/coverage/default/26.alert_handler_stress_all.2683265309
Short name T255
Test name
Test status
Simulation time 31710684816 ps
CPU time 1768.88 seconds
Started Aug 15 05:02:02 PM PDT 24
Finished Aug 15 05:31:31 PM PDT 24
Peak memory 283652 kb
Host smart-cc8d53a9-ec3b-495e-9b20-7414500d9e6e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2683265309 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 26.alert_ha
ndler_stress_all.2683265309
Directory /workspace/26.alert_handler_stress_all/latest

Test location /workspace/coverage/default/27.alert_handler_esc_alert_accum.1827743797
Short name T479
Test name
Test status
Simulation time 1407866698 ps
CPU time 96.8 seconds
Started Aug 15 05:02:05 PM PDT 24
Finished Aug 15 05:03:42 PM PDT 24
Peak memory 256280 kb
Host smart-1bfb3c20-d5eb-4b4a-a984-9c4a5141db7a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18277
43797 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_alert_accum.1827743797
Directory /workspace/27.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/27.alert_handler_esc_intr_timeout.1512000464
Short name T396
Test name
Test status
Simulation time 1084272792 ps
CPU time 25.23 seconds
Started Aug 15 05:02:05 PM PDT 24
Finished Aug 15 05:02:30 PM PDT 24
Peak memory 254932 kb
Host smart-0c8c53c4-12b6-460b-baad-4d4da3833475
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15120
00464 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_esc_intr_timeout.1512000464
Directory /workspace/27.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/27.alert_handler_lpg.277974007
Short name T73
Test name
Test status
Simulation time 144350611154 ps
CPU time 1970.83 seconds
Started Aug 15 05:02:04 PM PDT 24
Finished Aug 15 05:34:55 PM PDT 24
Peak memory 287408 kb
Host smart-aaa99c09-2b46-4306-abfc-d3d579f44e6b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=277974007 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg.277974007
Directory /workspace/27.alert_handler_lpg/latest

Test location /workspace/coverage/default/27.alert_handler_lpg_stub_clk.654566115
Short name T390
Test name
Test status
Simulation time 41418940583 ps
CPU time 2428.47 seconds
Started Aug 15 05:02:05 PM PDT 24
Finished Aug 15 05:42:34 PM PDT 24
Peak memory 289804 kb
Host smart-b6c34ebf-cba5-4d4f-8dd8-842745317e71
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=654566115 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_lpg_stub_clk.654566115
Directory /workspace/27.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/27.alert_handler_random_alerts.4048683758
Short name T663
Test name
Test status
Simulation time 1366862070 ps
CPU time 45.21 seconds
Started Aug 15 05:02:04 PM PDT 24
Finished Aug 15 05:02:49 PM PDT 24
Peak memory 248760 kb
Host smart-a2512d23-132e-4773-ab07-193ad6bbd291
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40486
83758 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_alerts.4048683758
Directory /workspace/27.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/27.alert_handler_random_classes.3152082028
Short name T516
Test name
Test status
Simulation time 137950740 ps
CPU time 14.13 seconds
Started Aug 15 05:02:04 PM PDT 24
Finished Aug 15 05:02:18 PM PDT 24
Peak memory 248584 kb
Host smart-15d12bb7-c011-41f0-a2c6-00750b61db02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31520
82028 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_random_classes.3152082028
Directory /workspace/27.alert_handler_random_classes/latest

Test location /workspace/coverage/default/27.alert_handler_sig_int_fail.2280245457
Short name T713
Test name
Test status
Simulation time 118706397 ps
CPU time 7.66 seconds
Started Aug 15 05:02:06 PM PDT 24
Finished Aug 15 05:02:13 PM PDT 24
Peak memory 248076 kb
Host smart-6d519d41-7c58-4ea8-b9b7-a59814ca3131
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22802
45457 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_sig_int_fail.2280245457
Directory /workspace/27.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/27.alert_handler_smoke.1200022843
Short name T366
Test name
Test status
Simulation time 122414263 ps
CPU time 8.86 seconds
Started Aug 15 05:02:04 PM PDT 24
Finished Aug 15 05:02:13 PM PDT 24
Peak memory 256888 kb
Host smart-bb5c3bd7-6e37-4c17-bb76-ce4057b99f19
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12000
22843 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 27.alert_handler_smoke.1200022843
Directory /workspace/27.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_entropy.496080731
Short name T62
Test name
Test status
Simulation time 93510402150 ps
CPU time 2733.09 seconds
Started Aug 15 05:02:10 PM PDT 24
Finished Aug 15 05:47:43 PM PDT 24
Peak memory 289512 kb
Host smart-430dc037-3ebc-4972-894b-067652375a91
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=496080731 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_entropy.496080731
Directory /workspace/28.alert_handler_entropy/latest

Test location /workspace/coverage/default/28.alert_handler_esc_alert_accum.2456403390
Short name T252
Test name
Test status
Simulation time 1691652618 ps
CPU time 76.22 seconds
Started Aug 15 05:02:09 PM PDT 24
Finished Aug 15 05:03:25 PM PDT 24
Peak memory 256428 kb
Host smart-3abf0088-375d-4bd5-b69a-3948dc8e5c69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24564
03390 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_alert_accum.2456403390
Directory /workspace/28.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/28.alert_handler_esc_intr_timeout.2085183004
Short name T360
Test name
Test status
Simulation time 8242980264 ps
CPU time 29.94 seconds
Started Aug 15 05:02:11 PM PDT 24
Finished Aug 15 05:02:41 PM PDT 24
Peak memory 248404 kb
Host smart-bab0664b-6647-4d4f-b84d-6c02ede32226
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20851
83004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_esc_intr_timeout.2085183004
Directory /workspace/28.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/28.alert_handler_lpg.1445879382
Short name T706
Test name
Test status
Simulation time 133792362019 ps
CPU time 2339.28 seconds
Started Aug 15 05:02:08 PM PDT 24
Finished Aug 15 05:41:08 PM PDT 24
Peak memory 289672 kb
Host smart-5d68c4e6-bfc9-48c6-9c89-f92378d5952d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1445879382 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg.1445879382
Directory /workspace/28.alert_handler_lpg/latest

Test location /workspace/coverage/default/28.alert_handler_lpg_stub_clk.374324846
Short name T277
Test name
Test status
Simulation time 42137439969 ps
CPU time 1059.83 seconds
Started Aug 15 05:02:08 PM PDT 24
Finished Aug 15 05:19:48 PM PDT 24
Peak memory 272956 kb
Host smart-05dc2000-9043-4c8f-97c1-04934527104c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=374324846 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_lpg_stub_clk.374324846
Directory /workspace/28.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/28.alert_handler_random_alerts.1870726079
Short name T488
Test name
Test status
Simulation time 1661616272 ps
CPU time 56.39 seconds
Started Aug 15 05:02:06 PM PDT 24
Finished Aug 15 05:03:03 PM PDT 24
Peak memory 256840 kb
Host smart-08392bdb-7aa0-4e9b-9d9b-07f9bb90c664
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18707
26079 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_alerts.1870726079
Directory /workspace/28.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/28.alert_handler_random_classes.3546543447
Short name T650
Test name
Test status
Simulation time 828267307 ps
CPU time 29.94 seconds
Started Aug 15 05:02:11 PM PDT 24
Finished Aug 15 05:02:42 PM PDT 24
Peak memory 248300 kb
Host smart-f15a233d-2554-47c6-bf18-2a87cd2d249a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35465
43447 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_random_classes.3546543447
Directory /workspace/28.alert_handler_random_classes/latest

Test location /workspace/coverage/default/28.alert_handler_sig_int_fail.855925847
Short name T112
Test name
Test status
Simulation time 4107738410 ps
CPU time 73.13 seconds
Started Aug 15 05:02:07 PM PDT 24
Finished Aug 15 05:03:20 PM PDT 24
Peak memory 256488 kb
Host smart-f346d48d-e714-4473-b036-e26f35fcdf3c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=85592
5847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_sig_int_fail.855925847
Directory /workspace/28.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/28.alert_handler_smoke.2024359532
Short name T407
Test name
Test status
Simulation time 315035198 ps
CPU time 20.97 seconds
Started Aug 15 05:02:06 PM PDT 24
Finished Aug 15 05:02:27 PM PDT 24
Peak memory 256768 kb
Host smart-68ba9a34-f6cd-4977-8130-531a8f2a7655
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20243
59532 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_handler_smoke.2024359532
Directory /workspace/28.alert_handler_smoke/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all.151131889
Short name T635
Test name
Test status
Simulation time 372317866076 ps
CPU time 2743.36 seconds
Started Aug 15 05:02:08 PM PDT 24
Finished Aug 15 05:47:52 PM PDT 24
Peak memory 287788 kb
Host smart-8a2f9963-ee83-4a3e-95d9-a2cceb168d04
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=151131889 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 28.alert_han
dler_stress_all.151131889
Directory /workspace/28.alert_handler_stress_all/latest

Test location /workspace/coverage/default/28.alert_handler_stress_all_with_rand_reset.1663052214
Short name T290
Test name
Test status
Simulation time 7847257547 ps
CPU time 221.63 seconds
Started Aug 15 05:02:10 PM PDT 24
Finished Aug 15 05:05:52 PM PDT 24
Peak memory 266880 kb
Host smart-cc457518-df4e-476b-bf0e-0b19caa3f638
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1663052214 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 28.alert_handler_stress_all_with_rand_reset.1663052214
Directory /workspace/28.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/29.alert_handler_entropy.1676960204
Short name T387
Test name
Test status
Simulation time 51773843047 ps
CPU time 3181.95 seconds
Started Aug 15 05:02:18 PM PDT 24
Finished Aug 15 05:55:20 PM PDT 24
Peak memory 281608 kb
Host smart-81a006b5-4c23-467a-9fc0-140ab489293f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1676960204 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_entropy.1676960204
Directory /workspace/29.alert_handler_entropy/latest

Test location /workspace/coverage/default/29.alert_handler_esc_alert_accum.2766663514
Short name T229
Test name
Test status
Simulation time 1612070760 ps
CPU time 120.8 seconds
Started Aug 15 05:02:18 PM PDT 24
Finished Aug 15 05:04:19 PM PDT 24
Peak memory 256920 kb
Host smart-42022d72-1485-4bb9-9e83-b6e16c06a393
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27666
63514 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_alert_accum.2766663514
Directory /workspace/29.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/29.alert_handler_esc_intr_timeout.2508820350
Short name T226
Test name
Test status
Simulation time 1808007389 ps
CPU time 53 seconds
Started Aug 15 05:02:18 PM PDT 24
Finished Aug 15 05:03:11 PM PDT 24
Peak memory 248408 kb
Host smart-4e734ab6-cb0a-4be4-9c15-47defd0f53b3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25088
20350 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_esc_intr_timeout.2508820350
Directory /workspace/29.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_lpg.2778893372
Short name T127
Test name
Test status
Simulation time 135572235754 ps
CPU time 1937.66 seconds
Started Aug 15 05:02:17 PM PDT 24
Finished Aug 15 05:34:35 PM PDT 24
Peak memory 280144 kb
Host smart-1334ba33-0116-4866-84a8-0832f9fb68e8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2778893372 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg.2778893372
Directory /workspace/29.alert_handler_lpg/latest

Test location /workspace/coverage/default/29.alert_handler_lpg_stub_clk.1149399362
Short name T475
Test name
Test status
Simulation time 27646603471 ps
CPU time 1605.14 seconds
Started Aug 15 05:02:18 PM PDT 24
Finished Aug 15 05:29:04 PM PDT 24
Peak memory 272020 kb
Host smart-098cae6a-1f47-4058-90b0-37d6d49156f4
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1149399362 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_lpg_stub_clk.1149399362
Directory /workspace/29.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/29.alert_handler_ping_timeout.899228529
Short name T602
Test name
Test status
Simulation time 13899165373 ps
CPU time 519 seconds
Started Aug 15 05:02:17 PM PDT 24
Finished Aug 15 05:10:56 PM PDT 24
Peak memory 247328 kb
Host smart-be05f22d-6f4e-43a4-826d-177c96d1a88c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=899228529 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_ping_timeout.899228529
Directory /workspace/29.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/29.alert_handler_random_alerts.2902099781
Short name T23
Test name
Test status
Simulation time 128371022 ps
CPU time 9.44 seconds
Started Aug 15 05:02:18 PM PDT 24
Finished Aug 15 05:02:27 PM PDT 24
Peak memory 248956 kb
Host smart-aa500522-f3b5-4697-a47f-0e2bed51371f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29020
99781 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_alerts.2902099781
Directory /workspace/29.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/29.alert_handler_random_classes.2556176158
Short name T563
Test name
Test status
Simulation time 876900246 ps
CPU time 20.76 seconds
Started Aug 15 05:02:17 PM PDT 24
Finished Aug 15 05:02:38 PM PDT 24
Peak memory 248564 kb
Host smart-35d3c00c-de36-4fb6-9e52-fbf0e030a041
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25561
76158 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_random_classes.2556176158
Directory /workspace/29.alert_handler_random_classes/latest

Test location /workspace/coverage/default/29.alert_handler_sig_int_fail.287369873
Short name T402
Test name
Test status
Simulation time 418383512 ps
CPU time 30.39 seconds
Started Aug 15 05:02:17 PM PDT 24
Finished Aug 15 05:02:48 PM PDT 24
Peak memory 256436 kb
Host smart-0f384ff0-2edf-4781-a719-da00ac87928f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28736
9873 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_sig_int_fail.287369873
Directory /workspace/29.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/29.alert_handler_smoke.2532934163
Short name T513
Test name
Test status
Simulation time 534390637 ps
CPU time 25.31 seconds
Started Aug 15 05:02:09 PM PDT 24
Finished Aug 15 05:02:34 PM PDT 24
Peak memory 256660 kb
Host smart-cd720728-2e1c-4914-ae7f-df65105183de
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25329
34163 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 29.alert_handler_smoke.2532934163
Directory /workspace/29.alert_handler_smoke/latest

Test location /workspace/coverage/default/29.alert_handler_stress_all_with_rand_reset.4176396843
Short name T113
Test name
Test status
Simulation time 4766814063 ps
CPU time 261.31 seconds
Started Aug 15 05:02:19 PM PDT 24
Finished Aug 15 05:06:40 PM PDT 24
Peak memory 267364 kb
Host smart-674526b3-3c95-40bc-8258-9917a87a2d7a
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4176396843 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 29.alert_handler_stress_all_with_rand_reset.4176396843
Directory /workspace/29.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/3.alert_handler_alert_accum_saturation.694138734
Short name T205
Test name
Test status
Simulation time 60862252 ps
CPU time 2.81 seconds
Started Aug 15 04:59:35 PM PDT 24
Finished Aug 15 04:59:38 PM PDT 24
Peak memory 248940 kb
Host smart-23ad3ab6-e43e-4309-9baa-5a3938874482
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=694138734 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm line
+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_alert_accum_saturation.694138734
Directory /workspace/3.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/3.alert_handler_entropy.974142211
Short name T501
Test name
Test status
Simulation time 37371646149 ps
CPU time 992.99 seconds
Started Aug 15 04:59:36 PM PDT 24
Finished Aug 15 05:16:09 PM PDT 24
Peak memory 283524 kb
Host smart-ac482afb-ea70-4b5c-b5b9-ac979115c601
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=974142211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy.974142211
Directory /workspace/3.alert_handler_entropy/latest

Test location /workspace/coverage/default/3.alert_handler_entropy_stress.4204222138
Short name T669
Test name
Test status
Simulation time 994578662 ps
CPU time 13.38 seconds
Started Aug 15 04:59:35 PM PDT 24
Finished Aug 15 04:59:48 PM PDT 24
Peak memory 248664 kb
Host smart-1adb0d61-415f-4c9e-a01f-393d8e9e4d97
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4204222138 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_entropy_stress.4204222138
Directory /workspace/3.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/3.alert_handler_esc_alert_accum.481479731
Short name T24
Test name
Test status
Simulation time 1316425365 ps
CPU time 97.71 seconds
Started Aug 15 04:59:34 PM PDT 24
Finished Aug 15 05:01:12 PM PDT 24
Peak memory 256880 kb
Host smart-98303036-b5d7-494c-b3dd-e9cbd517f933
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=48147
9731 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_alert_accum.481479731
Directory /workspace/3.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/3.alert_handler_esc_intr_timeout.4001064375
Short name T267
Test name
Test status
Simulation time 454149244 ps
CPU time 31.99 seconds
Started Aug 15 04:59:36 PM PDT 24
Finished Aug 15 05:00:08 PM PDT 24
Peak memory 256300 kb
Host smart-1aec1117-9409-46f4-88a5-d945caf300e5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40010
64375 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_esc_intr_timeout.4001064375
Directory /workspace/3.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_lpg_stub_clk.4204119188
Short name T569
Test name
Test status
Simulation time 214960973713 ps
CPU time 2740.59 seconds
Started Aug 15 04:59:36 PM PDT 24
Finished Aug 15 05:45:17 PM PDT 24
Peak memory 289776 kb
Host smart-809f7738-67bc-4c30-9b7b-b7da4ee3c1b5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4204119188 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_lpg_stub_clk.4204119188
Directory /workspace/3.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/3.alert_handler_ping_timeout.3982804614
Short name T304
Test name
Test status
Simulation time 5406726338 ps
CPU time 113.87 seconds
Started Aug 15 04:59:34 PM PDT 24
Finished Aug 15 05:01:28 PM PDT 24
Peak memory 248544 kb
Host smart-9eaf0f4f-f221-48e6-b980-5b698ae1e4f7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3982804614 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_ping_timeout.3982804614
Directory /workspace/3.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/3.alert_handler_random_alerts.2496702013
Short name T57
Test name
Test status
Simulation time 245270955 ps
CPU time 23.54 seconds
Started Aug 15 04:59:34 PM PDT 24
Finished Aug 15 04:59:58 PM PDT 24
Peak memory 256036 kb
Host smart-bb9ea319-b5da-43a8-adae-7e90812d6b69
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24967
02013 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_alerts.2496702013
Directory /workspace/3.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/3.alert_handler_random_classes.1779362534
Short name T474
Test name
Test status
Simulation time 2298324338 ps
CPU time 32.02 seconds
Started Aug 15 04:59:35 PM PDT 24
Finished Aug 15 05:00:07 PM PDT 24
Peak memory 248664 kb
Host smart-8d1ddf69-c5f5-491d-90bd-dcc2ad820c08
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17793
62534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_random_classes.1779362534
Directory /workspace/3.alert_handler_random_classes/latest

Test location /workspace/coverage/default/3.alert_handler_sec_cm.132483318
Short name T11
Test name
Test status
Simulation time 474286099 ps
CPU time 15.12 seconds
Started Aug 15 04:59:52 PM PDT 24
Finished Aug 15 05:00:07 PM PDT 24
Peak memory 269844 kb
Host smart-a3202378-959c-4d1b-af09-14a4e4a845d2
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=132483318 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sec_cm.132483318
Directory /workspace/3.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/3.alert_handler_sig_int_fail.1627759883
Short name T264
Test name
Test status
Simulation time 150534975 ps
CPU time 10.86 seconds
Started Aug 15 04:59:36 PM PDT 24
Finished Aug 15 04:59:47 PM PDT 24
Peak memory 248256 kb
Host smart-d5238774-403a-471c-8ba9-7e184ddbc229
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16277
59883 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_sig_int_fail.1627759883
Directory /workspace/3.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/3.alert_handler_smoke.1634231729
Short name T703
Test name
Test status
Simulation time 392827452 ps
CPU time 35.3 seconds
Started Aug 15 04:59:36 PM PDT 24
Finished Aug 15 05:00:11 PM PDT 24
Peak memory 256968 kb
Host smart-da713c5c-6852-4c69-b85e-fbdc1f1ac1ab
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16342
31729 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_handler_smoke.1634231729
Directory /workspace/3.alert_handler_smoke/latest

Test location /workspace/coverage/default/3.alert_handler_stress_all.2972369222
Short name T408
Test name
Test status
Simulation time 3412863686 ps
CPU time 56.32 seconds
Started Aug 15 04:59:34 PM PDT 24
Finished Aug 15 05:00:31 PM PDT 24
Peak memory 256972 kb
Host smart-b155fb3c-5e73-4076-8546-3aa027778636
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2972369222 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 3.alert_han
dler_stress_all.2972369222
Directory /workspace/3.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_entropy.93903513
Short name T523
Test name
Test status
Simulation time 58805108883 ps
CPU time 3001.59 seconds
Started Aug 15 05:02:18 PM PDT 24
Finished Aug 15 05:52:20 PM PDT 24
Peak memory 287528 kb
Host smart-79929e71-f9c2-42b5-90f8-caba791c7703
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=93903513 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_entropy.93903513
Directory /workspace/30.alert_handler_entropy/latest

Test location /workspace/coverage/default/30.alert_handler_esc_alert_accum.2548492232
Short name T364
Test name
Test status
Simulation time 11119758787 ps
CPU time 138.64 seconds
Started Aug 15 05:02:16 PM PDT 24
Finished Aug 15 05:04:35 PM PDT 24
Peak memory 256980 kb
Host smart-f5a7daa4-bfa4-4215-8044-af2c00832f00
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25484
92232 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_alert_accum.2548492232
Directory /workspace/30.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/30.alert_handler_esc_intr_timeout.3314895229
Short name T641
Test name
Test status
Simulation time 437807485 ps
CPU time 27.35 seconds
Started Aug 15 05:02:16 PM PDT 24
Finished Aug 15 05:02:44 PM PDT 24
Peak memory 248196 kb
Host smart-2366b61d-6bd1-4ab1-9dc2-2427ca7c698f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33148
95229 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_esc_intr_timeout.3314895229
Directory /workspace/30.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_lpg.3663650430
Short name T126
Test name
Test status
Simulation time 69102831098 ps
CPU time 1965.94 seconds
Started Aug 15 05:02:18 PM PDT 24
Finished Aug 15 05:35:04 PM PDT 24
Peak memory 273352 kb
Host smart-67a86c23-cb0f-45b2-9d94-23257c4c7b42
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3663650430 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg.3663650430
Directory /workspace/30.alert_handler_lpg/latest

Test location /workspace/coverage/default/30.alert_handler_lpg_stub_clk.3730885708
Short name T294
Test name
Test status
Simulation time 105007187728 ps
CPU time 2206.41 seconds
Started Aug 15 05:02:19 PM PDT 24
Finished Aug 15 05:39:06 PM PDT 24
Peak memory 288728 kb
Host smart-c9faa91f-4416-4785-8791-38fdba182042
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3730885708 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_lpg_stub_clk.3730885708
Directory /workspace/30.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/30.alert_handler_ping_timeout.2135834073
Short name T305
Test name
Test status
Simulation time 36088649461 ps
CPU time 386.55 seconds
Started Aug 15 05:02:19 PM PDT 24
Finished Aug 15 05:08:46 PM PDT 24
Peak memory 247588 kb
Host smart-bf6297cd-c960-4a81-bf86-deb0c37eaf7e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2135834073 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_ping_timeout.2135834073
Directory /workspace/30.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/30.alert_handler_random_alerts.1608803019
Short name T409
Test name
Test status
Simulation time 989721534 ps
CPU time 22.07 seconds
Started Aug 15 05:02:19 PM PDT 24
Finished Aug 15 05:02:41 PM PDT 24
Peak memory 248688 kb
Host smart-01757191-500d-4496-831a-f6fc5015f4ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16088
03019 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_alerts.1608803019
Directory /workspace/30.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/30.alert_handler_random_classes.2281185124
Short name T584
Test name
Test status
Simulation time 154904755 ps
CPU time 3.61 seconds
Started Aug 15 05:02:17 PM PDT 24
Finished Aug 15 05:02:21 PM PDT 24
Peak memory 240120 kb
Host smart-2cadfca6-3345-4754-811a-7e8729adb5cc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22811
85124 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_random_classes.2281185124
Directory /workspace/30.alert_handler_random_classes/latest

Test location /workspace/coverage/default/30.alert_handler_sig_int_fail.1846355819
Short name T363
Test name
Test status
Simulation time 335065683 ps
CPU time 24.75 seconds
Started Aug 15 05:02:20 PM PDT 24
Finished Aug 15 05:02:45 PM PDT 24
Peak memory 248184 kb
Host smart-e196a897-c2e1-4074-92a7-3f75f70212d7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18463
55819 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_sig_int_fail.1846355819
Directory /workspace/30.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/30.alert_handler_smoke.87677195
Short name T38
Test name
Test status
Simulation time 400602750 ps
CPU time 40.55 seconds
Started Aug 15 05:02:17 PM PDT 24
Finished Aug 15 05:02:58 PM PDT 24
Peak memory 256868 kb
Host smart-e38f40c4-d98a-41b2-b51b-07b2f5f389f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87677
195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_handler_smoke.87677195
Directory /workspace/30.alert_handler_smoke/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all.1175984724
Short name T3
Test name
Test status
Simulation time 5648806820 ps
CPU time 96.93 seconds
Started Aug 15 05:02:27 PM PDT 24
Finished Aug 15 05:04:04 PM PDT 24
Peak memory 256872 kb
Host smart-0326e523-2948-4048-89a0-1f6a685c3d8a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1175984724 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 30.alert_ha
ndler_stress_all.1175984724
Directory /workspace/30.alert_handler_stress_all/latest

Test location /workspace/coverage/default/30.alert_handler_stress_all_with_rand_reset.119944379
Short name T56
Test name
Test status
Simulation time 10046257037 ps
CPU time 274.47 seconds
Started Aug 15 05:02:32 PM PDT 24
Finished Aug 15 05:07:07 PM PDT 24
Peak memory 267384 kb
Host smart-977575c2-491a-484b-b04f-6ed3e123cba7
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=119944379 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 30.alert_handler_stress_all_with_rand_reset.119944379
Directory /workspace/30.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/31.alert_handler_entropy.350385968
Short name T654
Test name
Test status
Simulation time 13478273902 ps
CPU time 1128.31 seconds
Started Aug 15 05:02:28 PM PDT 24
Finished Aug 15 05:21:17 PM PDT 24
Peak memory 283692 kb
Host smart-5f6162bf-7e73-47d2-a9de-287e4b932ff6
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=350385968 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_entropy.350385968
Directory /workspace/31.alert_handler_entropy/latest

Test location /workspace/coverage/default/31.alert_handler_esc_alert_accum.3364747791
Short name T367
Test name
Test status
Simulation time 1743912832 ps
CPU time 41.55 seconds
Started Aug 15 05:02:31 PM PDT 24
Finished Aug 15 05:03:13 PM PDT 24
Peak memory 256204 kb
Host smart-6002a6e7-b354-4a7a-a693-6a3f17d01447
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33647
47791 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_alert_accum.3364747791
Directory /workspace/31.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/31.alert_handler_esc_intr_timeout.977476830
Short name T462
Test name
Test status
Simulation time 457898132 ps
CPU time 22.75 seconds
Started Aug 15 05:02:27 PM PDT 24
Finished Aug 15 05:02:50 PM PDT 24
Peak memory 248728 kb
Host smart-97e05230-3028-4835-b7d2-29cbad625282
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97747
6830 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_esc_intr_timeout.977476830
Directory /workspace/31.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_lpg.1118811048
Short name T341
Test name
Test status
Simulation time 64731987112 ps
CPU time 941.94 seconds
Started Aug 15 05:02:27 PM PDT 24
Finished Aug 15 05:18:09 PM PDT 24
Peak memory 273136 kb
Host smart-684c8bdb-3c4c-4c5d-a617-9d691873acd0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1118811048 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg.1118811048
Directory /workspace/31.alert_handler_lpg/latest

Test location /workspace/coverage/default/31.alert_handler_lpg_stub_clk.4287882040
Short name T559
Test name
Test status
Simulation time 37027106323 ps
CPU time 1349.21 seconds
Started Aug 15 05:02:26 PM PDT 24
Finished Aug 15 05:24:56 PM PDT 24
Peak memory 289424 kb
Host smart-a40a4b9a-8a61-4eac-b7c9-87c5b642a65f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4287882040 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_lpg_stub_clk.4287882040
Directory /workspace/31.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/31.alert_handler_ping_timeout.3009616371
Short name T588
Test name
Test status
Simulation time 8604349168 ps
CPU time 195.68 seconds
Started Aug 15 05:02:30 PM PDT 24
Finished Aug 15 05:05:45 PM PDT 24
Peak memory 248780 kb
Host smart-140ab2ce-4ab9-4563-9cef-83a9ebcc8412
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3009616371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_ping_timeout.3009616371
Directory /workspace/31.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/31.alert_handler_random_alerts.540107957
Short name T410
Test name
Test status
Simulation time 1024278598 ps
CPU time 54.11 seconds
Started Aug 15 05:02:27 PM PDT 24
Finished Aug 15 05:03:21 PM PDT 24
Peak memory 256416 kb
Host smart-2e76372e-224f-4cde-b181-35acb6f5ae7d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=54010
7957 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_alerts.540107957
Directory /workspace/31.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/31.alert_handler_random_classes.687322619
Short name T248
Test name
Test status
Simulation time 1378761224 ps
CPU time 29.71 seconds
Started Aug 15 05:02:27 PM PDT 24
Finished Aug 15 05:02:57 PM PDT 24
Peak memory 256892 kb
Host smart-8edf741f-f6f9-43af-94e8-baa0a841cf83
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=68732
2619 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_random_classes.687322619
Directory /workspace/31.alert_handler_random_classes/latest

Test location /workspace/coverage/default/31.alert_handler_sig_int_fail.3629995573
Short name T494
Test name
Test status
Simulation time 201634032 ps
CPU time 13.83 seconds
Started Aug 15 05:02:38 PM PDT 24
Finished Aug 15 05:02:52 PM PDT 24
Peak memory 248164 kb
Host smart-9764b318-320a-47da-bea3-43d4d5d026b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36299
95573 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_sig_int_fail.3629995573
Directory /workspace/31.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/31.alert_handler_smoke.348540583
Short name T368
Test name
Test status
Simulation time 2062373107 ps
CPU time 23.03 seconds
Started Aug 15 05:02:27 PM PDT 24
Finished Aug 15 05:02:51 PM PDT 24
Peak memory 256780 kb
Host smart-eb2bd5e6-2158-4c5c-af43-2b785c0874b0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34854
0583 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 31.alert_handler_smoke.348540583
Directory /workspace/31.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_entropy.3880305442
Short name T464
Test name
Test status
Simulation time 148753594786 ps
CPU time 2790.24 seconds
Started Aug 15 05:02:37 PM PDT 24
Finished Aug 15 05:49:08 PM PDT 24
Peak memory 289380 kb
Host smart-a2905ee1-5e85-4bba-b0e9-2dd6eb2a45bd
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3880305442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_entropy.3880305442
Directory /workspace/32.alert_handler_entropy/latest

Test location /workspace/coverage/default/32.alert_handler_esc_alert_accum.1954613364
Short name T587
Test name
Test status
Simulation time 6281629176 ps
CPU time 170.21 seconds
Started Aug 15 05:02:37 PM PDT 24
Finished Aug 15 05:05:27 PM PDT 24
Peak memory 256612 kb
Host smart-35419b53-734c-4b53-90a1-ea56558de222
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19546
13364 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_alert_accum.1954613364
Directory /workspace/32.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/32.alert_handler_esc_intr_timeout.1117660667
Short name T391
Test name
Test status
Simulation time 428588369 ps
CPU time 13.12 seconds
Started Aug 15 05:02:28 PM PDT 24
Finished Aug 15 05:02:41 PM PDT 24
Peak memory 256880 kb
Host smart-a0dfc2b7-3f50-4a62-9326-359851361f5e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11176
60667 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_esc_intr_timeout.1117660667
Directory /workspace/32.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_lpg.4019790442
Short name T316
Test name
Test status
Simulation time 557163475780 ps
CPU time 3137.26 seconds
Started Aug 15 05:02:36 PM PDT 24
Finished Aug 15 05:54:54 PM PDT 24
Peak memory 285736 kb
Host smart-6b03d0b1-c032-40b6-ae7c-7305b684c427
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4019790442 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg.4019790442
Directory /workspace/32.alert_handler_lpg/latest

Test location /workspace/coverage/default/32.alert_handler_lpg_stub_clk.3473798108
Short name T691
Test name
Test status
Simulation time 8659407393 ps
CPU time 774.21 seconds
Started Aug 15 05:02:38 PM PDT 24
Finished Aug 15 05:15:32 PM PDT 24
Peak memory 265132 kb
Host smart-3e760a15-6ac5-4ee2-b82d-fcb7ab367f09
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3473798108 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_lpg_stub_clk.3473798108
Directory /workspace/32.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/32.alert_handler_ping_timeout.1371388311
Short name T532
Test name
Test status
Simulation time 10480040596 ps
CPU time 208.37 seconds
Started Aug 15 05:02:36 PM PDT 24
Finished Aug 15 05:06:05 PM PDT 24
Peak memory 248808 kb
Host smart-e44d26d6-895a-4e65-9436-88f06cf65ae8
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1371388311 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_ping_timeout.1371388311
Directory /workspace/32.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/32.alert_handler_random_alerts.521285206
Short name T427
Test name
Test status
Simulation time 3154674974 ps
CPU time 61.12 seconds
Started Aug 15 05:02:27 PM PDT 24
Finished Aug 15 05:03:28 PM PDT 24
Peak memory 256656 kb
Host smart-159ba560-247a-4147-97f9-77c6bc23cd9c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=52128
5206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_alerts.521285206
Directory /workspace/32.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/32.alert_handler_random_classes.4108061800
Short name T612
Test name
Test status
Simulation time 1315708515 ps
CPU time 25.84 seconds
Started Aug 15 05:02:30 PM PDT 24
Finished Aug 15 05:02:56 PM PDT 24
Peak memory 256700 kb
Host smart-e6cd832c-b4ec-445b-87ec-7a4e671f737a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41080
61800 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_random_classes.4108061800
Directory /workspace/32.alert_handler_random_classes/latest

Test location /workspace/coverage/default/32.alert_handler_sig_int_fail.4105424198
Short name T374
Test name
Test status
Simulation time 1019596665 ps
CPU time 64.48 seconds
Started Aug 15 05:02:35 PM PDT 24
Finished Aug 15 05:03:40 PM PDT 24
Peak memory 256984 kb
Host smart-a5681457-fb8b-483f-a04e-292e97787634
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41054
24198 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_sig_int_fail.4105424198
Directory /workspace/32.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/32.alert_handler_smoke.1202769930
Short name T375
Test name
Test status
Simulation time 792619951 ps
CPU time 25.75 seconds
Started Aug 15 05:02:27 PM PDT 24
Finished Aug 15 05:02:53 PM PDT 24
Peak memory 256556 kb
Host smart-652c451f-400c-4a9b-9350-3e9a729c4a79
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12027
69930 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 32.alert_handler_smoke.1202769930
Directory /workspace/32.alert_handler_smoke/latest

Test location /workspace/coverage/default/32.alert_handler_stress_all_with_rand_reset.1406280578
Short name T496
Test name
Test status
Simulation time 1813810547 ps
CPU time 222.26 seconds
Started Aug 15 05:02:36 PM PDT 24
Finished Aug 15 05:06:18 PM PDT 24
Peak memory 265276 kb
Host smart-32d65379-36d7-4a00-bd2f-1e82637cbe98
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1406280578 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 32.alert_handler_stress_all_with_rand_reset.1406280578
Directory /workspace/32.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/33.alert_handler_entropy.1292725555
Short name T520
Test name
Test status
Simulation time 767287101843 ps
CPU time 2987.78 seconds
Started Aug 15 05:02:45 PM PDT 24
Finished Aug 15 05:52:33 PM PDT 24
Peak memory 289996 kb
Host smart-12c390d0-00e6-494f-a6c7-9fdcfe2aefbf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1292725555 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_entropy.1292725555
Directory /workspace/33.alert_handler_entropy/latest

Test location /workspace/coverage/default/33.alert_handler_esc_alert_accum.4023360183
Short name T13
Test name
Test status
Simulation time 3496981798 ps
CPU time 35.12 seconds
Started Aug 15 05:02:46 PM PDT 24
Finished Aug 15 05:03:21 PM PDT 24
Peak memory 256592 kb
Host smart-f271dae6-2072-4a4f-80fa-7491340fe6bc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40233
60183 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_alert_accum.4023360183
Directory /workspace/33.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/33.alert_handler_esc_intr_timeout.763277866
Short name T541
Test name
Test status
Simulation time 1082145967 ps
CPU time 18.96 seconds
Started Aug 15 05:02:45 PM PDT 24
Finished Aug 15 05:03:04 PM PDT 24
Peak memory 248308 kb
Host smart-1eddd2cc-18d7-48f3-9cb4-025448037d81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76327
7866 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_esc_intr_timeout.763277866
Directory /workspace/33.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_lpg.1993481457
Short name T345
Test name
Test status
Simulation time 30982358310 ps
CPU time 1818.32 seconds
Started Aug 15 05:02:46 PM PDT 24
Finished Aug 15 05:33:04 PM PDT 24
Peak memory 285444 kb
Host smart-7a9f0f7c-4043-4847-8415-8afbc93b463c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1993481457 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg.1993481457
Directory /workspace/33.alert_handler_lpg/latest

Test location /workspace/coverage/default/33.alert_handler_lpg_stub_clk.3720835746
Short name T509
Test name
Test status
Simulation time 5324105587 ps
CPU time 617.46 seconds
Started Aug 15 05:02:46 PM PDT 24
Finished Aug 15 05:13:04 PM PDT 24
Peak memory 272864 kb
Host smart-7391f088-65b4-4487-8453-879dcf9acaa7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3720835746 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_lpg_stub_clk.3720835746
Directory /workspace/33.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/33.alert_handler_ping_timeout.1964452190
Short name T307
Test name
Test status
Simulation time 27752048835 ps
CPU time 309.91 seconds
Started Aug 15 05:02:45 PM PDT 24
Finished Aug 15 05:07:55 PM PDT 24
Peak memory 247812 kb
Host smart-891fa24b-0f30-44d5-823b-179cffe319c7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1964452190 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_ping_timeout.1964452190
Directory /workspace/33.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/33.alert_handler_random_alerts.3238280754
Short name T500
Test name
Test status
Simulation time 1121969783 ps
CPU time 55.18 seconds
Started Aug 15 05:02:46 PM PDT 24
Finished Aug 15 05:03:41 PM PDT 24
Peak memory 256020 kb
Host smart-d98056f9-3343-43ea-b44a-cbb13fdb5e60
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32382
80754 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_alerts.3238280754
Directory /workspace/33.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/33.alert_handler_random_classes.2668553123
Short name T631
Test name
Test status
Simulation time 2684437043 ps
CPU time 28.82 seconds
Started Aug 15 05:02:44 PM PDT 24
Finished Aug 15 05:03:13 PM PDT 24
Peak memory 248028 kb
Host smart-c6024936-fec9-4ac9-80dd-59aac499398d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26685
53123 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_random_classes.2668553123
Directory /workspace/33.alert_handler_random_classes/latest

Test location /workspace/coverage/default/33.alert_handler_sig_int_fail.3549480143
Short name T637
Test name
Test status
Simulation time 1386064130 ps
CPU time 31.2 seconds
Started Aug 15 05:02:44 PM PDT 24
Finished Aug 15 05:03:16 PM PDT 24
Peak memory 256552 kb
Host smart-3c9e0084-7e17-4347-bd6c-78cf8095b8cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35494
80143 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_sig_int_fail.3549480143
Directory /workspace/33.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/33.alert_handler_smoke.2724973457
Short name T644
Test name
Test status
Simulation time 448422336 ps
CPU time 23.72 seconds
Started Aug 15 05:02:37 PM PDT 24
Finished Aug 15 05:03:01 PM PDT 24
Peak memory 256864 kb
Host smart-704be524-86ba-4f35-9081-815dd9f315b7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27249
73457 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_handler_smoke.2724973457
Directory /workspace/33.alert_handler_smoke/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all.3520547698
Short name T477
Test name
Test status
Simulation time 17528126851 ps
CPU time 1311.23 seconds
Started Aug 15 05:02:45 PM PDT 24
Finished Aug 15 05:24:36 PM PDT 24
Peak memory 289560 kb
Host smart-a6ecaa2c-dd76-4fc0-b6a3-20145a5d3999
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3520547698 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 33.alert_ha
ndler_stress_all.3520547698
Directory /workspace/33.alert_handler_stress_all/latest

Test location /workspace/coverage/default/33.alert_handler_stress_all_with_rand_reset.3142874768
Short name T100
Test name
Test status
Simulation time 4003593515 ps
CPU time 516.04 seconds
Started Aug 15 05:02:47 PM PDT 24
Finished Aug 15 05:11:23 PM PDT 24
Peak memory 269980 kb
Host smart-97447803-b8cb-40bb-ae44-3cf5c475b633
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3142874768 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 33.alert_handler_stress_all_with_rand_reset.3142874768
Directory /workspace/33.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/34.alert_handler_entropy.3493296048
Short name T529
Test name
Test status
Simulation time 53307893636 ps
CPU time 3121.25 seconds
Started Aug 15 05:02:53 PM PDT 24
Finished Aug 15 05:54:55 PM PDT 24
Peak memory 289508 kb
Host smart-46682cd8-fd9d-4942-a93c-fe3e0fd8077f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3493296048 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_entropy.3493296048
Directory /workspace/34.alert_handler_entropy/latest

Test location /workspace/coverage/default/34.alert_handler_esc_alert_accum.3928637379
Short name T379
Test name
Test status
Simulation time 4995667568 ps
CPU time 125.08 seconds
Started Aug 15 05:02:55 PM PDT 24
Finished Aug 15 05:05:01 PM PDT 24
Peak memory 256540 kb
Host smart-0e3043bc-840c-4aa6-a447-20351c3bbb14
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39286
37379 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_alert_accum.3928637379
Directory /workspace/34.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/34.alert_handler_esc_intr_timeout.3963946912
Short name T47
Test name
Test status
Simulation time 721468513 ps
CPU time 46.4 seconds
Started Aug 15 05:02:45 PM PDT 24
Finished Aug 15 05:03:31 PM PDT 24
Peak memory 248564 kb
Host smart-019a124e-702c-4d2f-ab6b-72ec112efa5c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39639
46912 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_esc_intr_timeout.3963946912
Directory /workspace/34.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_lpg_stub_clk.88497524
Short name T117
Test name
Test status
Simulation time 60974532012 ps
CPU time 1848.63 seconds
Started Aug 15 05:02:54 PM PDT 24
Finished Aug 15 05:33:43 PM PDT 24
Peak memory 273108 kb
Host smart-4515146a-6bae-43e5-99e9-5142cd1ec466
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=88497524 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_lpg_stub_clk.88497524
Directory /workspace/34.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/34.alert_handler_ping_timeout.3358343473
Short name T300
Test name
Test status
Simulation time 48934932028 ps
CPU time 465.18 seconds
Started Aug 15 05:02:55 PM PDT 24
Finished Aug 15 05:10:41 PM PDT 24
Peak memory 247664 kb
Host smart-fe3c6242-dc27-4a02-beca-1e005103987d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3358343473 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_ping_timeout.3358343473
Directory /workspace/34.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/34.alert_handler_random_alerts.231381509
Short name T447
Test name
Test status
Simulation time 216037052 ps
CPU time 15.03 seconds
Started Aug 15 05:02:45 PM PDT 24
Finished Aug 15 05:03:00 PM PDT 24
Peak memory 255488 kb
Host smart-0bc4896c-b2a5-4cde-bb4b-eb9c2a60fd91
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23138
1509 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_alerts.231381509
Directory /workspace/34.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/34.alert_handler_random_classes.1584274037
Short name T531
Test name
Test status
Simulation time 1983163621 ps
CPU time 17.89 seconds
Started Aug 15 05:02:46 PM PDT 24
Finished Aug 15 05:03:04 PM PDT 24
Peak memory 248164 kb
Host smart-30c992f4-b4be-4cfe-9832-25b72cece12e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15842
74037 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_random_classes.1584274037
Directory /workspace/34.alert_handler_random_classes/latest

Test location /workspace/coverage/default/34.alert_handler_sig_int_fail.2033717029
Short name T473
Test name
Test status
Simulation time 178607692 ps
CPU time 25.33 seconds
Started Aug 15 05:02:54 PM PDT 24
Finished Aug 15 05:03:19 PM PDT 24
Peak memory 248704 kb
Host smart-27cb50c5-d274-49bb-b6e3-8a783d283f6a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=20337
17029 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_sig_int_fail.2033717029
Directory /workspace/34.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/34.alert_handler_smoke.2366894403
Short name T37
Test name
Test status
Simulation time 174399365 ps
CPU time 18.17 seconds
Started Aug 15 05:02:46 PM PDT 24
Finished Aug 15 05:03:05 PM PDT 24
Peak memory 256888 kb
Host smart-0b904511-c6d6-44b8-84a5-4097320cd60f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23668
94403 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_handler_smoke.2366894403
Directory /workspace/34.alert_handler_smoke/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all.2605135482
Short name T507
Test name
Test status
Simulation time 20894932363 ps
CPU time 1945.66 seconds
Started Aug 15 05:02:55 PM PDT 24
Finished Aug 15 05:35:21 PM PDT 24
Peak memory 302824 kb
Host smart-ec509ff2-4336-4500-a355-6cb1752eb10f
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2605135482 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 34.alert_ha
ndler_stress_all.2605135482
Directory /workspace/34.alert_handler_stress_all/latest

Test location /workspace/coverage/default/34.alert_handler_stress_all_with_rand_reset.1158880095
Short name T539
Test name
Test status
Simulation time 1618469321 ps
CPU time 107.97 seconds
Started Aug 15 05:02:54 PM PDT 24
Finished Aug 15 05:04:42 PM PDT 24
Peak memory 265300 kb
Host smart-f0086920-402d-4481-a7b6-22aab073e97e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1158880095 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 34.alert_handler_stress_all_with_rand_reset.1158880095
Directory /workspace/34.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/35.alert_handler_entropy.3359606469
Short name T603
Test name
Test status
Simulation time 5856937614 ps
CPU time 806.54 seconds
Started Aug 15 05:02:55 PM PDT 24
Finished Aug 15 05:16:22 PM PDT 24
Peak memory 272996 kb
Host smart-d798e81f-db8a-432c-967c-a3c95dd7ed15
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3359606469 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_entropy.3359606469
Directory /workspace/35.alert_handler_entropy/latest

Test location /workspace/coverage/default/35.alert_handler_esc_alert_accum.44261707
Short name T620
Test name
Test status
Simulation time 534046751 ps
CPU time 24.81 seconds
Started Aug 15 05:02:54 PM PDT 24
Finished Aug 15 05:03:19 PM PDT 24
Peak memory 256236 kb
Host smart-ed5d88dd-6381-497d-82da-4dd3bd9ac4cf
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=44261
707 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_alert_accum.44261707
Directory /workspace/35.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/35.alert_handler_esc_intr_timeout.1122025043
Short name T377
Test name
Test status
Simulation time 214547376 ps
CPU time 8.51 seconds
Started Aug 15 05:02:55 PM PDT 24
Finished Aug 15 05:03:03 PM PDT 24
Peak memory 252356 kb
Host smart-cb43ae93-8849-46ae-bc2e-b978db9a7129
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11220
25043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_esc_intr_timeout.1122025043
Directory /workspace/35.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_lpg.857012132
Short name T76
Test name
Test status
Simulation time 36129585377 ps
CPU time 2179.92 seconds
Started Aug 15 05:03:04 PM PDT 24
Finished Aug 15 05:39:25 PM PDT 24
Peak memory 281536 kb
Host smart-5b6bc88d-238d-424f-adaf-68e601fb3836
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=857012132 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg.857012132
Directory /workspace/35.alert_handler_lpg/latest

Test location /workspace/coverage/default/35.alert_handler_lpg_stub_clk.2978532397
Short name T579
Test name
Test status
Simulation time 32672857730 ps
CPU time 1375.98 seconds
Started Aug 15 05:03:03 PM PDT 24
Finished Aug 15 05:25:59 PM PDT 24
Peak memory 287668 kb
Host smart-9649c67c-c525-49ba-906c-f95e18798780
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2978532397 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_lpg_stub_clk.2978532397
Directory /workspace/35.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/35.alert_handler_ping_timeout.4151148827
Short name T681
Test name
Test status
Simulation time 11572652538 ps
CPU time 499.15 seconds
Started Aug 15 05:03:01 PM PDT 24
Finished Aug 15 05:11:20 PM PDT 24
Peak memory 255736 kb
Host smart-aa82f7a8-68db-4a69-9fb6-a4d2c1b05fa2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4151148827 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_ping_timeout.4151148827
Directory /workspace/35.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/35.alert_handler_random_alerts.727829140
Short name T482
Test name
Test status
Simulation time 63187604 ps
CPU time 5.02 seconds
Started Aug 15 05:02:54 PM PDT 24
Finished Aug 15 05:03:00 PM PDT 24
Peak memory 248624 kb
Host smart-ad8c5c7f-d1d1-4e32-ab9e-f55d6bdb420d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=72782
9140 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_alerts.727829140
Directory /workspace/35.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/35.alert_handler_random_classes.1632059950
Short name T549
Test name
Test status
Simulation time 2663023003 ps
CPU time 36.17 seconds
Started Aug 15 05:02:55 PM PDT 24
Finished Aug 15 05:03:32 PM PDT 24
Peak memory 248852 kb
Host smart-8524f79f-3439-4a2b-bd34-aeff1a2a2a5b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16320
59950 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_random_classes.1632059950
Directory /workspace/35.alert_handler_random_classes/latest

Test location /workspace/coverage/default/35.alert_handler_sig_int_fail.4053099271
Short name T570
Test name
Test status
Simulation time 490622383 ps
CPU time 31.76 seconds
Started Aug 15 05:02:54 PM PDT 24
Finished Aug 15 05:03:26 PM PDT 24
Peak memory 248716 kb
Host smart-d171b846-4d89-48c3-9d58-9f535f820185
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40530
99271 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_sig_int_fail.4053099271
Directory /workspace/35.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/35.alert_handler_smoke.1056121010
Short name T1
Test name
Test status
Simulation time 248401271 ps
CPU time 22.5 seconds
Started Aug 15 05:02:54 PM PDT 24
Finished Aug 15 05:03:17 PM PDT 24
Peak memory 256768 kb
Host smart-84e6229e-9f31-43ba-adca-bf60fd06c3d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10561
21010 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_handler_smoke.1056121010
Directory /workspace/35.alert_handler_smoke/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all.2717921908
Short name T540
Test name
Test status
Simulation time 20926597363 ps
CPU time 1100.87 seconds
Started Aug 15 05:03:03 PM PDT 24
Finished Aug 15 05:21:24 PM PDT 24
Peak memory 286908 kb
Host smart-b3b047c0-7425-4f6b-addc-f5d21c5c65e8
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2717921908 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 35.alert_ha
ndler_stress_all.2717921908
Directory /workspace/35.alert_handler_stress_all/latest

Test location /workspace/coverage/default/35.alert_handler_stress_all_with_rand_reset.2739764746
Short name T441
Test name
Test status
Simulation time 3875207492 ps
CPU time 146.81 seconds
Started Aug 15 05:03:03 PM PDT 24
Finished Aug 15 05:05:30 PM PDT 24
Peak memory 265264 kb
Host smart-132fee56-ee63-4294-a24b-2f241d3223f0
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2739764746 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 35.alert_handler_stress_all_with_rand_reset.2739764746
Directory /workspace/35.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/36.alert_handler_entropy.379385865
Short name T232
Test name
Test status
Simulation time 332568073652 ps
CPU time 1136.63 seconds
Started Aug 15 05:03:06 PM PDT 24
Finished Aug 15 05:22:02 PM PDT 24
Peak memory 272604 kb
Host smart-ac91797c-2b37-44e0-ae76-ea21b063bc28
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=379385865 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_entropy.379385865
Directory /workspace/36.alert_handler_entropy/latest

Test location /workspace/coverage/default/36.alert_handler_esc_alert_accum.1866175223
Short name T251
Test name
Test status
Simulation time 2479336676 ps
CPU time 112.28 seconds
Started Aug 15 05:03:05 PM PDT 24
Finished Aug 15 05:04:58 PM PDT 24
Peak memory 257028 kb
Host smart-52b532b5-5d7a-4345-b8d0-4017fb75762e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18661
75223 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_alert_accum.1866175223
Directory /workspace/36.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/36.alert_handler_esc_intr_timeout.3361861228
Short name T695
Test name
Test status
Simulation time 383588240 ps
CPU time 13.8 seconds
Started Aug 15 05:03:06 PM PDT 24
Finished Aug 15 05:03:20 PM PDT 24
Peak memory 253308 kb
Host smart-b27e9493-7fac-4595-9df2-8313011730bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33618
61228 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_esc_intr_timeout.3361861228
Directory /workspace/36.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_lpg.1148732445
Short name T337
Test name
Test status
Simulation time 47231758305 ps
CPU time 879.54 seconds
Started Aug 15 05:03:04 PM PDT 24
Finished Aug 15 05:17:43 PM PDT 24
Peak memory 273060 kb
Host smart-43bb20a0-5327-4961-8f73-e1b9c2662903
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1148732445 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg.1148732445
Directory /workspace/36.alert_handler_lpg/latest

Test location /workspace/coverage/default/36.alert_handler_lpg_stub_clk.3900997796
Short name T401
Test name
Test status
Simulation time 114474532998 ps
CPU time 2203.89 seconds
Started Aug 15 05:03:16 PM PDT 24
Finished Aug 15 05:40:00 PM PDT 24
Peak memory 285616 kb
Host smart-e24e0a36-c19a-4e53-b74f-b5605a8eaac2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3900997796 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_lpg_stub_clk.3900997796
Directory /workspace/36.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/36.alert_handler_ping_timeout.22112331
Short name T317
Test name
Test status
Simulation time 9600154107 ps
CPU time 245.51 seconds
Started Aug 15 05:03:03 PM PDT 24
Finished Aug 15 05:07:09 PM PDT 24
Peak memory 248816 kb
Host smart-bed33b11-b64c-46d3-ae71-7471d773f8a9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=22112331 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov=
1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_ping_timeout.22112331
Directory /workspace/36.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/36.alert_handler_random_alerts.3309351199
Short name T614
Test name
Test status
Simulation time 338810117 ps
CPU time 29.11 seconds
Started Aug 15 05:03:03 PM PDT 24
Finished Aug 15 05:03:32 PM PDT 24
Peak memory 256820 kb
Host smart-e2de6699-3f4e-45f3-8cfd-7f58ec583ffe
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33093
51199 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_alerts.3309351199
Directory /workspace/36.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/36.alert_handler_random_classes.1732854060
Short name T710
Test name
Test status
Simulation time 4308091698 ps
CPU time 26.35 seconds
Started Aug 15 05:03:01 PM PDT 24
Finished Aug 15 05:03:28 PM PDT 24
Peak memory 248328 kb
Host smart-8375a09f-351e-40a2-8911-a04b692c64d2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17328
54060 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_random_classes.1732854060
Directory /workspace/36.alert_handler_random_classes/latest

Test location /workspace/coverage/default/36.alert_handler_sig_int_fail.413744506
Short name T450
Test name
Test status
Simulation time 405968771 ps
CPU time 15.39 seconds
Started Aug 15 05:03:02 PM PDT 24
Finished Aug 15 05:03:18 PM PDT 24
Peak memory 248092 kb
Host smart-bbeeb591-a08b-4b36-9f7a-5bb45645084a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41374
4506 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_sig_int_fail.413744506
Directory /workspace/36.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/36.alert_handler_smoke.2921864206
Short name T472
Test name
Test status
Simulation time 252783179 ps
CPU time 15.96 seconds
Started Aug 15 05:03:04 PM PDT 24
Finished Aug 15 05:03:20 PM PDT 24
Peak memory 253260 kb
Host smart-29ddaae9-d7f3-44dc-b8b8-0a3f8c511a6c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29218
64206 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_handler_smoke.2921864206
Directory /workspace/36.alert_handler_smoke/latest

Test location /workspace/coverage/default/36.alert_handler_stress_all.1166297003
Short name T93
Test name
Test status
Simulation time 56122017097 ps
CPU time 3103.34 seconds
Started Aug 15 05:03:15 PM PDT 24
Finished Aug 15 05:54:59 PM PDT 24
Peak memory 289552 kb
Host smart-58dd1a82-836c-455a-a56e-f9f3495dcac0
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1166297003 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 36.alert_ha
ndler_stress_all.1166297003
Directory /workspace/36.alert_handler_stress_all/latest

Test location /workspace/coverage/default/37.alert_handler_entropy.2582796915
Short name T59
Test name
Test status
Simulation time 196449438517 ps
CPU time 1591.84 seconds
Started Aug 15 05:03:15 PM PDT 24
Finished Aug 15 05:29:48 PM PDT 24
Peak memory 273160 kb
Host smart-a598bf0d-b135-4539-9c96-a844de4860d2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2582796915 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_entropy.2582796915
Directory /workspace/37.alert_handler_entropy/latest

Test location /workspace/coverage/default/37.alert_handler_esc_alert_accum.975920967
Short name T222
Test name
Test status
Simulation time 10701099779 ps
CPU time 161.78 seconds
Started Aug 15 05:03:15 PM PDT 24
Finished Aug 15 05:05:57 PM PDT 24
Peak memory 256580 kb
Host smart-082883d7-a4b2-4569-b38f-0bac1f94a09e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=97592
0967 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_alert_accum.975920967
Directory /workspace/37.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/37.alert_handler_esc_intr_timeout.1969734388
Short name T82
Test name
Test status
Simulation time 351139204 ps
CPU time 28.87 seconds
Started Aug 15 05:03:14 PM PDT 24
Finished Aug 15 05:03:43 PM PDT 24
Peak memory 248748 kb
Host smart-bb6bcdcc-81a6-4dd3-ba8a-1c4bdb84dc82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19697
34388 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_esc_intr_timeout.1969734388
Directory /workspace/37.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_lpg.1436556154
Short name T297
Test name
Test status
Simulation time 157215071260 ps
CPU time 2219.86 seconds
Started Aug 15 05:03:15 PM PDT 24
Finished Aug 15 05:40:15 PM PDT 24
Peak memory 273240 kb
Host smart-0ed1f479-37fb-44d4-9f11-ee779f00e5a0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1436556154 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg.1436556154
Directory /workspace/37.alert_handler_lpg/latest

Test location /workspace/coverage/default/37.alert_handler_lpg_stub_clk.4245473016
Short name T20
Test name
Test status
Simulation time 17511249286 ps
CPU time 994.12 seconds
Started Aug 15 05:03:27 PM PDT 24
Finished Aug 15 05:20:01 PM PDT 24
Peak memory 288904 kb
Host smart-a627e6fc-422a-4815-bb8a-515a9453ebdf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4245473016 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_lpg_stub_clk.4245473016
Directory /workspace/37.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/37.alert_handler_ping_timeout.3591965847
Short name T43
Test name
Test status
Simulation time 97350199139 ps
CPU time 287.12 seconds
Started Aug 15 05:03:14 PM PDT 24
Finished Aug 15 05:08:02 PM PDT 24
Peak memory 256880 kb
Host smart-25ab9eb7-ca2f-4304-af7c-e87a87391318
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3591965847 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_ping_timeout.3591965847
Directory /workspace/37.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/37.alert_handler_random_alerts.348658849
Short name T358
Test name
Test status
Simulation time 1289414169 ps
CPU time 32.38 seconds
Started Aug 15 05:03:16 PM PDT 24
Finished Aug 15 05:03:48 PM PDT 24
Peak memory 256244 kb
Host smart-81c058d3-783d-44c2-b264-75a8410b35b4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34865
8849 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_alerts.348658849
Directory /workspace/37.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/37.alert_handler_random_classes.2973041425
Short name T677
Test name
Test status
Simulation time 81122898 ps
CPU time 7.77 seconds
Started Aug 15 05:03:14 PM PDT 24
Finished Aug 15 05:03:22 PM PDT 24
Peak memory 253740 kb
Host smart-0909d7dc-e896-403d-8c36-89e9bc3b811e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29730
41425 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_random_classes.2973041425
Directory /workspace/37.alert_handler_random_classes/latest

Test location /workspace/coverage/default/37.alert_handler_sig_int_fail.2922992419
Short name T607
Test name
Test status
Simulation time 190945552 ps
CPU time 4.11 seconds
Started Aug 15 05:03:14 PM PDT 24
Finished Aug 15 05:03:18 PM PDT 24
Peak memory 240124 kb
Host smart-37a23836-61a0-4dc7-a47f-d7aeff2e9067
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=29229
92419 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_sig_int_fail.2922992419
Directory /workspace/37.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/37.alert_handler_smoke.1391541790
Short name T400
Test name
Test status
Simulation time 623482354 ps
CPU time 43.67 seconds
Started Aug 15 05:03:16 PM PDT 24
Finished Aug 15 05:04:00 PM PDT 24
Peak memory 256372 kb
Host smart-258da623-393d-475a-bb3c-9a6bee3c6475
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13915
41790 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_handler_smoke.1391541790
Directory /workspace/37.alert_handler_smoke/latest

Test location /workspace/coverage/default/37.alert_handler_stress_all.3891946004
Short name T80
Test name
Test status
Simulation time 607322326 ps
CPU time 38.76 seconds
Started Aug 15 05:03:24 PM PDT 24
Finished Aug 15 05:04:03 PM PDT 24
Peak memory 248748 kb
Host smart-d9cda33a-5f0b-4007-afae-d59610fcc611
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3891946004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 37.alert_ha
ndler_stress_all.3891946004
Directory /workspace/37.alert_handler_stress_all/latest

Test location /workspace/coverage/default/38.alert_handler_esc_alert_accum.3329490752
Short name T674
Test name
Test status
Simulation time 5934201927 ps
CPU time 27.7 seconds
Started Aug 15 05:03:26 PM PDT 24
Finished Aug 15 05:03:54 PM PDT 24
Peak memory 249132 kb
Host smart-a02c7bcc-ea96-47cd-bd7e-cca67fea5e03
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33294
90752 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_alert_accum.3329490752
Directory /workspace/38.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/38.alert_handler_esc_intr_timeout.1488676544
Short name T90
Test name
Test status
Simulation time 2658505419 ps
CPU time 43.76 seconds
Started Aug 15 05:03:26 PM PDT 24
Finished Aug 15 05:04:09 PM PDT 24
Peak memory 248648 kb
Host smart-23d35ac0-6d70-47cb-9be3-061e37a1fdc0
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14886
76544 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_esc_intr_timeout.1488676544
Directory /workspace/38.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_lpg.498479172
Short name T70
Test name
Test status
Simulation time 77885106270 ps
CPU time 2166.02 seconds
Started Aug 15 05:03:27 PM PDT 24
Finished Aug 15 05:39:33 PM PDT 24
Peak memory 273452 kb
Host smart-84aecda5-f4a0-4ba9-baff-696e170b0b30
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=498479172 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg.498479172
Directory /workspace/38.alert_handler_lpg/latest

Test location /workspace/coverage/default/38.alert_handler_lpg_stub_clk.3973149015
Short name T524
Test name
Test status
Simulation time 9731279522 ps
CPU time 1027.33 seconds
Started Aug 15 05:03:26 PM PDT 24
Finished Aug 15 05:20:34 PM PDT 24
Peak memory 289428 kb
Host smart-355f349c-e6c6-4370-a11a-bea84fa63b04
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3973149015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_lpg_stub_clk.3973149015
Directory /workspace/38.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/38.alert_handler_ping_timeout.909144374
Short name T459
Test name
Test status
Simulation time 4668385712 ps
CPU time 107.04 seconds
Started Aug 15 05:03:27 PM PDT 24
Finished Aug 15 05:05:14 PM PDT 24
Peak memory 256680 kb
Host smart-a614c88c-7169-4ca9-9572-ce1f8078053d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=909144374 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_ping_timeout.909144374
Directory /workspace/38.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/38.alert_handler_random_alerts.571105675
Short name T643
Test name
Test status
Simulation time 2473856646 ps
CPU time 49.52 seconds
Started Aug 15 05:03:25 PM PDT 24
Finished Aug 15 05:04:15 PM PDT 24
Peak memory 256908 kb
Host smart-39569e9f-ad22-46af-8a77-0eb6e877ec09
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=57110
5675 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_alerts.571105675
Directory /workspace/38.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/38.alert_handler_random_classes.1856468614
Short name T624
Test name
Test status
Simulation time 350560161 ps
CPU time 32.58 seconds
Started Aug 15 05:03:26 PM PDT 24
Finished Aug 15 05:03:59 PM PDT 24
Peak memory 256280 kb
Host smart-4614796e-1d8d-41dc-9e1b-caa33f9ed40f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18564
68614 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_random_classes.1856468614
Directory /workspace/38.alert_handler_random_classes/latest

Test location /workspace/coverage/default/38.alert_handler_sig_int_fail.1578662470
Short name T273
Test name
Test status
Simulation time 341322989 ps
CPU time 26.37 seconds
Started Aug 15 05:03:25 PM PDT 24
Finished Aug 15 05:03:51 PM PDT 24
Peak memory 255128 kb
Host smart-38a6b31e-e0c6-42c7-8cd0-6415fe72072c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15786
62470 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_sig_int_fail.1578662470
Directory /workspace/38.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/38.alert_handler_smoke.765257360
Short name T699
Test name
Test status
Simulation time 172560824 ps
CPU time 6.26 seconds
Started Aug 15 05:03:25 PM PDT 24
Finished Aug 15 05:03:31 PM PDT 24
Peak memory 254668 kb
Host smart-48894fe7-e07c-47b1-9ed7-1dda3880dc10
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=76525
7360 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_handler_smoke.765257360
Directory /workspace/38.alert_handler_smoke/latest

Test location /workspace/coverage/default/38.alert_handler_stress_all.1586375074
Short name T63
Test name
Test status
Simulation time 529037685337 ps
CPU time 2558.72 seconds
Started Aug 15 05:03:25 PM PDT 24
Finished Aug 15 05:46:05 PM PDT 24
Peak memory 289328 kb
Host smart-67595c57-e855-4f9f-b0f1-3807b0e58933
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1586375074 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 38.alert_ha
ndler_stress_all.1586375074
Directory /workspace/38.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_entropy.1019650746
Short name T645
Test name
Test status
Simulation time 375204469526 ps
CPU time 2451.26 seconds
Started Aug 15 05:03:33 PM PDT 24
Finished Aug 15 05:44:25 PM PDT 24
Peak memory 288332 kb
Host smart-ced61d20-9a08-4a16-a816-a6dda2bea189
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1019650746 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_entropy.1019650746
Directory /workspace/39.alert_handler_entropy/latest

Test location /workspace/coverage/default/39.alert_handler_esc_alert_accum.1407300694
Short name T495
Test name
Test status
Simulation time 1670377354 ps
CPU time 118.57 seconds
Started Aug 15 05:03:36 PM PDT 24
Finished Aug 15 05:05:34 PM PDT 24
Peak memory 256512 kb
Host smart-288673ab-9fb3-41f0-afd6-64bbb72106e4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14073
00694 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_alert_accum.1407300694
Directory /workspace/39.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/39.alert_handler_esc_intr_timeout.2492684129
Short name T451
Test name
Test status
Simulation time 337446900 ps
CPU time 21 seconds
Started Aug 15 05:03:32 PM PDT 24
Finished Aug 15 05:03:53 PM PDT 24
Peak memory 248160 kb
Host smart-85f694be-b848-46ac-8f93-c5d4ba529497
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24926
84129 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_esc_intr_timeout.2492684129
Directory /workspace/39.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_lpg.2020714826
Short name T606
Test name
Test status
Simulation time 42166634466 ps
CPU time 2688.31 seconds
Started Aug 15 05:03:34 PM PDT 24
Finished Aug 15 05:48:23 PM PDT 24
Peak memory 288408 kb
Host smart-0a5983c2-8b5d-49ca-abe8-9bc7269724d5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2020714826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg.2020714826
Directory /workspace/39.alert_handler_lpg/latest

Test location /workspace/coverage/default/39.alert_handler_lpg_stub_clk.266553577
Short name T618
Test name
Test status
Simulation time 98112469154 ps
CPU time 1598.42 seconds
Started Aug 15 05:03:34 PM PDT 24
Finished Aug 15 05:30:13 PM PDT 24
Peak memory 272916 kb
Host smart-9979fedd-9307-472c-b18b-98041ff5f2fc
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=266553577 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_lpg_stub_clk.266553577
Directory /workspace/39.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/39.alert_handler_ping_timeout.376563371
Short name T17
Test name
Test status
Simulation time 6583457041 ps
CPU time 278.67 seconds
Started Aug 15 05:03:34 PM PDT 24
Finished Aug 15 05:08:13 PM PDT 24
Peak memory 248552 kb
Host smart-0d42979b-8eb5-42ab-88cb-0bb19a4ca5cf
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=376563371 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_ping_timeout.376563371
Directory /workspace/39.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/39.alert_handler_random_alerts.508374189
Short name T371
Test name
Test status
Simulation time 889535828 ps
CPU time 28.31 seconds
Started Aug 15 05:03:35 PM PDT 24
Finished Aug 15 05:04:04 PM PDT 24
Peak memory 256240 kb
Host smart-d2f7fe61-159a-44f5-9590-c17086bc718b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=50837
4189 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_alerts.508374189
Directory /workspace/39.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/39.alert_handler_random_classes.4120885702
Short name T12
Test name
Test status
Simulation time 218866822 ps
CPU time 24.15 seconds
Started Aug 15 05:03:35 PM PDT 24
Finished Aug 15 05:03:59 PM PDT 24
Peak memory 255976 kb
Host smart-6e4bd172-b0a4-4f94-a02a-95f7b73ddb25
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41208
85702 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_random_classes.4120885702
Directory /workspace/39.alert_handler_random_classes/latest

Test location /workspace/coverage/default/39.alert_handler_sig_int_fail.2599542043
Short name T261
Test name
Test status
Simulation time 206883860 ps
CPU time 28.27 seconds
Started Aug 15 05:03:35 PM PDT 24
Finished Aug 15 05:04:04 PM PDT 24
Peak memory 248680 kb
Host smart-5949e4eb-2fc3-4953-91bd-66c3701c27b9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=25995
42043 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_sig_int_fail.2599542043
Directory /workspace/39.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/39.alert_handler_smoke.2774118358
Short name T74
Test name
Test status
Simulation time 896341565 ps
CPU time 29.63 seconds
Started Aug 15 05:03:33 PM PDT 24
Finished Aug 15 05:04:03 PM PDT 24
Peak memory 256132 kb
Host smart-50d45871-817f-4b76-8600-6ef15f1dc8c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27741
18358 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_handler_smoke.2774118358
Directory /workspace/39.alert_handler_smoke/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all.2432442701
Short name T649
Test name
Test status
Simulation time 3928976788 ps
CPU time 60.81 seconds
Started Aug 15 05:03:35 PM PDT 24
Finished Aug 15 05:04:36 PM PDT 24
Peak memory 256916 kb
Host smart-9f670d04-aa40-40fc-8d1f-3fb41b690f88
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2432442701 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 39.alert_ha
ndler_stress_all.2432442701
Directory /workspace/39.alert_handler_stress_all/latest

Test location /workspace/coverage/default/39.alert_handler_stress_all_with_rand_reset.1176593161
Short name T581
Test name
Test status
Simulation time 40620981211 ps
CPU time 522.45 seconds
Started Aug 15 05:03:34 PM PDT 24
Finished Aug 15 05:12:17 PM PDT 24
Peak memory 281688 kb
Host smart-7305c064-ce82-4ed4-b027-ed6069a08b01
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1176593161 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 39.alert_handler_stress_all_with_rand_reset.1176593161
Directory /workspace/39.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/4.alert_handler_alert_accum_saturation.1167427116
Short name T206
Test name
Test status
Simulation time 27301669 ps
CPU time 2.55 seconds
Started Aug 15 04:59:39 PM PDT 24
Finished Aug 15 04:59:42 PM PDT 24
Peak memory 248940 kb
Host smart-85dc9345-d69f-467e-b343-6600626ddb8a
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1167427116 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_alert_accum_saturation.1167427116
Directory /workspace/4.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/4.alert_handler_entropy.1447337735
Short name T64
Test name
Test status
Simulation time 16158227417 ps
CPU time 1289.37 seconds
Started Aug 15 04:59:42 PM PDT 24
Finished Aug 15 05:21:12 PM PDT 24
Peak memory 288792 kb
Host smart-9a7d9324-5cf3-4dab-8287-41201390153b
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1447337735 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy.1447337735
Directory /workspace/4.alert_handler_entropy/latest

Test location /workspace/coverage/default/4.alert_handler_entropy_stress.4150747534
Short name T433
Test name
Test status
Simulation time 214232021 ps
CPU time 11.87 seconds
Started Aug 15 04:59:52 PM PDT 24
Finished Aug 15 05:00:04 PM PDT 24
Peak memory 248696 kb
Host smart-8600742f-71a4-4a28-96f6-c0d0464f7cbb
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4150747534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_entropy_stress.4150747534
Directory /workspace/4.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/4.alert_handler_esc_alert_accum.3976790412
Short name T430
Test name
Test status
Simulation time 666035771 ps
CPU time 13.64 seconds
Started Aug 15 04:59:42 PM PDT 24
Finished Aug 15 04:59:55 PM PDT 24
Peak memory 256372 kb
Host smart-f7e81477-148d-457d-9ab6-f4f503dae265
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39767
90412 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_alert_accum.3976790412
Directory /workspace/4.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/4.alert_handler_esc_intr_timeout.1950939787
Short name T533
Test name
Test status
Simulation time 545838193 ps
CPU time 28.62 seconds
Started Aug 15 04:59:43 PM PDT 24
Finished Aug 15 05:00:11 PM PDT 24
Peak memory 256512 kb
Host smart-c994dab2-c020-4870-bbee-68a40d8f13cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19509
39787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_esc_intr_timeout.1950939787
Directory /workspace/4.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_lpg.991807474
Short name T557
Test name
Test status
Simulation time 18023471991 ps
CPU time 1677.44 seconds
Started Aug 15 04:59:42 PM PDT 24
Finished Aug 15 05:27:39 PM PDT 24
Peak memory 289040 kb
Host smart-0d99933e-5451-4d80-9da7-16e8b50a7ee0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=991807474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg.991807474
Directory /workspace/4.alert_handler_lpg/latest

Test location /workspace/coverage/default/4.alert_handler_lpg_stub_clk.4198531458
Short name T611
Test name
Test status
Simulation time 35341219088 ps
CPU time 2100.15 seconds
Started Aug 15 04:59:40 PM PDT 24
Finished Aug 15 05:34:40 PM PDT 24
Peak memory 287432 kb
Host smart-2915928c-7b33-405e-aa49-a44c33a215c7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4198531458 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_lpg_stub_clk.4198531458
Directory /workspace/4.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/4.alert_handler_ping_timeout.2416104328
Short name T586
Test name
Test status
Simulation time 16344549180 ps
CPU time 175.82 seconds
Started Aug 15 04:59:40 PM PDT 24
Finished Aug 15 05:02:36 PM PDT 24
Peak memory 248812 kb
Host smart-01587e8a-3576-4fdc-b313-3e2a02a28b1a
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2416104328 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_ping_timeout.2416104328
Directory /workspace/4.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/4.alert_handler_random_alerts.1462559080
Short name T567
Test name
Test status
Simulation time 591422906 ps
CPU time 13.65 seconds
Started Aug 15 04:59:52 PM PDT 24
Finished Aug 15 05:00:05 PM PDT 24
Peak memory 255636 kb
Host smart-2796a7af-f510-4be3-8c0e-fc7b1f8937ed
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14625
59080 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_alerts.1462559080
Directory /workspace/4.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/4.alert_handler_random_classes.1614145497
Short name T71
Test name
Test status
Simulation time 501362615 ps
CPU time 20.72 seconds
Started Aug 15 04:59:52 PM PDT 24
Finished Aug 15 05:00:12 PM PDT 24
Peak memory 247944 kb
Host smart-7dbff6fd-9b56-4694-99f6-70e5e4658854
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16141
45497 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_random_classes.1614145497
Directory /workspace/4.alert_handler_random_classes/latest

Test location /workspace/coverage/default/4.alert_handler_sec_cm.285706418
Short name T9
Test name
Test status
Simulation time 516361748 ps
CPU time 15.15 seconds
Started Aug 15 04:59:50 PM PDT 24
Finished Aug 15 05:00:06 PM PDT 24
Peak memory 270732 kb
Host smart-037aed6e-b9e0-48d4-8435-7216746deb31
User root
Command /workspace/default/simv +run_sec_cm_fi +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.t
cl +ntb_random_seed=285706418 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+
cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sec_cm.285706418
Directory /workspace/4.alert_handler_sec_cm/latest

Test location /workspace/coverage/default/4.alert_handler_sig_int_fail.4080222788
Short name T679
Test name
Test status
Simulation time 172153096 ps
CPU time 19.9 seconds
Started Aug 15 04:59:52 PM PDT 24
Finished Aug 15 05:00:12 PM PDT 24
Peak memory 256456 kb
Host smart-3ba9cb7e-bb14-4145-a8af-bb742891a128
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40802
22788 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_sig_int_fail.4080222788
Directory /workspace/4.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/4.alert_handler_smoke.3748572304
Short name T678
Test name
Test status
Simulation time 1719795297 ps
CPU time 65.21 seconds
Started Aug 15 04:59:43 PM PDT 24
Finished Aug 15 05:00:48 PM PDT 24
Peak memory 256876 kb
Host smart-e6a535cc-2a43-4e71-960a-0f5075d624dd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=37485
72304 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_handler_smoke.3748572304
Directory /workspace/4.alert_handler_smoke/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all.207827820
Short name T278
Test name
Test status
Simulation time 69596371187 ps
CPU time 1387.21 seconds
Started Aug 15 04:59:52 PM PDT 24
Finished Aug 15 05:22:59 PM PDT 24
Peak memory 287252 kb
Host smart-7b4f10bd-8f41-4cdc-8d64-11980da32079
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=207827820 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 4.alert_hand
ler_stress_all.207827820
Directory /workspace/4.alert_handler_stress_all/latest

Test location /workspace/coverage/default/4.alert_handler_stress_all_with_rand_reset.3211029656
Short name T279
Test name
Test status
Simulation time 2258991697 ps
CPU time 238.43 seconds
Started Aug 15 04:59:51 PM PDT 24
Finished Aug 15 05:03:50 PM PDT 24
Peak memory 273452 kb
Host smart-cef30935-f741-4a3d-bbc2-cd37916f7667
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3211029656 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 4.alert_handler_stress_all_with_rand_reset.3211029656
Directory /workspace/4.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/40.alert_handler_entropy.2368759579
Short name T111
Test name
Test status
Simulation time 108269941634 ps
CPU time 1931.98 seconds
Started Aug 15 05:03:33 PM PDT 24
Finished Aug 15 05:35:45 PM PDT 24
Peak memory 284376 kb
Host smart-78a19b1c-1c35-4e96-a21c-78dfe94bdd66
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2368759579 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_entropy.2368759579
Directory /workspace/40.alert_handler_entropy/latest

Test location /workspace/coverage/default/40.alert_handler_esc_alert_accum.992396875
Short name T662
Test name
Test status
Simulation time 1480032736 ps
CPU time 106.81 seconds
Started Aug 15 05:03:34 PM PDT 24
Finished Aug 15 05:05:21 PM PDT 24
Peak memory 256868 kb
Host smart-19a3903c-e587-4267-9f0b-feaa8f56ce8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=99239
6875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_esc_alert_accum.992396875
Directory /workspace/40.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/40.alert_handler_lpg.633125714
Short name T343
Test name
Test status
Simulation time 70020434906 ps
CPU time 2037.45 seconds
Started Aug 15 05:03:44 PM PDT 24
Finished Aug 15 05:37:42 PM PDT 24
Peak memory 284764 kb
Host smart-7c79edbf-bdc3-4246-8e4f-884cde62f8e3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=633125714 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg.633125714
Directory /workspace/40.alert_handler_lpg/latest

Test location /workspace/coverage/default/40.alert_handler_lpg_stub_clk.573299279
Short name T428
Test name
Test status
Simulation time 847786461279 ps
CPU time 2394.41 seconds
Started Aug 15 05:03:44 PM PDT 24
Finished Aug 15 05:43:38 PM PDT 24
Peak memory 287668 kb
Host smart-dd925c83-5626-4f4b-9dca-1eb3ce7f0a2e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=573299279 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_lpg_stub_clk.573299279
Directory /workspace/40.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/40.alert_handler_ping_timeout.736633389
Short name T309
Test name
Test status
Simulation time 25352160494 ps
CPU time 261.24 seconds
Started Aug 15 05:03:43 PM PDT 24
Finished Aug 15 05:08:04 PM PDT 24
Peak memory 248840 kb
Host smart-bd4e3ebd-fe3d-4d15-b4f7-3580efbadd03
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=736633389 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_ping_timeout.736633389
Directory /workspace/40.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/40.alert_handler_random_alerts.3181946517
Short name T702
Test name
Test status
Simulation time 1681367061 ps
CPU time 35.66 seconds
Started Aug 15 05:03:33 PM PDT 24
Finished Aug 15 05:04:09 PM PDT 24
Peak memory 256200 kb
Host smart-0c6e5144-02a3-4b29-97e9-f1470a59cd50
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=31819
46517 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_alerts.3181946517
Directory /workspace/40.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/40.alert_handler_random_classes.3507075128
Short name T119
Test name
Test status
Simulation time 917785289 ps
CPU time 55.58 seconds
Started Aug 15 05:03:35 PM PDT 24
Finished Aug 15 05:04:31 PM PDT 24
Peak memory 256228 kb
Host smart-515a23ab-540f-4bdc-8398-e421cf736def
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35070
75128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_random_classes.3507075128
Directory /workspace/40.alert_handler_random_classes/latest

Test location /workspace/coverage/default/40.alert_handler_sig_int_fail.2358910471
Short name T489
Test name
Test status
Simulation time 1420967253 ps
CPU time 25.7 seconds
Started Aug 15 05:03:34 PM PDT 24
Finished Aug 15 05:04:00 PM PDT 24
Peak memory 256260 kb
Host smart-4bcc085c-97d4-4eb1-a774-aa29b3c60e80
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23589
10471 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_sig_int_fail.2358910471
Directory /workspace/40.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/40.alert_handler_smoke.138154551
Short name T551
Test name
Test status
Simulation time 559101450 ps
CPU time 33.94 seconds
Started Aug 15 05:03:35 PM PDT 24
Finished Aug 15 05:04:09 PM PDT 24
Peak memory 256932 kb
Host smart-646851f4-befb-4804-b170-6802dfae5cac
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13815
4551 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_handler_smoke.138154551
Directory /workspace/40.alert_handler_smoke/latest

Test location /workspace/coverage/default/40.alert_handler_stress_all.3968945098
Short name T480
Test name
Test status
Simulation time 8377822672 ps
CPU time 66.85 seconds
Started Aug 15 05:03:44 PM PDT 24
Finished Aug 15 05:04:51 PM PDT 24
Peak memory 257056 kb
Host smart-50bdc894-3485-41b7-8185-c18cf6dce0ef
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3968945098 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 40.alert_ha
ndler_stress_all.3968945098
Directory /workspace/40.alert_handler_stress_all/latest

Test location /workspace/coverage/default/41.alert_handler_entropy.3328816195
Short name T118
Test name
Test status
Simulation time 12519876880 ps
CPU time 1145.23 seconds
Started Aug 15 05:03:45 PM PDT 24
Finished Aug 15 05:22:51 PM PDT 24
Peak memory 286164 kb
Host smart-150cc8ac-6994-40c6-9e84-59f234897a55
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3328816195 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_entropy.3328816195
Directory /workspace/41.alert_handler_entropy/latest

Test location /workspace/coverage/default/41.alert_handler_esc_alert_accum.3073083075
Short name T546
Test name
Test status
Simulation time 2975414478 ps
CPU time 63.95 seconds
Started Aug 15 05:03:47 PM PDT 24
Finished Aug 15 05:04:51 PM PDT 24
Peak memory 256468 kb
Host smart-5571a65b-9910-476b-a3ac-1eaf38f9ee65
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30730
83075 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_alert_accum.3073083075
Directory /workspace/41.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/41.alert_handler_esc_intr_timeout.2341341826
Short name T492
Test name
Test status
Simulation time 336823867 ps
CPU time 5.94 seconds
Started Aug 15 05:03:45 PM PDT 24
Finished Aug 15 05:03:51 PM PDT 24
Peak memory 240424 kb
Host smart-13a9f1bc-11bb-4156-9fcb-3a3c9b568a22
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23413
41826 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_esc_intr_timeout.2341341826
Directory /workspace/41.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_lpg.448627641
Short name T709
Test name
Test status
Simulation time 37896193625 ps
CPU time 937.87 seconds
Started Aug 15 05:03:44 PM PDT 24
Finished Aug 15 05:19:22 PM PDT 24
Peak memory 272692 kb
Host smart-6168274e-68c5-4926-bda0-1a243085e115
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=448627641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg.448627641
Directory /workspace/41.alert_handler_lpg/latest

Test location /workspace/coverage/default/41.alert_handler_lpg_stub_clk.1359507959
Short name T585
Test name
Test status
Simulation time 82038889095 ps
CPU time 1318.72 seconds
Started Aug 15 05:03:45 PM PDT 24
Finished Aug 15 05:25:45 PM PDT 24
Peak memory 289344 kb
Host smart-2e7476b7-3317-4a51-bdba-f608aedc44ba
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1359507959 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_lpg_stub_clk.1359507959
Directory /workspace/41.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/41.alert_handler_ping_timeout.2051848596
Short name T324
Test name
Test status
Simulation time 16957108149 ps
CPU time 360.49 seconds
Started Aug 15 05:03:44 PM PDT 24
Finished Aug 15 05:09:45 PM PDT 24
Peak memory 248840 kb
Host smart-a8402b13-e0dd-49a3-9327-299e0ea4a20e
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2051848596 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_ping_timeout.2051848596
Directory /workspace/41.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/41.alert_handler_random_alerts.368228447
Short name T659
Test name
Test status
Simulation time 6183633175 ps
CPU time 37.16 seconds
Started Aug 15 05:03:46 PM PDT 24
Finished Aug 15 05:04:24 PM PDT 24
Peak memory 256296 kb
Host smart-98e1803f-7d5a-4e2f-ba36-254fe2084a02
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36822
8447 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_alerts.368228447
Directory /workspace/41.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/41.alert_handler_random_classes.2171999190
Short name T440
Test name
Test status
Simulation time 295326833 ps
CPU time 22.76 seconds
Started Aug 15 05:03:47 PM PDT 24
Finished Aug 15 05:04:10 PM PDT 24
Peak memory 248676 kb
Host smart-6ed078f2-b3eb-4fea-ac5e-c59344b8419f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21719
99190 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_random_classes.2171999190
Directory /workspace/41.alert_handler_random_classes/latest

Test location /workspace/coverage/default/41.alert_handler_sig_int_fail.461709633
Short name T446
Test name
Test status
Simulation time 2463511035 ps
CPU time 59.54 seconds
Started Aug 15 05:03:46 PM PDT 24
Finished Aug 15 05:04:45 PM PDT 24
Peak memory 248776 kb
Host smart-c12b5a01-1e3e-4fef-a41e-470a061aa0c3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=46170
9633 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_sig_int_fail.461709633
Directory /workspace/41.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/41.alert_handler_smoke.878530660
Short name T223
Test name
Test status
Simulation time 1204107667 ps
CPU time 65.14 seconds
Started Aug 15 05:03:45 PM PDT 24
Finished Aug 15 05:04:50 PM PDT 24
Peak memory 256780 kb
Host smart-15013a61-1726-4014-9ccc-a1d4d0810741
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=87853
0660 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 41.alert_handler_smoke.878530660
Directory /workspace/41.alert_handler_smoke/latest

Test location /workspace/coverage/default/41.alert_handler_stress_all_with_rand_reset.2993277652
Short name T253
Test name
Test status
Simulation time 11685261044 ps
CPU time 680.9 seconds
Started Aug 15 05:03:46 PM PDT 24
Finished Aug 15 05:15:07 PM PDT 24
Peak memory 281640 kb
Host smart-96cc30f6-c8f9-4370-9962-b98681af53c5
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2993277652 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 41.alert_handler_stress_all_with_rand_reset.2993277652
Directory /workspace/41.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/42.alert_handler_entropy.4172006691
Short name T634
Test name
Test status
Simulation time 41379263886 ps
CPU time 1186.66 seconds
Started Aug 15 05:03:51 PM PDT 24
Finished Aug 15 05:23:38 PM PDT 24
Peak memory 287632 kb
Host smart-31eb89a0-5c57-40dd-ba9a-4d17d4afe336
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4172006691 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_entropy.4172006691
Directory /workspace/42.alert_handler_entropy/latest

Test location /workspace/coverage/default/42.alert_handler_esc_alert_accum.2810232150
Short name T619
Test name
Test status
Simulation time 2051629470 ps
CPU time 125.77 seconds
Started Aug 15 05:03:51 PM PDT 24
Finished Aug 15 05:05:57 PM PDT 24
Peak memory 256360 kb
Host smart-a420972f-5b27-4eb1-9bd7-44f8cc1bf55d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28102
32150 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_alert_accum.2810232150
Directory /workspace/42.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/42.alert_handler_esc_intr_timeout.1808593590
Short name T91
Test name
Test status
Simulation time 2239334574 ps
CPU time 74.24 seconds
Started Aug 15 05:03:52 PM PDT 24
Finished Aug 15 05:05:06 PM PDT 24
Peak memory 248864 kb
Host smart-08a1cdd0-0c5c-48c3-872e-70d65c792144
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18085
93590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_esc_intr_timeout.1808593590
Directory /workspace/42.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_lpg.1066028004
Short name T534
Test name
Test status
Simulation time 12917956429 ps
CPU time 968.85 seconds
Started Aug 15 05:03:52 PM PDT 24
Finished Aug 15 05:20:01 PM PDT 24
Peak memory 272932 kb
Host smart-3eaf38ce-cabf-4276-99aa-371db1cdba46
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1066028004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg.1066028004
Directory /workspace/42.alert_handler_lpg/latest

Test location /workspace/coverage/default/42.alert_handler_lpg_stub_clk.4036501794
Short name T78
Test name
Test status
Simulation time 39602598920 ps
CPU time 968.16 seconds
Started Aug 15 05:03:58 PM PDT 24
Finished Aug 15 05:20:07 PM PDT 24
Peak memory 281444 kb
Host smart-5e47b38f-76c0-4bbd-88fe-b9647374d520
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4036501794 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_lpg_stub_clk.4036501794
Directory /workspace/42.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/42.alert_handler_ping_timeout.1784523600
Short name T303
Test name
Test status
Simulation time 13439539534 ps
CPU time 550.6 seconds
Started Aug 15 05:03:51 PM PDT 24
Finished Aug 15 05:13:01 PM PDT 24
Peak memory 248824 kb
Host smart-1a814772-2746-4c07-aa64-078b833a2ff7
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1784523600 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_ping_timeout.1784523600
Directory /workspace/42.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/42.alert_handler_random_alerts.1408474002
Short name T53
Test name
Test status
Simulation time 1109786664 ps
CPU time 66.79 seconds
Started Aug 15 05:03:58 PM PDT 24
Finished Aug 15 05:05:05 PM PDT 24
Peak memory 256856 kb
Host smart-a03fff98-f172-44e0-83b1-2d84bd590e89
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14084
74002 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_alerts.1408474002
Directory /workspace/42.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/42.alert_handler_random_classes.2242292326
Short name T281
Test name
Test status
Simulation time 4619862391 ps
CPU time 58.06 seconds
Started Aug 15 05:03:59 PM PDT 24
Finished Aug 15 05:04:57 PM PDT 24
Peak memory 248316 kb
Host smart-9dde6394-8296-48cb-b265-3d918cd0547a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22422
92326 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_random_classes.2242292326
Directory /workspace/42.alert_handler_random_classes/latest

Test location /workspace/coverage/default/42.alert_handler_sig_int_fail.1959904298
Short name T683
Test name
Test status
Simulation time 882303185 ps
CPU time 15.48 seconds
Started Aug 15 05:03:50 PM PDT 24
Finished Aug 15 05:04:05 PM PDT 24
Peak memory 248676 kb
Host smart-ad168c1b-623d-4e3a-ab2a-a646f7a93a81
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19599
04298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_sig_int_fail.1959904298
Directory /workspace/42.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/42.alert_handler_smoke.3067442591
Short name T668
Test name
Test status
Simulation time 302861195 ps
CPU time 10.8 seconds
Started Aug 15 05:03:53 PM PDT 24
Finished Aug 15 05:04:04 PM PDT 24
Peak memory 255092 kb
Host smart-abbeffde-c573-4a61-aee6-18000cc5df44
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30674
42591 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 42.alert_handler_smoke.3067442591
Directory /workspace/42.alert_handler_smoke/latest

Test location /workspace/coverage/default/42.alert_handler_stress_all_with_rand_reset.2490346754
Short name T55
Test name
Test status
Simulation time 3924252745 ps
CPU time 232.45 seconds
Started Aug 15 05:03:59 PM PDT 24
Finished Aug 15 05:07:52 PM PDT 24
Peak memory 273552 kb
Host smart-8bd5aeb5-599a-41a5-9407-840e3cc22068
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2490346754 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 42.alert_handler_stress_all_with_rand_reset.2490346754
Directory /workspace/42.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/43.alert_handler_entropy.4102983945
Short name T594
Test name
Test status
Simulation time 58144037539 ps
CPU time 895.76 seconds
Started Aug 15 05:04:05 PM PDT 24
Finished Aug 15 05:19:01 PM PDT 24
Peak memory 265124 kb
Host smart-7ccc3910-b97f-42c5-9f50-7c196841a4ad
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4102983945 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_entropy.4102983945
Directory /workspace/43.alert_handler_entropy/latest

Test location /workspace/coverage/default/43.alert_handler_esc_alert_accum.3565849951
Short name T369
Test name
Test status
Simulation time 716361519 ps
CPU time 70.7 seconds
Started Aug 15 05:03:59 PM PDT 24
Finished Aug 15 05:05:10 PM PDT 24
Peak memory 256688 kb
Host smart-edc433ab-0503-4012-bfff-04bf4b133ea4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35658
49951 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_alert_accum.3565849951
Directory /workspace/43.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/43.alert_handler_esc_intr_timeout.21818286
Short name T601
Test name
Test status
Simulation time 500182498 ps
CPU time 24.74 seconds
Started Aug 15 05:04:00 PM PDT 24
Finished Aug 15 05:04:25 PM PDT 24
Peak memory 256784 kb
Host smart-986d8259-4daa-4bb6-9bfe-5d89acc9ff6e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21818
286 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_esc_intr_timeout.21818286
Directory /workspace/43.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_lpg.828303287
Short name T633
Test name
Test status
Simulation time 6703339444 ps
CPU time 569.99 seconds
Started Aug 15 05:03:59 PM PDT 24
Finished Aug 15 05:13:30 PM PDT 24
Peak memory 273352 kb
Host smart-5ea33874-edc7-4227-8d56-344cc63a6820
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=828303287 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg.828303287
Directory /workspace/43.alert_handler_lpg/latest

Test location /workspace/coverage/default/43.alert_handler_lpg_stub_clk.3814690950
Short name T642
Test name
Test status
Simulation time 18488340655 ps
CPU time 1449.39 seconds
Started Aug 15 05:04:04 PM PDT 24
Finished Aug 15 05:28:14 PM PDT 24
Peak memory 289440 kb
Host smart-dd5a996f-25ad-4f7e-82aa-46f2a45a7be0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3814690950 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_lpg_stub_clk.3814690950
Directory /workspace/43.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/43.alert_handler_ping_timeout.368061001
Short name T306
Test name
Test status
Simulation time 11946845128 ps
CPU time 125.48 seconds
Started Aug 15 05:04:00 PM PDT 24
Finished Aug 15 05:06:06 PM PDT 24
Peak memory 248732 kb
Host smart-fc85d874-819f-4b47-b0ee-2b693dce0add
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=368061001 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_ping_timeout.368061001
Directory /workspace/43.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/43.alert_handler_random_alerts.944497590
Short name T688
Test name
Test status
Simulation time 337445223 ps
CPU time 30.1 seconds
Started Aug 15 05:04:01 PM PDT 24
Finished Aug 15 05:04:31 PM PDT 24
Peak memory 256036 kb
Host smart-7bca6c72-937d-4588-8e55-952a0be2b325
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=94449
7590 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_alerts.944497590
Directory /workspace/43.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/43.alert_handler_random_classes.4240223863
Short name T51
Test name
Test status
Simulation time 217500521 ps
CPU time 27.77 seconds
Started Aug 15 05:04:03 PM PDT 24
Finished Aug 15 05:04:31 PM PDT 24
Peak memory 247984 kb
Host smart-77979c20-fdcf-4e11-b889-ced36bacc97e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42402
23863 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_random_classes.4240223863
Directory /workspace/43.alert_handler_random_classes/latest

Test location /workspace/coverage/default/43.alert_handler_smoke.2401388972
Short name T42
Test name
Test status
Simulation time 3291393620 ps
CPU time 57.15 seconds
Started Aug 15 05:04:01 PM PDT 24
Finished Aug 15 05:04:58 PM PDT 24
Peak memory 256952 kb
Host smart-3b9bd78b-cfea-46c5-9c97-ae56c07ad3d4
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24013
88972 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_handler_smoke.2401388972
Directory /workspace/43.alert_handler_smoke/latest

Test location /workspace/coverage/default/43.alert_handler_stress_all.1680060921
Short name T272
Test name
Test status
Simulation time 68678575764 ps
CPU time 1610.2 seconds
Started Aug 15 05:04:01 PM PDT 24
Finished Aug 15 05:30:51 PM PDT 24
Peak memory 289628 kb
Host smart-fca0fdcc-0745-411a-93f1-fc5c54c48904
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1680060921 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 43.alert_ha
ndler_stress_all.1680060921
Directory /workspace/43.alert_handler_stress_all/latest

Test location /workspace/coverage/default/44.alert_handler_entropy.90792655
Short name T664
Test name
Test status
Simulation time 123366328011 ps
CPU time 1463.58 seconds
Started Aug 15 05:04:08 PM PDT 24
Finished Aug 15 05:28:32 PM PDT 24
Peak memory 273036 kb
Host smart-ffe3f5ae-da65-4eab-a138-32d22c738c87
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=90792655 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -cm
line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_entropy.90792655
Directory /workspace/44.alert_handler_entropy/latest

Test location /workspace/coverage/default/44.alert_handler_esc_alert_accum.3687244128
Short name T283
Test name
Test status
Simulation time 1596747155 ps
CPU time 119.84 seconds
Started Aug 15 05:04:08 PM PDT 24
Finished Aug 15 05:06:08 PM PDT 24
Peak memory 256784 kb
Host smart-1a7b14f9-a1b3-46e6-b86a-7acb98394157
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36872
44128 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_alert_accum.3687244128
Directory /workspace/44.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/44.alert_handler_esc_intr_timeout.134456720
Short name T362
Test name
Test status
Simulation time 396905867 ps
CPU time 31.8 seconds
Started Aug 15 05:04:03 PM PDT 24
Finished Aug 15 05:04:35 PM PDT 24
Peak memory 256364 kb
Host smart-5cbd0bee-38ee-4da0-a6bc-d535c311d0d1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13445
6720 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_esc_intr_timeout.134456720
Directory /workspace/44.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_lpg.141516255
Short name T342
Test name
Test status
Simulation time 39836276005 ps
CPU time 921.74 seconds
Started Aug 15 05:04:09 PM PDT 24
Finished Aug 15 05:19:31 PM PDT 24
Peak memory 267208 kb
Host smart-61513a98-59aa-46cb-ba6e-d490fc475578
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=141516255 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg.141516255
Directory /workspace/44.alert_handler_lpg/latest

Test location /workspace/coverage/default/44.alert_handler_lpg_stub_clk.2592404280
Short name T517
Test name
Test status
Simulation time 39389609774 ps
CPU time 1805.03 seconds
Started Aug 15 05:04:16 PM PDT 24
Finished Aug 15 05:34:21 PM PDT 24
Peak memory 289696 kb
Host smart-35b38ecf-60d3-4263-95f4-9c57c69f7c82
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2592404280 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_lpg_stub_clk.2592404280
Directory /workspace/44.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/44.alert_handler_ping_timeout.689751356
Short name T322
Test name
Test status
Simulation time 3668486293 ps
CPU time 154.25 seconds
Started Aug 15 05:04:08 PM PDT 24
Finished Aug 15 05:06:42 PM PDT 24
Peak memory 255144 kb
Host smart-bccb3d25-bfc3-4afa-bda0-06e14e0f8175
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=689751356 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_ping_timeout.689751356
Directory /workspace/44.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/44.alert_handler_random_alerts.3225479298
Short name T582
Test name
Test status
Simulation time 713978101 ps
CPU time 38.79 seconds
Started Aug 15 05:04:03 PM PDT 24
Finished Aug 15 05:04:42 PM PDT 24
Peak memory 256240 kb
Host smart-d4b4aaef-8224-40ed-b5e6-7ec6b3e05fb2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32254
79298 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_alerts.3225479298
Directory /workspace/44.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/44.alert_handler_random_classes.1345960912
Short name T405
Test name
Test status
Simulation time 416240798 ps
CPU time 20.99 seconds
Started Aug 15 05:04:00 PM PDT 24
Finished Aug 15 05:04:21 PM PDT 24
Peak memory 248276 kb
Host smart-26781477-6a34-4d78-91d8-f697c8181d36
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13459
60912 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_random_classes.1345960912
Directory /workspace/44.alert_handler_random_classes/latest

Test location /workspace/coverage/default/44.alert_handler_sig_int_fail.103850593
Short name T256
Test name
Test status
Simulation time 257078938 ps
CPU time 31.29 seconds
Started Aug 15 05:04:10 PM PDT 24
Finished Aug 15 05:04:42 PM PDT 24
Peak memory 256256 kb
Host smart-1dfe31d1-07a4-475b-9704-7ca0b21de0d9
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10385
0593 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_sig_int_fail.103850593
Directory /workspace/44.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/44.alert_handler_smoke.653940872
Short name T693
Test name
Test status
Simulation time 1324151858 ps
CPU time 33.9 seconds
Started Aug 15 05:04:01 PM PDT 24
Finished Aug 15 05:04:36 PM PDT 24
Peak memory 256884 kb
Host smart-bdcbc0dc-9418-42c3-9c31-3fc0412cf834
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65394
0872 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 44.alert_handler_smoke.653940872
Directory /workspace/44.alert_handler_smoke/latest

Test location /workspace/coverage/default/44.alert_handler_stress_all_with_rand_reset.456442481
Short name T257
Test name
Test status
Simulation time 11217819283 ps
CPU time 196.23 seconds
Started Aug 15 05:04:07 PM PDT 24
Finished Aug 15 05:07:24 PM PDT 24
Peak memory 273144 kb
Host smart-7447cc95-7b4b-4388-ace9-2e95a6ba9c7e
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=456442481 -assert nopostproc +UVM_TESTNAME=alert
_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -
cm_log /dev/null -cm_name 44.alert_handler_stress_all_with_rand_reset.456442481
Directory /workspace/44.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/45.alert_handler_entropy.127076656
Short name T426
Test name
Test status
Simulation time 9222582884 ps
CPU time 817.68 seconds
Started Aug 15 05:04:18 PM PDT 24
Finished Aug 15 05:17:56 PM PDT 24
Peak memory 273424 kb
Host smart-94f83c8e-bf08-45b6-abff-686c473bb60c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=127076656 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_entropy.127076656
Directory /workspace/45.alert_handler_entropy/latest

Test location /workspace/coverage/default/45.alert_handler_esc_alert_accum.1132656014
Short name T543
Test name
Test status
Simulation time 1675045491 ps
CPU time 119.4 seconds
Started Aug 15 05:04:18 PM PDT 24
Finished Aug 15 05:06:17 PM PDT 24
Peak memory 256860 kb
Host smart-cc25dac3-00bf-484a-9b4a-f26e4636b88e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11326
56014 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_alert_accum.1132656014
Directory /workspace/45.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/45.alert_handler_esc_intr_timeout.587987756
Short name T89
Test name
Test status
Simulation time 1855441426 ps
CPU time 40.64 seconds
Started Aug 15 05:04:18 PM PDT 24
Finished Aug 15 05:04:59 PM PDT 24
Peak memory 256320 kb
Host smart-348c71a7-a57c-4a0e-bd90-bd3cb91a28bd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58798
7756 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_esc_intr_timeout.587987756
Directory /workspace/45.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_lpg.134112193
Short name T346
Test name
Test status
Simulation time 62946262757 ps
CPU time 3490.78 seconds
Started Aug 15 05:04:19 PM PDT 24
Finished Aug 15 06:02:30 PM PDT 24
Peak memory 288964 kb
Host smart-f4f9e310-f635-4519-b075-2f311c2816e0
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=134112193 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm li
ne+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg.134112193
Directory /workspace/45.alert_handler_lpg/latest

Test location /workspace/coverage/default/45.alert_handler_lpg_stub_clk.3184517435
Short name T639
Test name
Test status
Simulation time 148007155015 ps
CPU time 2279.52 seconds
Started Aug 15 05:04:18 PM PDT 24
Finished Aug 15 05:42:18 PM PDT 24
Peak memory 273368 kb
Host smart-d8fadc81-3207-4259-84e3-e2a52ffa6d49
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3184517435 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_lpg_stub_clk.3184517435
Directory /workspace/45.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/45.alert_handler_ping_timeout.670213193
Short name T228
Test name
Test status
Simulation time 33915188704 ps
CPU time 375.88 seconds
Started Aug 15 05:04:17 PM PDT 24
Finished Aug 15 05:10:33 PM PDT 24
Peak memory 248716 kb
Host smart-58e8a54c-7b01-41ef-b247-6db9700f1527
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=670213193 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_ping_timeout.670213193
Directory /workspace/45.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/45.alert_handler_random_alerts.4180936288
Short name T484
Test name
Test status
Simulation time 4063066123 ps
CPU time 29.76 seconds
Started Aug 15 05:04:09 PM PDT 24
Finished Aug 15 05:04:39 PM PDT 24
Peak memory 256096 kb
Host smart-4f84c27f-c561-488e-8205-92a9fbbf2200
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41809
36288 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_alerts.4180936288
Directory /workspace/45.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/45.alert_handler_random_classes.539425216
Short name T219
Test name
Test status
Simulation time 977713795 ps
CPU time 24.15 seconds
Started Aug 15 05:04:06 PM PDT 24
Finished Aug 15 05:04:31 PM PDT 24
Peak memory 256080 kb
Host smart-fabb74a5-3852-4b1d-a7fe-610feccdb981
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=53942
5216 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_random_classes.539425216
Directory /workspace/45.alert_handler_random_classes/latest

Test location /workspace/coverage/default/45.alert_handler_sig_int_fail.596861246
Short name T15
Test name
Test status
Simulation time 2654820766 ps
CPU time 24.61 seconds
Started Aug 15 05:04:18 PM PDT 24
Finished Aug 15 05:04:43 PM PDT 24
Peak memory 249880 kb
Host smart-ca5ecf51-d156-483a-915d-d8ceac23d9fc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=59686
1246 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_sig_int_fail.596861246
Directory /workspace/45.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/45.alert_handler_smoke.807103253
Short name T14
Test name
Test status
Simulation time 464000301 ps
CPU time 28.45 seconds
Started Aug 15 05:04:07 PM PDT 24
Finished Aug 15 05:04:36 PM PDT 24
Peak memory 256016 kb
Host smart-e7eaa7c3-94e2-4304-9ed7-6dbbc6dcc95f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=80710
3253 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_handler_smoke.807103253
Directory /workspace/45.alert_handler_smoke/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all.3743692062
Short name T276
Test name
Test status
Simulation time 110530029127 ps
CPU time 753.33 seconds
Started Aug 15 05:04:18 PM PDT 24
Finished Aug 15 05:16:51 PM PDT 24
Peak memory 265192 kb
Host smart-514f5209-0a25-41b3-9cbf-d1b6bbf80db3
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3743692062 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 45.alert_ha
ndler_stress_all.3743692062
Directory /workspace/45.alert_handler_stress_all/latest

Test location /workspace/coverage/default/45.alert_handler_stress_all_with_rand_reset.2897275443
Short name T247
Test name
Test status
Simulation time 11406633550 ps
CPU time 413.91 seconds
Started Aug 15 05:04:17 PM PDT 24
Finished Aug 15 05:11:11 PM PDT 24
Peak memory 266868 kb
Host smart-be97df90-125f-414f-8522-79a3d74ede13
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2897275443 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 45.alert_handler_stress_all_with_rand_reset.2897275443
Directory /workspace/45.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/46.alert_handler_entropy.630961151
Short name T110
Test name
Test status
Simulation time 54365393896 ps
CPU time 1695.88 seconds
Started Aug 15 05:04:25 PM PDT 24
Finished Aug 15 05:32:42 PM PDT 24
Peak memory 273084 kb
Host smart-0ccd4b5b-f7df-43b7-8046-9e4c57e81015
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=630961151 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -c
m line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_entropy.630961151
Directory /workspace/46.alert_handler_entropy/latest

Test location /workspace/coverage/default/46.alert_handler_esc_alert_accum.3503566696
Short name T416
Test name
Test status
Simulation time 14601255591 ps
CPU time 235.71 seconds
Started Aug 15 05:04:27 PM PDT 24
Finished Aug 15 05:08:23 PM PDT 24
Peak memory 256964 kb
Host smart-957253e2-cc47-4aa4-9740-652553df197c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35035
66696 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_alert_accum.3503566696
Directory /workspace/46.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/46.alert_handler_esc_intr_timeout.3093957045
Short name T512
Test name
Test status
Simulation time 616804478 ps
CPU time 22.31 seconds
Started Aug 15 05:04:28 PM PDT 24
Finished Aug 15 05:04:50 PM PDT 24
Peak memory 248172 kb
Host smart-a5e62553-8702-418b-a72f-9d4db1a28848
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=30939
57045 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_esc_intr_timeout.3093957045
Directory /workspace/46.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_lpg.1250226916
Short name T334
Test name
Test status
Simulation time 85206725693 ps
CPU time 1145.03 seconds
Started Aug 15 05:04:26 PM PDT 24
Finished Aug 15 05:23:31 PM PDT 24
Peak memory 271232 kb
Host smart-ff44800a-076b-4cd4-b213-8ea1e0a2b595
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1250226916 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg.1250226916
Directory /workspace/46.alert_handler_lpg/latest

Test location /workspace/coverage/default/46.alert_handler_lpg_stub_clk.3898235607
Short name T424
Test name
Test status
Simulation time 61771504035 ps
CPU time 1828.49 seconds
Started Aug 15 05:04:27 PM PDT 24
Finished Aug 15 05:34:55 PM PDT 24
Peak memory 273160 kb
Host smart-57ec2998-801e-4753-a1c0-04d7a1283d94
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3898235607 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_lpg_stub_clk.3898235607
Directory /workspace/46.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/46.alert_handler_ping_timeout.593383421
Short name T299
Test name
Test status
Simulation time 22359467677 ps
CPU time 258.07 seconds
Started Aug 15 05:04:27 PM PDT 24
Finished Aug 15 05:08:45 PM PDT 24
Peak memory 248720 kb
Host smart-d48e959c-9302-42cd-ad5a-b055cea218c2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=593383421 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_ping_timeout.593383421
Directory /workspace/46.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/46.alert_handler_random_alerts.2898401470
Short name T483
Test name
Test status
Simulation time 42944454 ps
CPU time 4.26 seconds
Started Aug 15 05:04:25 PM PDT 24
Finished Aug 15 05:04:29 PM PDT 24
Peak memory 240516 kb
Host smart-4f4450fc-6ebd-4556-aaff-bce38a88c0f5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28984
01470 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_alerts.2898401470
Directory /workspace/46.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/46.alert_handler_random_classes.1318293720
Short name T530
Test name
Test status
Simulation time 4347510806 ps
CPU time 67.03 seconds
Started Aug 15 05:04:27 PM PDT 24
Finished Aug 15 05:05:34 PM PDT 24
Peak memory 248364 kb
Host smart-1ecf1dbb-b69b-499c-a994-ffb9427e5993
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=13182
93720 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_random_classes.1318293720
Directory /workspace/46.alert_handler_random_classes/latest

Test location /workspace/coverage/default/46.alert_handler_sig_int_fail.561188068
Short name T461
Test name
Test status
Simulation time 348371484 ps
CPU time 11.8 seconds
Started Aug 15 05:04:26 PM PDT 24
Finished Aug 15 05:04:38 PM PDT 24
Peak memory 248104 kb
Host smart-7b0d68eb-9fe4-42b4-99f1-cfc71a0377e7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=56118
8068 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_sig_int_fail.561188068
Directory /workspace/46.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/46.alert_handler_smoke.228642819
Short name T418
Test name
Test status
Simulation time 4652204589 ps
CPU time 72.26 seconds
Started Aug 15 05:04:18 PM PDT 24
Finished Aug 15 05:05:30 PM PDT 24
Peak memory 256964 kb
Host smart-dcffa348-650d-4fcf-b44d-69535d7c7c82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22864
2819 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_handler_smoke.228642819
Directory /workspace/46.alert_handler_smoke/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all.374176576
Short name T497
Test name
Test status
Simulation time 31959858532 ps
CPU time 1849.16 seconds
Started Aug 15 05:04:26 PM PDT 24
Finished Aug 15 05:35:16 PM PDT 24
Peak memory 289400 kb
Host smart-d7a25166-73e1-4079-a926-4339921c640e
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=374176576 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 46.alert_han
dler_stress_all.374176576
Directory /workspace/46.alert_handler_stress_all/latest

Test location /workspace/coverage/default/46.alert_handler_stress_all_with_rand_reset.3563185775
Short name T571
Test name
Test status
Simulation time 4219317007 ps
CPU time 468.32 seconds
Started Aug 15 05:04:26 PM PDT 24
Finished Aug 15 05:12:14 PM PDT 24
Peak memory 270992 kb
Host smart-cc7385a9-07fc-4d7f-86fe-80537e61d281
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3563185775 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 46.alert_handler_stress_all_with_rand_reset.3563185775
Directory /workspace/46.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/47.alert_handler_entropy.3954326650
Short name T66
Test name
Test status
Simulation time 7219450770 ps
CPU time 798.89 seconds
Started Aug 15 05:04:39 PM PDT 24
Finished Aug 15 05:17:58 PM PDT 24
Peak memory 273256 kb
Host smart-d5c919cc-4166-412e-a398-e23ee18b6a86
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3954326650 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_entropy.3954326650
Directory /workspace/47.alert_handler_entropy/latest

Test location /workspace/coverage/default/47.alert_handler_esc_alert_accum.476242864
Short name T675
Test name
Test status
Simulation time 3381603234 ps
CPU time 92.01 seconds
Started Aug 15 05:04:36 PM PDT 24
Finished Aug 15 05:06:09 PM PDT 24
Peak memory 257016 kb
Host smart-3d96f846-f46a-4a10-8972-25606af11b0b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=47624
2864 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_alert_accum.476242864
Directory /workspace/47.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/47.alert_handler_esc_intr_timeout.120015901
Short name T686
Test name
Test status
Simulation time 373263071 ps
CPU time 25.31 seconds
Started Aug 15 05:04:34 PM PDT 24
Finished Aug 15 05:05:00 PM PDT 24
Peak memory 248648 kb
Host smart-7fc75254-9144-430e-bd97-f22ecb39c0ff
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12001
5901 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_esc_intr_timeout.120015901
Directory /workspace/47.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_lpg.2851424211
Short name T593
Test name
Test status
Simulation time 264291658299 ps
CPU time 1450.48 seconds
Started Aug 15 05:04:35 PM PDT 24
Finished Aug 15 05:28:46 PM PDT 24
Peak memory 289088 kb
Host smart-5af2d5cd-9098-4bfe-84b7-4b9296fd65de
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2851424211 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg.2851424211
Directory /workspace/47.alert_handler_lpg/latest

Test location /workspace/coverage/default/47.alert_handler_lpg_stub_clk.4058631971
Short name T486
Test name
Test status
Simulation time 34856990685 ps
CPU time 2316.65 seconds
Started Aug 15 05:04:37 PM PDT 24
Finished Aug 15 05:43:14 PM PDT 24
Peak memory 287764 kb
Host smart-d137aafd-003d-4c32-892b-7ecdb252059d
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4058631971 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_lpg_stub_clk.4058631971
Directory /workspace/47.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/47.alert_handler_ping_timeout.1280384875
Short name T315
Test name
Test status
Simulation time 9950401032 ps
CPU time 207.76 seconds
Started Aug 15 05:04:36 PM PDT 24
Finished Aug 15 05:08:03 PM PDT 24
Peak memory 248708 kb
Host smart-12e87106-efd0-432c-9dd0-61c025262be5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1280384875 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_ping_timeout.1280384875
Directory /workspace/47.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/47.alert_handler_random_alerts.1925110107
Short name T651
Test name
Test status
Simulation time 1552327468 ps
CPU time 25.3 seconds
Started Aug 15 05:04:27 PM PDT 24
Finished Aug 15 05:04:53 PM PDT 24
Peak memory 256200 kb
Host smart-b2e93971-1a21-482a-8853-50c7aff14dbb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=19251
10107 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_alerts.1925110107
Directory /workspace/47.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/47.alert_handler_random_classes.128107366
Short name T465
Test name
Test status
Simulation time 268264179 ps
CPU time 20.32 seconds
Started Aug 15 05:04:25 PM PDT 24
Finished Aug 15 05:04:46 PM PDT 24
Peak memory 248256 kb
Host smart-e9a188df-567f-4bef-a85c-1cc3327e238c
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12810
7366 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_random_classes.128107366
Directory /workspace/47.alert_handler_random_classes/latest

Test location /workspace/coverage/default/47.alert_handler_sig_int_fail.658541282
Short name T86
Test name
Test status
Simulation time 19351189 ps
CPU time 3.37 seconds
Started Aug 15 05:04:38 PM PDT 24
Finished Aug 15 05:04:42 PM PDT 24
Peak memory 240028 kb
Host smart-42f72072-a97a-4478-a8d7-b0858ba1d825
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=65854
1282 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_sig_int_fail.658541282
Directory /workspace/47.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/47.alert_handler_smoke.1583615718
Short name T370
Test name
Test status
Simulation time 508539720 ps
CPU time 33.99 seconds
Started Aug 15 05:04:26 PM PDT 24
Finished Aug 15 05:05:00 PM PDT 24
Peak memory 256156 kb
Host smart-e6d4c4a1-9e4b-4e83-b177-eddf7c343bdc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15836
15718 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_handler_smoke.1583615718
Directory /workspace/47.alert_handler_smoke/latest

Test location /workspace/coverage/default/47.alert_handler_stress_all.842152186
Short name T33
Test name
Test status
Simulation time 301014741963 ps
CPU time 1427.15 seconds
Started Aug 15 05:04:35 PM PDT 24
Finished Aug 15 05:28:22 PM PDT 24
Peak memory 289748 kb
Host smart-351d9070-5af5-4962-b2c3-44c75661882a
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=842152186 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 47.alert_han
dler_stress_all.842152186
Directory /workspace/47.alert_handler_stress_all/latest

Test location /workspace/coverage/default/48.alert_handler_entropy.1387245749
Short name T712
Test name
Test status
Simulation time 42008491896 ps
CPU time 871.62 seconds
Started Aug 15 05:04:42 PM PDT 24
Finished Aug 15 05:19:13 PM PDT 24
Peak memory 267244 kb
Host smart-073a4db1-e6fa-4087-8cf5-050638f632e2
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1387245749 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_entropy.1387245749
Directory /workspace/48.alert_handler_entropy/latest

Test location /workspace/coverage/default/48.alert_handler_esc_alert_accum.288286942
Short name T636
Test name
Test status
Simulation time 1201787537 ps
CPU time 23.06 seconds
Started Aug 15 05:04:35 PM PDT 24
Finished Aug 15 05:04:58 PM PDT 24
Peak memory 256300 kb
Host smart-2fe73cc8-6666-4ce3-ae47-7ef474ef56a2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=28828
6942 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_alert_accum.288286942
Directory /workspace/48.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/48.alert_handler_esc_intr_timeout.1814815058
Short name T552
Test name
Test status
Simulation time 52015498 ps
CPU time 2.75 seconds
Started Aug 15 05:04:34 PM PDT 24
Finished Aug 15 05:04:37 PM PDT 24
Peak memory 240064 kb
Host smart-830d822e-5e45-40e9-870a-ce8cb1b0c09b
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18148
15058 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_esc_intr_timeout.1814815058
Directory /workspace/48.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_lpg.1071433376
Short name T680
Test name
Test status
Simulation time 13726628973 ps
CPU time 1132.15 seconds
Started Aug 15 05:04:44 PM PDT 24
Finished Aug 15 05:23:36 PM PDT 24
Peak memory 273348 kb
Host smart-3cb5439a-d9d2-49e0-a9da-d05e02f816d9
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1071433376 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg.1071433376
Directory /workspace/48.alert_handler_lpg/latest

Test location /workspace/coverage/default/48.alert_handler_lpg_stub_clk.3249078034
Short name T347
Test name
Test status
Simulation time 19590017889 ps
CPU time 858.3 seconds
Started Aug 15 05:04:45 PM PDT 24
Finished Aug 15 05:19:04 PM PDT 24
Peak memory 273052 kb
Host smart-3c506e36-24f3-4788-bf1b-ffd912e76f35
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3249078034 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_lpg_stub_clk.3249078034
Directory /workspace/48.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/48.alert_handler_ping_timeout.4020151646
Short name T327
Test name
Test status
Simulation time 34374787240 ps
CPU time 444.02 seconds
Started Aug 15 05:04:47 PM PDT 24
Finished Aug 15 05:12:11 PM PDT 24
Peak memory 247684 kb
Host smart-4535e52c-3ba6-4bb6-adf4-69e08dd4f07c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4020151646 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_ping_timeout.4020151646
Directory /workspace/48.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/48.alert_handler_random_alerts.3938171297
Short name T218
Test name
Test status
Simulation time 160410121 ps
CPU time 4.29 seconds
Started Aug 15 05:04:35 PM PDT 24
Finished Aug 15 05:04:40 PM PDT 24
Peak memory 248764 kb
Host smart-fd8ab4d3-03ff-475e-9db7-badbe74caccc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=39381
71297 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_alerts.3938171297
Directory /workspace/48.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/48.alert_handler_random_classes.4003637245
Short name T558
Test name
Test status
Simulation time 556534113 ps
CPU time 32.36 seconds
Started Aug 15 05:04:37 PM PDT 24
Finished Aug 15 05:05:10 PM PDT 24
Peak memory 248264 kb
Host smart-8b0e4b5d-726d-4554-8ff9-fced063244bb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=40036
37245 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_random_classes.4003637245
Directory /workspace/48.alert_handler_random_classes/latest

Test location /workspace/coverage/default/48.alert_handler_sig_int_fail.1009341004
Short name T597
Test name
Test status
Simulation time 564927475 ps
CPU time 40.97 seconds
Started Aug 15 05:04:44 PM PDT 24
Finished Aug 15 05:05:25 PM PDT 24
Peak memory 256256 kb
Host smart-75bdecb2-b351-4592-824e-1b87723eb8c5
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10093
41004 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_sig_int_fail.1009341004
Directory /workspace/48.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/48.alert_handler_smoke.1817549295
Short name T548
Test name
Test status
Simulation time 312239334 ps
CPU time 27.2 seconds
Started Aug 15 05:04:34 PM PDT 24
Finished Aug 15 05:05:01 PM PDT 24
Peak memory 248788 kb
Host smart-41b6e3c5-408a-4633-8340-3a551fac9852
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=18175
49295 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_handler_smoke.1817549295
Directory /workspace/48.alert_handler_smoke/latest

Test location /workspace/coverage/default/48.alert_handler_stress_all.261650490
Short name T61
Test name
Test status
Simulation time 10185998004 ps
CPU time 191.27 seconds
Started Aug 15 05:04:43 PM PDT 24
Finished Aug 15 05:07:55 PM PDT 24
Peak memory 257044 kb
Host smart-95018757-6212-4eb2-b50f-a02478407851
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=261650490 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_han
dler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 48.alert_han
dler_stress_all.261650490
Directory /workspace/48.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_entropy.2552443987
Short name T106
Test name
Test status
Simulation time 9546415704 ps
CPU time 899.87 seconds
Started Aug 15 05:04:43 PM PDT 24
Finished Aug 15 05:19:43 PM PDT 24
Peak memory 272940 kb
Host smart-95c099fb-0d1d-434f-b0be-93f72fb60f35
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2552443987 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_entropy.2552443987
Directory /workspace/49.alert_handler_entropy/latest

Test location /workspace/coverage/default/49.alert_handler_esc_alert_accum.2214027881
Short name T560
Test name
Test status
Simulation time 641381491 ps
CPU time 54.75 seconds
Started Aug 15 05:04:44 PM PDT 24
Finished Aug 15 05:05:38 PM PDT 24
Peak memory 256948 kb
Host smart-8c211d40-1b22-48f2-8e0e-b203c7dab1b8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22140
27881 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_alert_accum.2214027881
Directory /workspace/49.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/49.alert_handler_esc_intr_timeout.3505672161
Short name T707
Test name
Test status
Simulation time 1004945725 ps
CPU time 59.18 seconds
Started Aug 15 05:04:44 PM PDT 24
Finished Aug 15 05:05:44 PM PDT 24
Peak memory 248520 kb
Host smart-e9fc9005-fee4-48df-97ac-97e71eeaed29
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=35056
72161 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_esc_intr_timeout.3505672161
Directory /workspace/49.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/49.alert_handler_lpg.2104950857
Short name T332
Test name
Test status
Simulation time 37395448316 ps
CPU time 2081.94 seconds
Started Aug 15 05:04:45 PM PDT 24
Finished Aug 15 05:39:27 PM PDT 24
Peak memory 288048 kb
Host smart-691d7abc-2f81-4c8e-8b1c-c0bde4b1b560
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2104950857 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg.2104950857
Directory /workspace/49.alert_handler_lpg/latest

Test location /workspace/coverage/default/49.alert_handler_lpg_stub_clk.2904395638
Short name T292
Test name
Test status
Simulation time 161304940260 ps
CPU time 2748.99 seconds
Started Aug 15 05:04:47 PM PDT 24
Finished Aug 15 05:50:37 PM PDT 24
Peak memory 289596 kb
Host smart-84c88788-f6bf-41d8-aa21-c437a13071d5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2904395638 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_lpg_stub_clk.2904395638
Directory /workspace/49.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/49.alert_handler_random_alerts.2353811210
Short name T487
Test name
Test status
Simulation time 1684871752 ps
CPU time 15.31 seconds
Started Aug 15 05:04:45 PM PDT 24
Finished Aug 15 05:05:01 PM PDT 24
Peak memory 248680 kb
Host smart-3dd2a523-4528-4cac-90db-be81f5db4acb
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=23538
11210 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_alerts.2353811210
Directory /workspace/49.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/49.alert_handler_random_classes.77149641
Short name T580
Test name
Test status
Simulation time 1161126578 ps
CPU time 38.34 seconds
Started Aug 15 05:04:43 PM PDT 24
Finished Aug 15 05:05:22 PM PDT 24
Peak memory 256972 kb
Host smart-448bfdd8-e39b-40a0-8c78-5f85ae673800
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77149
641 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_random_classes.77149641
Directory /workspace/49.alert_handler_random_classes/latest

Test location /workspace/coverage/default/49.alert_handler_sig_int_fail.1692120734
Short name T522
Test name
Test status
Simulation time 804359136 ps
CPU time 60.35 seconds
Started Aug 15 05:04:44 PM PDT 24
Finished Aug 15 05:05:45 PM PDT 24
Peak memory 249644 kb
Host smart-668309dc-1cd9-410d-925b-2bdc37d43227
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=16921
20734 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_sig_int_fail.1692120734
Directory /workspace/49.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/49.alert_handler_smoke.2663397078
Short name T25
Test name
Test status
Simulation time 271975790 ps
CPU time 24.77 seconds
Started Aug 15 05:04:45 PM PDT 24
Finished Aug 15 05:05:10 PM PDT 24
Peak memory 256804 kb
Host smart-d94dcf33-aa7b-47be-8d01-eb2a55cfcefc
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=26633
97078 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_handler_smoke.2663397078
Directory /workspace/49.alert_handler_smoke/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all.1957122342
Short name T604
Test name
Test status
Simulation time 343169709177 ps
CPU time 1864.74 seconds
Started Aug 15 05:04:45 PM PDT 24
Finished Aug 15 05:35:50 PM PDT 24
Peak memory 281500 kb
Host smart-d301db0e-d17e-4324-a191-6d0aba6459ce
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=1957122342 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 49.alert_ha
ndler_stress_all.1957122342
Directory /workspace/49.alert_handler_stress_all/latest

Test location /workspace/coverage/default/49.alert_handler_stress_all_with_rand_reset.3963651882
Short name T608
Test name
Test status
Simulation time 9381493213 ps
CPU time 174.55 seconds
Started Aug 15 05:04:52 PM PDT 24
Finished Aug 15 05:07:47 PM PDT 24
Peak memory 265292 kb
Host smart-e4db2776-2911-46ed-b169-6a4603334c57
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3963651882 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 49.alert_handler_stress_all_with_rand_reset.3963651882
Directory /workspace/49.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/5.alert_handler_alert_accum_saturation.3055341848
Short name T204
Test name
Test status
Simulation time 18330077 ps
CPU time 2.48 seconds
Started Aug 15 04:59:48 PM PDT 24
Finished Aug 15 04:59:51 PM PDT 24
Peak memory 248856 kb
Host smart-96051c4f-2685-42f6-bee6-7b1b8b1a175c
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3055341848 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_alert_accum_saturation.3055341848
Directory /workspace/5.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/5.alert_handler_entropy.3678671555
Short name T28
Test name
Test status
Simulation time 33780204845 ps
CPU time 1454.13 seconds
Started Aug 15 04:59:50 PM PDT 24
Finished Aug 15 05:24:04 PM PDT 24
Peak memory 288848 kb
Host smart-3e252843-eeb5-49bb-aae7-22a5d80dfe13
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3678671555 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy.3678671555
Directory /workspace/5.alert_handler_entropy/latest

Test location /workspace/coverage/default/5.alert_handler_entropy_stress.2556666934
Short name T388
Test name
Test status
Simulation time 399992960 ps
CPU time 8.29 seconds
Started Aug 15 04:59:50 PM PDT 24
Finished Aug 15 04:59:58 PM PDT 24
Peak memory 248720 kb
Host smart-5d268724-8582-40f7-98ff-e8fd8b2cd2dc
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2556666934 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_entropy_stress.2556666934
Directory /workspace/5.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/5.alert_handler_esc_alert_accum.3448322964
Short name T83
Test name
Test status
Simulation time 3322243251 ps
CPU time 198.8 seconds
Started Aug 15 04:59:50 PM PDT 24
Finished Aug 15 05:03:09 PM PDT 24
Peak memory 257020 kb
Host smart-f299739d-e200-4925-bab0-49b3652032f2
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34483
22964 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_alert_accum.3448322964
Directory /workspace/5.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/5.alert_handler_esc_intr_timeout.3646927780
Short name T423
Test name
Test status
Simulation time 999006071 ps
CPU time 17.75 seconds
Started Aug 15 04:59:49 PM PDT 24
Finished Aug 15 05:00:07 PM PDT 24
Peak memory 248656 kb
Host smart-cfe42dc9-eea2-46c7-9882-8a2e268f1b75
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=36469
27780 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_esc_intr_timeout.3646927780
Directory /workspace/5.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_lpg.2160628655
Short name T340
Test name
Test status
Simulation time 15395241386 ps
CPU time 722.14 seconds
Started Aug 15 04:59:50 PM PDT 24
Finished Aug 15 05:11:52 PM PDT 24
Peak memory 272996 kb
Host smart-def99a64-a2fe-4a59-921d-3ffd0f983f55
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2160628655 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg.2160628655
Directory /workspace/5.alert_handler_lpg/latest

Test location /workspace/coverage/default/5.alert_handler_lpg_stub_clk.1455382215
Short name T46
Test name
Test status
Simulation time 69766948535 ps
CPU time 2751.59 seconds
Started Aug 15 04:59:50 PM PDT 24
Finished Aug 15 05:45:42 PM PDT 24
Peak memory 289268 kb
Host smart-60c745ea-358d-421d-bad7-395bf8c1a155
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1455382215 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_lpg_stub_clk.1455382215
Directory /workspace/5.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/5.alert_handler_ping_timeout.595128411
Short name T623
Test name
Test status
Simulation time 12844627080 ps
CPU time 535.71 seconds
Started Aug 15 04:59:52 PM PDT 24
Finished Aug 15 05:08:48 PM PDT 24
Peak memory 247668 kb
Host smart-163bc1d1-d141-45e3-bd4a-0800aec53758
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=595128411 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_ping_timeout.595128411
Directory /workspace/5.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/5.alert_handler_random_alerts.1102298337
Short name T420
Test name
Test status
Simulation time 93790356 ps
CPU time 5.96 seconds
Started Aug 15 04:59:50 PM PDT 24
Finished Aug 15 04:59:57 PM PDT 24
Peak memory 248752 kb
Host smart-3f14b362-f5c2-41eb-b056-2fdd33aa0e59
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=11022
98337 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_alerts.1102298337
Directory /workspace/5.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/5.alert_handler_random_classes.3373885721
Short name T705
Test name
Test status
Simulation time 430824612 ps
CPU time 26.81 seconds
Started Aug 15 04:59:49 PM PDT 24
Finished Aug 15 05:00:16 PM PDT 24
Peak memory 256456 kb
Host smart-e51032ff-c3fa-4b51-bdd1-a4bd2c3885e1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33738
85721 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_random_classes.3373885721
Directory /workspace/5.alert_handler_random_classes/latest

Test location /workspace/coverage/default/5.alert_handler_sig_int_fail.3367154187
Short name T652
Test name
Test status
Simulation time 584912688 ps
CPU time 35.11 seconds
Started Aug 15 04:59:51 PM PDT 24
Finished Aug 15 05:00:26 PM PDT 24
Peak memory 248744 kb
Host smart-97ef1f80-369a-4528-9214-4d8bab3ca98d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=33671
54187 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_sig_int_fail.3367154187
Directory /workspace/5.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/5.alert_handler_smoke.694995022
Short name T381
Test name
Test status
Simulation time 59814924 ps
CPU time 4.59 seconds
Started Aug 15 04:59:49 PM PDT 24
Finished Aug 15 04:59:54 PM PDT 24
Peak memory 248744 kb
Host smart-dc846d8c-10c2-48ba-8db6-8dc031cd3059
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=69499
5022 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_handler_smoke.694995022
Directory /workspace/5.alert_handler_smoke/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all.3477805578
Short name T266
Test name
Test status
Simulation time 18638058189 ps
CPU time 1118.44 seconds
Started Aug 15 04:59:51 PM PDT 24
Finished Aug 15 05:18:29 PM PDT 24
Peak memory 270384 kb
Host smart-6ded5534-40d5-4a52-a21e-5939f149c7ef
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3477805578 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 5.alert_han
dler_stress_all.3477805578
Directory /workspace/5.alert_handler_stress_all/latest

Test location /workspace/coverage/default/5.alert_handler_stress_all_with_rand_reset.2499109599
Short name T125
Test name
Test status
Simulation time 12426907441 ps
CPU time 337.12 seconds
Started Aug 15 04:59:54 PM PDT 24
Finished Aug 15 05:05:31 PM PDT 24
Peak memory 270000 kb
Host smart-38bdcde0-c2cb-4f0c-b8a7-d75d049d2388
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2499109599 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 5.alert_handler_stress_all_with_rand_reset.2499109599
Directory /workspace/5.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/6.alert_handler_alert_accum_saturation.4145721077
Short name T208
Test name
Test status
Simulation time 167440427 ps
CPU time 3.97 seconds
Started Aug 15 05:00:00 PM PDT 24
Finished Aug 15 05:00:04 PM PDT 24
Peak memory 248972 kb
Host smart-37e738cc-d60e-46b7-93e1-120c3851a6e9
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=4145721077 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_alert_accum_saturation.4145721077
Directory /workspace/6.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/6.alert_handler_entropy.2379928626
Short name T295
Test name
Test status
Simulation time 11132894379 ps
CPU time 1077.72 seconds
Started Aug 15 04:59:51 PM PDT 24
Finished Aug 15 05:17:49 PM PDT 24
Peak memory 288616 kb
Host smart-8c0b17d5-50c1-4fba-a903-28b395658988
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2379928626 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy.2379928626
Directory /workspace/6.alert_handler_entropy/latest

Test location /workspace/coverage/default/6.alert_handler_entropy_stress.1627344267
Short name T389
Test name
Test status
Simulation time 882617163 ps
CPU time 12.87 seconds
Started Aug 15 04:59:59 PM PDT 24
Finished Aug 15 05:00:12 PM PDT 24
Peak memory 248648 kb
Host smart-2c36f4fb-8fa2-492e-8158-254f71b7bd24
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1627344267 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_entropy_stress.1627344267
Directory /workspace/6.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/6.alert_handler_esc_alert_accum.1041176707
Short name T632
Test name
Test status
Simulation time 8767845214 ps
CPU time 131.63 seconds
Started Aug 15 04:59:49 PM PDT 24
Finished Aug 15 05:02:01 PM PDT 24
Peak memory 256916 kb
Host smart-92f519d0-e790-4190-8b19-e3d197e20c88
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10411
76707 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_alert_accum.1041176707
Directory /workspace/6.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/6.alert_handler_esc_intr_timeout.926247370
Short name T655
Test name
Test status
Simulation time 1768520055 ps
CPU time 46.76 seconds
Started Aug 15 04:59:49 PM PDT 24
Finished Aug 15 05:00:36 PM PDT 24
Peak memory 256968 kb
Host smart-a766fcd6-f79f-48bd-8c70-e81b2357ac12
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=92624
7370 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_esc_intr_timeout.926247370
Directory /workspace/6.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/6.alert_handler_lpg.3935729015
Short name T521
Test name
Test status
Simulation time 208509903145 ps
CPU time 3141.18 seconds
Started Aug 15 04:59:50 PM PDT 24
Finished Aug 15 05:52:12 PM PDT 24
Peak memory 286112 kb
Host smart-ce60c2e8-ce3a-4a70-92b2-8ab8f7f3a058
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3935729015 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg.3935729015
Directory /workspace/6.alert_handler_lpg/latest

Test location /workspace/coverage/default/6.alert_handler_lpg_stub_clk.4176945449
Short name T39
Test name
Test status
Simulation time 177147034605 ps
CPU time 2569.93 seconds
Started Aug 15 04:59:49 PM PDT 24
Finished Aug 15 05:42:39 PM PDT 24
Peak memory 281600 kb
Host smart-e221c801-e059-42f4-8e99-9058b84a08eb
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4176945449 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_lpg_stub_clk.4176945449
Directory /workspace/6.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/6.alert_handler_random_alerts.2478262991
Short name T478
Test name
Test status
Simulation time 403265649 ps
CPU time 28.21 seconds
Started Aug 15 04:59:49 PM PDT 24
Finished Aug 15 05:00:17 PM PDT 24
Peak memory 256200 kb
Host smart-fe670fd4-8362-4d04-9ddf-94a668e5894e
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=24782
62991 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_alerts.2478262991
Directory /workspace/6.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/6.alert_handler_random_classes.2184659046
Short name T672
Test name
Test status
Simulation time 637298242 ps
CPU time 15.06 seconds
Started Aug 15 04:59:53 PM PDT 24
Finished Aug 15 05:00:08 PM PDT 24
Peak memory 256332 kb
Host smart-bdf26caf-cafd-4e80-a628-078a6c8d0ec3
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21846
59046 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_random_classes.2184659046
Directory /workspace/6.alert_handler_random_classes/latest

Test location /workspace/coverage/default/6.alert_handler_sig_int_fail.587212811
Short name T629
Test name
Test status
Simulation time 293069423 ps
CPU time 32.62 seconds
Started Aug 15 04:59:48 PM PDT 24
Finished Aug 15 05:00:20 PM PDT 24
Peak memory 248196 kb
Host smart-d16dd181-6615-40f7-acc3-6cd26fdbef07
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=58721
2811 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_sig_int_fail.587212811
Directory /workspace/6.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/6.alert_handler_smoke.1538733455
Short name T425
Test name
Test status
Simulation time 2113796761 ps
CPU time 36.13 seconds
Started Aug 15 04:59:49 PM PDT 24
Finished Aug 15 05:00:25 PM PDT 24
Peak memory 256388 kb
Host smart-eb10bf00-ee89-49cf-82b3-84c072d318be
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15387
33455 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 6.alert_handler_smoke.1538733455
Directory /workspace/6.alert_handler_smoke/latest

Test location /workspace/coverage/default/6.alert_handler_stress_all_with_rand_reset.2226792697
Short name T98
Test name
Test status
Simulation time 6293537751 ps
CPU time 145.18 seconds
Started Aug 15 05:00:00 PM PDT 24
Finished Aug 15 05:02:25 PM PDT 24
Peak memory 266388 kb
Host smart-6fa85fae-0278-4c8b-9646-b5b39dbe08be
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2226792697 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 6.alert_handler_stress_all_with_rand_reset.2226792697
Directory /workspace/6.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/7.alert_handler_alert_accum_saturation.2855355363
Short name T215
Test name
Test status
Simulation time 36320595 ps
CPU time 2.58 seconds
Started Aug 15 04:59:59 PM PDT 24
Finished Aug 15 05:00:02 PM PDT 24
Peak memory 248864 kb
Host smart-236b352c-c266-4c35-a6dd-667314b83859
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2855355363 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_alert_accum_saturation.2855355363
Directory /workspace/7.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/7.alert_handler_entropy.1648038452
Short name T87
Test name
Test status
Simulation time 9022075745 ps
CPU time 1010.26 seconds
Started Aug 15 05:00:00 PM PDT 24
Finished Aug 15 05:16:50 PM PDT 24
Peak memory 289172 kb
Host smart-45eace13-d754-4253-b21f-7352b207ec83
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1648038452 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy.1648038452
Directory /workspace/7.alert_handler_entropy/latest

Test location /workspace/coverage/default/7.alert_handler_entropy_stress.3501140156
Short name T547
Test name
Test status
Simulation time 934940459 ps
CPU time 12.47 seconds
Started Aug 15 05:00:00 PM PDT 24
Finished Aug 15 05:00:13 PM PDT 24
Peak memory 248772 kb
Host smart-b7409530-d1d8-411c-ab02-ae7098982b1f
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3501140156 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_entropy_stress.3501140156
Directory /workspace/7.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/7.alert_handler_esc_alert_accum.2277069209
Short name T432
Test name
Test status
Simulation time 10095097749 ps
CPU time 88.12 seconds
Started Aug 15 05:00:00 PM PDT 24
Finished Aug 15 05:01:28 PM PDT 24
Peak memory 256788 kb
Host smart-398580f0-45bb-43f1-b747-fa70eb4559cd
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=22770
69209 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_alert_accum.2277069209
Directory /workspace/7.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/7.alert_handler_esc_intr_timeout.880573071
Short name T394
Test name
Test status
Simulation time 268301540 ps
CPU time 18.12 seconds
Started Aug 15 05:00:07 PM PDT 24
Finished Aug 15 05:00:25 PM PDT 24
Peak memory 248200 kb
Host smart-6ba45fc3-d4c7-42e7-aaee-4d62f8a401b6
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=88057
3071 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_esc_intr_timeout.880573071
Directory /workspace/7.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_lpg.4220616432
Short name T596
Test name
Test status
Simulation time 87584508495 ps
CPU time 1218.06 seconds
Started Aug 15 04:59:58 PM PDT 24
Finished Aug 15 05:20:17 PM PDT 24
Peak memory 284856 kb
Host smart-c2e5d683-9893-4849-8419-48873d573836
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=4220616432 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg.4220616432
Directory /workspace/7.alert_handler_lpg/latest

Test location /workspace/coverage/default/7.alert_handler_lpg_stub_clk.3505811052
Short name T19
Test name
Test status
Simulation time 73997500546 ps
CPU time 1525.3 seconds
Started Aug 15 05:00:00 PM PDT 24
Finished Aug 15 05:25:25 PM PDT 24
Peak memory 288816 kb
Host smart-9c41206e-dbdd-45c2-89d9-e1843804b4a3
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3505811052 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_lpg_stub_clk.3505811052
Directory /workspace/7.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/7.alert_handler_ping_timeout.724500831
Short name T537
Test name
Test status
Simulation time 3202195227 ps
CPU time 137.78 seconds
Started Aug 15 05:00:02 PM PDT 24
Finished Aug 15 05:02:24 PM PDT 24
Peak memory 255040 kb
Host smart-31c71278-45c9-4c35-9ea5-60b3b8341c54
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=724500831 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_cov
=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_ping_timeout.724500831
Directory /workspace/7.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/7.alert_handler_random_alerts.1419121959
Short name T526
Test name
Test status
Simulation time 752129973 ps
CPU time 34.83 seconds
Started Aug 15 04:59:58 PM PDT 24
Finished Aug 15 05:00:33 PM PDT 24
Peak memory 256880 kb
Host smart-cab4015f-1144-470d-b0c2-41c0c678ad6f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=14191
21959 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_alerts.1419121959
Directory /workspace/7.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/7.alert_handler_random_classes.4136956616
Short name T701
Test name
Test status
Simulation time 325477821 ps
CPU time 35.28 seconds
Started Aug 15 05:00:03 PM PDT 24
Finished Aug 15 05:00:42 PM PDT 24
Peak memory 248028 kb
Host smart-910f6d14-8780-412b-beff-539d54def779
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41369
56616 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_random_classes.4136956616
Directory /workspace/7.alert_handler_random_classes/latest

Test location /workspace/coverage/default/7.alert_handler_sig_int_fail.1768853709
Short name T285
Test name
Test status
Simulation time 721805256 ps
CPU time 52.01 seconds
Started Aug 15 05:00:00 PM PDT 24
Finished Aug 15 05:00:52 PM PDT 24
Peak memory 255616 kb
Host smart-cd7e6e41-26d3-493f-ba09-82ab4a4d8b8a
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=17688
53709 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branc
h+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_sig_int_fail.1768853709
Directory /workspace/7.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/7.alert_handler_smoke.2188632428
Short name T505
Test name
Test status
Simulation time 1096329431 ps
CPU time 34.31 seconds
Started Aug 15 05:00:00 PM PDT 24
Finished Aug 15 05:00:35 PM PDT 24
Peak memory 256876 kb
Host smart-82d461dd-3fa9-4257-90e4-f76c1f3bdfe7
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21886
32428 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 7.alert_handler_smoke.2188632428
Directory /workspace/7.alert_handler_smoke/latest

Test location /workspace/coverage/default/7.alert_handler_stress_all_with_rand_reset.2286141862
Short name T269
Test name
Test status
Simulation time 4009733042 ps
CPU time 252.16 seconds
Started Aug 15 05:00:07 PM PDT 24
Finished Aug 15 05:04:19 PM PDT 24
Peak memory 266460 kb
Host smart-916e6018-8657-4b1d-9452-e0e2ea3de3a9
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2286141862 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 7.alert_handler_stress_all_with_rand_reset.2286141862
Directory /workspace/7.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/8.alert_handler_alert_accum_saturation.2448271446
Short name T207
Test name
Test status
Simulation time 141766554 ps
CPU time 3.54 seconds
Started Aug 15 05:00:02 PM PDT 24
Finished Aug 15 05:00:10 PM PDT 24
Peak memory 248884 kb
Host smart-a3dabc53-3e1e-45ca-95e3-ebd5e0e83c60
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=2448271446 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_alert_accum_saturation.2448271446
Directory /workspace/8.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/8.alert_handler_entropy.2574258359
Short name T444
Test name
Test status
Simulation time 167231063998 ps
CPU time 2472.65 seconds
Started Aug 15 05:00:00 PM PDT 24
Finished Aug 15 05:41:13 PM PDT 24
Peak memory 284516 kb
Host smart-835c755a-7dd2-4a43-87a8-243889a09a9f
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2574258359 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy.2574258359
Directory /workspace/8.alert_handler_entropy/latest

Test location /workspace/coverage/default/8.alert_handler_entropy_stress.1589493856
Short name T438
Test name
Test status
Simulation time 1179677558 ps
CPU time 13.74 seconds
Started Aug 15 04:59:59 PM PDT 24
Finished Aug 15 05:00:13 PM PDT 24
Peak memory 248768 kb
Host smart-bcc37e3d-249d-4630-be22-e749058a5d21
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1589493856 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_entropy_stress.1589493856
Directory /workspace/8.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/8.alert_handler_esc_alert_accum.386662787
Short name T657
Test name
Test status
Simulation time 4247585119 ps
CPU time 54.92 seconds
Started Aug 15 04:59:58 PM PDT 24
Finished Aug 15 05:00:54 PM PDT 24
Peak memory 256468 kb
Host smart-1088c6f7-0dce-4cb2-866a-68891d745dd8
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=38666
2787 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_alert_accum.386662787
Directory /workspace/8.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/8.alert_handler_esc_intr_timeout.2737227347
Short name T30
Test name
Test status
Simulation time 763559895 ps
CPU time 18.18 seconds
Started Aug 15 05:00:00 PM PDT 24
Finished Aug 15 05:00:18 PM PDT 24
Peak memory 248332 kb
Host smart-0e48a152-e353-473f-a6bc-6446c286e258
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=27372
27347 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_esc_intr_timeout.2737227347
Directory /workspace/8.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/8.alert_handler_lpg.1556094819
Short name T331
Test name
Test status
Simulation time 45824085218 ps
CPU time 746.92 seconds
Started Aug 15 04:59:58 PM PDT 24
Finished Aug 15 05:12:25 PM PDT 24
Peak memory 272520 kb
Host smart-20558d9a-b6bf-4f82-a921-55c5ff600d10
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=1556094819 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg.1556094819
Directory /workspace/8.alert_handler_lpg/latest

Test location /workspace/coverage/default/8.alert_handler_lpg_stub_clk.2989125041
Short name T101
Test name
Test status
Simulation time 36112749845 ps
CPU time 648.97 seconds
Started Aug 15 05:00:00 PM PDT 24
Finished Aug 15 05:10:49 PM PDT 24
Peak memory 273308 kb
Host smart-db7b5c9d-fae5-4ede-b002-e6977d5429de
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=2989125041 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_stub_clk_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_lpg_stub_clk.2989125041
Directory /workspace/8.alert_handler_lpg_stub_clk/latest

Test location /workspace/coverage/default/8.alert_handler_random_alerts.4275369450
Short name T625
Test name
Test status
Simulation time 382805805 ps
CPU time 7.94 seconds
Started Aug 15 04:59:59 PM PDT 24
Finished Aug 15 05:00:07 PM PDT 24
Peak memory 248728 kb
Host smart-b393545c-1a83-4561-827c-4d76d1f8faef
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=42753
69450 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_alerts.4275369450
Directory /workspace/8.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/8.alert_handler_random_classes.3253057088
Short name T565
Test name
Test status
Simulation time 816259643 ps
CPU time 42.52 seconds
Started Aug 15 05:00:01 PM PDT 24
Finished Aug 15 05:00:43 PM PDT 24
Peak memory 256572 kb
Host smart-cd30c712-6f17-4d3d-83d9-38be02064df1
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=32530
57088 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bra
nch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_random_classes.3253057088
Directory /workspace/8.alert_handler_random_classes/latest

Test location /workspace/coverage/default/8.alert_handler_sig_int_fail.775199942
Short name T491
Test name
Test status
Simulation time 533916312 ps
CPU time 30.93 seconds
Started Aug 15 05:00:01 PM PDT 24
Finished Aug 15 05:00:32 PM PDT 24
Peak memory 248800 kb
Host smart-4b8b32f1-8d49-4407-8da6-175b929ad737
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=77519
9942 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_sig_int_fail.775199942
Directory /workspace/8.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/8.alert_handler_smoke.151868559
Short name T660
Test name
Test status
Simulation time 448376728 ps
CPU time 14.98 seconds
Started Aug 15 04:59:59 PM PDT 24
Finished Aug 15 05:00:15 PM PDT 24
Peak memory 256748 kb
Host smart-c7364c5f-3656-42c3-8741-a9e061575e82
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=15186
8559 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert
-cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_handler_smoke.151868559
Directory /workspace/8.alert_handler_smoke/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all.4101292838
Short name T413
Test name
Test status
Simulation time 25856659323 ps
CPU time 310.33 seconds
Started Aug 15 05:00:03 PM PDT 24
Finished Aug 15 05:05:17 PM PDT 24
Peak memory 256904 kb
Host smart-7d3d6396-476a-4ae4-8ac5-5b5ac5663e89
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=4101292838 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 8.alert_han
dler_stress_all.4101292838
Directory /workspace/8.alert_handler_stress_all/latest

Test location /workspace/coverage/default/8.alert_handler_stress_all_with_rand_reset.2229826650
Short name T704
Test name
Test status
Simulation time 1944928687 ps
CPU time 135.35 seconds
Started Aug 15 05:00:01 PM PDT 24
Finished Aug 15 05:02:16 PM PDT 24
Peak memory 265280 kb
Host smart-0f619c75-a213-46b3-b462-ccc096eae884
User root
Command /workspace/default/simv +run_stress_all_with_rand_reset +test_timeout_ns=10000000000 +stress_seq=alert_handler_stress_all_vseq +UVM_NO_RELNOTES +UVM_V
ERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=2229826650 -assert nopostproc +UVM_TESTNAME=aler
t_handler_base_test +UVM_TEST_SEQ=alert_handler_common_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb
-cm_log /dev/null -cm_name 8.alert_handler_stress_all_with_rand_reset.2229826650
Directory /workspace/8.alert_handler_stress_all_with_rand_reset/latest

Test location /workspace/coverage/default/9.alert_handler_alert_accum_saturation.3110535534
Short name T199
Test name
Test status
Simulation time 93517713 ps
CPU time 3.58 seconds
Started Aug 15 05:00:11 PM PDT 24
Finished Aug 15 05:00:15 PM PDT 24
Peak memory 248944 kb
Host smart-5d04dc72-4f92-4537-9baa-35f437231d47
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=3110535534 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_alert_accum_saturation_vseq +en_cov=1 -cm lin
e+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_alert_accum_saturation.3110535534
Directory /workspace/9.alert_handler_alert_accum_saturation/latest

Test location /workspace/coverage/default/9.alert_handler_entropy.3306546481
Short name T21
Test name
Test status
Simulation time 264524168609 ps
CPU time 2283.07 seconds
Started Aug 15 05:00:15 PM PDT 24
Finished Aug 15 05:38:18 PM PDT 24
Peak memory 289624 kb
Host smart-b21e3d61-fd73-4669-a350-9356b114171c
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3306546481 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_vseq +en_cov=1 -
cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy.3306546481
Directory /workspace/9.alert_handler_entropy/latest

Test location /workspace/coverage/default/9.alert_handler_entropy_stress.1079551782
Short name T708
Test name
Test status
Simulation time 768939379 ps
CPU time 13.71 seconds
Started Aug 15 05:00:15 PM PDT 24
Finished Aug 15 05:00:29 PM PDT 24
Peak memory 248708 kb
Host smart-aba9910c-0a9e-4e2e-aa17-efe767fc2a7e
User root
Command /workspace/default/simv +en_scb=0 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_
seed=1079551782 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_entropy_stress_vseq +en_cov=1 -cm line+cond+f
sm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_entropy_stress.1079551782
Directory /workspace/9.alert_handler_entropy_stress/latest

Test location /workspace/coverage/default/9.alert_handler_esc_alert_accum.1020600474
Short name T622
Test name
Test status
Simulation time 3426663910 ps
CPU time 93.6 seconds
Started Aug 15 05:00:12 PM PDT 24
Finished Aug 15 05:01:46 PM PDT 24
Peak memory 257044 kb
Host smart-68dadc49-9d51-42c3-8578-319428877041
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=10206
00474 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_alert_accum_vseq +en_cov=1 -cm line+cond+fsm+tgl+br
anch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_alert_accum.1020600474
Directory /workspace/9.alert_handler_esc_alert_accum/latest

Test location /workspace/coverage/default/9.alert_handler_esc_intr_timeout.4161551413
Short name T422
Test name
Test status
Simulation time 292963156 ps
CPU time 7.16 seconds
Started Aug 15 05:00:13 PM PDT 24
Finished Aug 15 05:00:20 PM PDT 24
Peak memory 250848 kb
Host smart-998a7c68-7ab6-47df-9f5f-56181c7d7093
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=41615
51413 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_esc_intr_timeout_vseq +en_cov=1 -cm line+cond+fsm+tgl+b
ranch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_esc_intr_timeout.4161551413
Directory /workspace/9.alert_handler_esc_intr_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_lpg.3011290707
Short name T469
Test name
Test status
Simulation time 22716563910 ps
CPU time 1309.88 seconds
Started Aug 15 05:00:14 PM PDT 24
Finished Aug 15 05:22:04 PM PDT 24
Peak memory 272472 kb
Host smart-759387c0-f651-4ae3-9405-399f2a32e920
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3011290707 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_lpg_vseq +en_cov=1 -cm l
ine+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_lpg.3011290707
Directory /workspace/9.alert_handler_lpg/latest

Test location /workspace/coverage/default/9.alert_handler_ping_timeout.3602495216
Short name T302
Test name
Test status
Simulation time 9500912232 ps
CPU time 200.93 seconds
Started Aug 15 05:00:11 PM PDT 24
Finished Aug 15 05:03:32 PM PDT 24
Peak memory 248800 kb
Host smart-7581f5c9-6b55-4624-a5c8-c4e044c72ac5
User root
Command /workspace/default/simv +test_timeout_ns=1_000_000_000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools
/sim.tcl +ntb_random_seed=3602495216 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_ping_timeout_vseq +en_co
v=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_ping_timeout.3602495216
Directory /workspace/9.alert_handler_ping_timeout/latest

Test location /workspace/coverage/default/9.alert_handler_random_alerts.1234477422
Short name T621
Test name
Test status
Simulation time 1489229721 ps
CPU time 23.54 seconds
Started Aug 15 05:00:14 PM PDT 24
Finished Aug 15 05:00:37 PM PDT 24
Peak memory 248712 kb
Host smart-13b6f552-8405-44a9-a95c-ba92c3f2647f
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=12344
77422 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_alerts_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_alerts.1234477422
Directory /workspace/9.alert_handler_random_alerts/latest

Test location /workspace/coverage/default/9.alert_handler_random_classes.219407894
Short name T45
Test name
Test status
Simulation time 3896362297 ps
CPU time 55.51 seconds
Started Aug 15 05:00:23 PM PDT 24
Finished Aug 15 05:01:19 PM PDT 24
Peak memory 257060 kb
Host smart-b4e8f853-6c15-4aef-bbc0-0fec868ded18
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=21940
7894 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_random_classes_vseq +en_cov=1 -cm line+cond+fsm+tgl+bran
ch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_random_classes.219407894
Directory /workspace/9.alert_handler_random_classes/latest

Test location /workspace/coverage/default/9.alert_handler_sig_int_fail.648995764
Short name T275
Test name
Test status
Simulation time 761301202 ps
CPU time 45.31 seconds
Started Aug 15 05:00:11 PM PDT 24
Finished Aug 15 05:00:57 PM PDT 24
Peak memory 248800 kb
Host smart-d22813f5-00a6-4d18-a1ce-4bcb2894b526
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=64899
5764 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_sig_int_fail_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch
+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_sig_int_fail.648995764
Directory /workspace/9.alert_handler_sig_int_fail/latest

Test location /workspace/coverage/default/9.alert_handler_smoke.3445255233
Short name T687
Test name
Test status
Simulation time 740526755 ps
CPU time 9.13 seconds
Started Aug 15 05:00:12 PM PDT 24
Finished Aug 15 05:00:21 PM PDT 24
Peak memory 248628 kb
Host smart-fcb6bbdb-de10-4a52-9514-fab1828c7e8d
User root
Command /workspace/default/simv +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /workspace/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=34452
55233 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_handler_smoke_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+asser
t -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_handler_smoke.3445255233
Directory /workspace/9.alert_handler_smoke/latest

Test location /workspace/coverage/default/9.alert_handler_stress_all.3769664170
Short name T280
Test name
Test status
Simulation time 60387340898 ps
CPU time 1207.08 seconds
Started Aug 15 05:00:14 PM PDT 24
Finished Aug 15 05:20:21 PM PDT 24
Peak memory 287656 kb
Host smart-815475a6-ad59-42c1-8d59-bdeb38f65355
User root
Command /workspace/default/simv +test_timeout_ns=15_000_000_000 +test_timeout_ns=10000000000 +UVM_NO_RELNOTES +UVM_VERBOSITY=UVM_LOW -licqueue -ucli -do /work
space/mnt/repo_top/hw/dv/tools/sim.tcl +ntb_random_seed=3769664170 -assert nopostproc +UVM_TESTNAME=alert_handler_base_test +UVM_TEST_SEQ=alert_ha
ndler_stress_all_vseq +en_cov=1 -cm line+cond+fsm+tgl+branch+assert -cm_dir /workspace/coverage/default.vdb -cm_log /dev/null -cm_name 9.alert_han
dler_stress_all.3769664170
Directory /workspace/9.alert_handler_stress_all/latest
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