Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
100.00	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

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Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	10	0	10	100.00
Crosses	16	0	16	100.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
esc_index_cp	4	0	4	100.00	100	1	1	0
loc_alert_cause_cp	2	0	2	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_loc_alert_cause_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
loc_alert_cause_cross_alert_index	8	0	8	100.00	100	1	1	0
loc_alert_cause_cross_class_index	8	0	8	100.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_i[0x0]	51459	1			T4	20		T21	2		T6	328
class_i[0x1]	44280	1			T4	700		T21	273		T18	4141
class_i[0x2]	35951	1			T13	15		T4	17		T21	317
class_i[0x3]	41339	1			T13	62		T21	257		T19	2551

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Summary for Variable esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_index_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
alert[0x0]	43930	1			T13	21		T4	705		T21	23
alert[0x1]	43048	1			T13	22		T4	6		T21	2
alert[0x2]	44179	1			T13	15		T4	15		T21	2
alert[0x3]	41872	1			T13	19		T4	11		T21	822

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Summary for Variable loc_alert_cause_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	2	0	2	100.00

User Defined Bins for loc_alert_cause_cp

Excluded/Illegal bins

NAME	COUNT	STATUS
il	0	Illegal

Covered bins

NAME

COUNT

AT LEAST

STATUS

TEST

COUNT

TEST

COUNT

TEST

COUNT

esc_integrity_fail

172762

1

T13

77

T4

737

T21

849

esc_ping_fail

267

1

T15

1

T16

5

T17

7

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Summary for Cross loc_alert_cause_cross_alert_index

Samples crossed: loc_alert_cause_cp esc_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_alert_index

Bins

loc_alert_cause_cp	esc_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	alert[0x0]	43842	1			T13	21		T4	705		T21	23
esc_integrity_fail	alert[0x1]	42980	1			T13	22		T4	6		T21	2
esc_integrity_fail	alert[0x2]	44122	1			T13	15		T4	15		T21	2
esc_integrity_fail	alert[0x3]	41818	1			T13	19		T4	11		T21	822
esc_ping_fail	alert[0x0]	88	1			T16	1		T17	2		T91	5
esc_ping_fail	alert[0x1]	68	1			T15	1		T16	2		T17	3
esc_ping_fail	alert[0x2]	57	1			T16	1		T17	1		T226	1
esc_ping_fail	alert[0x3]	54	1			T16	1		T17	1		T91	3

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Summary for Cross loc_alert_cause_cross_class_index

Samples crossed: loc_alert_cause_cp class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	8	0	8	100.00

Automatically Generated Cross Bins for loc_alert_cause_cross_class_index

Bins

loc_alert_cause_cp	class_index_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
esc_integrity_fail	class_i[0x0]	51402	1			T4	20		T21	2		T6	328
esc_integrity_fail	class_i[0x1]	44215	1			T4	700		T21	273		T18	4141
esc_integrity_fail	class_i[0x2]	35882	1			T13	15		T4	17		T21	317
esc_integrity_fail	class_i[0x3]	41263	1			T13	62		T21	257		T19	2551
esc_ping_fail	class_i[0x0]	57	1			T228	6		T307	1		T302	1
esc_ping_fail	class_i[0x1]	65	1			T16	5		T228	1		T308	6
esc_ping_fail	class_i[0x2]	69	1			T15	1		T91	8		T228	1
esc_ping_fail	class_i[0x3]	76	1			T17	7		T226	5		T228	1