Detail Report for Assertions

Assertions Uncovered:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.u_edn_req.u_prim_packer_fifo.DataOStableWhenPending_A	0	0	561260441	0	0	624
tb.dut.u_edn_req.u_prim_packer_fifo.ValidOPairedWithReadyI_A	0	0	561260441	0	0	0

Assertions Success:

ASSERTIONS	CATEGORY	SEVERITY	ATTEMPTS	REAL SUCCESSES	FAILURES	INCOMPLETE	SRC
tb.dut.AckPKnownO_A	0	0	561260441	561104358	0	0
tb.dut.CheckAccuCntDw	0	0	624	624	0	0
tb.dut.CheckEscCntDw	0	0	624	624	0	0
tb.dut.CheckNAlerts	0	0	624	624	0	0
tb.dut.CheckNClasses	0	0	624	624	0	0
tb.dut.CheckNEscSev	0	0	624	624	0	0
tb.dut.CrashdumpKnownO_A	0	0	561260441	561104358	0	0
tb.dut.EdnKnownO_A	0	0	561260441	561104358	0	0
tb.dut.EscPKnownO_A	0	0	561260441	561104358	0	0
tb.dut.FpvSecCmPingTimerCnterCheck_A	0	0	561260441	70	0	0
tb.dut.FpvSecCmPingTimerDoubleLfsrCheck_A	0	0	561260441	70	0	0
tb.dut.FpvSecCmPingTimerEscCnterCheck_A	0	0	561260441	70	0	0
tb.dut.FpvSecCmPingTimerFsmCheck_A	0	0	561260441	70	0	0
tb.dut.FpvSecCmRegWeOnehotCheck_A	0	0	561260441	70	0	0
tb.dut.IrqAKnownO_A	0	0	561260441	561104358	0	0
tb.dut.IrqBKnownO_A	0	0	561260441	561104358	0	0
tb.dut.IrqCKnownO_A	0	0	561260441	561104358	0	0
tb.dut.IrqDKnownO_A	0	0	561260441	561104358	0	0
tb.dut.TlAReadyKnownO_A	0	0	561260441	561104358	0	0
tb.dut.TlDValidKnownO_A	0	0	561260441	561104358	0	0
tb.dut.alert_handler_csr_assert.TlulOOBAddrErr_A	0	0	584909846	190771	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_0_rd_A	0	0	584909846	10150	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_10_rd_A	0	0	584909846	10189	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_11_rd_A	0	0	584909846	11442	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_12_rd_A	0	0	584909846	11235	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_13_rd_A	0	0	584909846	9207	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_14_rd_A	0	0	584909846	8908	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_15_rd_A	0	0	584909846	10048	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_16_rd_A	0	0	584909846	10038	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_17_rd_A	0	0	584909846	10577	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_18_rd_A	0	0	584909846	10247	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_19_rd_A	0	0	584909846	11385	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_1_rd_A	0	0	584909846	9971	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_20_rd_A	0	0	584909846	9786	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_21_rd_A	0	0	584909846	9990	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_22_rd_A	0	0	584909846	9986	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_23_rd_A	0	0	584909846	10086	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_24_rd_A	0	0	584909846	12523	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_25_rd_A	0	0	584909846	9134	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_26_rd_A	0	0	584909846	11230	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_27_rd_A	0	0	584909846	9099	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_28_rd_A	0	0	584909846	8753	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_29_rd_A	0	0	584909846	10019	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_2_rd_A	0	0	584909846	8941	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_30_rd_A	0	0	584909846	10165	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_31_rd_A	0	0	584909846	11087	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_32_rd_A	0	0	584909846	10032	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_33_rd_A	0	0	584909846	9190	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_34_rd_A	0	0	584909846	10133	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_35_rd_A	0	0	584909846	10240	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_36_rd_A	0	0	584909846	12573	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_37_rd_A	0	0	584909846	11025	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_38_rd_A	0	0	584909846	10003	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_39_rd_A	0	0	584909846	9894	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_3_rd_A	0	0	584909846	9181	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_40_rd_A	0	0	584909846	8968	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_41_rd_A	0	0	584909846	10019	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_42_rd_A	0	0	584909846	10270	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_43_rd_A	0	0	584909846	9937	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_44_rd_A	0	0	584909846	11265	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_45_rd_A	0	0	584909846	8796	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_46_rd_A	0	0	584909846	9141	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_47_rd_A	0	0	584909846	10222	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_48_rd_A	0	0	584909846	8805	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_49_rd_A	0	0	584909846	8777	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_4_rd_A	0	0	584909846	10379	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_50_rd_A	0	0	584909846	8944	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_51_rd_A	0	0	584909846	10025	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_52_rd_A	0	0	584909846	9953	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_53_rd_A	0	0	584909846	8987	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_54_rd_A	0	0	584909846	11089	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_55_rd_A	0	0	584909846	10321	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_56_rd_A	0	0	584909846	10044	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_57_rd_A	0	0	584909846	10016	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_58_rd_A	0	0	584909846	10462	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_59_rd_A	0	0	584909846	8908	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_5_rd_A	0	0	584909846	12376	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_60_rd_A	0	0	584909846	10106	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_61_rd_A	0	0	584909846	10124	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_62_rd_A	0	0	584909846	10225	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_63_rd_A	0	0	584909846	10218	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_64_rd_A	0	0	584909846	10350	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_6_rd_A	0	0	584909846	8935	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_7_rd_A	0	0	584909846	11078	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_8_rd_A	0	0	584909846	9238	0	0
tb.dut.alert_handler_csr_assert.alert_regwen_9_rd_A	0	0	584909846	10042	0	0
tb.dut.alert_handler_csr_assert.classa_regwen_rd_A	0	0	584909846	8988	0	0
tb.dut.alert_handler_csr_assert.classb_regwen_rd_A	0	0	584909846	11130	0	0
tb.dut.alert_handler_csr_assert.classc_regwen_rd_A	0	0	584909846	10129	0	0
tb.dut.alert_handler_csr_assert.classd_regwen_rd_A	0	0	584909846	11433	0	0
tb.dut.alert_handler_csr_assert.intr_enable_rd_A	0	0	584909846	17062	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_0_rd_A	0	0	584909846	10064	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_1_rd_A	0	0	584909846	10331	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_2_rd_A	0	0	584909846	11187	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_3_rd_A	0	0	584909846	11368	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_4_rd_A	0	0	584909846	10104	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_5_rd_A	0	0	584909846	10038	0	0
tb.dut.alert_handler_csr_assert.loc_alert_regwen_6_rd_A	0	0	584909846	8913	0	0
tb.dut.alert_handler_csr_assert.ping_timer_regwen_rd_A	0	0	584909846	10302	0	0
tb.dut.gen_classes[0].FpvSecCmAccuCnterCheck_A	0	0	561260441	70	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerCnterCheck_A	0	0	561260441	70	0	0
tb.dut.gen_classes[0].FpvSecCmEscTimerFsmCheck_A	0	0	561260441	70	0	0
tb.dut.gen_classes[0].u_accu.CountSaturateStable_A	0	0	561260441	4090	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigBkwd_A	0	0	561260441	162878	0	0
tb.dut.gen_classes[0].u_accu.DisabledNoTrigFwd_A	0	0	561260441	302125581	0	0
tb.dut.gen_classes[0].u_esc_timer.AccuFailToFsmError_A	0	0	561260441	206	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig0_A	0	0	561260441	749	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckAccumTrig1_A	0	0	561260441	57	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckClr_A	0	0	561260441	378	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckEn_A	0	0	560975925	255865667	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase0_A	0	0	561260441	834	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase1_A	0	0	561260441	801	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase2_A	0	0	561260441	790	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckPhase3_A	0	0	561260441	777	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeout0_A	0	0	561260441	1531	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt1_A	0	0	561260441	183758	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutSt2_A	0	0	561260441	1414	0	0
tb.dut.gen_classes[0].u_esc_timer.CheckTimeoutStTrig_A	0	0	561260441	54	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStAllEscAsserted_A	0	0	561260441	1144	0	0
tb.dut.gen_classes[0].u_esc_timer.ErrorStIsTerminal_A	0	0	561260441	934	0	0
tb.dut.gen_classes[0].u_esc_timer.EscStateOut_A	0	0	560970317	560904326	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs.AssertConnected_A	0	0	624	624	0	0
tb.dut.gen_classes[0].u_esc_timer.u_state_regs_A	0	0	561260441	561104358	0	0
tb.dut.gen_classes[1].FpvSecCmAccuCnterCheck_A	0	0	561260441	70	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerCnterCheck_A	0	0	561260441	70	0	0
tb.dut.gen_classes[1].FpvSecCmEscTimerFsmCheck_A	0	0	561260441	70	0	0
tb.dut.gen_classes[1].u_accu.CountSaturateStable_A	0	0	561260441	5765	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigBkwd_A	0	0	561260441	164351	0	0
tb.dut.gen_classes[1].u_accu.DisabledNoTrigFwd_A	0	0	561260441	314145574	0	0
tb.dut.gen_classes[1].u_esc_timer.AccuFailToFsmError_A	0	0	561260441	181	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig0_A	0	0	561260441	432	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckAccumTrig1_A	0	0	561260441	26	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckClr_A	0	0	561260441	179	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckEn_A	0	0	560975925	230954922	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase0_A	0	0	561260441	511	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase1_A	0	0	561260441	496	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase2_A	0	0	561260441	492	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckPhase3_A	0	0	561260441	486	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeout0_A	0	0	561260441	1891	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt1_A	0	0	561260441	228901	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutSt2_A	0	0	561260441	1795	0	0
tb.dut.gen_classes[1].u_esc_timer.CheckTimeoutStTrig_A	0	0	561260441	65	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStAllEscAsserted_A	0	0	561260441	1130	0	0
tb.dut.gen_classes[1].u_esc_timer.ErrorStIsTerminal_A	0	0	561260441	920	0	0
tb.dut.gen_classes[1].u_esc_timer.EscStateOut_A	0	0	560970317	560904326	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs.AssertConnected_A	0	0	624	624	0	0
tb.dut.gen_classes[1].u_esc_timer.u_state_regs_A	0	0	561260441	561104358	0	0
tb.dut.gen_classes[2].FpvSecCmAccuCnterCheck_A	0	0	561260441	70	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerCnterCheck_A	0	0	561260441	70	0	0
tb.dut.gen_classes[2].FpvSecCmEscTimerFsmCheck_A	0	0	561260441	70	0	0
tb.dut.gen_classes[2].u_accu.CountSaturateStable_A	0	0	561260441	1557	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigBkwd_A	0	0	561260441	187187	0	0
tb.dut.gen_classes[2].u_accu.DisabledNoTrigFwd_A	0	0	561260441	299320324	0	0
tb.dut.gen_classes[2].u_esc_timer.AccuFailToFsmError_A	0	0	561260441	177	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig0_A	0	0	561260441	442	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckAccumTrig1_A	0	0	561260441	26	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckClr_A	0	0	561260441	192	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckEn_A	0	0	560975925	237975764	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase0_A	0	0	561260441	498	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase1_A	0	0	561260441	485	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase2_A	0	0	561260441	478	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckPhase3_A	0	0	561260441	474	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeout0_A	0	0	561260441	455	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt1_A	0	0	561260441	57675	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutSt2_A	0	0	561260441	380	0	0
tb.dut.gen_classes[2].u_esc_timer.CheckTimeoutStTrig_A	0	0	561260441	46	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStAllEscAsserted_A	0	0	561260441	1077	0	0
tb.dut.gen_classes[2].u_esc_timer.ErrorStIsTerminal_A	0	0	561260441	867	0	0
tb.dut.gen_classes[2].u_esc_timer.EscStateOut_A	0	0	560970317	560904326	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs.AssertConnected_A	0	0	624	624	0	0
tb.dut.gen_classes[2].u_esc_timer.u_state_regs_A	0	0	561260441	561104358	0	0
tb.dut.gen_classes[3].FpvSecCmAccuCnterCheck_A	0	0	561260441	70	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerCnterCheck_A	0	0	561260441	70	0	0
tb.dut.gen_classes[3].FpvSecCmEscTimerFsmCheck_A	0	0	561260441	70	0	0
tb.dut.gen_classes[3].u_accu.CountSaturateStable_A	0	0	561260441	5659	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigBkwd_A	0	0	561260441	147413	0	0
tb.dut.gen_classes[3].u_accu.DisabledNoTrigFwd_A	0	0	561260441	315192929	0	0
tb.dut.gen_classes[3].u_esc_timer.AccuFailToFsmError_A	0	0	561260441	168	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig0_A	0	0	561260441	428	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckAccumTrig1_A	0	0	561260441	13	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckClr_A	0	0	561260441	168	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckEn_A	0	0	560975925	240395777	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase0_A	0	0	561260441	485	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase1_A	0	0	561260441	479	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase2_A	0	0	561260441	474	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckPhase3_A	0	0	561260441	468	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeout0_A	0	0	561260441	941	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt1_A	0	0	561260441	119428	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutSt2_A	0	0	561260441	862	0	0
tb.dut.gen_classes[3].u_esc_timer.CheckTimeoutStTrig_A	0	0	561260441	59	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStAllEscAsserted_A	0	0	561260441	1129	0	0
tb.dut.gen_classes[3].u_esc_timer.ErrorStIsTerminal_A	0	0	561260441	919	0	0
tb.dut.gen_classes[3].u_esc_timer.EscStateOut_A	0	0	560970317	560904326	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs.AssertConnected_A	0	0	624	624	0	0
tb.dut.gen_classes[3].u_esc_timer.u_state_regs_A	0	0	561260441	561104358	0	0
tb.dut.tlul_assert_device.aKnown_A	0	0	584909846	81162533	0	0
tb.dut.tlul_assert_device.aKnown_AKnownEnable	0	0	584909846	584271610	0	0
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