Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
94.92	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	15	0	15	100.00
Crosses	44	3	41	93.18

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
esc_sig_index_cp	4	0	4	100.00	100	1	1	0
esc_sig_len_cp	11	0	11	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::esc_sig_length_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
len_per_esc_sig	44	3	41	93.18	100	1	1	0

Summary for Variable esc_sig_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for esc_sig_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	143	1			T4	1		T18	7		T6	2
index[0x1]	165	1			T4	2		T18	1		T6	2
index[0x2]	173	1			T3	1		T4	5		T5	1
index[0x3]	189	1			T11	1		T4	1		T5	1

---

Summary for Variable esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	11	0	11	100.00

User Defined Bins for esc_sig_len_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
lens_less_than_1000[0]	211	1			T11	1		T4	5		T5	1
lens_less_than_1000[1]	115	1			T3	1		T4	2		T6	1
lens_less_than_1000[2]	88	1			T21	1		T18	1		T43	2
lens_less_than_1000[3]	84	1			T4	1		T6	2		T43	2
lens_less_than_1000[4]	54	1			T69	5		T71	1		T220	1
lens_less_than_1000[5]	43	1			T5	1		T228	1		T247	1
lens_less_than_1000[6]	28	1			T4	1		T45	1		T47	1
lens_less_than_1000[7]	17	1			T81	1		T248	2		T86	1
lens_less_than_1000[8]	10	1			T6	1		T44	1		T66	1
lens_less_than_1000[9]	2	1			T249	1		T250	1		-	-
len_2	18	1			T18	7		T122	1		T29	1

---

Summary for Cross len_per_esc_sig

Samples crossed: esc_sig_index_cp esc_sig_len_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	44	3	41	93.18	3

Automatically Generated Cross Bins for len_per_esc_sig

Uncovered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	NUMBER	STATUS
[index[0x0] , index[0x1]]	[lens_less_than_1000[9]]	--	--	2
[index[0x3]]	[lens_less_than_1000[9]]	0	1	1

Covered bins

esc_sig_index_cp	esc_sig_len_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
index[0x0]	lens_less_than_1000[0]	42	1			T6	1		T66	1		T69	1
index[0x0]	lens_less_than_1000[1]	13	1			T63	1		T251	1		T247	1
index[0x0]	lens_less_than_1000[2]	18	1			T43	1		T66	1		T27	1
index[0x0]	lens_less_than_1000[3]	24	1			T4	1		T6	1		T252	1
index[0x0]	lens_less_than_1000[4]	12	1			T69	1		T220	1		T253	1
index[0x0]	lens_less_than_1000[5]	14	1			T228	1		T80	1		T254	1
index[0x0]	lens_less_than_1000[6]	6	1			T45	1		T255	1		T256	1
index[0x0]	lens_less_than_1000[7]	2	1			T248	1		T257	1		-	-
index[0x0]	lens_less_than_1000[8]	2	1			T258	1		T257	1		-	-
index[0x0]	len_2	10	1			T18	7		T29	1		T259	1
index[0x1]	lens_less_than_1000[0]	53	1			T4	1		T22	1		T231	1
index[0x1]	lens_less_than_1000[1]	33	1			T6	1		T47	1		T260	1
index[0x1]	lens_less_than_1000[2]	23	1			T18	1		T43	1		T47	1
index[0x1]	lens_less_than_1000[3]	18	1			T43	1		T65	1		T27	1
index[0x1]	lens_less_than_1000[4]	12	1			T261	1		T82	1		T262	1
index[0x1]	lens_less_than_1000[5]	7	1			T247	1		T33	1		T40	1
index[0x1]	lens_less_than_1000[6]	8	1			T4	1		T47	1		T263	1
index[0x1]	lens_less_than_1000[7]	6	1			T248	1		T90	3		T98	1
index[0x1]	lens_less_than_1000[8]	3	1			T6	1		T97	1		T264	1
index[0x1]	len_2	2	1			T85	1		T265	1		-	-
index[0x2]	lens_less_than_1000[0]	65	1			T4	3		T5	1		T43	1
index[0x2]	lens_less_than_1000[1]	33	1			T3	1		T4	2		T66	1
index[0x2]	lens_less_than_1000[2]	13	1			T73	1		T266	1		T267	1
index[0x2]	lens_less_than_1000[3]	17	1			T6	1		T43	1		T47	1
index[0x2]	lens_less_than_1000[4]	21	1			T69	3		T184	1		T268	1
index[0x2]	lens_less_than_1000[5]	8	1			T184	1		T97	1		T269	1
index[0x2]	lens_less_than_1000[6]	9	1			T86	1		T270	1		T59	1
index[0x2]	lens_less_than_1000[7]	1	1			T271	1		-	-		-	-
index[0x2]	lens_less_than_1000[8]	2	1			T44	1		T85	1		-	-
index[0x2]	lens_less_than_1000[9]	2	1			T249	1		T250	1		-	-
index[0x2]	len_2	2	1			T80	1		T272	1		-	-
index[0x3]	lens_less_than_1000[0]	51	1			T11	1		T4	1		T66	1
index[0x3]	lens_less_than_1000[1]	36	1			T67	4		T29	1		T71	1
index[0x3]	lens_less_than_1000[2]	34	1			T21	1		T75	1		T47	2
index[0x3]	lens_less_than_1000[3]	25	1			T273	1		T248	1		T57	2
index[0x3]	lens_less_than_1000[4]	9	1			T69	1		T71	1		T78	1
index[0x3]	lens_less_than_1000[5]	14	1			T5	1		T80	1		T86	1
index[0x3]	lens_less_than_1000[6]	5	1			T57	1		T274	1		T275	1
index[0x3]	lens_less_than_1000[7]	8	1			T81	1		T86	1		T276	4
index[0x3]	lens_less_than_1000[8]	3	1			T66	1		T125	1		T105	1
index[0x3]	len_2	4	1			T122	1		T277	1		T278	1