Unified Coverage Report :: Group :: alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

Group : alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

SCORE	WEIGHT	GOAL	AT LEAST	AUTO BIN MAX	PRINT MISSING
96.30	1	100	1	64	64

Source File(s) :
/workspace/default/sim-vcs/../src/lowrisc_dv_alert_handler_env_0.1/alert_handler_env_cov.sv

---

Summary for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
Variables	14	0	14	100.00
Crosses	40	2	38	95.00

Variables for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

VARIABLE	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	AUTO BIN MAX	COMMENT
class_index_cp	4	0	4	100.00	100	1	1	0
intr_timeout_cnt_cp	10	0	10	100.00	100	1	1	0

Crosses for Group alert_handler_env_pkg::alert_handler_env_cov::intr_timeout_cnt_cg

CROSS	EXPECTED	UNCOVERED	COVERED	PERCENT	GOAL	WEIGHT	AT LEAST	PRINT MISSING	COMMENT
class_cnt_cross	40	2	38	95.00	100	1	1	0

Summary for Variable class_index_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	4	0	4	100.00

User Defined Bins for class_index_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	54	1			T3	1		T4	1		T23	1
class_index[0x1]	65	1			T4	1		T77	1		T78	1
class_index[0x2]	46	1			T6	3		T49	1		T79	1
class_index[0x3]	59	1			T21	1		T75	1		T49	1

---

Summary for Variable intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT
User Defined Bins	10	0	10	100.00

User Defined Bins for intr_timeout_cnt_cp

Bins

NAME	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
intr_timeout_cnt[0]	70	1			T3	1		T4	1		T6	2
intr_timeout_cnt[1]	45	1			T6	1		T77	1		T78	1
intr_timeout_cnt[2]	26	1			T75	1		T77	1		T79	1
intr_timeout_cnt[3]	26	1			T79	2		T279	3		T87	1
intr_timeout_cnt[4]	12	1			T4	1		T21	1		T49	1
intr_timeout_cnt[5]	13	1			T77	1		T81	2		T83	1
intr_timeout_cnt[6]	11	1			T77	1		T83	1		T280	1
intr_timeout_cnt[7]	8	1			T40	1		T85	1		T56	1
intr_timeout_cnt[8]	7	1			T49	1		T124	1		T79	1
intr_timeout_cnt[9]	6	1			T40	1		T125	1		T87	1

---

Summary for Cross class_cnt_cross

Samples crossed: class_index_cp intr_timeout_cnt_cp

CATEGORY	EXPECTED	UNCOVERED	COVERED	PERCENT	MISSING
Automatically Generated Cross Bins	40	2	38	95.00	2

Automatically Generated Cross Bins for class_cnt_cross

Uncovered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	NUMBER	STATUS
[class_index[0x1]]	[intr_timeout_cnt[5]]	0	1	1
[class_index[0x2]]	[intr_timeout_cnt[8]]	0	1	1

Covered bins

class_index_cp	intr_timeout_cnt_cp	COUNT	AT LEAST	STATUS		TEST	COUNT		TEST	COUNT		TEST	COUNT
class_index[0x0]	intr_timeout_cnt[0]	14	1			T3	1		T23	1		T82	1
class_index[0x0]	intr_timeout_cnt[1]	13	1			T57	1		T281	1		T282	1
class_index[0x0]	intr_timeout_cnt[2]	6	1			T283	1		T284	1		T285	1
class_index[0x0]	intr_timeout_cnt[3]	7	1			T90	5		T286	1		T257	1
class_index[0x0]	intr_timeout_cnt[4]	4	1			T4	1		T80	1		T287	1
class_index[0x0]	intr_timeout_cnt[5]	5	1			T81	1		T83	1		T276	2
class_index[0x0]	intr_timeout_cnt[6]	1	1			T102	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[7]	2	1			T56	1		T288	1		-	-
class_index[0x0]	intr_timeout_cnt[8]	1	1			T79	1		-	-		-	-
class_index[0x0]	intr_timeout_cnt[9]	1	1			T40	1		-	-		-	-
class_index[0x1]	intr_timeout_cnt[0]	21	1			T4	1		T82	1		T84	1
class_index[0x1]	intr_timeout_cnt[1]	13	1			T78	1		T40	1		T289	2
class_index[0x1]	intr_timeout_cnt[2]	8	1			T77	1		T79	1		T37	1
class_index[0x1]	intr_timeout_cnt[3]	8	1			T79	1		T87	1		T97	1
class_index[0x1]	intr_timeout_cnt[4]	3	1			T101	2		T287	1		-	-
class_index[0x1]	intr_timeout_cnt[6]	7	1			T83	1		T284	1		T99	3
class_index[0x1]	intr_timeout_cnt[7]	2	1			T60	1		T290	1		-	-
class_index[0x1]	intr_timeout_cnt[8]	2	1			T57	1		T108	1		-	-
class_index[0x1]	intr_timeout_cnt[9]	1	1			T290	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[0]	15	1			T6	2		T111	1		T276	1
class_index[0x2]	intr_timeout_cnt[1]	11	1			T6	1		T87	1		T88	1
class_index[0x2]	intr_timeout_cnt[2]	4	1			T89	1		T97	1		T287	1
class_index[0x2]	intr_timeout_cnt[3]	6	1			T79	1		T275	1		T291	3
class_index[0x2]	intr_timeout_cnt[4]	4	1			T49	1		T90	1		T98	2
class_index[0x2]	intr_timeout_cnt[5]	3	1			T292	1		T288	1		T293	1
class_index[0x2]	intr_timeout_cnt[6]	1	1			T280	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[7]	1	1			T85	1		-	-		-	-
class_index[0x2]	intr_timeout_cnt[9]	1	1			T293	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[0]	20	1			T37	1		T84	1		T294	1
class_index[0x3]	intr_timeout_cnt[1]	8	1			T77	1		T56	1		T57	1
class_index[0x3]	intr_timeout_cnt[2]	8	1			T75	1		T81	1		T113	2
class_index[0x3]	intr_timeout_cnt[3]	5	1			T279	3		T290	1		T295	1
class_index[0x3]	intr_timeout_cnt[4]	1	1			T21	1		-	-		-	-
class_index[0x3]	intr_timeout_cnt[5]	5	1			T77	1		T81	1		T296	1
class_index[0x3]	intr_timeout_cnt[6]	2	1			T77	1		T297	1		-	-
class_index[0x3]	intr_timeout_cnt[7]	3	1			T40	1		T297	2		-	-
class_index[0x3]	intr_timeout_cnt[8]	4	1			T49	1		T124	1		T298	1
class_index[0x3]	intr_timeout_cnt[9]	3	1			T125	1		T87	1		T97	1